84764 lines
6.1 MiB
84764 lines
6.1 MiB
; --------------------------------------------------------------------------------
|
|
; @Title: IMX8XDXL On-Chip Peripherals
|
|
; @Props: Released
|
|
; @Author: KWI, JON
|
|
; @Changelog: 2020-07-15 KWI
|
|
; 2021-04-02 KWI
|
|
; 2022-01-22 JON
|
|
; @Manufacturer: NXP - NXP Semiconductors
|
|
; @Doc: SVD generated based on: MIMX8DL1_ca35.svd, MIMX8DL1_cm4.svd,
|
|
; MIMX8SL1_ca35.svd, MIMX8SL1_cm4.svd
|
|
; @Core: Cortex-A35, Cortex-M4F
|
|
; @Chip: IMX8DXL, IMX8DXL-CM4, IMX8DXL-SCU
|
|
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: perimx8dxl.per 19837 2025-08-20 12:38:08Z jhuang $
|
|
|
|
sif (CORENAME()=="CORTEXA35")
|
|
tree "Core Registers (Cortex-A35)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.ON center tree
|
|
tree.open "AArch64"
|
|
tree "ID Registers"
|
|
rgroup.quad spr:0x30000++0x0
|
|
line.quad 0x00 "MIDR_EL1,Main ID Register"
|
|
hexmask.quad.byte 0x00 24.--31. 0x01 "IMPLEMENTER,Implementer code"
|
|
bitfld.quad 0x00 20.--23. "VARIANT,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 16.--19. "ARCHITECTURE,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme"
|
|
newline
|
|
hexmask.quad.word 0x00 4.--15. 0x10 "PARTNUM,Primary Part Number"
|
|
bitfld.quad 0x00 0.--3. "REVISION,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.quad spr:0x30040++0x00
|
|
line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0"
|
|
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
|
|
bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
|
|
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
|
|
newline
|
|
bitfld.quad 0x00 12.--15. "EL3,EL3 exception handling" "Reserved,Reserved,AArch32/AArch64,?..."
|
|
bitfld.quad 0x00 8.--11. "EL2,EL2 exception handling" "Reserved,Reserved,AArch32/AArch64,?..."
|
|
bitfld.quad 0x00 4.--7. "EL1,EL1 exception handling" "Reserved,Reserved,AArch32/AArch64,?..."
|
|
newline
|
|
bitfld.quad 0x00 0.--3. "EL0,EL0 exception handling" "Reserved,Reserved,AArch32/AArch64,?..."
|
|
rgroup.quad spr:0x30050++0x00
|
|
line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0"
|
|
bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,1,?..."
|
|
bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,3,?..."
|
|
bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,5,?..."
|
|
newline
|
|
bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,Implemented,?..."
|
|
bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..."
|
|
bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented,?..."
|
|
rgroup.quad spr:0x30060++0x00
|
|
line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0"
|
|
bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..."
|
|
bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions are implemented" "Not implemented,Implemented,?..."
|
|
bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions are implemented" "Not implemented,Implemented,?..."
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..."
|
|
rgroup.quad spr:0x30070++0x00
|
|
line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0"
|
|
bitfld.quad 0x00 28.--31. "TGRAN4,4KB granule supported" "Supported,?..."
|
|
bitfld.quad 0x00 24.--27. "TGRAN64,64KB granule supported" "Supported,?..."
|
|
bitfld.quad 0x00 20.--23. "TGRAN16,16KB granule supported" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
|
|
newline
|
|
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..."
|
|
rgroup.quad spr:0x30054++0x00
|
|
line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0"
|
|
rgroup.quad spr:0x30055++0x00
|
|
line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1"
|
|
rgroup.quad spr:0x30041++0x00
|
|
line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1"
|
|
rgroup.quad spr:0x30051++0x00
|
|
line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1"
|
|
rgroup.quad spr:0x30061++0x00
|
|
line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1"
|
|
rgroup.quad spr:0x30071++0x00
|
|
line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1"
|
|
rgroup.quad spr:0x30010++0x00
|
|
line.quad 0x00 "ID_PFR0_EL1,AArch32 Processor Feature Register 0"
|
|
bitfld.quad 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
|
|
bitfld.quad 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup.quad spr:0x30011++0x00
|
|
line.quad 0x00 "ID_PFR1_EL1,AArch32 Processor Feature Register 1"
|
|
bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 12.--15. "V,Virtualization Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "S,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup.quad spr:0x30012++0x00
|
|
line.quad 0x00 "ID_DFR0_EL1,AArch32 Debug Feature Register 0"
|
|
bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 20.--23. "MPROFDBG,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
|
|
bitfld.quad 0x00 16.--19. "MMAPTRC,Trace Model (Memory-Mapped) Support" "Not supported,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 12.--15. "COPTRC,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.quad 0x00 4.--7. "COPSDBG,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 0.--3. "COPDBG,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup.quad spr:0x30013++0x00
|
|
line.quad 0x00 "ID_AFR0_EL1,AArch32 Auxiliary Feature Register 0 EL1"
|
|
rgroup.quad spr:0x30014++0x00
|
|
line.quad 0x00 "ID_MMFR0_EL1,AArch32 Memory Model Feature Register 0"
|
|
bitfld.quad 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
|
|
bitfld.quad 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
|
|
bitfld.quad 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
|
|
bitfld.quad 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
|
|
bitfld.quad 0x00 8.--11. "OS,Outer Shareable Support" "Reserved,Implemented,?..."
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.quad 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,VMSAv7,?..."
|
|
rgroup.quad spr:0x30015++0x00
|
|
line.quad 0x00 "ID_MMFR1_EL1,AArch32 Memory Model Feature Register 1"
|
|
bitfld.quad 0x00 28.--31. "BPRED,Indicates branch predictor management requirements" "Reserved,Reserved,Reserved,Reserved,Not required,?..."
|
|
bitfld.quad 0x00 24.--27. "L1TSTCLN,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.quad 0x00 20.--23. "L1UNI,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "L1HVD,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.quad 0x00 12.--15. "L1UNISW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.quad 0x00 8.--11. "L1HVDSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "L1UNIVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.quad 0x00 0.--3. "L1HVDVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
|
|
rgroup.quad spr:0x30016++0x00
|
|
line.quad 0x00 "ID_MMFR2_EL1,AArch32 Memory Model Feature Register 2"
|
|
bitfld.quad 0x00 28.--31. "HWACCFLG,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.quad 0x00 24.--27. "WFISTALL,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 20.--23. "MEMBARR,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "UNITLB,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 12.--15. "HVDTLB,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.quad 0x00 8.--11. "LL1HVDRNG,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "L1HVDBG,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.quad 0x00 0.--3. "L1HVDFG,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup.quad spr:0x30017++0x00
|
|
line.quad 0x00 "ID_MMFR3_EL1,AArch32 Memory Model Feature Register 3"
|
|
bitfld.quad 0x00 28.--31. "SUPERSEC,Supersection support" "Supported,?..."
|
|
bitfld.quad 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
|
|
bitfld.quad 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 4.--7. "CMSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 0.--3. "CMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
|
|
rgroup.quad spr:0x30020++0x00
|
|
line.quad 0x00 "ID_ISAR0_EL1,AArch32 Instruction Set Attribute Register 0"
|
|
bitfld.quad 0x00 24.--27. "DIVIDE,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 20.--23. "DEBUG,Debug Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 16.--19. "COPROC,Coprocessor Instructions Support" "Not supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 12.--15. "CMPBRANCH,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 8.--11. "BITFIELD,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 4.--7. "BITCOUNT,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 0.--3. "SWAP,Swap Instructions Support" "Not supported,?..."
|
|
rgroup.quad spr:0x30021++0x00
|
|
line.quad 0x00 "ID_ISAR1_EL1,AArch32 Instruction Set Attribute Register 1"
|
|
bitfld.quad 0x00 28.--31. "JAZELLE,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 24.--27. "INTERWORK,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 20.--23. "IMMEDIATE,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "IFTHEN,If Then Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 12.--15. "EXTEND,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 8.--11. "EXCEPT_AR,Exception A and R Instructions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "EXCEPT,Exception in ARM Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 0.--3. "ENDIAN,Endian Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.quad spr:0x30022++0x00
|
|
line.quad 0x00 "ID_ISAR2_EL1,AArch32 Instruction Set Attribute Register 2"
|
|
bitfld.quad 0x00 28.--31. "REVERSAL,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 24.--27. "PSR_AR,PSR Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 20.--23. "MULTU,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "MULTS,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 12.--15. "MULT,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 8.--11. "MULTIACCESSINT,Multi-Access Interruptible Instructions Support" "Not supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "MEMHINT,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 0.--3. "LOADSTORE,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup.quad spr:0x30023++0x00
|
|
line.quad 0x00 "ID_ISAR3_EL1,AArch32 Instruction Set Attribute Register 3"
|
|
bitfld.quad 0x00 28.--31. "THUMBEE,Thumb-EE Extensions Support" "Not supported,?..."
|
|
bitfld.quad 0x00 24.--27. "TRUENOP,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 20.--23. "THUMBCOPY,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "TABBRANCH,Table Branch Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 12.--15. "SYNCHPRIM,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 8.--11. "SVC,SVC Instructions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "SIMD,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 0.--3. "SATURATE,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.quad spr:0x30024++0x00
|
|
line.quad 0x00 "ID_ISAR4_EL1,AArch32 Instruction Set Attribute Register 4"
|
|
bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
|
|
bitfld.quad 0x00 24.--27. "PSR_M,PSR_M Instructions Support" "Not supported,?..."
|
|
bitfld.quad 0x00 20.--23. "SYNCHPRIM_FRAC,Synchronization Primitive instructions" "Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "BARRIER,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 12.--15. "SMC,SMC Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 8.--11. "WRITEBACK,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "WITHSHIFTS,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 0.--3. "UNPRIV,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup.quad spr:0x30025++0x00
|
|
line.quad 0x00 "ID_ISAR5_EL1,AArch32 Instruction Set Attribute Register 5"
|
|
bitfld.quad 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.quad 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.quad 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
|
|
bitfld.quad 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.quad spr:0x30005++0x00
|
|
line.quad 0x00 "MPIDR_EL1,Multiprocessor Affinity Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Highest level affinity field"
|
|
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
|
|
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
|
|
newline
|
|
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
|
|
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
|
|
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
|
|
rgroup.quad spr:0x30006++0x0
|
|
line.quad 0x00 "REVIDR_EL1,Revision ID Register"
|
|
rgroup.quad spr:0x33007++0x00
|
|
line.quad 0x00 "DCZID_EL0,Data Cache Zero ID Register"
|
|
bitfld.quad 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited"
|
|
bitfld.quad 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
rgroup.quad spr:0x31007++0x00
|
|
line.quad 0x00 "AIDR_EL1,Auxiliary ID Register"
|
|
group.quad spr:0x34000++0x0
|
|
line.quad 0x00 "VPIDR_EL2,Virtualization Processor ID Register"
|
|
hexmask.quad.byte 0x00 24.--31. 0x01 "IMPLEMENTER,Implementer code"
|
|
bitfld.quad 0x00 20.--23. "VARIANT,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 16.--19. "ARCHITECTURE,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme"
|
|
newline
|
|
hexmask.quad.word 0x00 4.--15. 0x10 "PARTNUM,Primary Part Number"
|
|
bitfld.quad 0x00 0.--3. "REVISION,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.quad spr:0x34005++0x00
|
|
line.quad 0x00 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Highest level affinity field"
|
|
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
|
|
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
|
|
newline
|
|
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
|
|
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
|
|
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
|
|
tree.end
|
|
tree "System Control and Configuration"
|
|
group.quad spr:0x36111++0x00
|
|
line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register"
|
|
bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled"
|
|
group.quad spr:0x30100++0x0
|
|
line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)"
|
|
bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
|
|
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
|
|
newline
|
|
bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
|
|
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
newline
|
|
bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes"
|
|
bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
|
|
bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes"
|
|
bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
|
|
group.quad spr:0x34100++0x0
|
|
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
|
|
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
|
|
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
newline
|
|
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
|
|
group.quad spr:0x36100++0x0
|
|
line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)"
|
|
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
|
|
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
newline
|
|
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
|
|
group.quad spr:0x31F20++0x00
|
|
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
|
|
bitfld.quad 0x00 44. "ENDCCASCI,Enable Data Cache Clean As data cache Clean/Invalidate" "Disabled,Enabled"
|
|
bitfld.quad 0x00 30. "CDIDIS,Disable Cryptographic Dual Issue" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
|
|
bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
|
|
bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes"
|
|
bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams"
|
|
bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 17. "STRIDE,Configure the sequence length that triggers data prefetch streams" "2 linefills,3 linefills"
|
|
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8"
|
|
newline
|
|
bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes"
|
|
bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache Data RAM Error Injection Enable" "Disabled,Enabled"
|
|
group.quad spr:0x31F21++0x00
|
|
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
|
|
bitfld.quad 0x00 6. "SMPEN,Enable hardware management ofdata coherency with other processors in the multiprocessor" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
|
|
newline
|
|
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
|
|
group.quad spr:0x30101++0x0
|
|
line.quad 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)"
|
|
group.quad spr:0x34101++0x0
|
|
line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)"
|
|
bitfld.quad 0x00 6. "L2ACTLR,L2ACTLR write access control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5. "L2ECTLR,L2ECTLR write access control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 4. "L2CTLR,L2CTLR write access control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "CPUECTLR,CPUECTLR write access control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 0. "CPUACTLR,CPUACTLR write access control" "Disabled,Enabled"
|
|
group.quad spr:0x36101++0x0
|
|
line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)"
|
|
bitfld.quad 0x00 6. "L2ACTLR,L2ACTLR write access control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5. "L2ECTLR,L2ECTLR write access control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 4. "L2CTLR,L2CTLR write access control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "CPUECTLR,CPUECTLR write access control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 0. "CPUACTLR,CPUACTLR write access control" "Disabled,Enabled"
|
|
group.quad spr:0x30102++0x00
|
|
line.quad 0x00 "CPACR_EL1,Architectural Feature Access Control Register"
|
|
bitfld.quad 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,Not trapped"
|
|
group.quad spr:0x36110++0x0
|
|
line.quad 0x00 "SCR_EL3,Secure Configuration Register"
|
|
bitfld.quad 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
|
|
bitfld.quad 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.quad 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled"
|
|
bitfld.quad 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64"
|
|
newline
|
|
bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
|
|
bitfld.quad 0x00 8. "HCE,Hypervisor Call enable" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes"
|
|
bitfld.quad 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
|
|
newline
|
|
bitfld.quad 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
|
|
bitfld.quad 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
|
|
newline
|
|
bitfld.quad 0x00 0. "NS,Secure mode " "Secure,Non-secure"
|
|
group.quad spr:0x34110++0x00
|
|
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
|
|
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
|
|
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
|
|
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
|
|
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
|
|
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
|
|
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
|
|
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
|
|
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
|
|
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
|
|
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
|
|
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
|
|
newline
|
|
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
|
|
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort" "Not pending,Pending"
|
|
newline
|
|
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
|
|
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
|
|
newline
|
|
bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled"
|
|
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
|
|
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
|
|
group.quad spr:0x30510++0x00
|
|
line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Registers 0 (EL1)"
|
|
group.quad spr:0x30511++0x00
|
|
line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Registers 1 (EL1)"
|
|
group.quad spr:0x34510++0x00
|
|
line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Registers 0 (EL2)"
|
|
group.quad spr:0x34511++0x00
|
|
line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Registers 1 (EL2)"
|
|
group.quad spr:0x36510++0x00
|
|
line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Registers 0 (EL3)"
|
|
group.quad spr:0x36511++0x00
|
|
line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Registers 1 (EL3)"
|
|
tree.open "Exception Syndrome Registers"
|
|
if (((per.q(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
elif (((per.q(spr:0x30520))&0xFC000000)==0x04000000)
|
|
if (((per.q(spr:0x30520))&0x1000000)==0x1000000)
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
|
|
else
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
|
|
endif
|
|
elif (((per.q(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
|
|
if (((per.q(spr:0x30520))&0x1000000)==0x1000000)
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
else
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
endif
|
|
elif (((per.q(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
|
|
if (((per.q(spr:0x30520))&0x1000000)==0x1000000)
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
else
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
endif
|
|
elif (((per.q(spr:0x30520))&0xFC000000)==0x18000000)
|
|
if (((per.q(spr:0x30520))&0x1000000)==0x1000000)
|
|
if (((per.q(spr:0x30520))&0x08)==0x08)
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
newline
|
|
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
else
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x30520))&0x08)==0x08)
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
newline
|
|
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
else
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
endif
|
|
endif
|
|
elif (((per.q(spr:0x30520))&0xFC000000)==0x1C000000)
|
|
if (((per.q(spr:0x30520))&0x1000000)==0x1000000)
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
else
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
endif
|
|
elif (((per.q(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
|
|
elif (((per.q(spr:0x30520))&0xFC000000)==0x60000000)
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3"
|
|
bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
elif (((per.q(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
|
|
newline
|
|
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
|
|
elif (((per.q(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
|
|
if (((per.q(spr:0x30520))&0x3F)==0x10)
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
|
|
newline
|
|
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
|
|
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
|
|
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..."
|
|
else
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
|
|
newline
|
|
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
|
|
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
|
|
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..."
|
|
endif
|
|
elif (((per.q(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
|
|
if (((per.q(spr:0x30520))&0x3F)==0x10)
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..."
|
|
else
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..."
|
|
endif
|
|
elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
|
|
elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
|
|
elif (((per.q(spr:0x30520))&0xFD000000)==0xBD000000)
|
|
if (((per.q(spr:0x30520))&0x3F)==0x11)
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized"
|
|
newline
|
|
bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..."
|
|
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
|
|
else
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
|
|
endif
|
|
elif (((per.q(spr:0x30520))&0xFD000000)==0xBC000000)
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
elif (((per.q(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
elif (((per.q(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
elif (((per.q(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
elif (((per.q(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
|
|
else
|
|
group.quad spr:0x30520++0x00
|
|
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
endif
|
|
if (((per.q(spr:0x34520))&0xFC000000)==(0x00000000||0x24000000||0x38000000||0x88000000||0x98000000))
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==0x04000000)
|
|
if (((per.q(spr:0x34520))&0x1000000)==0x1000000)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
|
|
else
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
|
|
endif
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
|
|
if (((per.q(spr:0x34520))&0x1000000)==0x1000000)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
else
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
endif
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
|
|
if (((per.q(spr:0x34520))&0x1000000)==0x1000000)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
else
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
endif
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==0x18000000)
|
|
if (((per.q(spr:0x34520))&0x1000000)==0x1000000)
|
|
if (((per.q(spr:0x34520))&0x08)==0x08)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
newline
|
|
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
else
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x34520))&0x08)==0x08)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
newline
|
|
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
else
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
endif
|
|
endif
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==0x1C000000)
|
|
if (((per.q(spr:0x34520))&0x1000000)==0x1000000)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
else
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
endif
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000||0x5C000000))
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==0x4C000000)
|
|
if ((((per.q(spr:0x34520))&0x1000000)==0x1000000)&&(((per.q(spr:0x34520))&0xF0000)==0x80000))
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
|
|
elif (((per.q(spr:0x34520))&0xF0000)==0x80000)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
|
|
else
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
|
|
endif
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==0x60000000)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3"
|
|
bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==0x68000000)
|
|
if (((per.q(spr:0x34520))&0x02)==0x02)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 1. "ERET,Indicates whether an ERET or ERETA* instruction was trapped to EL2" "ERET,ERETA*"
|
|
bitfld.quad 0x00 0. "ERETA,Indicates whether an ERETAA or ERETAB instruction was trapped to EL2" "ERETAA,ERETAB"
|
|
else
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 1. "ERET,Indicates whether an ERET or ERETA* instruction was trapped to EL2" "ERET,ERETA*"
|
|
endif
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
|
|
newline
|
|
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
|
|
elif (((per.q(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
|
|
if (((per.q(spr:0x34520))&0x3F)==0x10)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
|
|
newline
|
|
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
|
|
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
|
|
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..."
|
|
else
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
|
|
newline
|
|
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
|
|
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
|
|
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..."
|
|
endif
|
|
elif (((per.q(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
|
|
if (((per.q(spr:0x34520))&0x3F)==0x10)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..."
|
|
else
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..."
|
|
endif
|
|
elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
|
|
elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
|
|
elif (((per.q(spr:0x34520))&0xFD000000)==0xBD000000)
|
|
if (((per.q(spr:0x34520))&0x3F)==0x11)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized"
|
|
newline
|
|
bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..."
|
|
newline
|
|
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
|
|
else
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
|
|
endif
|
|
elif (((per.q(spr:0x34520))&0xFD000000)==0xBC000000)
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
elif (((per.q(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
|
|
else
|
|
group.quad spr:0x34520++0x00
|
|
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,ERET/ERETAA/ERETAB,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
|
|
endif
|
|
if (((per.q(spr:0x36520))&0xFC000000)==(0x00000000||0x24000000||0x38000000||0x88000000||0x98000000))
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
elif (((per.q(spr:0x36520))&0xFC000000)==0x04000000)
|
|
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
|
|
else
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
|
|
endif
|
|
elif (((per.q(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
|
|
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
else
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
endif
|
|
elif (((per.q(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
|
|
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
else
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
endif
|
|
elif (((per.q(spr:0x36520))&0xFC000000)==0x18000000)
|
|
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
|
|
if (((per.q(spr:0x36520))&0x08)==0x08)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
newline
|
|
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
else
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x36520))&0x08)==0x08)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
newline
|
|
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
else
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
endif
|
|
endif
|
|
elif (((per.q(spr:0x36520))&0xFC000000)==0x1C000000)
|
|
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
else
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
endif
|
|
elif (((per.q(spr:0x36520))&0xFC000000)==0x4C000000)
|
|
if ((((per.q(spr:0x36520))&0x1000000)==0x1000000)&&(((per.q(spr:0x36520))&0xF0000)==0x80000))
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
newline
|
|
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
|
|
elif (((per.q(spr:0x36520))&0xF0000)==0x80000)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
|
|
else
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL2)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
|
|
endif
|
|
elif (((per.q(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000||0x5C000000))
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
|
|
elif (((per.q(spr:0x36520))&0xFC000000)==0x60000000)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3"
|
|
bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
|
|
elif (((per.q(spr:0x36520))&0xFC000000)==0x7C000000)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
hexmask.quad.long 0x00 0.--24. 1. "IMPL_DEF,Implementation defined"
|
|
elif (((per.q(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE"
|
|
newline
|
|
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
|
|
elif (((per.q(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
|
|
if (((per.q(spr:0x36520))&0x3F)==0x10)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
|
|
newline
|
|
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
|
|
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
|
|
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..."
|
|
else
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
|
|
newline
|
|
bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
|
|
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
|
|
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..."
|
|
endif
|
|
elif (((per.q(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
|
|
if (((per.q(spr:0x36520))&0x3F)==0x10)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..."
|
|
else
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
|
|
newline
|
|
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
|
|
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,?..."
|
|
endif
|
|
elif (((per.q(spr:0x36520))&0xFC800000)==0xB0800000)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
|
|
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
|
|
elif (((per.q(spr:0x36520))&0xFC800000)==0xB0000000)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
|
|
elif (((per.q(spr:0x36520))&0xFD000000)==0xBD000000)
|
|
if (((per.q(spr:0x36520))&0x3F)==0x11)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized"
|
|
newline
|
|
bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..."
|
|
newline
|
|
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
|
|
else
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 9. "EA,External abort type" "No,Yes"
|
|
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
|
|
endif
|
|
elif (((per.q(spr:0x36520))&0xFD000000)==0xBC000000)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
|
|
elif (((per.q(spr:0x36520))&0xFC000000)==0xF0000000)
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
|
|
newline
|
|
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
|
|
else
|
|
group.quad spr:0x36520++0x00
|
|
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
|
|
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Pointer Authentication,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
|
|
endif
|
|
tree.end
|
|
newline
|
|
if (((per.q(spr:0x34501))&0x200)==0x200)
|
|
group.quad spr:0x34501++0x00
|
|
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
|
|
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
|
|
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/L1,Sync. parity/on memory access/on TTW/L2,Sync. parity/on memory access/on TTW/L3,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
|
|
else
|
|
group.quad spr:0x34501++0x00
|
|
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
|
|
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
|
|
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
|
|
newline
|
|
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/L1,Permission/section,Sync. external/on TTW/L2,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/L1,Reserved,Sync. parity/on TTW/L2,?..."
|
|
endif
|
|
group.quad spr:0x30600++0x00
|
|
line.quad 0x00 "FAR_EL1,Fault Address Register (EL1)"
|
|
group.quad spr:0x34600++0x00
|
|
line.quad 0x00 "FAR_EL2,Fault Address Register (EL2)"
|
|
group.quad spr:0x36600++0x00
|
|
line.quad 0x00 "FAR_EL3,Fault Address Register (EL3)"
|
|
group.quad spr:0x34604++0x00
|
|
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
|
|
hexmask.quad 0x00 4.--39. 0x10 "FIPA[47:12],Bits [47:12] of the faulting intermediate physical address"
|
|
group.quad spr:0x30C00++0x00
|
|
line.quad 0x00 "VBAR_EL1,Vector Base Address Register (EL1)"
|
|
hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level"
|
|
group.quad spr:0x34C00++0x00
|
|
line.quad 0x00 "VBAR_EL2,Vector Base Address Register (EL2)"
|
|
hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level"
|
|
group.quad spr:0x36C00++0x00
|
|
line.quad 0x00 "VBAR_EL3,Vector Base Address Register (EL3)"
|
|
hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level"
|
|
rgroup.quad spr:0x36C01++0x00
|
|
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
|
|
group.quad spr:0x36C02++0x00
|
|
line.quad 0x00 "RMR_EL3,Reset Management Register"
|
|
bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested"
|
|
bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64"
|
|
rgroup.quad spr:0x30C10++0x00
|
|
line.quad 0x00 "ISR_EL1,Interrupt Status Register"
|
|
bitfld.quad 0x00 8. "A,External abort pending flag" "Not pending,Pending"
|
|
bitfld.quad 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
|
|
bitfld.quad 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
|
|
rgroup.quad spr:0x31F30++0x00
|
|
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register"
|
|
hexmask.quad.tbyte 0x00 18.--39. 0x4 "PERIPHBASE[39:18],Holds the physical base address of the memory-mapped GIC CPU interface registers"
|
|
group.quad spr:0x30D01++0x00
|
|
line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register"
|
|
group.quad spr:0x33D02++0x00
|
|
line.quad 0x00 "TPIDR_EL0,Software Thread ID Register (EL0)"
|
|
group.quad spr:0x33D03++0x00
|
|
line.quad 0x00 "TPIDRRO_EL0,Read-Only Software Thread ID Register (EL0)"
|
|
group.quad spr:0x30D04++0x00
|
|
line.quad 0x00 "TPIDR_EL1,Software Thread ID Register (EL1)"
|
|
group.quad spr:0x34D02++0x00
|
|
line.quad 0x00 "TPIDR_EL2,Software Thread ID Register (EL2)"
|
|
group.quad spr:0x36D02++0x00
|
|
line.quad 0x00 "TPIDR_EL3,Software Thread ID Register (EL3)"
|
|
tree.end
|
|
tree "System Instructions"
|
|
wgroup.quad spr:0x10710++0x00
|
|
line.quad 0x00 "IC_IALLUIS,IC_IALLUIS"
|
|
wgroup.quad spr:0x10750++0x00
|
|
line.quad 0x00 "IC_IALLU,IC_IALLU"
|
|
wgroup.quad spr:0x13751++0x00
|
|
line.quad 0x00 "IC_IVAU,IC_IVAU"
|
|
wgroup.quad spr:0x13741++0x00
|
|
line.quad 0x00 "DC_ZVA,DC_ZVA"
|
|
wgroup.quad spr:0x10761++0x00
|
|
line.quad 0x00 "DC_IVAC,DC_IVAC"
|
|
wgroup.quad spr:0x10762++0x00
|
|
line.quad 0x00 "DC_ISW,DC_ISW"
|
|
wgroup.quad spr:0x137A1++0x00
|
|
line.quad 0x00 "DC_CVAC,DC_CVAC"
|
|
wgroup.quad spr:0x107A2++0x00
|
|
line.quad 0x00 "DC_CSW,DC_CSW"
|
|
wgroup.quad spr:0x137B1++0x00
|
|
line.quad 0x00 "DC_CVAU,DC_CVAU"
|
|
wgroup.quad spr:0x137E1++0x00
|
|
line.quad 0x00 "DC_CIVAC,DC_CIVAC"
|
|
wgroup.quad spr:0x107E2++0x00
|
|
line.quad 0x00 "DC_CISW,DC_CISW"
|
|
wgroup.quad spr:0x10780++0x00
|
|
line.quad 0x00 "AT_S1E1R,AT_S1E1R"
|
|
wgroup.quad spr:0x10781++0x00
|
|
line.quad 0x00 "AT_S1E1W,AT_S1E1W"
|
|
wgroup.quad spr:0x10782++0x00
|
|
line.quad 0x00 "AT_S1E0R,AT_S1E0R"
|
|
wgroup.quad spr:0x10783++0x00
|
|
line.quad 0x00 "AT_S1E0W,AT_S1E0W"
|
|
wgroup.quad spr:0x14784++0x00
|
|
line.quad 0x00 "AT_S12E1R,AT_S12E1R"
|
|
wgroup.quad spr:0x14785++0x00
|
|
line.quad 0x00 "AT_S12E1W,AT_S12E1W"
|
|
wgroup.quad spr:0x14786++0x00
|
|
line.quad 0x00 "AT_S12E0R,AT_S12E0R"
|
|
wgroup.quad spr:0x14787++0x00
|
|
line.quad 0x00 "AT_S12E0W,AT_S12E0W"
|
|
wgroup.quad spr:0x14780++0x00
|
|
line.quad 0x00 "AT_S1E2R,AT_S1E2R"
|
|
wgroup.quad spr:0x14781++0x00
|
|
line.quad 0x00 "AT_S1E2W,AT_S1E2W"
|
|
wgroup.quad spr:0x16780++0x00
|
|
line.quad 0x00 "AT_S1E3R,AT_S1E3R"
|
|
wgroup.quad spr:0x16781++0x00
|
|
line.quad 0x00 "AT_S1E3W,AT_S1E3W"
|
|
wgroup.quad spr:0x10870++0x00
|
|
line.quad 0x00 "TLBI_VMALLE1,TLBI_VMALLE1"
|
|
wgroup.quad spr:0x10871++0x00
|
|
line.quad 0x00 "TLBI_VAE1,TLBI_VAE1"
|
|
wgroup.quad spr:0x10872++0x00
|
|
line.quad 0x00 "TLBI_ASIDE1,TLBI_ASIDE1"
|
|
wgroup.quad spr:0x10873++0x00
|
|
line.quad 0x00 "TLBI_VAAE1,TLBI_VAAE1"
|
|
wgroup.quad spr:0x10875++0x00
|
|
line.quad 0x00 "TLBI_VALE1,TLBI_VALE1"
|
|
wgroup.quad spr:0x10877++0x00
|
|
line.quad 0x00 "TLBI_VAALE1,TLBI_VAALE1"
|
|
wgroup.quad spr:0x10830++0x00
|
|
line.quad 0x00 "TLBI_VMALLE1IS,TLBI_VMALLE1IS"
|
|
wgroup.quad spr:0x10831++0x00
|
|
line.quad 0x00 "TLBI_VAE1IS,TLBI_VAE1IS"
|
|
wgroup.quad spr:0x10832++0x00
|
|
line.quad 0x00 "TLBI_ASIDE1IS,TLBI_ASIDE1IS"
|
|
wgroup.quad spr:0x10833++0x00
|
|
line.quad 0x00 "TLBI_VAAE1IS,TLBI_VAAE1IS"
|
|
wgroup.quad spr:0x10835++0x00
|
|
line.quad 0x00 "TLBI_VALE1IS,TLBI_VALE1IS"
|
|
wgroup.quad spr:0x10837++0x00
|
|
line.quad 0x00 "TLBI_VAALE1IS,TLBI_VAALE1IS"
|
|
wgroup.quad spr:0x14801++0x00
|
|
line.quad 0x00 "TLBI_IPAS2E1IS,TLBI_IPAS2E1IS"
|
|
wgroup.quad spr:0x14805++0x00
|
|
line.quad 0x00 "TLBI_IPAS2LE1IS,TLBI_IPAS2LE1IS"
|
|
wgroup.quad spr:0x14841++0x00
|
|
line.quad 0x00 "TLBI_IPAS2E1,TLBI_IPAS2E1"
|
|
wgroup.quad spr:0x14845++0x00
|
|
line.quad 0x00 "TLBI_IPAS2LE1,TLBI_IPAS2LE1"
|
|
wgroup.quad spr:0x14871++0x00
|
|
line.quad 0x00 "TLBI_VAE2,TLBI_VAE2"
|
|
wgroup.quad spr:0x14875++0x00
|
|
line.quad 0x00 "TLBI_VALE2,TLBI_VALE2"
|
|
wgroup.quad spr:0x14876++0x00
|
|
line.quad 0x00 "TLBI_VMALLS12E1,TLBI_VMALLS12E1"
|
|
wgroup.quad spr:0x14831++0x00
|
|
line.quad 0x00 "TLBI_VAE2IS,TLBI_VAE2IS"
|
|
wgroup.quad spr:0x14835++0x00
|
|
line.quad 0x00 "TLBI_VALE2IS,TLBI_VALE2IS"
|
|
wgroup.quad spr:0x14836++0x00
|
|
line.quad 0x00 "TLBI_VMALLS12E1IS,TLBI_VMALLS12E1IS"
|
|
wgroup.quad spr:0x16871++0x00
|
|
line.quad 0x00 "TLBI_VAE3,TLBI_VAE3"
|
|
wgroup.quad spr:0x16875++0x00
|
|
line.quad 0x00 "TLBI_VALE3,TLBI_VALE3"
|
|
wgroup.quad spr:0x16831++0x00
|
|
line.quad 0x00 "TLBI_VAE3IS,TLBI_VAE3IS"
|
|
wgroup.quad spr:0x16835++0x00
|
|
line.quad 0x00 "TLBI_VALE3IS,TLBI_VALE3IS"
|
|
wgroup.quad spr:0x14870++0x00
|
|
line.quad 0x00 "TLBI_ALLE2,TLBI_ALLE2"
|
|
wgroup.quad spr:0x14830++0x00
|
|
line.quad 0x00 "TLBI_ALLE2IS,TLBI_ALLE2IS"
|
|
wgroup.quad spr:0x14874++0x00
|
|
line.quad 0x00 "TLBI_ALLE1,TLBI_ALLE1"
|
|
wgroup.quad spr:0x14834++0x00
|
|
line.quad 0x00 "TLBI_ALLE1IS,TLBI_ALLE1IS"
|
|
wgroup.quad spr:0x16870++0x00
|
|
line.quad 0x00 "TLBI_ALLE3,TLBI_ALLE3"
|
|
wgroup.quad spr:0x16830++0x00
|
|
line.quad 0x00 "TLBI_ALLE3IS,TLBI_ALLE3IS"
|
|
tree.end
|
|
tree "Memory Management Unit"
|
|
group.quad spr:0x30100++0x0
|
|
line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)"
|
|
bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
|
|
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
|
|
newline
|
|
bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
|
|
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
newline
|
|
bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes"
|
|
bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
|
|
bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes"
|
|
bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
|
|
group.quad spr:0x34100++0x0
|
|
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
|
|
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
|
|
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
newline
|
|
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
|
|
group.quad spr:0x36100++0x0
|
|
line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)"
|
|
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
|
|
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
newline
|
|
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
|
|
group.quad spr:0x30200++0x00
|
|
line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)"
|
|
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
|
|
hexmask.quad 0x00 0.--47. 0x01 "BADDR,Translation table base address"
|
|
group.quad spr:0x30201++0x00
|
|
line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)"
|
|
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
|
|
hexmask.quad 0x00 0.--47. 0x01 "BADDR,Translation table base address"
|
|
group.quad spr:0x34200++0x00
|
|
line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)"
|
|
hexmask.quad 0x00 1.--47. 0x02 "BADDR,Translation table base address"
|
|
group.quad spr:0x36200++0x00
|
|
line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)"
|
|
hexmask.quad 0x00 0.--47. 0x01 "BADDR,Translation table base address"
|
|
group.quad spr:0x30202++0x00
|
|
line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)"
|
|
bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored"
|
|
bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit"
|
|
bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
|
|
newline
|
|
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,16 KB,4 KB,64 KB"
|
|
bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
newline
|
|
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled"
|
|
bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1"
|
|
newline
|
|
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB,16 KB,?..."
|
|
newline
|
|
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.quad 0x00 7. "EPD0,Translation table walk disable for translations using TTBR0" "Enabled,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.quad spr:0x34202++0x00
|
|
line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)"
|
|
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
|
|
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,16 KB,?..."
|
|
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
newline
|
|
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.quad spr:0x36202++0x00
|
|
line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)"
|
|
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
|
|
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,16 KB,?..."
|
|
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
newline
|
|
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.quad spr:0x34300++0x00
|
|
line.quad 0x00 "DACR32_EL2,Domain Access Control Register"
|
|
bitfld.quad 0x00 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.quad 0x00 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.quad 0x00 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
bitfld.quad 0x00 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.quad 0x00 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.quad 0x00 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.quad 0x00 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.quad 0x00 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
bitfld.quad 0x00 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.quad 0x00 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.quad 0x00 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.quad 0x00 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.quad 0x00 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.quad 0x00 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
bitfld.quad 0x00 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000)
|
|
group.quad spr:0x30740++0x00
|
|
line.quad 0x00 "PAR_EL1,Physical Address Register"
|
|
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
|
|
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-not nGnRnE,?..."
|
|
newline
|
|
hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address"
|
|
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
newline
|
|
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
|
|
elif (((per.q(spr:0x30740))&0x01)==0x00)
|
|
group.quad spr:0x30740++0x00
|
|
line.quad 0x00 "PAR_EL1,Physical Address Register"
|
|
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
|
|
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
|
|
newline
|
|
hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address"
|
|
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
newline
|
|
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
|
|
else
|
|
group.quad spr:0x30740++0x00
|
|
line.quad 0x00 "PAR_EL1,Physical Address Register"
|
|
newline
|
|
bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
|
|
bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Reserved,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
|
|
endif
|
|
tree.open "Memory Attribute Indirection Registers"
|
|
group.quad spr:0x30A20++0x00
|
|
line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register"
|
|
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
group.quad spr:0x34A20++0x00
|
|
line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register"
|
|
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
group.quad spr:0x36A20++0x00
|
|
line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register"
|
|
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
newline
|
|
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient/RW no allocate,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient/RW no allocate,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
|
|
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
|
|
group.quad spr:0x30A30++0x00
|
|
line.quad 0x00 "AMAIR_EL1,Memory Attribute Indirection Register (EL1)"
|
|
group.quad spr:0x34A30++0x00
|
|
line.quad 0x00 "AMAIR_EL2,Memory Attribute Indirection Register (EL2)"
|
|
group.quad spr:0x36A30++0x00
|
|
line.quad 0x00 "AMAIR_EL3,Memory Attribute Indirection Register (EL3)"
|
|
tree.end
|
|
newline
|
|
group.quad spr:0x30D01++0x00
|
|
line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register"
|
|
tree.end
|
|
tree "Virtualization Extensions"
|
|
group.quad spr:0x34100++0x0
|
|
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
|
|
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
|
|
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
|
|
group.quad spr:0x34110++0x00
|
|
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
|
|
bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes"
|
|
bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes"
|
|
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,AArch64"
|
|
newline
|
|
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
|
|
bitfld.quad 0x00 28. "TDZ,Traps DC ZVA instruction" "Disabled,Enabled"
|
|
bitfld.quad 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
|
|
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
|
|
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
|
|
bitfld.quad 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
|
|
bitfld.quad 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
|
|
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
|
|
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
|
|
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
|
|
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
|
|
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
|
|
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "No effect,Inner Shareable,Outer Shareable,Full system"
|
|
bitfld.quad 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
|
|
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort" "Not aborted,Aborted"
|
|
newline
|
|
bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed"
|
|
newline
|
|
bitfld.quad 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed"
|
|
bitfld.quad 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed"
|
|
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
|
|
bitfld.quad 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
|
|
group.quad spr:0x34111++0x00
|
|
line.quad 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)"
|
|
bitfld.quad 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
|
|
bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
|
|
bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
|
|
newline
|
|
bitfld.quad 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
|
|
bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
|
|
newline
|
|
bitfld.quad 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
|
|
bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6"
|
|
group.quad spr:0x34112++0x00
|
|
line.quad 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)"
|
|
bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
|
|
bitfld.quad 0x00 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
|
|
group.quad spr:0x36131++0x00
|
|
line.quad 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)"
|
|
bitfld.quad 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
|
|
bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
|
|
bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes"
|
|
bitfld.quad 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
|
|
bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
|
|
newline
|
|
bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
|
|
bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
|
|
group.quad spr:0x36112++0x00
|
|
line.quad 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)"
|
|
bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
|
|
bitfld.quad 0x00 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
|
|
group.quad spr:0x34113++0x00
|
|
line.quad 0x00 "HSTR_EL2,Hypervisor System Trap Register"
|
|
bitfld.quad 0x00 16. "TTEE,Trap ThumbEE" "Not supported,?..."
|
|
bitfld.quad 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped"
|
|
bitfld.quad 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped"
|
|
newline
|
|
bitfld.quad 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped"
|
|
bitfld.quad 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped"
|
|
bitfld.quad 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped"
|
|
newline
|
|
bitfld.quad 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped"
|
|
bitfld.quad 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped"
|
|
bitfld.quad 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped"
|
|
newline
|
|
bitfld.quad 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped"
|
|
bitfld.quad 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped"
|
|
bitfld.quad 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped"
|
|
newline
|
|
bitfld.quad 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped"
|
|
bitfld.quad 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped"
|
|
bitfld.quad 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped"
|
|
group.quad spr:0x34117++0x00
|
|
line.quad 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register"
|
|
group.quad spr:0x34210++0x00
|
|
line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register"
|
|
hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table"
|
|
hexmask.quad 0x00 1.--47. 1. "BADDR,Translation table base address"
|
|
group.quad spr:0x34212++0x00
|
|
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
|
|
bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,?..."
|
|
bitfld.quad 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,16 KB,?..."
|
|
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
newline
|
|
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
|
|
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
|
|
bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
|
|
newline
|
|
bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.quad spr:0x34604++0x00
|
|
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
|
|
hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting IPA bits"
|
|
tree.end
|
|
tree "Cache Control and Configuration"
|
|
rgroup.quad spr:0x33001++0x0
|
|
line.quad 0x00 "CTR_EL0,Cache Type Register"
|
|
bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "L1IP,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
|
|
bitfld.quad 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
group.quad spr:0x32000++0x0
|
|
line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register"
|
|
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
|
|
bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
|
|
rgroup.quad spr:0x31000++0x0
|
|
line.quad 0x00 "CCSIDR_EL1,Current Cache Size ID Register"
|
|
bitfld.quad 0x00 31. "WT,Write-Through" "Not Supported,?..."
|
|
bitfld.quad 0x00 30. "WB,Write-Back" "Not Supported,Supported"
|
|
bitfld.quad 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
|
|
newline
|
|
bitfld.quad 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
|
|
hexmask.quad.word 0x00 13.--27. 1. 1. "NUMSETS,Number of Sets"
|
|
hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOCIATIVITY,Associativity"
|
|
newline
|
|
bitfld.quad 0x00 0.--2. "LINESIZE,Line Size" "Reserved,Reserved,16 words,?..."
|
|
rgroup.quad spr:0x31001++0x0
|
|
line.quad 0x00 "CLIDR_EL1,Cache Level ID Register"
|
|
bitfld.quad 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..."
|
|
bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,L1 cache,?..."
|
|
bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,No L2 cache,L2 cache,?..."
|
|
newline
|
|
bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Reserved,L2 cache,?..."
|
|
bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
|
|
bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
|
|
newline
|
|
bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate,?..."
|
|
tree "Level 1 memory system"
|
|
rgroup.quad spr:0x33F00++0x00
|
|
line.quad 0x00 "CDBGDR0_EL3,Cache Debug Data Register 0"
|
|
rgroup.quad spr:0x33F01++0x00
|
|
line.quad 0x00 "CDBGDR1_EL3,Cache Debug Data Register 1"
|
|
rgroup.quad spr:0x33F02++0x00
|
|
line.quad 0x00 "CDBGDR2_EL3,Cache Debug Data Register 2"
|
|
rgroup.quad spr:0x33F03++0x00
|
|
line.quad 0x00 "CDBGDR3_EL3,Cache Debug Data Register 3"
|
|
wgroup.quad spr:0x33F20++0x00
|
|
line.quad 0x00 "CDBGDCT_EL3,Data Cache Tag Read Operation Register"
|
|
wgroup.quad spr:0x33F21++0x00
|
|
line.quad 0x00 "CDBGICT_EL3,Instruction Cache Tag Read Operation Register"
|
|
wgroup.quad spr:0x33F40++0x00
|
|
line.quad 0x00 "CDBGDCD_EL3,Data Cache Data Read Operation Register"
|
|
wgroup.quad spr:0x33F41++0x00
|
|
line.quad 0x00 "CDBGICD_EL3,Instruction Cache Data Read Operation Register"
|
|
wgroup.quad spr:0x33F42++0x00
|
|
line.quad 0x00 "CDBGTD_EL3,TLB Data Read Operation Register"
|
|
if (((per.q(spr:0x31F22))&0x7F000000)==0x000000000)
|
|
group.quad spr:0x31F22++0x00
|
|
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
newline
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Way 0,Way 1,?..."
|
|
newline
|
|
hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address"
|
|
elif (((per.q(spr:0x31F22))&0x7F000000)==0x01000000)
|
|
group.quad spr:0x31F22++0x00
|
|
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
newline
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Bank 0,Bank 1,?..."
|
|
newline
|
|
hexmask.quad.word 0x00 0.--11. 0x01 "RAMADDR,RAM address"
|
|
elif (((per.q(spr:0x31F22))&0x7F000000)==0x08000000)
|
|
group.quad spr:0x31F22++0x00
|
|
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
newline
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Way 0,Way 1,Way 2,Way 3,?..."
|
|
newline
|
|
hexmask.quad.word 0x00 0.--11. 0x01 "RAMADDR,RAM address"
|
|
elif (((per.q(spr:0x31F22))&0x7F000000)==0x09000000)
|
|
group.quad spr:0x31F22++0x00
|
|
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
newline
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7"
|
|
newline
|
|
hexmask.quad.word 0x00 0.--11. 0x01 "RAMADDR,RAM address"
|
|
elif (((per.q(spr:0x31F22))&0x7F000000)==0x0A000000)
|
|
group.quad spr:0x31F22++0x00
|
|
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
newline
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Dirty RAM,?..."
|
|
newline
|
|
hexmask.quad.word 0x00 0.--11. 0x01 "RAMADDR,RAM address"
|
|
elif (((per.q(spr:0x31F22))&0x7F000000)==0x18000000)
|
|
group.quad spr:0x31F22++0x00
|
|
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
newline
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Way 0,Way 1,?..."
|
|
newline
|
|
hexmask.quad.word 0x00 0.--11. 0x01 "RAMADDR,RAM address"
|
|
else
|
|
group.quad spr:0x31F22++0x00
|
|
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register EL1"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
newline
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
hexmask.quad.word 0x00 0.--11. 0x01 "RAMADDR,RAM address"
|
|
endif
|
|
tree.end
|
|
tree "Level 2 memory system"
|
|
group.quad spr:0x31B02++0x0
|
|
line.quad 0x00 "L2CTLR_EL1,L2 Control Register"
|
|
bitfld.quad 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
|
|
bitfld.quad 0x00 22. "CPUCP,CPU Cache Protection" "Not implemented,ECC implemented"
|
|
bitfld.quad 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Not implemented,ECC implemented"
|
|
newline
|
|
bitfld.quad 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycles"
|
|
bitfld.quad 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles"
|
|
group.quad spr:0x31B03++0x0
|
|
line.quad 0x00 "L2ECTLR_EL1,L2 Extended Control Register"
|
|
bitfld.quad 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
|
|
bitfld.quad 0x00 29. "AACASYNCERR,AXI/ACE/CHI asynchronous error" "No error,Error"
|
|
bitfld.quad 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
|
|
group.quad spr:0x31F00++0x00
|
|
line.quad 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register"
|
|
bitfld.quad 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3"
|
|
bitfld.quad 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
|
|
if (((per.q(spr:0x31F23))&0x7F000000)==0x10000000)
|
|
group.quad spr:0x31F23++0x00
|
|
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
newline
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--21. "C/W,Indicates the RAM where the first memory error occurred" "Way 0,Way 1,Way 2,Way 3,Way 4,Way 5,Way 6,Way 7,?..."
|
|
newline
|
|
hexmask.quad.word 0x00 3.--16. 1. "IND,Index"
|
|
elif (((per.q(spr:0x31F23))&0x7F000000)==0x11000000)
|
|
group.quad spr:0x31F23++0x00
|
|
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
newline
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--21. "C/W,Indicates the RAM where the first memory error occurred" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7,?..."
|
|
newline
|
|
hexmask.quad.word 0x00 3.--16. 1. "IND,Index"
|
|
elif (((per.q(spr:0x31F23))&0x7F000000)==0x12000000)
|
|
group.quad spr:0x31F23++0x00
|
|
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
newline
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--21. "C/W,Indicates the RAM where the first memory error occurred" "CPU0/Way 0,CPU0/Way 1,CPU0/Way 2,CPU0/Way 3,CPU1/Way 0,CPU1/Way 1,CPU1/Way 2,CPU1/Way 3,CPU2/Way 0,CPU2/Way 1,CPU2/Way 2,CPU2/Way 3,CPU3/Way 0,CPU3/Way 1,CPU3/Way 2,CPU3/Way 3"
|
|
newline
|
|
hexmask.quad.word 0x00 3.--16. 1. "IND,Index"
|
|
else
|
|
group.quad spr:0x31F23++0x00
|
|
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
newline
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
hexmask.quad.word 0x00 3.--16. 1. "IND,Index"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "System Performance Monitor"
|
|
group.quad spr:0x339C0++0x00
|
|
line.quad 0x00 "PMCR_EL0,Performance Monitor Control Register"
|
|
rhexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code"
|
|
rhexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code"
|
|
rbitfld.quad 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
|
|
bitfld.quad 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
|
|
bitfld.quad 0x00 4. "X,Export Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
|
|
eventfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
|
|
newline
|
|
eventfld.quad 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
|
|
bitfld.quad 0x00 0. "E,All Counters enable" "Disabled,Enabled"
|
|
group.quad spr:0x339C1++0x00
|
|
line.quad 0x00 "PMCNTENSET_EL0,Count Enable Set Register "
|
|
bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
|
|
group.quad spr:0x339C2++0x00
|
|
line.quad 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register"
|
|
bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled"
|
|
group.quad spr:0x339C3++0x00
|
|
line.quad 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register"
|
|
eventfld.quad 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
|
|
eventfld.quad 0x00 5. "P5,Event Counter 5 overflow clear bit" "Disabled,Enabled"
|
|
eventfld.quad 0x00 4. "P4,Event Counter 4 overflow clear bit" "Disabled,Enabled"
|
|
eventfld.quad 0x00 3. "P3,Event Counter 3 overflow clear bit" "Disabled,Enabled"
|
|
newline
|
|
eventfld.quad 0x00 2. "P2,Event Counter 2 overflow clear bit" "Disabled,Enabled"
|
|
eventfld.quad 0x00 1. "P1,Event Counter 1 overflow clear bit" "Disabled,Enabled"
|
|
eventfld.quad 0x00 0. "P0,Event Counter 0 overflow clear bit" "Disabled,Enabled"
|
|
wgroup.quad spr:0x339C4++0x00
|
|
line.quad 0x00 "PMSWINC_EL0,Performance Monitor Software Increment"
|
|
bitfld.quad 0x00 5. "P5,Increment PMN5" "No action,Increment"
|
|
bitfld.quad 0x00 4. "P4,Increment PMN4" "No action,Increment"
|
|
bitfld.quad 0x00 3. "P3,Increment PMN3" "No action,Increment"
|
|
bitfld.quad 0x00 2. "P2,Increment PMN2" "No action,Increment"
|
|
newline
|
|
bitfld.quad 0x00 1. "P1,Increment PMN1" "No action,Increment"
|
|
bitfld.quad 0x00 0. "P0,Increment PMN0" "No action,Increment"
|
|
group.quad spr:0x339C5++0x00
|
|
line.quad 0x00 "PMSELR_EL0,Performance Monitor Select Register"
|
|
bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.open "Common Event Identification Registers"
|
|
rgroup.quad spr:0x339C6++0x00
|
|
line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register"
|
|
bitfld.quad 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,?..."
|
|
bitfld.quad 0x00 30. "CHAIN,Chain" "Reserved,Implemented"
|
|
bitfld.quad 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented"
|
|
newline
|
|
bitfld.quad 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Not implemented,?..."
|
|
bitfld.quad 0x00 27. "INST_SPEC,Instruction speculatively executed" "Reserved,Implemented"
|
|
bitfld.quad 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented"
|
|
newline
|
|
bitfld.quad 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented"
|
|
bitfld.quad 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Not implemented,Implemented"
|
|
bitfld.quad 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Not implemented,Implemented"
|
|
newline
|
|
bitfld.quad 0x00 22. "L2D_CACHE,Level 2 data cache access" "Not implemented,Implemented"
|
|
bitfld.quad 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Reserved,Implemented"
|
|
bitfld.quad 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Reserved,Implemented"
|
|
newline
|
|
bitfld.quad 0x00 19. "MEM_ACCESS,Data memory access" "Reserved,Implemented"
|
|
bitfld.quad 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Reserved,Implemented"
|
|
bitfld.quad 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented"
|
|
newline
|
|
bitfld.quad 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Reserved,Implemented"
|
|
bitfld.quad 0x00 15. "UNALIGNED_LDST_RETIRED,UNALIGNED_LDST_RETIRED" "Reserved,Implemented"
|
|
bitfld.quad 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,?..."
|
|
newline
|
|
bitfld.quad 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Reserved,Implemented"
|
|
bitfld.quad 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Reserved,Implemented"
|
|
bitfld.quad 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Reserved,Implemented"
|
|
newline
|
|
bitfld.quad 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Reserved,Implemented"
|
|
bitfld.quad 0x00 9. "EXC_TAKEN,Exception taken" "Reserved,Implemented"
|
|
bitfld.quad 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Reserved,Implemented"
|
|
newline
|
|
bitfld.quad 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Reserved,Implemented"
|
|
bitfld.quad 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Reserved,Implemented"
|
|
bitfld.quad 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Reserved,Implemented"
|
|
newline
|
|
bitfld.quad 0x00 4. "L1D_CACHE,Level 1 data cache access" "Reserved,Implemented"
|
|
bitfld.quad 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Reserved,Implemented"
|
|
bitfld.quad 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Reserved,Implemented"
|
|
newline
|
|
bitfld.quad 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Reserved,Implemented"
|
|
bitfld.quad 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Reserved,Implemented"
|
|
rgroup.quad spr:0x339C7++0x00
|
|
line.quad 0x00 "PMCEID1_EL0,Common Event Identification Register"
|
|
bitfld.quad 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,?..."
|
|
bitfld.quad 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Not implemented,?..."
|
|
bitfld.quad 0x00 14. "L2I_TLB_REFILL,Attributable Level 2 instruction TLB refill" "Not implemented,?..."
|
|
newline
|
|
bitfld.quad 0x00 13. "L2D_TLB_REFIL,Attributable Level 2 data or unified TLB refill" "Not implemented,?..."
|
|
bitfld.quad 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Not implemented,?..."
|
|
bitfld.quad 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,?..."
|
|
newline
|
|
bitfld.quad 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,?..."
|
|
bitfld.quad 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,?..."
|
|
bitfld.quad 0x00 8. "L2I_CACHE_REFILL,Attributable Level 2 instruction cache refill" "Not implemented,?..."
|
|
newline
|
|
bitfld.quad 0x00 7. "L2I_CACHE,Attributable Level 2 instruction cache access" "Not implemented,?..."
|
|
bitfld.quad 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Not implemented,?..."
|
|
bitfld.quad 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Not implemented,?..."
|
|
newline
|
|
bitfld.quad 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Not implemented,?..."
|
|
bitfld.quad 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,?..."
|
|
bitfld.quad 0x00 2. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Not implemented,?..."
|
|
newline
|
|
bitfld.quad 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,?..."
|
|
bitfld.quad 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocation without refill" "Not implemented,?..."
|
|
tree.end
|
|
newline
|
|
group.quad spr:0x339D0++0x00
|
|
line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register"
|
|
if (((per.q(spr:0x339C5))&0x1F)==0x1F)
|
|
group.quad spr:0x339D1++0x00
|
|
line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
|
|
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:0x339D1++0x00
|
|
line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
|
|
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
|
|
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
endif
|
|
group.quad spr:0x339D2++0x00
|
|
line.quad 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register"
|
|
group.quad spr:0x339E0++0x00
|
|
line.quad 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register"
|
|
bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
|
|
group.quad spr:0x309E1++0x00
|
|
line.quad 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set"
|
|
bitfld.quad 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.quad spr:0x309E2++0x00
|
|
line.quad 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear"
|
|
eventfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
|
|
eventfld.quad 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.quad 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.quad 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
newline
|
|
eventfld.quad 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.quad 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.quad 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
group.quad spr:0x339E3++0x00
|
|
line.quad 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register"
|
|
bitfld.quad 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.quad spr:0x33E80++0x00
|
|
line.quad 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0"
|
|
group.quad spr:(0x33E80+0x40)++0x00
|
|
line.quad 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0"
|
|
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
|
|
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
group.quad spr:0x33E81++0x00
|
|
line.quad 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1"
|
|
group.quad spr:(0x33E81+0x40)++0x00
|
|
line.quad 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1"
|
|
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
|
|
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
group.quad spr:0x33E82++0x00
|
|
line.quad 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2"
|
|
group.quad spr:(0x33E82+0x40)++0x00
|
|
line.quad 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2"
|
|
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
|
|
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
group.quad spr:0x33E83++0x00
|
|
line.quad 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3"
|
|
group.quad spr:(0x33E83+0x40)++0x00
|
|
line.quad 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3"
|
|
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
|
|
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
group.quad spr:0x33E84++0x00
|
|
line.quad 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4"
|
|
group.quad spr:(0x33E84+0x40)++0x00
|
|
line.quad 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4"
|
|
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
|
|
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
group.quad spr:0x33E85++0x00
|
|
line.quad 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5"
|
|
group.quad spr:(0x33E85+0x40)++0x00
|
|
line.quad 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5"
|
|
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
|
|
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
group.quad spr:0x33EF7++0x00
|
|
line.quad 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register"
|
|
bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "System Timer Registers"
|
|
group.quad spr:0x33E00++0x00
|
|
line.quad 0x00 "CNTFRQ_EL0,Counter-timer Frequency Register"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CF,Clock frequency"
|
|
rgroup.quad spr:0x33E01++0x00
|
|
line.quad 0x00 "CNTPCT_EL0,Counter-timer Physical Count Register"
|
|
rgroup.quad spr:0x33E02++0x00
|
|
line.quad 0x00 "CNTVCT_EL0,Counter-timer Virtual Count Register"
|
|
group.quad spr:0x34E03++0x00
|
|
line.quad 0x00 "CNTVOFF_EL2,Counter-timer Virtual Offset Register"
|
|
group.quad spr:0x30E10++0x00
|
|
line.quad 0x00 "CNTKCTL_EL1,Counter-timer Kernel Control Register"
|
|
bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled"
|
|
bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled"
|
|
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI generates an event when the event stream is enabled" "0 to 1,1 to 0"
|
|
newline
|
|
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter CNTVCT and the frequency Register CNTFRQ are accessible from EL0 mode" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter CNTPCT and the frequency Register CNTFRQ are accessible from EL0 mode" "Disabled,Enabled"
|
|
group.quad spr:0x34E10++0x00
|
|
line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control Register"
|
|
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI generates an event when the event stream is enabled" "0 to 1,1 to 0"
|
|
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "EL1PCEN,Controls whether the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
|
|
newline
|
|
bitfld.quad 0x00 0. "EL1PCTEN,Controls whether the physical counter CNTPCT is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
|
|
group.quad spr:0x33E20++0x00
|
|
line.quad 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue Register"
|
|
hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL1 physical timer"
|
|
group.quad spr:0x33E21++0x00
|
|
line.quad 0x00 "CNTP_CTL_EL0,Counter-timer Physical Timer Control Register"
|
|
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
|
|
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
|
|
group.quad spr:0x33E22++0x00
|
|
line.quad 0x00 "CNTP_CVAL_EL0,Counter-timer Physical Timer CompareValue Register"
|
|
group.quad spr:0x33E30++0x00
|
|
line.quad 0x00 "CNTV_TVAL_EL0,Counter-timer Virtual Timer TimerValue Register"
|
|
hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL1 virtual timer"
|
|
group.quad spr:0x33E31++0x00
|
|
line.quad 0x00 "CNTV_CTL_EL0,Counter-timer Virtual Timer Control Register"
|
|
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
|
|
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
|
|
group.quad spr:0x33E32++0x00
|
|
line.quad 0x00 "CNTV_CVAL_EL0,Counter-timer Virtual Timer CompareValue Register"
|
|
group.quad spr:0x34E20++0x00
|
|
line.quad 0x00 "CNTHP_TVAL_EL2,Counter-timer Hypervisor Physical Timer TimerValue Register"
|
|
hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL2 physical timer"
|
|
group.quad spr:0x34E21++0x00
|
|
line.quad 0x00 "CNTHP_CTL_EL2,Counter-timer Hypervisor Physical Timer Control Register"
|
|
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
|
|
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
|
|
group.quad spr:0x34E22++0x00
|
|
line.quad 0x00 "CNTHP_CVAL_EL2,Counter-timer Hypervisor Physical Timer CompareValue Register"
|
|
group.quad spr:0x37E20++0x00
|
|
line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical Secure Timer TimerValue Register"
|
|
hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the secure physical timer"
|
|
group.quad spr:0x37E21++0x00
|
|
line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control Register"
|
|
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
|
|
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
|
|
group.quad spr:0x37E22++0x00
|
|
line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue Register"
|
|
tree.end
|
|
tree "Generic Interrupt Controller System Registers"
|
|
tree "AArch64 GIC Physical CPU Interface System Registers"
|
|
tree.open "Interrupt Controller Active Priorities Registers"
|
|
group.quad spr:0x30C84++0x00
|
|
line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)"
|
|
bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
|
|
group.quad spr:0x30C90++0x00
|
|
line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)"
|
|
bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
|
|
tree.end
|
|
newline
|
|
if (((per.q(spr:0x30CB6))&0x10000000000)==0x00)
|
|
wgroup.quad spr:0x30CB6++0x00
|
|
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
|
|
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
|
|
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
|
|
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
|
|
else
|
|
wgroup.quad spr:0x30CB6++0x00
|
|
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
|
|
newline
|
|
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
endif
|
|
group.quad spr:0x30C83++0x00
|
|
line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0"
|
|
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
|
|
group.quad spr:0x30CC3++0x00
|
|
line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1"
|
|
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
|
|
group.quad spr:0x30CC4++0x00
|
|
line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)"
|
|
rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported"
|
|
rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
|
|
newline
|
|
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Zero,Non-zero"
|
|
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
|
|
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
|
|
newline
|
|
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask Register is used as a hint for interrupt distribution" "Disabled,Enabled"
|
|
bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 0. "CBPR,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 interrupts" "Separate registers,Same Register"
|
|
group.quad spr:0x36CC4++0x00
|
|
line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)"
|
|
rbitfld.quad 0x00 19. "ExtRange,Extended INTID range" "Not supported,Supported"
|
|
rbitfld.quad 0x00 18. "RSS,Range Selector Support" "0 - 15,0 - 255"
|
|
newline
|
|
rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
|
|
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
|
|
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
|
|
newline
|
|
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
|
|
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop"
|
|
bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop"
|
|
bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same Register"
|
|
bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same Register"
|
|
if (((per.q(spr:0x30CC4))&0x3800)==0x00)
|
|
wgroup.quad spr:0x30CB1++0x00
|
|
line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register"
|
|
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
|
|
wgroup.quad spr:0x30C81++0x00
|
|
line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0"
|
|
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
|
|
wgroup.quad spr:0x30CC1++0x00
|
|
line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1"
|
|
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
|
|
rgroup.quad spr:0x30C82++0x00
|
|
line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0"
|
|
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
|
|
rgroup.quad spr:0x30CC2++0x00
|
|
line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
|
|
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
|
|
elif (((per.q(spr:0x30CC4))&0x3800)==0x800)
|
|
wgroup.quad spr:0x30CB1++0x00
|
|
line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register"
|
|
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
|
|
wgroup.quad spr:0x30C81++0x00
|
|
line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0"
|
|
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
|
|
wgroup.quad spr:0x30CC1++0x00
|
|
line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1"
|
|
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
|
|
rgroup.quad spr:0x30C82++0x00
|
|
line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0"
|
|
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
|
|
rgroup.quad spr:0x30CC2++0x00
|
|
line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
|
|
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
|
|
endif
|
|
hgroup.quad spr:0x30C80++0x00
|
|
hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0"
|
|
in
|
|
hgroup.quad spr:0x30CC0++0x00
|
|
hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1"
|
|
in
|
|
newline
|
|
group.quad spr:0x30CC6++0x00
|
|
line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Controller Interrupt Group 0 Enable Register"
|
|
bitfld.quad 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
|
|
group.quad spr:0x30CC7++0x00
|
|
line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Controller Interrupt Group 1 Enable Register (EL1)"
|
|
bitfld.quad 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled"
|
|
group.quad spr:0x36CC7++0x00
|
|
line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Controller Interrupt Group 1 Enable Register (EL3)"
|
|
bitfld.quad 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
|
|
group.quad spr:0x30460++0x00
|
|
line.quad 0x00 "ICC_PMR_EL1,Interrupt Controller Interrupt Priority Mask Register"
|
|
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,The priority mask level for the CPU interface"
|
|
rgroup.quad spr:0x30CB3++0x00
|
|
line.quad 0x00 "ICC_RPR_EL1,Interrupt Controller Running Priority Register"
|
|
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,The current running priority on the CPU interface"
|
|
if (((per.q(spr:0x30CB7))&0x10000000000)==0x00)
|
|
wgroup.quad spr:0x30CB7++0x00
|
|
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
|
|
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
|
|
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
|
|
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated."
|
|
else
|
|
wgroup.quad spr:0x30CB7++0x00
|
|
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
|
|
newline
|
|
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
endif
|
|
if (((per.q(spr:0x30CB5))&0x10000000000)==0x00)
|
|
wgroup.quad spr:0x30CB5++0x00
|
|
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
|
|
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
|
|
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
|
|
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
|
|
else
|
|
wgroup.quad spr:0x30CB5++0x00
|
|
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
|
|
newline
|
|
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
endif
|
|
group.quad spr:0x30CC5++0x00
|
|
line.quad 0x00 "ICC_SRE_EL1,Interrupt Controller System Register Enable Register (EL1)"
|
|
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
|
|
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
|
|
bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
|
|
group.quad spr:0x34C95++0x00
|
|
line.quad 0x00 "ICC_SRE_EL2,Interrupt Controller System Register Enable Register (EL2)"
|
|
bitfld.quad 0x00 3. "ENABLE,Enables lower Exception level access to ICC_SRE_EL1" "Trapped,Not trapped"
|
|
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
|
|
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
|
|
group.quad spr:0x36CC5++0x00
|
|
line.quad 0x00 "ICC_SRE_EL3,Interrupt Controller System Register Enable Register (EL3)"
|
|
bitfld.quad 0x00 3. "ENABLE,Enables lower Exception level access to ICC_SRE_EL1/ICC_SRE_EL2" "Trapped,Not trapped"
|
|
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
|
|
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "AArch64 Virtual Interface Control System Registers"
|
|
tree.open "Hypervisor Active Priorities Registers"
|
|
group.quad spr:0x34C80++0x00
|
|
line.quad 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
|
|
bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
|
|
group.quad spr:0x34C90++0x00
|
|
line.quad 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
|
|
bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
|
|
tree.end
|
|
newline
|
|
rgroup.quad spr:0x34CB3++0x00
|
|
line.quad 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register"
|
|
bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
|
|
bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
|
|
rgroup.quad spr:0x34CB5++0x00
|
|
line.quad 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register"
|
|
bitfld.quad 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
|
|
bitfld.quad 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
|
|
bitfld.quad 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
|
|
newline
|
|
bitfld.quad 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
|
|
if (((per.q(spr:0x34CB1))&0x400000)==0x400000)
|
|
group.quad spr:0x34CB0++0x00
|
|
line.quad 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register"
|
|
bitfld.quad 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
|
|
bitfld.quad 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
|
|
bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
|
|
bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:0x34CB0++0x00
|
|
line.quad 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register"
|
|
bitfld.quad 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
|
|
bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
|
|
bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
|
|
endif
|
|
if (((per.q(spr:0x34CC0+0x0))&0x2000000000000000)==0x00)
|
|
group.quad spr:(0x34CC0+0x0)++0x00
|
|
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
|
|
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware"
|
|
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
|
|
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
|
|
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
|
|
else
|
|
group.quad spr:(0x34CC0+0x0)++0x00
|
|
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
|
|
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware"
|
|
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
|
|
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID for hardware interrupts"
|
|
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
|
|
endif
|
|
if (((per.q(spr:0x34CC0+0x1))&0x2000000000000000)==0x00)
|
|
group.quad spr:(0x34CC0+0x1)++0x00
|
|
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
|
|
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware"
|
|
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
|
|
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
|
|
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
|
|
else
|
|
group.quad spr:(0x34CC0+0x1)++0x00
|
|
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
|
|
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware"
|
|
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
|
|
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID for hardware interrupts"
|
|
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
|
|
endif
|
|
if (((per.q(spr:0x34CC0+0x2))&0x2000000000000000)==0x00)
|
|
group.quad spr:(0x34CC0+0x2)++0x00
|
|
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
|
|
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware"
|
|
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
|
|
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
|
|
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
|
|
else
|
|
group.quad spr:(0x34CC0+0x2)++0x00
|
|
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
|
|
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware"
|
|
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
|
|
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID for hardware interrupts"
|
|
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
|
|
endif
|
|
if (((per.q(spr:0x34CC0+0x3))&0x2000000000000000)==0x00)
|
|
group.quad spr:(0x34CC0+0x3)++0x00
|
|
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
|
|
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware"
|
|
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
|
|
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
|
|
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
|
|
else
|
|
group.quad spr:(0x34CC0+0x3)++0x00
|
|
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
|
|
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware"
|
|
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
|
|
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID for hardware interrupts"
|
|
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
|
|
endif
|
|
rgroup.quad spr:0x34CB2++0x00
|
|
line.quad 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register"
|
|
bitfld.quad 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
|
|
bitfld.quad 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
|
|
bitfld.quad 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
|
|
newline
|
|
bitfld.quad 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
|
|
bitfld.quad 0x00 3. "NP,No Pending" "Not asserted,Asserted"
|
|
bitfld.quad 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
|
|
newline
|
|
bitfld.quad 0x00 1. "U,Underflow" "Not asserted,Asserted"
|
|
bitfld.quad 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
|
|
group.quad spr:0x34CB7++0x00
|
|
line.quad 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register"
|
|
hexmask.quad.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
|
|
bitfld.quad 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
|
|
bitfld.quad 0x00 18.--20. "VBPR1,Virtual Binary Point Register Group 1" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
|
|
newline
|
|
bitfld.quad 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
|
|
bitfld.quad 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
|
|
bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
|
|
newline
|
|
bitfld.quad 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
|
|
bitfld.quad 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
|
|
rgroup.quad spr:0x34CB1++0x00
|
|
line.quad 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register"
|
|
bitfld.quad 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented minus one" "0,1,2,3,4,5,6,7"
|
|
bitfld.quad 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
|
|
newline
|
|
bitfld.quad 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
|
|
bitfld.quad 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
|
|
bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
|
|
newline
|
|
bitfld.quad 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
|
|
bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented List registers minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree.end
|
|
tree "Debug Registers"
|
|
rgroup.quad spr:0x23010++0x00
|
|
line.quad 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register"
|
|
bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
|
|
group.quad spr:0x20020++0x00
|
|
line.quad 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register"
|
|
bitfld.quad 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
|
|
bitfld.quad 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
|
|
group.quad spr:0x23040++0x00
|
|
line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "HIGHWORD,Writes to this register set DTRRX to the value in this field and do not change RXfull"
|
|
hexmask.quad.long 0x00 0.--31. 1. "LOWWORD,Writes to this register set DTRTX to the value in this field and set TXfull to 1"
|
|
rgroup.quad spr:0x23050++0x00
|
|
line.quad 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register"
|
|
wgroup.quad spr:0x23050++0x00
|
|
line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register"
|
|
group.quad spr:0x24070++0x00
|
|
line.quad 0x00 "DBGVCR32_EL2,Vector Catch Register"
|
|
bitfld.quad 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Low,High"
|
|
bitfld.quad 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Low,High"
|
|
bitfld.quad 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Low,High"
|
|
bitfld.quad 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Low,High"
|
|
newline
|
|
bitfld.quad 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Low,High"
|
|
bitfld.quad 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Low,High"
|
|
bitfld.quad 0x00 7. "SF,FIQ vector catch enable in Secure state" "Low,High"
|
|
bitfld.quad 0x00 6. "SI,IRQ vector catch enable in Secure state" "Low,High"
|
|
newline
|
|
bitfld.quad 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Low,High"
|
|
bitfld.quad 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Low,High"
|
|
bitfld.quad 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Low,High"
|
|
bitfld.quad 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Low,High"
|
|
group.quad spr:0x20002++0x00
|
|
line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register"
|
|
if (((per.q(spr:0x20114))&0x02)==0x02)
|
|
group.quad spr:0x20022++0x00
|
|
line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
|
|
bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.quad 0x00 27. "RXO,Save/restore bit" "Low,High"
|
|
bitfld.quad 0x00 26. "TXU,Save/restore bit" "Low,High"
|
|
newline
|
|
bitfld.quad 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3"
|
|
bitfld.quad 0x00 21. "TDA,Save/restore bit" "Low,High"
|
|
bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
|
|
bitfld.quad 0x00 14. "HDE,Save/restore bit" "Low,High"
|
|
newline
|
|
bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled"
|
|
bitfld.quad 0x00 6. "ERR,Save/restore bit" "Low,High"
|
|
bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:0x20022++0x00
|
|
line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
|
|
rbitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
|
|
rbitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
|
|
rbitfld.quad 0x00 27. "RXO,Save/restore bit" "Low,High"
|
|
rbitfld.quad 0x00 26. "TXU,Save/restore bit" "Low,High"
|
|
newline
|
|
rbitfld.quad 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3"
|
|
rbitfld.quad 0x00 21. "TDA,Save/restore bit" "Low,High"
|
|
bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
|
|
bitfld.quad 0x00 14. "HDE,Save/restore bit" "Low,High"
|
|
newline
|
|
bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
|
|
bitfld.quad 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled"
|
|
rbitfld.quad 0x00 6. "ERR,Save/restore bit" "Low,High"
|
|
bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled"
|
|
endif
|
|
group.quad spr:0x20032++0x00
|
|
line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register"
|
|
group.quad spr:0x20062++0x00
|
|
line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register"
|
|
rgroup.quad spr:0x20100++0x00
|
|
line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register"
|
|
hexmask.quad 0x00 12.--47. 0x10 "ROMADDR,ROM base physical address"
|
|
bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid"
|
|
wgroup.quad spr:0x20104++0x00
|
|
line.quad 0x00 "OSLAR_EL1,OS Lock Access Register"
|
|
bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock"
|
|
rgroup.quad spr:0x20114++0x00
|
|
line.quad 0x00 "OSLSR_EL1,OS Lock Status Register"
|
|
bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,?..."
|
|
bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked"
|
|
bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Impelemented,?..."
|
|
group.quad spr:0x20134++0x00
|
|
line.quad 0x00 "OSDLR_EL1,OS Double-lock Register"
|
|
bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
|
|
group.quad spr:0x20144++0x00
|
|
line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register"
|
|
bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes"
|
|
group.quad spr:0x20786++0x00
|
|
line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set"
|
|
bitfld.quad 0x00 7. "CT7,Claim Tag 7 Set" "Reserved,Set"
|
|
bitfld.quad 0x00 6. "CT6,Claim Tag 6 Set" "Reserved,Set"
|
|
bitfld.quad 0x00 5. "CT5,Claim Tag 5 Set" "Reserved,Set"
|
|
bitfld.quad 0x00 4. "CT4,Claim Tag 4 Set" "Reserved,Set"
|
|
newline
|
|
bitfld.quad 0x00 3. "CT3,Claim Tag 3 Set" "Reserved,Set"
|
|
bitfld.quad 0x00 2. "CT2,Claim Tag 2 Set" "Reserved,Set"
|
|
bitfld.quad 0x00 1. "CT1,Claim Tag 1 Set" "Reserved,Set"
|
|
bitfld.quad 0x00 0. "CT0,Claim Tag 0 Set" "Reserved,Set"
|
|
group.quad spr:0x20796++0x00
|
|
line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear"
|
|
bitfld.quad 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
|
|
bitfld.quad 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
|
|
bitfld.quad 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
|
|
bitfld.quad 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.quad 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
|
|
bitfld.quad 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
|
|
bitfld.quad 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
|
|
bitfld.quad 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
|
|
rgroup.quad spr:0x207E6++0x00
|
|
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status Register"
|
|
bitfld.quad 0x00 6.--7. "SNID,Secure non-invasive debug" "Not implemented,Reserved,Disabled,Enabled"
|
|
bitfld.quad 0x00 4.--5. "SID,Secure invasive debug" "Not implemented,Reserved,Disabled,Enabled"
|
|
bitfld.quad 0x00 2.--3. "NSNID,Non-secure non-invasive debug" "Not implemented,Reserved,Reserved,Enabled"
|
|
bitfld.quad 0x00 0.--1. "NSID,Non-secure invasive debug" "Not implemented,Reserved,Disabled,Enabled"
|
|
tree.end
|
|
tree "Breakpoint Registers"
|
|
tree "Breakpoint 0"
|
|
if (((per.q(spr:0x20005+0x0))&0xF00000)<=0x100000)
|
|
group.quad spr:(0x20004+0x0)++0x00
|
|
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
|
|
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
|
|
elif (((((per.q(spr:0x20005+0x0))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x0))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x700000)))
|
|
group.quad spr:(0x20004+0x0)++0x00
|
|
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00))
|
|
group.quad spr:(0x20004+0x0)++0x00
|
|
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
|
|
group.quad spr:(0x20004+0x0)++0x00
|
|
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
|
|
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00))
|
|
group.quad spr:(0x20004+0x0)++0x00
|
|
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
|
|
group.quad spr:(0x20004+0x0)++0x00
|
|
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
|
|
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xD00000))
|
|
group.quad spr:(0x20004+0x0)++0x00
|
|
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
|
|
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xF00000))
|
|
group.quad spr:(0x20004+0x0)++0x00
|
|
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
|
|
else
|
|
rgroup.quad spr:(0x20004+0x0)++0x00
|
|
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
|
|
endif
|
|
if (((per.q(spr:0x20005+0x0))&0x2000)==0x2000)
|
|
if (((per.q(spr:0x20005+0x0))&0xC000)==0x0000)
|
|
group.quad spr:(0x20005+0x0)++0x00
|
|
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20005+0x0))&0xC000)==0x4000)
|
|
group.quad spr:(0x20005+0x0)++0x00
|
|
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20005+0x0))&0xC000)==0x8000)
|
|
group.quad spr:(0x20005+0x0)++0x00
|
|
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20005+0x0)++0x00
|
|
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x20005+0x0))&0xC000)==0xC000)
|
|
group.quad spr:(0x20005+0x0)++0x00
|
|
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20005+0x0)++0x00
|
|
line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint 1"
|
|
if (((per.q(spr:0x20005+0x10))&0xF00000)<=0x100000)
|
|
group.quad spr:(0x20004+0x10)++0x00
|
|
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
|
|
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
|
|
elif (((((per.q(spr:0x20005+0x10))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x10))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x700000)))
|
|
group.quad spr:(0x20004+0x10)++0x00
|
|
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00))
|
|
group.quad spr:(0x20004+0x10)++0x00
|
|
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
|
|
group.quad spr:(0x20004+0x10)++0x00
|
|
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
|
|
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00))
|
|
group.quad spr:(0x20004+0x10)++0x00
|
|
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
|
|
group.quad spr:(0x20004+0x10)++0x00
|
|
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
|
|
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xD00000))
|
|
group.quad spr:(0x20004+0x10)++0x00
|
|
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
|
|
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xF00000))
|
|
group.quad spr:(0x20004+0x10)++0x00
|
|
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
|
|
else
|
|
rgroup.quad spr:(0x20004+0x10)++0x00
|
|
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
|
|
endif
|
|
if (((per.q(spr:0x20005+0x10))&0x2000)==0x2000)
|
|
if (((per.q(spr:0x20005+0x10))&0xC000)==0x0000)
|
|
group.quad spr:(0x20005+0x10)++0x00
|
|
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20005+0x10))&0xC000)==0x4000)
|
|
group.quad spr:(0x20005+0x10)++0x00
|
|
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20005+0x10))&0xC000)==0x8000)
|
|
group.quad spr:(0x20005+0x10)++0x00
|
|
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20005+0x10)++0x00
|
|
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x20005+0x10))&0xC000)==0xC000)
|
|
group.quad spr:(0x20005+0x10)++0x00
|
|
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20005+0x10)++0x00
|
|
line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint 2"
|
|
if (((per.q(spr:0x20005+0x20))&0xF00000)<=0x100000)
|
|
group.quad spr:(0x20004+0x20)++0x00
|
|
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
|
|
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
|
|
elif (((((per.q(spr:0x20005+0x20))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x20))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x700000)))
|
|
group.quad spr:(0x20004+0x20)++0x00
|
|
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00))
|
|
group.quad spr:(0x20004+0x20)++0x00
|
|
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
|
|
group.quad spr:(0x20004+0x20)++0x00
|
|
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
|
|
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00))
|
|
group.quad spr:(0x20004+0x20)++0x00
|
|
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
|
|
group.quad spr:(0x20004+0x20)++0x00
|
|
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
|
|
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xD00000))
|
|
group.quad spr:(0x20004+0x20)++0x00
|
|
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
|
|
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xF00000))
|
|
group.quad spr:(0x20004+0x20)++0x00
|
|
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
|
|
else
|
|
rgroup.quad spr:(0x20004+0x20)++0x00
|
|
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
|
|
endif
|
|
if (((per.q(spr:0x20005+0x20))&0x2000)==0x2000)
|
|
if (((per.q(spr:0x20005+0x20))&0xC000)==0x0000)
|
|
group.quad spr:(0x20005+0x20)++0x00
|
|
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20005+0x20))&0xC000)==0x4000)
|
|
group.quad spr:(0x20005+0x20)++0x00
|
|
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20005+0x20))&0xC000)==0x8000)
|
|
group.quad spr:(0x20005+0x20)++0x00
|
|
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20005+0x20)++0x00
|
|
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x20005+0x20))&0xC000)==0xC000)
|
|
group.quad spr:(0x20005+0x20)++0x00
|
|
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20005+0x20)++0x00
|
|
line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint 3"
|
|
if (((per.q(spr:0x20005+0x30))&0xF00000)<=0x100000)
|
|
group.quad spr:(0x20004+0x30)++0x00
|
|
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
|
|
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
|
|
elif (((((per.q(spr:0x20005+0x30))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x30))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x700000)))
|
|
group.quad spr:(0x20004+0x30)++0x00
|
|
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00))
|
|
group.quad spr:(0x20004+0x30)++0x00
|
|
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
|
|
group.quad spr:(0x20004+0x30)++0x00
|
|
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
|
|
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00))
|
|
group.quad spr:(0x20004+0x30)++0x00
|
|
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
|
|
group.quad spr:(0x20004+0x30)++0x00
|
|
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
|
|
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xD00000))
|
|
group.quad spr:(0x20004+0x30)++0x00
|
|
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
|
|
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xF00000))
|
|
group.quad spr:(0x20004+0x30)++0x00
|
|
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
|
|
else
|
|
rgroup.quad spr:(0x20004+0x30)++0x00
|
|
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
|
|
endif
|
|
if (((per.q(spr:0x20005+0x30))&0x2000)==0x2000)
|
|
if (((per.q(spr:0x20005+0x30))&0xC000)==0x0000)
|
|
group.quad spr:(0x20005+0x30)++0x00
|
|
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20005+0x30))&0xC000)==0x4000)
|
|
group.quad spr:(0x20005+0x30)++0x00
|
|
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20005+0x30))&0xC000)==0x8000)
|
|
group.quad spr:(0x20005+0x30)++0x00
|
|
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20005+0x30)++0x00
|
|
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x20005+0x30))&0xC000)==0xC000)
|
|
group.quad spr:(0x20005+0x30)++0x00
|
|
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20005+0x30)++0x00
|
|
line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint 4"
|
|
if (((per.q(spr:0x20005+0x40))&0xF00000)<=0x100000)
|
|
group.quad spr:(0x20004+0x40)++0x00
|
|
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
|
|
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
|
|
elif (((((per.q(spr:0x20005+0x40))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x40))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x700000)))
|
|
group.quad spr:(0x20004+0x40)++0x00
|
|
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00))
|
|
group.quad spr:(0x20004+0x40)++0x00
|
|
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
|
|
group.quad spr:(0x20004+0x40)++0x00
|
|
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
|
|
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00))
|
|
group.quad spr:(0x20004+0x40)++0x00
|
|
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
|
|
group.quad spr:(0x20004+0x40)++0x00
|
|
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
|
|
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xD00000))
|
|
group.quad spr:(0x20004+0x40)++0x00
|
|
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
|
|
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xF00000))
|
|
group.quad spr:(0x20004+0x40)++0x00
|
|
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
|
|
else
|
|
rgroup.quad spr:(0x20004+0x40)++0x00
|
|
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
|
|
endif
|
|
if (((per.q(spr:0x20005+0x40))&0x2000)==0x2000)
|
|
if (((per.q(spr:0x20005+0x40))&0xC000)==0x0000)
|
|
group.quad spr:(0x20005+0x40)++0x00
|
|
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20005+0x40))&0xC000)==0x4000)
|
|
group.quad spr:(0x20005+0x40)++0x00
|
|
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20005+0x40))&0xC000)==0x8000)
|
|
group.quad spr:(0x20005+0x40)++0x00
|
|
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20005+0x40)++0x00
|
|
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x20005+0x40))&0xC000)==0xC000)
|
|
group.quad spr:(0x20005+0x40)++0x00
|
|
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20005+0x40)++0x00
|
|
line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint 5"
|
|
if (((per.q(spr:0x20005+0x50))&0xF00000)<=0x100000)
|
|
group.quad spr:(0x20004+0x50)++0x00
|
|
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
|
|
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
|
|
elif (((((per.q(spr:0x20005+0x50))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x50))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x700000)))
|
|
group.quad spr:(0x20004+0x50)++0x00
|
|
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00))
|
|
group.quad spr:(0x20004+0x50)++0x00
|
|
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
|
|
group.quad spr:(0x20004+0x50)++0x00
|
|
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
|
|
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00))
|
|
group.quad spr:(0x20004+0x50)++0x00
|
|
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
|
|
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
|
|
group.quad spr:(0x20004+0x50)++0x00
|
|
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
|
|
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
|
|
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xD00000))
|
|
group.quad spr:(0x20004+0x50)++0x00
|
|
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
|
|
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xF00000))
|
|
group.quad spr:(0x20004+0x50)++0x00
|
|
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
|
|
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
|
|
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
|
|
else
|
|
rgroup.quad spr:(0x20004+0x50)++0x00
|
|
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
|
|
endif
|
|
if (((per.q(spr:0x20005+0x50))&0x2000)==0x2000)
|
|
if (((per.q(spr:0x20005+0x50))&0xC000)==0x0000)
|
|
group.quad spr:(0x20005+0x50)++0x00
|
|
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20005+0x50))&0xC000)==0x4000)
|
|
group.quad spr:(0x20005+0x50)++0x00
|
|
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20005+0x50))&0xC000)==0x8000)
|
|
group.quad spr:(0x20005+0x50)++0x00
|
|
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20005+0x50)++0x00
|
|
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x20005+0x50))&0xC000)==0xC000)
|
|
group.quad spr:(0x20005+0x50)++0x00
|
|
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20005+0x50)++0x00
|
|
line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
|
|
bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
newline
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
|
|
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
|
|
newline
|
|
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "Watchpoint Control Registers"
|
|
tree "Watchpoint 0"
|
|
group.quad spr:(0x20006+0x0)++0x00
|
|
line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)"
|
|
hexmask.quad 0x00 2.--48. 0x04 "ADDRESS,Data address"
|
|
if (((per.q(spr:0x20007+0x0))&0x2000)==0x0000)
|
|
if (((per.q(spr:0x20007+0x0))&0xC000)==0xC000)
|
|
group.quad spr:(0x20007+0x0)++0x00
|
|
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20007+0x0)++0x00
|
|
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x20007+0x0))&0xC000)==0x0000)
|
|
group.quad spr:(0x20007+0x0)++0x00
|
|
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20007+0x0))&0xC000)==0x8000)
|
|
group.quad spr:(0x20007+0x0)++0x00
|
|
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20007+0x0)++0x00
|
|
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Superisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Watchpoint 1"
|
|
group.quad spr:(0x20006+0x10)++0x00
|
|
line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)"
|
|
hexmask.quad 0x00 2.--48. 0x04 "ADDRESS,Data address"
|
|
if (((per.q(spr:0x20007+0x10))&0x2000)==0x0000)
|
|
if (((per.q(spr:0x20007+0x10))&0xC000)==0xC000)
|
|
group.quad spr:(0x20007+0x10)++0x00
|
|
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20007+0x10)++0x00
|
|
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x20007+0x10))&0xC000)==0x0000)
|
|
group.quad spr:(0x20007+0x10)++0x00
|
|
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20007+0x10))&0xC000)==0x8000)
|
|
group.quad spr:(0x20007+0x10)++0x00
|
|
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20007+0x10)++0x00
|
|
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Superisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Watchpoint 2"
|
|
group.quad spr:(0x20006+0x20)++0x00
|
|
line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)"
|
|
hexmask.quad 0x00 2.--48. 0x04 "ADDRESS,Data address"
|
|
if (((per.q(spr:0x20007+0x20))&0x2000)==0x0000)
|
|
if (((per.q(spr:0x20007+0x20))&0xC000)==0xC000)
|
|
group.quad spr:(0x20007+0x20)++0x00
|
|
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20007+0x20)++0x00
|
|
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x20007+0x20))&0xC000)==0x0000)
|
|
group.quad spr:(0x20007+0x20)++0x00
|
|
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20007+0x20))&0xC000)==0x8000)
|
|
group.quad spr:(0x20007+0x20)++0x00
|
|
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20007+0x20)++0x00
|
|
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Superisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Watchpoint 3"
|
|
group.quad spr:(0x20006+0x30)++0x00
|
|
line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)"
|
|
hexmask.quad 0x00 2.--48. 0x04 "ADDRESS,Data address"
|
|
if (((per.q(spr:0x20007+0x30))&0x2000)==0x0000)
|
|
if (((per.q(spr:0x20007+0x30))&0xC000)==0xC000)
|
|
group.quad spr:(0x20007+0x30)++0x00
|
|
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20007+0x30)++0x00
|
|
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.q(spr:0x20007+0x30))&0xC000)==0x0000)
|
|
group.quad spr:(0x20007+0x30)++0x00
|
|
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
elif (((per.q(spr:0x20007+0x30))&0xC000)==0x8000)
|
|
group.quad spr:(0x20007+0x30)++0x00
|
|
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
else
|
|
group.quad spr:(0x20007+0x30)++0x00
|
|
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
|
|
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
|
|
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
|
|
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
|
|
newline
|
|
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
|
|
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Superisor,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "AArch32"
|
|
tree "ID Registers"
|
|
rgroup.long c15:0x0000++0x0
|
|
line.long 0x0 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code"
|
|
bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8"
|
|
newline
|
|
hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number"
|
|
bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long c15:0x0100++0x0
|
|
line.long 0x0 "CTR,Cache Type Register"
|
|
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
newline
|
|
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
|
|
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
rgroup.long c15:0x0200++0x0
|
|
line.long 0x0 "TCMTR,TCM Type Register"
|
|
rgroup.long c15:0x0300++0x0
|
|
line.long 0x0 "TLBTR,TLB Type Register"
|
|
rgroup.long c15:0x0500++0x0
|
|
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
|
|
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
|
|
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
|
|
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
|
|
rgroup.long c15:0x0600++0x0
|
|
line.long 0x0 "REVIDR,Revision ID Register"
|
|
rgroup.long c15:0x0410++0x00
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
|
|
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
|
|
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,VMSAv7,?..."
|
|
rgroup.long c15:0x0510++0x00
|
|
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,No flushing,?..."
|
|
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
|
|
rgroup.long c15:0x0610++0x00
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup.long c15:0x0710++0x00
|
|
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
|
|
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
|
|
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
|
|
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x0020++0x00
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
|
|
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
|
|
rgroup.long c15:0x0120++0x00
|
|
line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1"
|
|
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x0220++0x00
|
|
line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2"
|
|
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup.long c15:0x0320++0x00
|
|
line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3"
|
|
bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x0420++0x00
|
|
line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4"
|
|
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup.long c15:0x0520++0x00
|
|
line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5"
|
|
bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x0010++0x00
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x0110++0x00
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
|
|
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x0210++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Not implemented,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup.long c15:0x0310++0x00
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
tree.end
|
|
tree "System Control and Configuration"
|
|
group.long c15:0x0001++0x0
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
|
|
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
|
|
newline
|
|
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
newline
|
|
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
|
|
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
|
|
newline
|
|
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
|
|
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
|
|
group.quad c15:0x100F0++0x01
|
|
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
|
|
bitfld.quad 0x00 44. "ENDCCASCI,Enable Data Cache Clean As data cache Clean/Invalidate" "Disabled,Enabled"
|
|
bitfld.quad 0x00 30. "CDIDIS,Disable Cryptographic Dual Issue" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
|
|
bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled"
|
|
newline
|
|
bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
|
|
bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes"
|
|
bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams"
|
|
bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "2 linefills,3 linefills"
|
|
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8"
|
|
newline
|
|
bitfld.quad 0x00 11. "DYNSDIS,Disable dynamic stride adjustment for prefetch streams" "No,Yes"
|
|
bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache Data RAM Error Injection Enable" "Disabled,Enabled"
|
|
group.quad c15:0x110F0++0x01
|
|
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
|
|
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
|
|
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
|
|
newline
|
|
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
|
|
if (((per.q(c15:0x120F0))&0x7F000000)==0x000000000)
|
|
group.quad c15:0x120F0++0x01
|
|
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Way 0,Way 1,?..."
|
|
newline
|
|
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
|
|
elif (((per.q(c15:0x120F0))&0x7F000000)==0x01000000)
|
|
group.quad c15:0x120F0++0x01
|
|
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Bank 0,Bank 1,?..."
|
|
newline
|
|
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
|
|
elif (((per.q(c15:0x120F0))&0x7F000000)==0x08000000)
|
|
group.quad c15:0x120F0++0x01
|
|
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Way 0,Way 1,Way 2,Way 3,?..."
|
|
newline
|
|
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
|
|
elif (((per.q(c15:0x120F0))&0x7F000000)==0x09000000)
|
|
group.quad c15:0x120F0++0x01
|
|
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7"
|
|
newline
|
|
hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address"
|
|
elif (((per.q(c15:0x120F0))&0x7F000000)==0x0A000000)
|
|
group.quad c15:0x120F0++0x01
|
|
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Dirty RAM,?..."
|
|
newline
|
|
hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address"
|
|
elif (((per.q(c15:0x120F0))&0x7F000000)==0x18000000)
|
|
group.quad c15:0x120F0++0x01
|
|
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "Way 0,Way 1,?..."
|
|
newline
|
|
hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address"
|
|
else
|
|
group.quad c15:0x120F0++0x01
|
|
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
hexmask.quad.word 0x00 0.--11. 0x01 "RAD,RAM address"
|
|
endif
|
|
group.long c15:0x0101++0x0
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
|
|
group.long c15:0x0201++0x00
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x0 22.--23. "CP11,Coprocesor access control" "Denied,EL1 only,Reserved,Full"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "CP10,Coprocesor access control" "Denied,EL1 only,Reserved,Full"
|
|
group.long c15:0x0011++0x0
|
|
line.long 0x0 "SCR,Secure Configuration Register"
|
|
bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
|
|
bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
|
|
bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes"
|
|
bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Not taken,Taken"
|
|
newline
|
|
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in FIQ mode or Monitor mode" "Not taken,Taken"
|
|
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in IRQ mode or Monitor mode" "Not taken,Taken"
|
|
newline
|
|
bitfld.long 0x00 0. "NS,Secure mode" "Secure,Non-secure"
|
|
group.long c15:0x0111++0x00
|
|
line.long 0x00 "SDER,Secure Debug Enable Register"
|
|
bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
group.long c15:0x0131++0x00
|
|
line.long 0x00 "SDCR,Secure Debug Control Register"
|
|
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
|
|
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
|
|
group.long c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
newline
|
|
bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
group.long c15:0x000C++0x00
|
|
line.long 0x00 "VBAR,Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
|
|
group.long c15:0x010C++0x00
|
|
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
|
|
rgroup.long c15:0x001C++0x00
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending"
|
|
bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
|
|
group.long c15:0x020C++0x00
|
|
line.long 0x00 "RMR,Reset Management Register"
|
|
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64"
|
|
rgroup.long c15:0x0015++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
rgroup.long c15:0x0115++0x00
|
|
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
|
|
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
|
|
newline
|
|
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
|
|
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Async. external,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/on memory access,Async. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/L1,Sync. parity/on memory access/on TTW/L2,Sync. parity/on memory access/on TTW/L3,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,?..."
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/L1,Sync. parity/on memory access/on TTW/L2,Sync. parity/on memory access/on TTW/L3,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
|
|
else
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
|
|
newline
|
|
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
|
|
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/section,Instruction cache maintenance,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/L1,Permission/section,Sync. external/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/L1,Reserved,Sync. parity/L2,?..."
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/L1,Permission/section,Sync. external/on TTW/L2,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/L1,Reserved,Sync. parity/on TTW/L2,?..."
|
|
endif
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
rgroup.long c15:0x103F++0x00
|
|
line.long 0x00 "CBAR,Configuration Base Address Register"
|
|
hexmask.long.word 0x00 18.--31. 0x04 "PERIPHBASE[31:18],Periphbase[31:18]"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 "PERIPHBASE[39:32],Periphbase[39:32]"
|
|
rgroup.long c15:0x000D++0x00
|
|
line.long 0x00 "FCSEIDR,FCSE Process ID register"
|
|
group.long c15:0x020D++0x00
|
|
line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register"
|
|
rgroup.long c15:0x030D++0x00
|
|
line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register"
|
|
group.long c15:0x040D++0x00
|
|
line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register"
|
|
tree "System Instructions"
|
|
wgroup.long c15:0x0017++0x00
|
|
line.long 0x00 "ICIALLUIS,ICIALLUIS"
|
|
wgroup.long c15:0x0617++0x00
|
|
line.long 0x00 "BPIALLIS,BPIALLIS"
|
|
wgroup.long c15:0x0057++0x00
|
|
line.long 0x00 "ICIALLU,ICIALLU"
|
|
wgroup.long c15:0x0157++0x00
|
|
line.long 0x00 "ICIMVAU,ICIMVAU"
|
|
wgroup.long c15:0x0457++0x00
|
|
line.long 0x00 "CP15ISB,CP15ISB"
|
|
wgroup.long c15:0x0657++0x00
|
|
line.long 0x00 "BPIALL,BPIALL"
|
|
wgroup.long c15:0x0757++0x00
|
|
line.long 0x00 "BPIMVA,BPIMVA"
|
|
wgroup.long c15:0x0167++0x00
|
|
line.long 0x00 "DCIMVAC,DCIMVAC"
|
|
wgroup.long c15:0x0267++0x00
|
|
line.long 0x00 "DCISW,DCISW"
|
|
wgroup.long c15:0x0087++0x00
|
|
line.long 0x00 "ATS1CPR,ATS1CPR"
|
|
wgroup.long c15:0x0187++0x00
|
|
line.long 0x00 "ATS1CPW,ATS1CPW"
|
|
wgroup.long c15:0x0287++0x00
|
|
line.long 0x00 "ATS1CUR,ATS1CUR"
|
|
wgroup.long c15:0x0387++0x00
|
|
line.long 0x00 "ATS1CUW,ATS1CUW"
|
|
wgroup.long c15:0x0487++0x00
|
|
line.long 0x00 "ATS12NSOPR,ATS12NSOPR"
|
|
wgroup.long c15:0x0587++0x00
|
|
line.long 0x00 "ATS12NSOPW,ATS12NSOPW"
|
|
wgroup.long c15:0x0687++0x00
|
|
line.long 0x00 "ATS12NSOUR,ATS12NSOUR"
|
|
wgroup.long c15:0x0787++0x00
|
|
line.long 0x00 "ATS12NSOUW,ATS12NSOUW"
|
|
wgroup.long c15:0x01A7++0x00
|
|
line.long 0x00 "DCCMVAC,DCCMVAC"
|
|
wgroup.long c15:0x02A7++0x00
|
|
line.long 0x00 "DCCSW,DCCSW"
|
|
wgroup.long c15:0x04A7++0x00
|
|
line.long 0x00 "CP15DSB,CP15DSB"
|
|
wgroup.long c15:0x05A7++0x00
|
|
line.long 0x00 "CP15DMB,CP15DMB"
|
|
wgroup.long c15:0x01B7++0x00
|
|
line.long 0x00 "DCCMVAU,DCCMVAU"
|
|
wgroup.long c15:0x01E7++0x00
|
|
line.long 0x00 "DCCIMVAC,DCCIMVAC"
|
|
wgroup.long c15:0x02E7++0x00
|
|
line.long 0x00 "DCCISW,DCCISW"
|
|
wgroup.long c15:0x4087++0x00
|
|
line.long 0x00 "ATS1HR,ATS1HR"
|
|
wgroup.long c15:0x4187++0x00
|
|
line.long 0x00 "ATS1HW,ATS1HW"
|
|
wgroup.long c15:0x0038++0x00
|
|
line.long 0x00 "TLBIALLIS,TLBIALLIS"
|
|
wgroup.long c15:0x0138++0x00
|
|
line.long 0x00 "TLBIMVAIS,TLBIMVAIS"
|
|
wgroup.long c15:0x0238++0x00
|
|
line.long 0x00 "TLBIASIDIS,TLBIASIDIS"
|
|
wgroup.long c15:0x0338++0x00
|
|
line.long 0x00 "TLBIMVAAIS,TLBIMVAAIS"
|
|
wgroup.long c15:0x0538++0x00
|
|
line.long 0x00 "TLBIMVALIS,TLBIMVALIS"
|
|
wgroup.long c15:0x0738++0x00
|
|
line.long 0x00 "TLBIMVAALIS,TLBIMVAALIS"
|
|
wgroup.long c15:0x0058++0x00
|
|
line.long 0x00 "ITLBIALL,ITLBIALL"
|
|
wgroup.long c15:0x0158++0x00
|
|
line.long 0x00 "ITLBIMVA,ITLBIMVA"
|
|
wgroup.long c15:0x0258++0x00
|
|
line.long 0x00 "ITLBIASID,ITLBIASID"
|
|
wgroup.long c15:0x0068++0x00
|
|
line.long 0x00 "DTLBIALL,DTLBIALL"
|
|
wgroup.long c15:0x0168++0x00
|
|
line.long 0x00 "DTLBIMVA,DTLBIMVA"
|
|
wgroup.long c15:0x0268++0x00
|
|
line.long 0x00 "DTLBIASID,DTLBIASID"
|
|
wgroup.long c15:0x0078++0x00
|
|
line.long 0x00 "TLBIALL,TLBIALL"
|
|
wgroup.long c15:0x0178++0x00
|
|
line.long 0x00 "TLBIMVA,TLBIMVA"
|
|
wgroup.long c15:0x0278++0x00
|
|
line.long 0x00 "TLBIASID,TLBIASID"
|
|
wgroup.long c15:0x0378++0x00
|
|
line.long 0x00 "TLBIMVAA,TLBIMVAA"
|
|
wgroup.long c15:0x0578++0x00
|
|
line.long 0x00 "TLBIMVAL,TLBIMVAL"
|
|
wgroup.long c15:0x0778++0x00
|
|
line.long 0x00 "TLBIMVAAL,TLBIMVAAL"
|
|
wgroup.long c15:0x4108++0x00
|
|
line.long 0x00 "TLBIIPAS2IS,TLBIIPAS2IS"
|
|
wgroup.long c15:0x4508++0x00
|
|
line.long 0x00 "TLBIIPAS2LIS,TLBIIPAS2LIS"
|
|
wgroup.long c15:0x4038++0x00
|
|
line.long 0x00 "TLBIALLHIS,TLBIALLHIS"
|
|
wgroup.long c15:0x4138++0x00
|
|
line.long 0x00 "TLBIMVAHIS,TLBIMVAHIS"
|
|
wgroup.long c15:0x4438++0x00
|
|
line.long 0x00 "TLBIALLNSNHIS,TLBIALLNSNHIS"
|
|
wgroup.long c15:0x4538++0x00
|
|
line.long 0x00 "TLBIMVALHIS,TLBIMVALHIS"
|
|
wgroup.long c15:0x4148++0x00
|
|
line.long 0x00 "TLBIIPAS2,TLBIIPAS2"
|
|
wgroup.long c15:0x4548++0x00
|
|
line.long 0x00 "TLBIIPAS2L,TLBIIPAS2L"
|
|
wgroup.long c15:0x4078++0x00
|
|
line.long 0x00 "TLBIALLH,TLBIALLH"
|
|
wgroup.long c15:0x4178++0x00
|
|
line.long 0x00 "TLBIMVAH,TLBIMVAH"
|
|
wgroup.long c15:0x4478++0x00
|
|
line.long 0x00 "TLBIALLNSNH,TLBIALLNSNH"
|
|
wgroup.long c15:0x4578++0x00
|
|
line.long 0x00 "TLBIMVALH,TLBIMVALH"
|
|
tree.end
|
|
tree.end
|
|
tree "Memory Management Unit"
|
|
group.long c15:0x0001++0x0
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
|
|
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
|
|
newline
|
|
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
newline
|
|
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
|
|
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
|
|
newline
|
|
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
|
|
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
|
|
group.long c15:0x4001++0x0
|
|
line.long 0x00 "HSCTLR,System Control Register"
|
|
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
|
|
newline
|
|
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
|
|
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
|
|
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x0 5. "CP15BEN,C15 barrier enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. "M,MMU enable" "Disabled,Enabled"
|
|
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
|
|
group.quad c15:0x10020++0x01
|
|
line.quad 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
|
|
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
|
|
newline
|
|
newline
|
|
group.quad c15:0x11020++0x01
|
|
line.quad 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
|
|
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
|
|
newline
|
|
newline
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
|
|
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
|
|
bitfld.long 0x00 22. "A1,Selects TTBR0 or TTBR1 to defines the ASID" "TTBR0,TTBR1"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
|
|
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base 0 address"
|
|
bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
|
|
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
|
|
group.long c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base 1 address"
|
|
bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
|
|
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
|
|
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
|
|
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
endif
|
|
group.quad c15:0x14020++0x01
|
|
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
|
|
hexmask.quad 0x00 1.--47. 0x02 "BADDR,Translation table base address"
|
|
group.long c15:0x4202++0x00
|
|
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
|
|
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x0003++0x00
|
|
line.long 0x00 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x01)==0x00))
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,Physical Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 "PA,Physical Address"
|
|
bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long"
|
|
newline
|
|
bitfld.long 0x00 10. "NOS,Not Outer Shareable attribute for the region" "No,Yes"
|
|
bitfld.long 0x00 9. "NS,Non-secure" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. "SH,Shareable attribute for the region" "No,Yes"
|
|
bitfld.long 0x00 4.--6. "INNER,Inner memory attributes for the region" "Non-cacheable,Device-nGnRnE,Reserved,Device-nGnRE,Reserved,Write-Back/Write-Allocate,Write-Through,Write-Back/No Write-Allocate"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "OUTER,Outer memory attributes for the region" "Non-cacheable,Write-Back/Write-Allocate,Write-Through/No Write-Allocate,Write-Back/No Write-Allocate"
|
|
bitfld.long 0x00 1. "SS,Supersection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
|
|
elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x01)==0x01))
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,Physical Address Register"
|
|
newline
|
|
bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long"
|
|
newline
|
|
bitfld.long 0x00 6. "FS[5],Fault status bit [5] - External abort type" "Internal,External"
|
|
newline
|
|
bitfld.long 0x00 1.--5. "FS[4:0],Fault status bit [4:0] - Abort source" "Reserved,Alignment,Debug,Access flag/L1,Instruction,Translation/L1,Access flag/L2,Translation/L2,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp. exclusive access,SError,Reserved,Reserved,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..."
|
|
newline
|
|
bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
|
|
elif ((((per.l(c15:0x0202))&0x80000000)==0x80000000)&&(((per.l(c15:0x10070))&0x01)==0x00))
|
|
group.quad c15:0x10070++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA"
|
|
hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address"
|
|
newline
|
|
bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" "Short,Long"
|
|
bitfld.quad 0x00 9. "NS,Non-secure" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
newline
|
|
newline
|
|
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
|
|
else
|
|
group.quad c15:0x10070++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
newline
|
|
bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" "Short,Long"
|
|
bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
|
|
newline
|
|
bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address size/TTBR,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC/on TTW/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
|
|
newline
|
|
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
|
|
endif
|
|
tree.open "Memory Attribute Indirection Registers"
|
|
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
|
|
group.long c15:0x002A++0x00
|
|
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
|
|
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
group.long c15:0x012A++0x00
|
|
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
|
|
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
group.long c15:0x010D++0x00
|
|
line.long 0x0 "CONTEXTIDR,Context ID Register"
|
|
else
|
|
group.long c15:0x002A++0x0
|
|
line.long 0x00 "PRRR,Primary Region Remap Register"
|
|
bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
newline
|
|
bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
newline
|
|
bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
newline
|
|
bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
newline
|
|
bitfld.long 0x00 19. "NS1,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 18. "NS0,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
newline
|
|
bitfld.long 0x00 17. "DS1,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. "DS0,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,?..."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,?..."
|
|
group.long c15:0x012A++0x0
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
group.long c15:0x010D++0x00
|
|
line.long 0x0 "CONTEXTIDR,Context ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier"
|
|
endif
|
|
rgroup.long c15:0x003A++0x00
|
|
line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
|
|
rgroup.long c15:0x013A++0x00
|
|
line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
|
|
rgroup.long c15:0x403A++0x00
|
|
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
|
|
rgroup.long c15:0x413A++0x00
|
|
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
|
|
tree.end
|
|
tree.end
|
|
tree "Virtualization Extensions"
|
|
group.long c15:0x4000++0x0
|
|
line.long 0x00 "VPIDR,Virtualization Processor ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code"
|
|
bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8"
|
|
hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number"
|
|
newline
|
|
bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long c15:0x4500++0x00
|
|
line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register"
|
|
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
|
|
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
|
|
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
|
|
group.long c15:0x420D++0x00
|
|
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
|
|
group.long c15:0x4001++0x0
|
|
line.long 0x00 "HSCTLR,System Control Register"
|
|
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
|
|
newline
|
|
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
|
|
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
|
|
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x0 5. "CP15BEN,C15 barrier enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. "M,MMU enable" "Disabled,Enabled"
|
|
group.long c15:0x4101++0x00
|
|
line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register"
|
|
bitfld.long 0x00 6. "L2ACTLR,L2ACTLR write access control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. "L2ECTLR,L2ECTLR write access control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "L2CTLR,L2CTLR write access control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. "CPUECTLR,CPUECTLR write access control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "CPUACTLR,CPUACTLR write access control" "Disabled,Enabled"
|
|
rgroup.long c15:0x4711++0x00
|
|
line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register"
|
|
group.long c15:0x4011++0x00
|
|
line.long 0x00 "HCR,Hypervisor Configuration Register"
|
|
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "No effect,Inner Shareable,Outer Shareable,Full system"
|
|
bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "No aborted,Aborted"
|
|
bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. "AMO,A-bit Mask Override" "No override,Override"
|
|
newline
|
|
bitfld.long 0x00 4. "IMO,I-bit Mask Override" "No override,Override"
|
|
bitfld.long 0x00 3. "FMO,F-bit Mask Override" "No override,Override"
|
|
newline
|
|
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
|
|
newline
|
|
bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
|
|
group.long c15:0x4411++0x00
|
|
line.long 0x00 "HCR2,Hypervisor Configuration Register 2"
|
|
bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes"
|
|
bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes"
|
|
group.long c15:0x4111++0x00
|
|
line.long 0x00 "HDCR,Hypervisor Debug Control Register"
|
|
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
|
|
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
|
|
newline
|
|
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
|
|
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
|
|
newline
|
|
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
|
|
newline
|
|
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
|
|
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long c15:0x4211++0x00
|
|
line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register"
|
|
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
|
|
bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped"
|
|
bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped"
|
|
group.long c15:0x4311++0x00
|
|
line.long 0x00 "HSTR,Hypervisor System Trap Register"
|
|
bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Not supported,?..."
|
|
bitfld.long 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped"
|
|
newline
|
|
bitfld.long 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped"
|
|
bitfld.long 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped"
|
|
newline
|
|
bitfld.long 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped"
|
|
bitfld.long 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped"
|
|
newline
|
|
bitfld.long 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped"
|
|
bitfld.long 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped"
|
|
newline
|
|
bitfld.long 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped"
|
|
bitfld.long 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped"
|
|
newline
|
|
bitfld.long 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped"
|
|
bitfld.long 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped"
|
|
newline
|
|
bitfld.long 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped"
|
|
bitfld.long 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped"
|
|
newline
|
|
bitfld.long 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped"
|
|
group.quad c15:0x14020++0x01
|
|
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
|
|
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
|
|
group.long c15:0x4202++0x00
|
|
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
|
|
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
|
|
group.quad c15:0x16020++0x01
|
|
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
|
|
hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table"
|
|
hexmask.quad 0x00 1.--47. 1. "BADDR,Translation table base address"
|
|
group.long c15:0x4212++0x00
|
|
line.long 0x00 "VTCR,Virtualization Translation Control Register"
|
|
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "Second,First,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High"
|
|
bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long c15:0x4006++0x00
|
|
line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register"
|
|
rgroup.long c15:0x4015++0x00
|
|
line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register"
|
|
rgroup.long c15:0x4115++0x00
|
|
line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Register"
|
|
if ((per.l(c15:0x04025)&0xFC000000)==(0x00000000||0x38000000||0x88000000))
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
elif (((per.l(c15:0x4025))&0xFC000000)==0x4000000)
|
|
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
|
|
else
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
|
|
endif
|
|
elif (((per.l(c15:0x4025))&0xFC000000)==(0xC000000||0x20000000||0x14000000))
|
|
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "OPC2,The Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 14.--16. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCR,MRC/VMRS"
|
|
else
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
bitfld.long 0x00 17.--19. "OPC2,The Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 14.--16. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCR,MRC/VMRS"
|
|
endif
|
|
elif (((per.l(c15:0x4025))&0xFC000000)==(0x10000000||0x30000000))
|
|
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--13. "RT2,The Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCRR,MRRC"
|
|
else
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--19. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--13. "RT2,The Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCRR,MRRC"
|
|
endif
|
|
elif (((per.l(c15:0x4025))&0xFC000000)==0x18000000)
|
|
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
|
|
if (((per.l(c15:0x4025))&0x08)==0x08)
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..."
|
|
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC"
|
|
else
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
bitfld.long 0x00 5.--8. "RN,The Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..."
|
|
newline
|
|
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC"
|
|
endif
|
|
else
|
|
if (((per.l(c15:0x4025))&0x08)==0x08)
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
newline
|
|
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..."
|
|
newline
|
|
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC"
|
|
else
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "RN,The Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..."
|
|
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC"
|
|
endif
|
|
endif
|
|
elif (((per.l(c15:0x4025))&0xFC000000)==0x1C000000)
|
|
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "TA,Indicates trapped use of Advanced SIMD functionality" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0.--3. "COPROC,The number of the coprocessor accessed by the trapped operation" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CP10,?..."
|
|
else
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
bitfld.long 0x00 5. "TA,Indicates trapped use of Advanced SIMD functionality" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "COPROC,The number of the coprocessor accessed by the trapped operation" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CP10,?..."
|
|
endif
|
|
elif (((per.l(c15:0x4025))&0xFC000000)==(0x44000000||0x48000000))
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
|
|
elif ((((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000))&&(((per.l(c15:0x4025))&0x3F)==0x10))
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 10. "FNV,FAR not Valid" "HIFAR valid,HIFAR invalid"
|
|
newline
|
|
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
|
|
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Reserved,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,?..."
|
|
elif ((((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000))&&(((per.l(c15:0x4025))&0x3F)!=0x10))
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
|
|
newline
|
|
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Reserved,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,?..."
|
|
elif (((per.l(c15:0x4025))&0xFD000000)==(0x91000000||0x95000000))
|
|
if (((per.l(c15:0x4025))&0x3F)==(0x11))
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
|
|
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
|
|
newline
|
|
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
|
|
bitfld.long 0x00 16.--19. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 14. "AR,Acquire/Release semantics present" "Absent,Present"
|
|
bitfld.long 0x00 10.--11. "AET,Asynchronous Error Type" "UC,UEU,UEO/CE,UER"
|
|
newline
|
|
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
|
|
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
|
|
newline
|
|
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
|
|
else
|
|
if (((per.l(c15:0x4025))&0x3F)==(0x10))
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
|
|
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
|
|
newline
|
|
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
|
|
bitfld.long 0x00 16.--19. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 14. "AR,Acquire/Release semantics present" "Absent,Present"
|
|
bitfld.long 0x00 10. "FNV,FAR not Valid" "Valid,Invalid"
|
|
newline
|
|
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
|
|
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
|
|
newline
|
|
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
|
|
else
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
|
|
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
|
|
newline
|
|
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
|
|
bitfld.long 0x00 16.--19. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 14. "AR,Acquire/Release semantics present" "Absent,Present"
|
|
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
|
|
newline
|
|
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
|
|
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
|
|
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
|
|
endif
|
|
endif
|
|
elif (((per.l(c15:0x4025))&0xFD000000)==(0x90000000||0x94000000))
|
|
if (((per.l(c15:0x4025))&0x3F)==(0x11))
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
|
|
bitfld.long 0x00 10.--11. "AET,Asynchronous Error Type" "UC,UEU,UEO/CE,UER"
|
|
newline
|
|
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
|
|
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
|
|
newline
|
|
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
|
|
else
|
|
if (((per.l(c15:0x4025))&0x3F)==(0x10))
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
|
|
bitfld.long 0x00 10. "FNV,FAR not Valid" "Valid,Invalid"
|
|
newline
|
|
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
|
|
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
|
|
newline
|
|
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
|
|
else
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
|
|
bitfld.long 0x00 9. "EA,External abort type" "Internal,External"
|
|
newline
|
|
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
|
|
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
|
|
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
|
|
endif
|
|
endif
|
|
elif (((per.l(c15:0x4025))&0xFD000000)==(0x4C000000||0x4D000000))
|
|
if (((per.l(c15:0x4025))&0xF0000)==(0x80000))
|
|
if (((per.l(c15:0x4025))&0x1000000)==(0x1000000))
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional"
|
|
else
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
|
|
bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional"
|
|
endif
|
|
else
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional"
|
|
endif
|
|
else
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hypervisor Syndrome Register"
|
|
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped SIDM/Floating point register,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
|
|
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
|
|
newline
|
|
hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome"
|
|
endif
|
|
group.long c15:0x4206++0x00
|
|
line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register"
|
|
group.long c15:0x4406++0x00
|
|
line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register"
|
|
hexmask.long 0x00 4.--31. 1. "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address"
|
|
tree.open "Hypervisor Memory Attribute Indirection Registers"
|
|
group.long c15:0x402A++0x00
|
|
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
|
|
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
group.long c15:0x412A++0x00
|
|
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
|
|
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
|
|
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
|
|
tree.end
|
|
newline
|
|
group.long c15:0x400C++0x00
|
|
line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address"
|
|
tree.end
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x0100++0x0
|
|
line.long 0x0 "CTR,Cache Type Register"
|
|
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
newline
|
|
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
|
|
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
|
|
rgroup.long c15:0x1100++0x0
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..."
|
|
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
|
|
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,No L2 cache,L1/L2 cleaned,?..."
|
|
newline
|
|
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,L2 cache not implemented,L2 cache implemented,?..."
|
|
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
|
|
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Separate I/D,?..."
|
|
rgroup.long c15:0x1000++0x0
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..."
|
|
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
|
|
bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
|
|
hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,16 words,?..."
|
|
group.long c15:0x2000++0x0
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
|
|
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
|
|
tree "Level 1 memory system"
|
|
rgroup.long c15:0x300F++0x00
|
|
line.long 0x00 "DL1DATA0,Data L1 Data 0 Register"
|
|
rgroup.long c15:0x310F++0x00
|
|
line.long 0x00 "DL1DATA1,Data L1 Data 1 Register"
|
|
rgroup.long c15:0x320F++0x00
|
|
line.long 0x00 "DL1DATA2,Data L1 Data 2 Register"
|
|
rgroup.long c15:0x330F++0x00
|
|
line.long 0x00 "DL1DATA3,Data L1 Data 3 Register"
|
|
wgroup.long c15:0x302F++0x00
|
|
line.long 0x00 "DCTROR,Data Cache Tag Read Operation Register"
|
|
wgroup.long c15:0x312F++0x00
|
|
line.long 0x00 "ICTROR,Instruction Cache Tag Read Operation Register"
|
|
wgroup.long c15:0x304F++0x00
|
|
line.long 0x00 "DCDROR,Data Cache Data Read Operation Register"
|
|
wgroup.long c15:0x314F++0x00
|
|
line.long 0x00 "ICDROR,Instruction Cache Data Read Operation Register"
|
|
wgroup.long c15:0x324F++0x00
|
|
line.long 0x00 "TLBDROR,TLB Data Read Operation Register"
|
|
tree.end
|
|
tree "Level 2 memory system"
|
|
rgroup.long c15:0x1209++0x0
|
|
line.long 0x00 "L2CTLR,L2 Control Register"
|
|
bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
|
|
bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Not implemented,ECC implemented"
|
|
bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Not implemented,ECC implemented"
|
|
newline
|
|
bitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycles"
|
|
bitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles"
|
|
group.long c15:0x1309++0x0
|
|
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
|
|
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
|
|
bitfld.long 0x00 29. "AACASYNCERR,AXI/ACE/CHI asynchronous error" "No error,Error"
|
|
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
|
|
group.long c15:0x100F++0x00
|
|
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
|
|
bitfld.long 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
|
|
if (((per.q(c15:0x130F0))&0x7F000000)==0x10000000)
|
|
group.quad c15:0x130F0++0x01
|
|
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--21. "C/W,Indicates the RAM where the first memory error occurred" "Way 0,Way 1,Way 2,Way 3,Way 4,Way 5,Way 6,Way 7,?..."
|
|
newline
|
|
hexmask.quad.tbyte 0x00 3.--16. 0x08 "RAD,RAM address"
|
|
elif (((per.q(c15:0x130F0))&0x7F000000)==0x11000000)
|
|
group.quad c15:0x130F0++0x01
|
|
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--21. "C/W,Indicates the RAM where the first memory error occurred" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7,?..."
|
|
newline
|
|
hexmask.quad.tbyte 0x00 3.--16. 0x08 "RAD,RAM address"
|
|
elif (((per.q(c15:0x130F0))&0x7F000000)==0x12000000)
|
|
group.quad c15:0x130F0++0x01
|
|
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
bitfld.quad 0x00 18.--21. "C/W,Indicates the RAM where the first memory error occurred" "CPU0/Way 0,CPU0/Way 1,CPU0/Way 2,CPU0/Way 3,CPU1/Way 0,CPU1/Way 1,CPU1/Way 2,CPU1/Way 3,CPU2/Way 0,CPU2/Way 1,CPU2/Way 2,CPU2/Way 3,CPU3/Way 0,CPU3/Way 1,CPU3/Way 2,CPU3/Way 3"
|
|
newline
|
|
hexmask.quad.tbyte 0x00 3.--16. 0x08 "RAD,RAM address"
|
|
else
|
|
group.quad c15:0x130F0++0x01
|
|
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
|
|
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
|
|
newline
|
|
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
|
|
newline
|
|
hexmask.quad.tbyte 0x00 3.--16. 0x08 "RAD,RAM address"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "System Performance Monitor"
|
|
group.long c15:0x00c9++0x00
|
|
line.long 0x00 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
|
|
bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
|
|
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,?..."
|
|
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
|
|
group.long c15:0x01c9++0x00
|
|
line.long 0x00 "PMCNTENSET,Count Enable Set Register "
|
|
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
|
|
group.long c15:0x02c9++0x00
|
|
line.long 0x00 "PMCNTENCLR,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled"
|
|
newline
|
|
eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled"
|
|
group.long c15:0x03c9++0x00
|
|
line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register"
|
|
eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
|
|
newline
|
|
eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
|
|
wgroup.long c15:0x04c9++0x00
|
|
line.long 0x00 "PMSWINC,Performance Monitor Software Increment"
|
|
bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment"
|
|
bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment"
|
|
bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment"
|
|
bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment"
|
|
newline
|
|
bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment"
|
|
bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x05c9++0x00
|
|
line.long 0x00 "PMSELR,Performance Monitor Select Register"
|
|
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.open "Common Event Identification Registers"
|
|
rgroup.long c15:0x06C9++0x00
|
|
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
|
|
bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,?..."
|
|
bitfld.long 0x00 30. "EVENT30,Chain" "Reserved,Implemented"
|
|
newline
|
|
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Reserved,Implemented"
|
|
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,?..."
|
|
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Reserved,Implemented"
|
|
newline
|
|
bitfld.long 0x00 26. "EVENT26,Local memory error" "Reserved,Implemented"
|
|
bitfld.long 0x00 25. "EVENT25,Bus access" "Reserved,Implemented"
|
|
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
|
|
newline
|
|
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Reserved,Implemented"
|
|
newline
|
|
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Reserved,Implemented"
|
|
bitfld.long 0x00 19. "EVENT19,Data memory access" "Reserved,Implemented"
|
|
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Reserved,Implemented"
|
|
newline
|
|
bitfld.long 0x00 17. "EVENT17,Cycle" "Reserved,Implemented"
|
|
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Reserved,Implemented"
|
|
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Reserved,Implemented"
|
|
newline
|
|
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,?..."
|
|
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Reserved,Implemented"
|
|
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Reserved,Implemented"
|
|
newline
|
|
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Reserved,Implemented"
|
|
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Reserved,Implemented"
|
|
bitfld.long 0x00 9. "EVENT9,Exception taken" "Reserved,Implemented"
|
|
newline
|
|
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Reserved,Implemented"
|
|
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Reserved,Implemented"
|
|
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Reserved,Implemented"
|
|
newline
|
|
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Reserved,Implemented"
|
|
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Reserved,Implemented"
|
|
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Reserved,Implemented"
|
|
newline
|
|
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Reserved,Implemented"
|
|
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Reserved,Implemented"
|
|
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Reserved,Implemented"
|
|
rgroup.long c15:0x07C9++0x0
|
|
line.long 0x00 "PMCEID1,Common Event Identification Register 1"
|
|
bitfld.long 0x00 16. "EVENT48,Attributable Level 2 instruction TLB access" "Not implemented,?..."
|
|
bitfld.long 0x00 15. "EVENT47,Attributable Level 2 data or unified TLB access" "Not implemented,?..."
|
|
bitfld.long 0x00 14. "EVENT46,Attributable Level 2 instruction TLB refill" "Not implemented,?..."
|
|
newline
|
|
bitfld.long 0x00 13. "EVENT45,Attributable Level 2 data or unified TLB refill" "Not implemented,?..."
|
|
bitfld.long 0x00 12. "EVENT44,Attributable Level 3 data or unified cache write-back" "Not implemented,?..."
|
|
bitfld.long 0x00 11. "EVENT43,Attributable Level 3 data or unified cache access" "Not implemented,?..."
|
|
newline
|
|
bitfld.long 0x00 10. "EVENT42,Attributable Level 3 data or unified cache refill" "Not implemented,?..."
|
|
bitfld.long 0x00 9. "EVENT41,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,?..."
|
|
bitfld.long 0x00 8. "EVENT40,Attributable Level 2 instruction cache refill" "Not implemented,?..."
|
|
newline
|
|
bitfld.long 0x00 7. "EVENT39,Attributable Level 2 instruction cache access" "Not implemented,?..."
|
|
bitfld.long 0x00 6. "EVENT38,Level 1 instruction TLB access" "Not implemented,?..."
|
|
bitfld.long 0x00 5. "EVENT37,Level 1 data or unified TLB access" "Not implemented,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "EVENT36,No operation issued due to backend" "Not implemented,?..."
|
|
bitfld.long 0x00 3. "EVENT35,No operation issued due to the frontend" "Not implemented,?..."
|
|
bitfld.long 0x00 2. "EVENT34,Instruction architecturally executed mispredicted branch" "Not implemented,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "EVENT33,Instruction architecturally executed branch" "Not implemented,?..."
|
|
bitfld.long 0x00 0. "EVENT32,Level 2 data cache allocation without refill" "Not implemented,?..."
|
|
tree.end
|
|
newline
|
|
if (((per.q(c15:0x00c9))&0x40)==0x40)
|
|
group.quad c15:0x10090++0x01
|
|
line.quad 0x00 "PMCCNTR,Performance Monitor Cycle Count Register"
|
|
else
|
|
group.long c15:0x00d9++0x00
|
|
line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register"
|
|
endif
|
|
if (((per.q(c15:0x05c9))&0x1F)==0x1F)
|
|
group.long c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register"
|
|
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
else
|
|
group.long c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register"
|
|
endif
|
|
group.long c15:0x02d9++0x00
|
|
line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register"
|
|
group.long c15:0x00e9++0x00
|
|
line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register"
|
|
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
|
|
group.long c15:0x01e9++0x00
|
|
line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set"
|
|
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.long c15:0x02e9++0x00
|
|
line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear"
|
|
eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
newline
|
|
eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
group.long c15:0x03e9++0x00
|
|
line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register"
|
|
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.long c15:0x8E++0x00
|
|
line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0"
|
|
group.long c15:(0x8E+0x40)++0x00
|
|
line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0"
|
|
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
group.long c15:0x18E++0x00
|
|
line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1"
|
|
group.long c15:(0x18E+0x40)++0x00
|
|
line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1"
|
|
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
group.long c15:0x28E++0x00
|
|
line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2"
|
|
group.long c15:(0x28E+0x40)++0x00
|
|
line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2"
|
|
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
group.long c15:0x38E++0x00
|
|
line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3"
|
|
group.long c15:(0x38E+0x40)++0x00
|
|
line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3"
|
|
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
group.long c15:0x48E++0x00
|
|
line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4"
|
|
group.long c15:(0x48E+0x40)++0x00
|
|
line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4"
|
|
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
group.long c15:0x58E++0x00
|
|
line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5"
|
|
group.long c15:(0x58E+0x40)++0x00
|
|
line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5"
|
|
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
|
|
group.long c15:0x07FE++0x00
|
|
line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register"
|
|
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "System Timer Registers"
|
|
group.long c15:0x000E++0x00
|
|
line.long 0x00 "CNTFRQ,Counter Frequency Register"
|
|
rgroup.quad c15:0x100E0++0x01
|
|
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
|
|
group.long c15:0x001E++0x00
|
|
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
|
|
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
|
|
newline
|
|
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter CNTVCT and the frequency register CNTFRQ are accessible from EL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter CNTPCT and the frequency register CNTFRQ are accessible from EL0 modes" "Not accessible,Accessible"
|
|
group.long c15:0x002E++0x00
|
|
line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register"
|
|
if (((per.q(c15:0x012E))&0x01)==0x01)
|
|
group.long c15:0x012E++0x00
|
|
line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register"
|
|
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
|
|
else
|
|
group.long c15:0x012E++0x00
|
|
line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register"
|
|
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
|
|
endif
|
|
group.long c15:0x003E++0x00
|
|
line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register"
|
|
if (((per.q(c15:0x013E))&0x01)==0x01)
|
|
group.long c15:0x013E++0x00
|
|
line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register"
|
|
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
|
|
else
|
|
group.long c15:0x013E++0x00
|
|
line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register"
|
|
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
|
|
endif
|
|
group.quad c15:0x110E0++0x01
|
|
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
|
|
group.quad c15:0x120E0++0x01
|
|
line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register"
|
|
group.quad c15:0x130E0++0x01
|
|
line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register"
|
|
group.quad c15:0x140E0++0x01
|
|
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
|
|
group.long c15:0x401E++0x00
|
|
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
|
|
bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter CNTPCT is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
|
|
group.long c15:0x402E++0x00
|
|
line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register"
|
|
if (((per.q(c15:0x412E))&0x01)==0x01)
|
|
group.long c15:0x412E++0x00
|
|
line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register"
|
|
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
|
|
else
|
|
group.long c15:0x412E++0x00
|
|
line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register"
|
|
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
|
|
endif
|
|
group.quad c15:0x160E0++0x01
|
|
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register"
|
|
tree.end
|
|
tree "Generic Interrupt Controller System Registers"
|
|
tree "AArch32 GIC Physical CPU Interface System Registers"
|
|
tree.open "Interrupt Controller Active Priorities Registers"
|
|
group.long c15:0x048C++0x00
|
|
line.long 0x00 "ICC_AP0R0,Active Priorities 0 Register 0"
|
|
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
|
|
group.long c15:0x009C++0x00
|
|
line.long 0x00 "ICC_AP1R0,Active Priorities 1 Register 0"
|
|
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
|
|
tree.end
|
|
newline
|
|
if (((per.q(c15:0x110C0))&0x10000000000)==0x00)
|
|
wgroup.quad c15:0x110C0++0x01
|
|
line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1"
|
|
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list,All PEs excluding self"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
|
|
bitfld.quad 0x00 24.--27. "INTID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
|
|
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
|
|
else
|
|
wgroup.quad c15:0x110C0++0x01
|
|
line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list,All PEs excluding self"
|
|
newline
|
|
bitfld.quad 0x00 24.--27. "INTID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
endif
|
|
group.long c15:0x038C++0x00
|
|
line.long 0x00 "ICC_BPR0,Binary Point Register 0"
|
|
bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt priority field control and interrupt preemption control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
|
|
group.long c15:0x03CC++0x00
|
|
line.long 0x00 "ICC_BPR1,Binary Point Register 1"
|
|
bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt priority field control and interrupt preemption control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
|
|
group.long c15:0x04CC++0x00
|
|
line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1"
|
|
rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported"
|
|
rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
|
|
newline
|
|
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
|
|
rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported"
|
|
rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
|
|
newline
|
|
rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1"
|
|
group.long c15:0x64CC++0x00
|
|
line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3"
|
|
rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported"
|
|
rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
|
|
newline
|
|
rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
|
|
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
|
|
rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
|
|
newline
|
|
rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
|
|
rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register"
|
|
bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register"
|
|
if (((per.q(c15:0x04CC))&0x3800)==0x0000)
|
|
wgroup.long c15:0x01BC++0x00
|
|
line.long 0x00 "ICC_DIR,Deactivate Interrupt Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
|
|
wgroup.long c15:0x018C++0x00
|
|
line.long 0x00 "ICC_EOIR0,End Of Interrupt Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
|
|
wgroup.long c15:0x01CC++0x00
|
|
line.long 0x00 "ICC_EOIR1,End Of Interrupt Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access."
|
|
rgroup.long c15:0x028C++0x00
|
|
line.long 0x00 "ICC_HPPIR0,Highest Prioity Pending Interrupt Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
|
|
rgroup.long c15:0x02CC++0x00
|
|
line.long 0x00 "ICC_HPPIR1,Highest Prioity Pending Interrupt Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
|
|
else
|
|
wgroup.long c15:0x01BC++0x00
|
|
line.long 0x00 "ICC_DIR,Deactivate Interrupt Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
|
|
wgroup.long c15:0x018C++0x00
|
|
line.long 0x00 "ICC_EOIR0,End Of Interrupt Register 0"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
|
|
wgroup.long c15:0x01CC++0x00
|
|
line.long 0x00 "ICC_EOIR1,End Of Interrupt Register 1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access."
|
|
rgroup.long c15:0x028C++0x00
|
|
line.long 0x00 "ICC_HPPIR0,Highest Prioity Pending Interrupt Register 0"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt"
|
|
rgroup.long c15:0x02CC++0x00
|
|
line.long 0x00 "ICC_HPPIR1,Highest Prioity Pending Interrupt Register 1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt"
|
|
endif
|
|
hgroup.long c15:0x008C++0x00
|
|
hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0"
|
|
in
|
|
hgroup.long c15:0x00CC++0x00
|
|
hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1"
|
|
in
|
|
group.long c15:0x06CC++0x00
|
|
line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0"
|
|
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
|
|
group.long c15:0x07CC++0x00
|
|
line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1"
|
|
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
|
|
group.long c15:0x0064++0x00
|
|
line.long 0x00 "ICC_PMR,Priority Mask Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
|
|
rgroup.long c15:0x03BC++0x00
|
|
line.long 0x00 "ICC_RPR,Running Priority Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
|
|
if (((per.q(c15:0x120C0))&0x10000000000)==0x00)
|
|
wgroup.quad c15:0x120C0++0x01
|
|
line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0"
|
|
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list,All PEs excluding self"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
|
|
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
|
|
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
|
|
else
|
|
wgroup.quad c15:0x120C0++0x01
|
|
line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list,All PEs excluding self"
|
|
newline
|
|
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
endif
|
|
if (((per.q(c15:0x100C0))&0x10000000000)==0x00)
|
|
wgroup.quad c15:0x100C0++0x01
|
|
line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1"
|
|
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list,All PEs excluding self"
|
|
newline
|
|
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
|
|
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
|
|
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
|
|
else
|
|
wgroup.quad c15:0x100C0++0x01
|
|
line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1"
|
|
newline
|
|
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list,All PEs excluding self"
|
|
newline
|
|
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
endif
|
|
group.long c15:0x05CC++0x00
|
|
line.long 0x00 "ICC_SRE,System Register Enable Register for EL1"
|
|
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
|
|
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
|
|
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
|
|
group.long c15:0x459C++0x00
|
|
line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2"
|
|
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
|
|
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
|
|
group.long c15:0x65CC++0x00
|
|
line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3"
|
|
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
|
|
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
|
|
group.long c15:0x67CC++0x00
|
|
line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable"
|
|
bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
|
|
tree.end
|
|
tree "AArch32 Virtual Interface Control System Registers"
|
|
tree.open "Hypervisor Active Priorities Registers"
|
|
group.long c15:0x408C++0x00
|
|
line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
|
|
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
|
|
group.long c15:0x409C++0x00
|
|
line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
|
|
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
|
|
tree.end
|
|
newline
|
|
rgroup.long c15:0x438C++0x00
|
|
line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register"
|
|
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
|
|
rgroup.long c15:0x458C++0x00
|
|
line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register"
|
|
bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
|
|
bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
|
|
bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
|
|
if (((per.q(c15:0x41BC))&0x480000)==0x480000)
|
|
group.long c15:0x40BC++0x00
|
|
line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register"
|
|
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
|
|
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
|
|
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
|
|
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
|
|
elif (((per.q(c15:0x41BC))&0x480000)==0x080000)
|
|
group.long c15:0x40BC++0x00
|
|
line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register"
|
|
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
|
|
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
|
|
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
|
|
elif (((per.q(c15:0x41BC))&0x480000)==0x400000)
|
|
group.long c15:0x40BC++0x00
|
|
line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register"
|
|
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
|
|
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
|
|
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
|
|
else
|
|
group.long c15:0x40BC++0x00
|
|
line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register"
|
|
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
|
|
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
|
|
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
|
|
newline
|
|
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
|
|
endif
|
|
group.long c15:(0x40CC+0x0)++0x00
|
|
line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0"
|
|
group.long c15:(0x40CC+0x100)++0x00
|
|
line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1"
|
|
group.long c15:(0x40CC+0x200)++0x00
|
|
line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2"
|
|
group.long c15:(0x40CC+0x300)++0x00
|
|
line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3"
|
|
if (((per.q(c15:0x40EC+0x0))&0x20000000)==0x20000000)
|
|
group.long c15:(0x40EC+0x0)++0x00
|
|
line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0"
|
|
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt"
|
|
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
|
|
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
|
|
else
|
|
group.long c15:(0x40EC+0x0)++0x00
|
|
line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0"
|
|
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt"
|
|
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
|
|
bitfld.long 0x00 9. "EOI,Asserted EOI maintenance interrupt" "Not asserted,Asserted"
|
|
endif
|
|
if (((per.q(c15:0x40EC+0x100))&0x20000000)==0x20000000)
|
|
group.long c15:(0x40EC+0x100)++0x00
|
|
line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1"
|
|
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt"
|
|
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
|
|
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
|
|
else
|
|
group.long c15:(0x40EC+0x100)++0x00
|
|
line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1"
|
|
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt"
|
|
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
|
|
bitfld.long 0x00 9. "EOI,Asserted EOI maintenance interrupt" "Not asserted,Asserted"
|
|
endif
|
|
if (((per.q(c15:0x40EC+0x200))&0x20000000)==0x20000000)
|
|
group.long c15:(0x40EC+0x200)++0x00
|
|
line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2"
|
|
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt"
|
|
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
|
|
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
|
|
else
|
|
group.long c15:(0x40EC+0x200)++0x00
|
|
line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2"
|
|
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt"
|
|
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
|
|
bitfld.long 0x00 9. "EOI,Asserted EOI maintenance interrupt" "Not asserted,Asserted"
|
|
endif
|
|
if (((per.q(c15:0x40EC+0x300))&0x20000000)==0x20000000)
|
|
group.long c15:(0x40EC+0x300)++0x00
|
|
line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3"
|
|
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt"
|
|
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
|
|
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
|
|
else
|
|
group.long c15:(0x40EC+0x300)++0x00
|
|
line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3"
|
|
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
|
|
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Triggered by Software,Hardware interrupt"
|
|
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
|
|
bitfld.long 0x00 9. "EOI,Asserted EOI maintenance interrupt" "Not asserted,Asserted"
|
|
endif
|
|
rgroup.long c15:0x42BC++0x00
|
|
line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register"
|
|
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
|
|
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
|
|
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
|
|
newline
|
|
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
|
|
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
|
|
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
|
|
newline
|
|
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
|
|
group.long c15:0x478C++0x00
|
|
line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
|
|
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
|
|
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register Group 1" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
|
|
newline
|
|
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
|
|
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
|
|
newline
|
|
bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
|
|
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
|
|
group.long c15:0x449C++0x00
|
|
line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register"
|
|
group.long c15:0x41BC++0x00
|
|
line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register"
|
|
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented minus one" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
|
|
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
|
|
newline
|
|
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
|
|
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree.end
|
|
tree "Debug Registers"
|
|
tree "Coresight Management Registers"
|
|
rgroup.long c14:0x0000++0x00
|
|
line.long 0x00 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x00 28.--31. "WRP,Number of Watchpoint Register Pairs" "Reserved,Reserved,Reserved,4,?..."
|
|
bitfld.long 0x00 24.--27. "BRP,Number of Breakpoint Register Pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
|
|
bitfld.long 0x00 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "Reserved,Two context,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 16.--19. 1. "VERSION,Debug Architecture Version"
|
|
bitfld.long 0x00 14. "NSUHD,Secure User halting debug-mode" "Reserved,Not supported"
|
|
bitfld.long 0x00 12. "SE,Security Extensions implemented" "Reserved,Implemented"
|
|
rgroup.long c14:0x0060++0x00
|
|
line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register"
|
|
group.long c14:0x0070++0x00
|
|
line.long 0x00 "DBGVCR,Debug Vector Catch register"
|
|
bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "IRQVCE_NS,IRQ vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
|
|
group.long c14:0x0020++0x000
|
|
line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register"
|
|
bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled"
|
|
group.long c14:0x0200++0x00
|
|
line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)"
|
|
if (((per.l(c14:0x0411))&0x02)==0x02)
|
|
group.long c14:0x0220++0x00
|
|
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. "INTDIS,Used for save/restore of EDSCR.INTdis" "Don't disabled interrupts,Disabled interrupts targeting non-sec EL1,Disabled all interrupts,Disabled all interrupts"
|
|
bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
|
|
rbitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
rbitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
|
|
else
|
|
group.long c14:0x0220++0x00
|
|
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
|
|
rbitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22.--23. "INTDIS,Used for save/restore of EDSCR.INTdis" "Don't disabled interrupts,Disabled interrupts targeting non-sec EL1,Disabled all interrupts,Disabled all interrupts"
|
|
rbitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
|
|
rbitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
rbitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
|
|
endif
|
|
rgroup.long c14:0x0010++0x00
|
|
line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)"
|
|
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
|
|
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
|
|
group.long c14:0x0230++0x00
|
|
line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)"
|
|
rgroup.long c14:0x0050++0x00
|
|
line.long 0x00 "DBGDTRTXINT,Debug Transmit Register (Internal View)"
|
|
wgroup.long c14:0x0050++0x00
|
|
line.long 0x00 "DBGDTRRXINT,Debug Receive Register (Internal View)"
|
|
group.long c14:0x0687++0x00
|
|
line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x00 7. "CT7,Claim Tag 7 Set" "Not set,Set"
|
|
bitfld.long 0x00 6. "CT6,Claim Tag 6 Set" "Not set,Set"
|
|
bitfld.long 0x00 5. "CT5,Claim Tag 5 Set" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 4. "CT4,Claim Tag 4 Set" "Not set,Set"
|
|
bitfld.long 0x00 3. "CT3,Claim Tag 3 Set" "Not set,Set"
|
|
bitfld.long 0x00 2. "CT2,Claim Tag 2 Set" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. "CT1,Claim Tag 1 Set" "Not set,Set"
|
|
bitfld.long 0x00 0. "CT0,Claim Tag 0 Set" "Not set,Set"
|
|
group.long c14:0x0697++0x00
|
|
line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
|
|
rgroup.long c14:0x06E7++0x00
|
|
line.long 0x00 "DBGAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. "SNDFI,Secure non-invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 6. "SNDE,Secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. "SIDFI,Secure invasive debug features implementation" "No effect,Implemented"
|
|
newline
|
|
bitfld.long 0x00 4. "SIDE,Secure invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. "NSNDFI,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. "NSNDE,Non-secure non-invasive debug enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "NSIDFI,Non-secure invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. "NSIDE,Non-secure invasive debug enable" "0,1"
|
|
rgroup.long c14:0x0707++0x00
|
|
line.long 0x00 "DBGDEVID2,Debug Device ID Register 2"
|
|
rgroup.long c14:0x0717++0x00
|
|
line.long 0x00 "DBGDEVID1,Debug Device ID Register 1"
|
|
bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" "0,1,No offset,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long c14:0x0727++0x000
|
|
line.long 0x00 "DBGDEVID,Debug Device ID Register 0"
|
|
bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..."
|
|
bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" "Not implemented,?..."
|
|
bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..."
|
|
bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..."
|
|
bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
|
|
bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..."
|
|
tree.end
|
|
newline
|
|
rgroup.quad c14:0x10010++0x001
|
|
line.quad 0x00 "DBGDRAR,Debug ROM Address Register"
|
|
hexmask.quad.word 0x00 32.--47. 0x1 "ROMADDR,ROM physical address"
|
|
hexmask.quad.tbyte 0x00 12.--31. 0x10 "ROMADDR,ROM physical address"
|
|
bitfld.quad 0x00 1. "VALID1,ROM table address valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.quad 0x00 0. "VALID0,ROM table address valid" "Not valid,Valid"
|
|
rgroup.quad c14:0x10020++0x001
|
|
line.quad 0x00 "DBGDSAR,Debug Self Address Offset Register"
|
|
wgroup.long c14:0x0401++0x000
|
|
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
|
|
rgroup.long c14:0x0411++0x000
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,?..."
|
|
bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..."
|
|
if (((per.l(c14:0x0411))&0x2)==0x02)
|
|
group.long c14:0x0260++0x000
|
|
line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
|
|
else
|
|
rgroup.long c14:0x0260++0x000
|
|
line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
|
|
endif
|
|
group.long c14:0x0431++0x000
|
|
line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register"
|
|
bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked"
|
|
group.long c14:0x0441++0x000
|
|
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Low,High"
|
|
tree.end
|
|
tree "Breakpoint Registers"
|
|
if (((per.l(c14:0x500+0x0))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
|
|
group.long c14:(0x0400+0x0)++0x000 "Breakpoint 0"
|
|
line.long 0x00 "DBGBVR0,Breakpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison"
|
|
elif (((per.l(c14:0x500+0x0))&0xF00000)==(0x600000||0x700000||0x800000||0x900000||0xC00000||0xD00000||0xE00000||0xF00000))
|
|
rgroup.long c14:(0x0400+0x0)++0x000 "Breakpoint 0"
|
|
line.long 0x00 "DBGBVR0,Breakpoint Value Register"
|
|
else
|
|
group.long c14:(0x0400+0x0)++0x000 "Breakpoint 0"
|
|
line.long 0x00 "DBGBVR0,Breakpoint Value Register"
|
|
endif
|
|
if (((per.l(c14:0x0500+0x0))&0x2000)==0x2000)
|
|
if (((per.l(c14:0x0500+0x0))&0xC000)==0xC000)
|
|
group.long c14:(0x0500+0x0)++0x00
|
|
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 0 is generated" "Supervisor,?..."
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.l(c14:0x0500+0x0))&0xC000)==0x8000)
|
|
group.long c14:(0x0500+0x0)++0x00
|
|
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 0 is generated" "Reserved,System,Reserved,User/System"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.long c14:(0x0500+0x0)++0x00
|
|
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 0 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long c14:(0x0500+0x0)++0x00
|
|
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 0 is generated" "User/System,System,User,User/System"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(c14:0x500+0x10))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
|
|
group.long c14:(0x0400+0x10)++0x000 "Breakpoint 1"
|
|
line.long 0x00 "DBGBVR1,Breakpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison"
|
|
elif (((per.l(c14:0x500+0x10))&0xF00000)==(0x600000||0x700000||0x800000||0x900000||0xC00000||0xD00000||0xE00000||0xF00000))
|
|
rgroup.long c14:(0x0400+0x10)++0x000 "Breakpoint 1"
|
|
line.long 0x00 "DBGBVR1,Breakpoint Value Register"
|
|
else
|
|
group.long c14:(0x0400+0x10)++0x000 "Breakpoint 1"
|
|
line.long 0x00 "DBGBVR1,Breakpoint Value Register"
|
|
endif
|
|
if (((per.l(c14:0x0500+0x10))&0x2000)==0x2000)
|
|
if (((per.l(c14:0x0500+0x10))&0xC000)==0xC000)
|
|
group.long c14:(0x0500+0x10)++0x00
|
|
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 1 is generated" "Supervisor,?..."
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.l(c14:0x0500+0x10))&0xC000)==0x8000)
|
|
group.long c14:(0x0500+0x10)++0x00
|
|
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 1 is generated" "Reserved,System,Reserved,User/System"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.long c14:(0x0500+0x10)++0x00
|
|
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 1 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long c14:(0x0500+0x10)++0x00
|
|
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 1 is generated" "User/System,System,User,User/System"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(c14:0x500+0x20))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
|
|
group.long c14:(0x0400+0x20)++0x000 "Breakpoint 2"
|
|
line.long 0x00 "DBGBVR2,Breakpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison"
|
|
elif (((per.l(c14:0x500+0x20))&0xF00000)==(0x600000||0x700000||0x800000||0x900000||0xC00000||0xD00000||0xE00000||0xF00000))
|
|
rgroup.long c14:(0x0400+0x20)++0x000 "Breakpoint 2"
|
|
line.long 0x00 "DBGBVR2,Breakpoint Value Register"
|
|
else
|
|
group.long c14:(0x0400+0x20)++0x000 "Breakpoint 2"
|
|
line.long 0x00 "DBGBVR2,Breakpoint Value Register"
|
|
endif
|
|
if (((per.l(c14:0x0500+0x20))&0x2000)==0x2000)
|
|
if (((per.l(c14:0x0500+0x20))&0xC000)==0xC000)
|
|
group.long c14:(0x0500+0x20)++0x00
|
|
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 2 is generated" "Supervisor,?..."
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.l(c14:0x0500+0x20))&0xC000)==0x8000)
|
|
group.long c14:(0x0500+0x20)++0x00
|
|
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 2 is generated" "Reserved,System,Reserved,User/System"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.long c14:(0x0500+0x20)++0x00
|
|
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 2 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long c14:(0x0500+0x20)++0x00
|
|
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 2 is generated" "User/System,System,User,User/System"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(c14:0x500+0x30))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
|
|
group.long c14:(0x0400+0x30)++0x000 "Breakpoint 3"
|
|
line.long 0x00 "DBGBVR3,Breakpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison"
|
|
elif (((per.l(c14:0x500+0x30))&0xF00000)==(0x600000||0x700000||0x800000||0x900000||0xC00000||0xD00000||0xE00000||0xF00000))
|
|
rgroup.long c14:(0x0400+0x30)++0x000 "Breakpoint 3"
|
|
line.long 0x00 "DBGBVR3,Breakpoint Value Register"
|
|
else
|
|
group.long c14:(0x0400+0x30)++0x000 "Breakpoint 3"
|
|
line.long 0x00 "DBGBVR3,Breakpoint Value Register"
|
|
endif
|
|
if (((per.l(c14:0x0500+0x30))&0x2000)==0x2000)
|
|
if (((per.l(c14:0x0500+0x30))&0xC000)==0xC000)
|
|
group.long c14:(0x0500+0x30)++0x00
|
|
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 3 is generated" "Supervisor,?..."
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.l(c14:0x0500+0x30))&0xC000)==0x8000)
|
|
group.long c14:(0x0500+0x30)++0x00
|
|
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 3 is generated" "Reserved,System,Reserved,User/System"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.long c14:(0x0500+0x30)++0x00
|
|
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 3 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long c14:(0x0500+0x30)++0x00
|
|
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 3 is generated" "User/System,System,User,User/System"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(c14:0x500+0x40))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
|
|
group.long c14:(0x0400+0x40)++0x000 "Breakpoint 4"
|
|
line.long 0x00 "DBGBVR4,Breakpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison"
|
|
elif (((per.l(c14:0x500+0x40))&0xF00000)==(0x600000||0x700000||0x800000||0x900000||0xC00000||0xD00000||0xE00000||0xF00000))
|
|
rgroup.long c14:(0x0400+0x40)++0x000 "Breakpoint 4"
|
|
line.long 0x00 "DBGBVR4,Breakpoint Value Register"
|
|
else
|
|
group.long c14:(0x0400+0x40)++0x000 "Breakpoint 4"
|
|
line.long 0x00 "DBGBVR4,Breakpoint Value Register"
|
|
endif
|
|
if (((per.l(c14:0x0500+0x40))&0x2000)==0x2000)
|
|
if (((per.l(c14:0x0500+0x40))&0xC000)==0xC000)
|
|
group.long c14:(0x0500+0x40)++0x00
|
|
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 4 is generated" "Supervisor,?..."
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.l(c14:0x0500+0x40))&0xC000)==0x8000)
|
|
group.long c14:(0x0500+0x40)++0x00
|
|
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 4 is generated" "Reserved,System,Reserved,User/System"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.long c14:(0x0500+0x40)++0x00
|
|
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 4 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long c14:(0x0500+0x40)++0x00
|
|
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 4 is generated" "User/System,System,User,User/System"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(c14:0x500+0x50))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
|
|
group.long c14:(0x0400+0x50)++0x000 "Breakpoint 5"
|
|
line.long 0x00 "DBGBVR5,Breakpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison"
|
|
elif (((per.l(c14:0x500+0x50))&0xF00000)==(0x600000||0x700000||0x800000||0x900000||0xC00000||0xD00000||0xE00000||0xF00000))
|
|
rgroup.long c14:(0x0400+0x50)++0x000 "Breakpoint 5"
|
|
line.long 0x00 "DBGBVR5,Breakpoint Value Register"
|
|
else
|
|
group.long c14:(0x0400+0x50)++0x000 "Breakpoint 5"
|
|
line.long 0x00 "DBGBVR5,Breakpoint Value Register"
|
|
endif
|
|
if (((per.l(c14:0x0500+0x50))&0x2000)==0x2000)
|
|
if (((per.l(c14:0x0500+0x50))&0xC000)==0xC000)
|
|
group.long c14:(0x0500+0x50)++0x00
|
|
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 5 is generated" "Supervisor,?..."
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
elif (((per.l(c14:0x0500+0x50))&0xC000)==0x8000)
|
|
group.long c14:(0x0500+0x50)++0x00
|
|
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 5 is generated" "Reserved,System,Reserved,User/System"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.long c14:(0x0500+0x50)++0x00
|
|
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 5 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long c14:(0x0500+0x50)++0x00
|
|
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
|
|
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
|
|
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
|
|
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--8. "BAS,Byte 3 address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
|
|
bitfld.long 0x00 1.--2. "PMC,Determines the Exception level or levels at which a breakpoint debug event for breakpoint 5 is generated" "User/System,System,User,User/System"
|
|
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:0x0141++0x00
|
|
line.long 0x00 "DBGBXVR4,Debug Breakpoint Extended Value Register 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. "VMID,VMID value"
|
|
group.long c14:0x0151++0x00
|
|
line.long 0x00 "DBGBXVR5,Debug Breakpoint Extended Value Register 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. "VMID,VMID value"
|
|
tree.end
|
|
tree "Watchpoint Control Registers"
|
|
group.long c14:(0x0600+0x0)++0x000 "Watchpoint 0"
|
|
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
|
|
if (((per.l(c14:0x0700+0x0))&0x2000)==0x2000)
|
|
if (((per.l(c14:0x0700+0x0))&0xC000)==0xC000)
|
|
group.long c14:(0x0700+0x0)++0x000
|
|
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 0 is generated" "Supervisor,?..."
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
elif (((per.l(c14:0x0700+0x0))&0x8000)==0x8000)
|
|
group.long c14:(0x0700+0x0)++0x000
|
|
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 0 is generated" "Reserved,System,Reserved,User/System"
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.long c14:(0x0700+0x0)++0x000
|
|
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 0 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long c14:(0x0700+0x0)++0x000
|
|
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 0 is generated" "Reserved,System,User,User/System"
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(0x0600+0x10)++0x000 "Watchpoint 1"
|
|
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
|
|
if (((per.l(c14:0x0700+0x10))&0x2000)==0x2000)
|
|
if (((per.l(c14:0x0700+0x10))&0xC000)==0xC000)
|
|
group.long c14:(0x0700+0x10)++0x000
|
|
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 1 is generated" "Supervisor,?..."
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
elif (((per.l(c14:0x0700+0x10))&0x8000)==0x8000)
|
|
group.long c14:(0x0700+0x10)++0x000
|
|
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 1 is generated" "Reserved,System,Reserved,User/System"
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.long c14:(0x0700+0x10)++0x000
|
|
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 1 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long c14:(0x0700+0x10)++0x000
|
|
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 1 is generated" "Reserved,System,User,User/System"
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(0x0600+0x20)++0x000 "Watchpoint 2"
|
|
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
|
|
if (((per.l(c14:0x0700+0x20))&0x2000)==0x2000)
|
|
if (((per.l(c14:0x0700+0x20))&0xC000)==0xC000)
|
|
group.long c14:(0x0700+0x20)++0x000
|
|
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 2 is generated" "Supervisor,?..."
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
elif (((per.l(c14:0x0700+0x20))&0x8000)==0x8000)
|
|
group.long c14:(0x0700+0x20)++0x000
|
|
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 2 is generated" "Reserved,System,Reserved,User/System"
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.long c14:(0x0700+0x20)++0x000
|
|
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 2 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long c14:(0x0700+0x20)++0x000
|
|
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 2 is generated" "Reserved,System,User,User/System"
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(0x0600+0x30)++0x000 "Watchpoint 3"
|
|
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
|
|
if (((per.l(c14:0x0700+0x30))&0x2000)==0x2000)
|
|
if (((per.l(c14:0x0700+0x30))&0xC000)==0xC000)
|
|
group.long c14:(0x0700+0x30)++0x000
|
|
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 3 is generated" "Supervisor,?..."
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
elif (((per.l(c14:0x0700+0x30))&0x8000)==0x8000)
|
|
group.long c14:(0x0700+0x30)++0x000
|
|
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 3 is generated" "Reserved,System,Reserved,User/System"
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
else
|
|
group.long c14:(0x0700+0x30)++0x000
|
|
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 3 is generated" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long c14:(0x0700+0x30)++0x000
|
|
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
|
|
bitfld.long 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
|
|
bitfld.long 0x00 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x00 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 5.--12. 0x01 "BAS,Byte address select"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x00 1.--2. "PAC,Determines the Exception level or levels at which a watchpoint debug event for watchpoint 3 is generated" "Reserved,System,User,User/System"
|
|
bitfld.long 0x00 0. "WE,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.OFF
|
|
AUTOINDENT.POP
|
|
tree.open "Interrupt Controller (GIC-500)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
base COMP.BASE("GICD",-1.)
|
|
width 17.
|
|
tree "Distributor Interface"
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)))
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)"
|
|
rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DS ,Disable Security" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ARE_NS ,Affinity Routing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ARE_S ,Affinity Routing Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLEGRP1S ,Enable Secure Group 1 interrupts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled"
|
|
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)"
|
|
rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ARE_NS ,Affinity Routing Enable" "Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLEGRP1A ,Enable Group 1 interrupts" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICD_CTLR,Distributor Control Register"
|
|
rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DS ,Disable Security" "Reserved,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ARE ,Affinity Routing Enable" "Reserved,Enabled"
|
|
bitfld.long 0x00 1. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x0004++0x03
|
|
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 25. " NO1N ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported"
|
|
bitfld.long 0x00 24. " A3V ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported"
|
|
bitfld.long 0x00 19.--23. " IDBITS ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
|
|
textline " "
|
|
bitfld.long 0x00 17. " LPIS ,Indicates whether the implementation supports LPIs" "Not supported,Supported"
|
|
bitfld.long 0x00 16. " MBIS ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported"
|
|
bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " CPUNUMBER ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 0.--4. " ITLN ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved"
|
|
rgroup.long 0x0008++0x03
|
|
line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register"
|
|
bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..."
|
|
bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000)
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI"
|
|
wgroup.long 0x48++0x03
|
|
line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI"
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50))
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI"
|
|
else
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58))
|
|
wgroup.long 0x58++0x03
|
|
line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI"
|
|
else
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)"
|
|
endif
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register"
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register"
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register"
|
|
endif
|
|
width 17.
|
|
tree "Group Registers"
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080))
|
|
group.long 0x0080++0x03
|
|
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1"
|
|
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)
|
|
group.long 0x0080++0x03
|
|
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0"
|
|
bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0080++0x03
|
|
hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1))
|
|
group.long 0x0084++0x03
|
|
line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1))
|
|
group.long 0x0084++0x03
|
|
line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 "
|
|
bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0084++0x03
|
|
hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 "
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2))
|
|
group.long 0x0088++0x03
|
|
line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2))
|
|
group.long 0x0088++0x03
|
|
line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 "
|
|
bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0088++0x03
|
|
hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 "
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3))
|
|
group.long 0x008C++0x03
|
|
line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3))
|
|
group.long 0x008C++0x03
|
|
line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 "
|
|
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x008C++0x03
|
|
hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 "
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4))
|
|
group.long 0x0090++0x03
|
|
line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4))
|
|
group.long 0x0090++0x03
|
|
line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 "
|
|
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0090++0x03
|
|
hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 "
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5))
|
|
group.long 0x0094++0x03
|
|
line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5))
|
|
group.long 0x0094++0x03
|
|
line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 "
|
|
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0094++0x03
|
|
hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 "
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6))
|
|
group.long 0x0098++0x03
|
|
line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6))
|
|
group.long 0x0098++0x03
|
|
line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 "
|
|
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0098++0x03
|
|
hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 "
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7))
|
|
group.long 0x009C++0x03
|
|
line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7))
|
|
group.long 0x009C++0x03
|
|
line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 "
|
|
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x009C++0x03
|
|
hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 "
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8))
|
|
group.long 0x00A0++0x03
|
|
line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8))
|
|
group.long 0x00A0++0x03
|
|
line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 "
|
|
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00A0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 "
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9))
|
|
group.long 0x00A4++0x03
|
|
line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9))
|
|
group.long 0x00A4++0x03
|
|
line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 "
|
|
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00A4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 "
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA))
|
|
group.long 0x00A8++0x03
|
|
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA))
|
|
group.long 0x00A8++0x03
|
|
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
|
|
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00A8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB))
|
|
group.long 0x00AC++0x03
|
|
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB))
|
|
group.long 0x00AC++0x03
|
|
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
|
|
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00AC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC))
|
|
group.long 0x00B0++0x03
|
|
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC))
|
|
group.long 0x00B0++0x03
|
|
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
|
|
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00B0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD))
|
|
group.long 0x00B4++0x03
|
|
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD))
|
|
group.long 0x00B4++0x03
|
|
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
|
|
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00B4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE))
|
|
group.long 0x00B8++0x03
|
|
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE))
|
|
group.long 0x00B8++0x03
|
|
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
|
|
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00B8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF))
|
|
group.long 0x00BC++0x03
|
|
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF))
|
|
group.long 0x00BC++0x03
|
|
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
|
|
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00BC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
|
|
group.long 0x00C0++0x03
|
|
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
|
|
group.long 0x00C0++0x03
|
|
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
|
|
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00C0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
|
|
group.long 0x00C4++0x03
|
|
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
|
|
group.long 0x00C4++0x03
|
|
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
|
|
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00C4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
|
|
group.long 0x00C8++0x03
|
|
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
|
|
group.long 0x00C8++0x03
|
|
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
|
|
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00C8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
|
|
group.long 0x00CC++0x03
|
|
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
|
|
group.long 0x00CC++0x03
|
|
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
|
|
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00CC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
|
|
group.long 0x00D0++0x03
|
|
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
|
|
group.long 0x00D0++0x03
|
|
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
|
|
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00D0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
|
|
group.long 0x00D4++0x03
|
|
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
|
|
group.long 0x00D4++0x03
|
|
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
|
|
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00D4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
|
|
group.long 0x00D8++0x03
|
|
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
|
|
group.long 0x00D8++0x03
|
|
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
|
|
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00D8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
|
|
group.long 0x00DC++0x03
|
|
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
|
|
group.long 0x00DC++0x03
|
|
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
|
|
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00DC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
|
|
group.long 0x00E0++0x03
|
|
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
|
|
group.long 0x00E0++0x03
|
|
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
|
|
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00E0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
|
|
group.long 0x00E4++0x03
|
|
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
|
|
group.long 0x00E4++0x03
|
|
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
|
|
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00E4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A))
|
|
group.long 0x00E8++0x03
|
|
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A))
|
|
group.long 0x00E8++0x03
|
|
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
|
|
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00E8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
|
|
group.long 0x00EC++0x03
|
|
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
|
|
group.long 0x00EC++0x03
|
|
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
|
|
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00EC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
|
|
group.long 0x00F0++0x03
|
|
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
|
|
group.long 0x00F0++0x03
|
|
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
|
|
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00F0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
|
|
group.long 0x00F4++0x03
|
|
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
|
|
group.long 0x00F4++0x03
|
|
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
|
|
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00F4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
|
|
group.long 0x00F8++0x03
|
|
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)"
|
|
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1"
|
|
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
|
|
group.long 0x00F8++0x03
|
|
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
|
|
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00F8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
|
|
endif
|
|
tree.end
|
|
width 24.
|
|
tree "Set/Clear Enable Registers"
|
|
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
|
|
hgroup.long 0x0100++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
else
|
|
group.long 0x0100++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x0104++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0104++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x0108++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0108++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x010C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x010C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x0110++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0110++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x0114++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0114++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x0118++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0118++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x011C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x011C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x0120++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0120++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x0124++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0124++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x0128++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0128++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x012C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x012C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x0130++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0130++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x0134++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0134++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x0138++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0138++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x013C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x013C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
|
|
group.long 0x0140++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0140++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
|
|
group.long 0x0144++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0144++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
|
|
group.long 0x0148++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0148++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
|
|
group.long 0x014C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x014C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
|
|
group.long 0x0150++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0150++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
|
|
group.long 0x0154++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0154++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
|
|
group.long 0x0158++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0158++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
|
|
group.long 0x015C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x015C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
|
|
group.long 0x0160++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0160++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
|
|
group.long 0x0164++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0164++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0x0168++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0168++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0x016C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x016C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0x0170++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0170++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0x0174++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0174++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0x0178++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0178++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
|
|
endif
|
|
tree.end
|
|
width 22.
|
|
tree "Set/Clear Pending Registers"
|
|
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
|
|
hgroup.long 0x0200++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
else
|
|
group.long 0x0200++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x0204++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0204++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x0208++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0208++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x020C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x020C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x0210++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0210++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x0214++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0214++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x0218++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0218++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x021C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x021C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x0220++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0220++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x0224++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0224++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x0228++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0228++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x022C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x022C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x0230++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0230++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x0234++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0234++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x0238++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0238++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x023C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x023C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
|
|
group.long 0x0240++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0240++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
|
|
group.long 0x0244++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0244++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
|
|
group.long 0x0248++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0248++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
|
|
group.long 0x024C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x024C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
|
|
group.long 0x0250++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0250++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
|
|
group.long 0x0254++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0254++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
|
|
group.long 0x0258++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0258++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
|
|
group.long 0x025C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x025C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
|
|
group.long 0x0260++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0260++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
|
|
group.long 0x0264++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0264++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0x0268++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0268++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0x026C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x026C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0x0270++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0270++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0x0274++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0274++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0x0278++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x0278++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
|
|
endif
|
|
tree.end
|
|
width 24.
|
|
tree "Set/Clear Active Registers"
|
|
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
|
|
hgroup.long 0x0300++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
newline
|
|
else
|
|
group.long 0x0300++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x0304++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0304++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x0308++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0308++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x030C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active"
|
|
else
|
|
hgroup.long 0x030C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x0310++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0310++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x0314++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0314++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x0318++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0318++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x031C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active"
|
|
else
|
|
hgroup.long 0x031C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x0320++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0320++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x0324++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0324++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x0328++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0328++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x032C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active"
|
|
else
|
|
hgroup.long 0x032C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x0330++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0330++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x0334++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0334++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x0338++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0338++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x033C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active"
|
|
else
|
|
hgroup.long 0x033C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
|
|
group.long 0x0340++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0340++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
|
|
group.long 0x0344++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0344++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
|
|
group.long 0x0348++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0348++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
|
|
group.long 0x034C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active"
|
|
else
|
|
hgroup.long 0x034C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
|
|
group.long 0x0350++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0350++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
|
|
group.long 0x0354++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0354++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
|
|
group.long 0x0358++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0358++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
|
|
group.long 0x035C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active"
|
|
else
|
|
hgroup.long 0x035C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
|
|
group.long 0x0360++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0360++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
|
|
group.long 0x0364++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0364++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0x0368++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0368++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0x036C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active"
|
|
else
|
|
hgroup.long 0x036C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0x0370++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0370++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0x0374++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0374++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0x0378++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0378++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
|
|
endif
|
|
tree.end
|
|
width 20.
|
|
tree "Priority Registers"
|
|
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
|
|
hgroup.long 0x400++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
|
|
hgroup.long 0x404++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
|
|
hgroup.long 0x40C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 "
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 "
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 "
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 "
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 "
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 "
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 "
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 "
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 "
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 "
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 "
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 "
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 "
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 "
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 "
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 "
|
|
else
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
|
|
hgroup.long 0x424++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
|
|
hgroup.long 0x428++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
|
|
hgroup.long 0x42C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
|
|
hgroup.long 0x430++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
|
|
hgroup.long 0x434++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
|
|
hgroup.long 0x438++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
|
|
hgroup.long 0x43C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 "
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 "
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 "
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 "
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 "
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 "
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 "
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 "
|
|
else
|
|
hgroup.long 0x440++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
|
|
hgroup.long 0x444++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
|
|
hgroup.long 0x448++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
|
|
hgroup.long 0x44C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
|
|
hgroup.long 0x450++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
|
|
hgroup.long 0x454++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
|
|
hgroup.long 0x458++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
|
|
hgroup.long 0x45C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 "
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 "
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 "
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 "
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 "
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 "
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 "
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 "
|
|
else
|
|
hgroup.long 0x460++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
|
|
hgroup.long 0x464++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
|
|
hgroup.long 0x468++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
|
|
hgroup.long 0x46C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
|
|
hgroup.long 0x470++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
|
|
hgroup.long 0x474++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
|
|
hgroup.long 0x478++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
|
|
hgroup.long 0x47C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 "
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 "
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 "
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 "
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 "
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 "
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 "
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 "
|
|
else
|
|
hgroup.long 0x480++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
|
|
hgroup.long 0x484++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
|
|
hgroup.long 0x488++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
|
|
hgroup.long 0x48C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
|
|
hgroup.long 0x490++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
|
|
hgroup.long 0x494++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
|
|
hgroup.long 0x498++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
|
|
hgroup.long 0x49C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 "
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 "
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 "
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 "
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 "
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 "
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 "
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 "
|
|
else
|
|
hgroup.long 0x4A0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
|
|
hgroup.long 0x4A4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
|
|
hgroup.long 0x4A8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
|
|
hgroup.long 0x4AC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
|
|
hgroup.long 0x4B0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
|
|
hgroup.long 0x4B4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
|
|
hgroup.long 0x4B8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
|
|
hgroup.long 0x4BC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 "
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 "
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 "
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 "
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 "
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 "
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 "
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 "
|
|
else
|
|
hgroup.long 0x4C0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
|
|
hgroup.long 0x4C4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
|
|
hgroup.long 0x4C8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
|
|
hgroup.long 0x4CC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
|
|
hgroup.long 0x4D0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
|
|
hgroup.long 0x4D4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
|
|
hgroup.long 0x4D8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
|
|
hgroup.long 0x4DC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 "
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 "
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 "
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 "
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 "
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 "
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 "
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 "
|
|
else
|
|
hgroup.long 0x4E0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
|
|
hgroup.long 0x4E4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
|
|
hgroup.long 0x4E8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
|
|
hgroup.long 0x4EC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
|
|
hgroup.long 0x4F0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
|
|
hgroup.long 0x4F4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
|
|
hgroup.long 0x4F8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
|
|
hgroup.long 0x4FC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 "
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 "
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 "
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 "
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 "
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 "
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 "
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 "
|
|
else
|
|
hgroup.long 0x500++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
|
|
hgroup.long 0x504++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
|
|
hgroup.long 0x508++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
|
|
hgroup.long 0x50C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
|
|
hgroup.long 0x510++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
|
|
hgroup.long 0x514++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
|
|
hgroup.long 0x518++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
|
|
hgroup.long 0x51C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 "
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 "
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 "
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 "
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 "
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 "
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 "
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 "
|
|
else
|
|
hgroup.long 0x520++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
|
|
hgroup.long 0x524++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
|
|
hgroup.long 0x528++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
|
|
hgroup.long 0x52C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
|
|
hgroup.long 0x530++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
|
|
hgroup.long 0x534++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
|
|
hgroup.long 0x538++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
|
|
hgroup.long 0x53C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 "
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 "
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 "
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 "
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 "
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 "
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 "
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 "
|
|
else
|
|
hgroup.long 0x540++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
|
|
hgroup.long 0x544++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
|
|
hgroup.long 0x548++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
|
|
hgroup.long 0x54C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
|
|
hgroup.long 0x550++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
|
|
hgroup.long 0x554++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
|
|
hgroup.long 0x558++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
|
|
hgroup.long 0x55C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 "
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 "
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 "
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 "
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 "
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 "
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 "
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 "
|
|
else
|
|
hgroup.long 0x560++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
|
|
hgroup.long 0x564++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
|
|
hgroup.long 0x568++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
|
|
hgroup.long 0x56C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
|
|
hgroup.long 0x570++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
|
|
hgroup.long 0x574++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
|
|
hgroup.long 0x578++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
|
|
hgroup.long 0x57C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 "
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 "
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 "
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 "
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 "
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 "
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 "
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 "
|
|
else
|
|
hgroup.long 0x580++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
|
|
hgroup.long 0x584++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
|
|
hgroup.long 0x588++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
|
|
hgroup.long 0x58C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
|
|
hgroup.long 0x590++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
|
|
hgroup.long 0x594++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
|
|
hgroup.long 0x598++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
|
|
hgroup.long 0x59C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 "
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 "
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 "
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 "
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 "
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 "
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 "
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 "
|
|
else
|
|
hgroup.long 0x5A0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
|
|
hgroup.long 0x5A4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
|
|
hgroup.long 0x5A8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
|
|
hgroup.long 0x5AC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
|
|
hgroup.long 0x5B0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
|
|
hgroup.long 0x5B4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
|
|
hgroup.long 0x5B8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
|
|
hgroup.long 0x5BC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 "
|
|
group.long 0x5C4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 "
|
|
group.long 0x5C8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 "
|
|
group.long 0x5CC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 "
|
|
group.long 0x5D0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 "
|
|
group.long 0x5D4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 "
|
|
group.long 0x5D8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 "
|
|
group.long 0x5DC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 "
|
|
else
|
|
hgroup.long 0x5C0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
|
|
hgroup.long 0x5C4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
|
|
hgroup.long 0x5C8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
|
|
hgroup.long 0x5CC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
|
|
hgroup.long 0x5D0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
|
|
hgroup.long 0x5D4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
|
|
hgroup.long 0x5D8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
|
|
hgroup.long 0x5DC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 "
|
|
group.long 0x5E4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 "
|
|
group.long 0x5E8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 "
|
|
group.long 0x5EC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 "
|
|
group.long 0x5F0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 "
|
|
group.long 0x5F4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 "
|
|
group.long 0x5F8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 "
|
|
group.long 0x5FC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 "
|
|
else
|
|
hgroup.long 0x5E0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
|
|
hgroup.long 0x5E4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
|
|
hgroup.long 0x5E8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
|
|
hgroup.long 0x5EC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
|
|
hgroup.long 0x5F0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
|
|
hgroup.long 0x5F4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
|
|
hgroup.long 0x5F8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
|
|
hgroup.long 0x5FC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 "
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 "
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 "
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 "
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 "
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 "
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 "
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 "
|
|
else
|
|
hgroup.long 0x600++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
|
|
hgroup.long 0x604++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
|
|
hgroup.long 0x608++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
|
|
hgroup.long 0x60C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
|
|
hgroup.long 0x610++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
|
|
hgroup.long 0x614++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
|
|
hgroup.long 0x618++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
|
|
hgroup.long 0x61C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 "
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 "
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 "
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 "
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 "
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 "
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 "
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 "
|
|
else
|
|
hgroup.long 0x620++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
|
|
hgroup.long 0x624++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
|
|
hgroup.long 0x628++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
|
|
hgroup.long 0x62C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
|
|
hgroup.long 0x630++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
|
|
hgroup.long 0x634++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
|
|
hgroup.long 0x638++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
|
|
hgroup.long 0x63C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 "
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 "
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 "
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 "
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 "
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 "
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 "
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 "
|
|
else
|
|
hgroup.long 0x640++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
|
|
hgroup.long 0x644++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
|
|
hgroup.long 0x648++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
|
|
hgroup.long 0x64C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
|
|
hgroup.long 0x650++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
|
|
hgroup.long 0x654++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
|
|
hgroup.long 0x658++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
|
|
hgroup.long 0x65C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 "
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 "
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 "
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 "
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 "
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 "
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 "
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 "
|
|
else
|
|
hgroup.long 0x660++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
|
|
hgroup.long 0x664++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
|
|
hgroup.long 0x668++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
|
|
hgroup.long 0x66C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
|
|
hgroup.long 0x670++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
|
|
hgroup.long 0x674++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
|
|
hgroup.long 0x678++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
|
|
hgroup.long 0x67C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 "
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 "
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 "
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 "
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 "
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 "
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 "
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 "
|
|
else
|
|
hgroup.long 0x680++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
|
|
hgroup.long 0x684++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
|
|
hgroup.long 0x688++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
|
|
hgroup.long 0x68C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
|
|
hgroup.long 0x690++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
|
|
hgroup.long 0x694++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
|
|
hgroup.long 0x698++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
|
|
hgroup.long 0x69C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 "
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 "
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 "
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 "
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 "
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 "
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 "
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 "
|
|
else
|
|
hgroup.long 0x6A0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
|
|
hgroup.long 0x6A4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
|
|
hgroup.long 0x6A8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
|
|
hgroup.long 0x6AC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
|
|
hgroup.long 0x6B0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
|
|
hgroup.long 0x6B4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
|
|
hgroup.long 0x6B8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
|
|
hgroup.long 0x6BC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 "
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 "
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 "
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 "
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 "
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 "
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 "
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 "
|
|
else
|
|
hgroup.long 0x6C0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
|
|
hgroup.long 0x6C4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
|
|
hgroup.long 0x6C8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
|
|
hgroup.long 0x6CC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
|
|
hgroup.long 0x6D0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
|
|
hgroup.long 0x6D4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
|
|
hgroup.long 0x6D8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
|
|
hgroup.long 0x6DC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 "
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 "
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 "
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 "
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 "
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 "
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 "
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 "
|
|
else
|
|
hgroup.long 0x6E0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
|
|
hgroup.long 0x6E4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
|
|
hgroup.long 0x6E8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
|
|
hgroup.long 0x6EC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
|
|
hgroup.long 0x6F0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
|
|
hgroup.long 0x6F4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
|
|
hgroup.long 0x6F8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
|
|
hgroup.long 0x6FC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 "
|
|
group.long 0x704++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 "
|
|
group.long 0x708++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 "
|
|
group.long 0x70C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 "
|
|
group.long 0x710++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 "
|
|
group.long 0x714++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 "
|
|
group.long 0x718++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 "
|
|
group.long 0x71C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 "
|
|
else
|
|
hgroup.long 0x700++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
|
|
hgroup.long 0x704++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
|
|
hgroup.long 0x708++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
|
|
hgroup.long 0x70C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
|
|
hgroup.long 0x710++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
|
|
hgroup.long 0x714++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
|
|
hgroup.long 0x718++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
|
|
hgroup.long 0x71C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
|
|
group.long 0x720++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 "
|
|
group.long 0x724++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 "
|
|
group.long 0x728++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 "
|
|
group.long 0x72C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 "
|
|
group.long 0x730++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 "
|
|
group.long 0x734++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 "
|
|
group.long 0x738++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 "
|
|
group.long 0x73C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 "
|
|
else
|
|
hgroup.long 0x720++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
|
|
hgroup.long 0x724++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
|
|
hgroup.long 0x728++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
|
|
hgroup.long 0x72C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
|
|
hgroup.long 0x730++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
|
|
hgroup.long 0x734++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
|
|
hgroup.long 0x738++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
|
|
hgroup.long 0x73C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0x740++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 "
|
|
group.long 0x744++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 "
|
|
group.long 0x748++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 "
|
|
group.long 0x74C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 "
|
|
group.long 0x750++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 "
|
|
group.long 0x754++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 "
|
|
group.long 0x758++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 "
|
|
group.long 0x75C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 "
|
|
else
|
|
hgroup.long 0x740++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
|
|
hgroup.long 0x744++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
|
|
hgroup.long 0x748++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
|
|
hgroup.long 0x74C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
|
|
hgroup.long 0x750++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
|
|
hgroup.long 0x754++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
|
|
hgroup.long 0x758++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
|
|
hgroup.long 0x75C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0x760++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 "
|
|
group.long 0x764++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 "
|
|
group.long 0x768++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 "
|
|
group.long 0x76C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 "
|
|
group.long 0x770++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 "
|
|
group.long 0x774++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 "
|
|
group.long 0x778++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 "
|
|
group.long 0x77C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 "
|
|
else
|
|
hgroup.long 0x760++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
|
|
hgroup.long 0x764++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
|
|
hgroup.long 0x768++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
|
|
hgroup.long 0x76C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
|
|
hgroup.long 0x770++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
|
|
hgroup.long 0x774++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
|
|
hgroup.long 0x778++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
|
|
hgroup.long 0x77C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0x780++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 "
|
|
group.long 0x784++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 "
|
|
group.long 0x788++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 "
|
|
group.long 0x78C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 "
|
|
group.long 0x790++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 "
|
|
group.long 0x794++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 "
|
|
group.long 0x798++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 "
|
|
group.long 0x79C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 "
|
|
else
|
|
hgroup.long 0x780++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
|
|
hgroup.long 0x784++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
|
|
hgroup.long 0x788++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
|
|
hgroup.long 0x78C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
|
|
hgroup.long 0x790++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
|
|
hgroup.long 0x794++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
|
|
hgroup.long 0x798++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
|
|
hgroup.long 0x79C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0x7A0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 "
|
|
group.long 0x7A4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 "
|
|
group.long 0x7A8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 "
|
|
group.long 0x7AC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 "
|
|
group.long 0x7B0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 "
|
|
group.long 0x7B4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 "
|
|
group.long 0x7B8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 "
|
|
group.long 0x7BC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 "
|
|
else
|
|
hgroup.long 0x7A0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
|
|
hgroup.long 0x7A4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
|
|
hgroup.long 0x7A8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
|
|
hgroup.long 0x7AC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
|
|
hgroup.long 0x7B0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
|
|
hgroup.long 0x7B4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
|
|
hgroup.long 0x7B8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
|
|
hgroup.long 0x7BC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0x7C0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 "
|
|
group.long 0x7C4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 "
|
|
group.long 0x7C8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 "
|
|
group.long 0x7CC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 "
|
|
group.long 0x7D0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 "
|
|
group.long 0x7D4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 "
|
|
group.long 0x7D8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 "
|
|
group.long 0x7DC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 "
|
|
else
|
|
hgroup.long 0x7C0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
|
|
hgroup.long 0x7C4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
|
|
hgroup.long 0x7C8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
|
|
hgroup.long 0x7CC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
|
|
hgroup.long 0x7D0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
|
|
hgroup.long 0x7D4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
|
|
hgroup.long 0x7D8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
|
|
hgroup.long 0x7DC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
|
|
endif
|
|
tree.end
|
|
width 19.
|
|
tree "Interrupt Targets Registers"
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1)
|
|
hgroup.long 0x800++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0"
|
|
hgroup.long 0x804++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1"
|
|
hgroup.long 0x808++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2"
|
|
hgroup.long 0x80C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3"
|
|
hgroup.long 0x810++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4"
|
|
hgroup.long 0x814++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5"
|
|
hgroup.long 0x818++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6"
|
|
hgroup.long 0x81C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7"
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 "
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 "
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 "
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 "
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 "
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 "
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 "
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 "
|
|
else
|
|
hgroup.long 0x820++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
|
|
hgroup.long 0x824++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
|
|
hgroup.long 0x828++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
|
|
hgroup.long 0x82C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
|
|
hgroup.long 0x830++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
|
|
hgroup.long 0x834++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
|
|
hgroup.long 0x838++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
|
|
hgroup.long 0x83C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 "
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 "
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 "
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 "
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 "
|
|
group.long 0x854++0x03
|
|
line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 "
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 "
|
|
group.long 0x85C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 "
|
|
else
|
|
hgroup.long 0x840++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
|
|
hgroup.long 0x844++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
|
|
hgroup.long 0x848++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
|
|
hgroup.long 0x84C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
|
|
hgroup.long 0x850++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
|
|
hgroup.long 0x854++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
|
|
hgroup.long 0x858++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
|
|
hgroup.long 0x85C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 "
|
|
group.long 0x864++0x03
|
|
line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 "
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 "
|
|
group.long 0x86C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 "
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 "
|
|
group.long 0x874++0x03
|
|
line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 "
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 "
|
|
group.long 0x87C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 "
|
|
else
|
|
hgroup.long 0x860++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
|
|
hgroup.long 0x864++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
|
|
hgroup.long 0x868++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
|
|
hgroup.long 0x86C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
|
|
hgroup.long 0x870++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
|
|
hgroup.long 0x874++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
|
|
hgroup.long 0x878++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
|
|
hgroup.long 0x87C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 "
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 "
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 "
|
|
group.long 0x88C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 "
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 "
|
|
group.long 0x894++0x03
|
|
line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 "
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 "
|
|
group.long 0x89C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 "
|
|
else
|
|
hgroup.long 0x880++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
|
|
hgroup.long 0x884++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
|
|
hgroup.long 0x888++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
|
|
hgroup.long 0x88C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
|
|
hgroup.long 0x890++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
|
|
hgroup.long 0x894++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
|
|
hgroup.long 0x898++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
|
|
hgroup.long 0x89C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 "
|
|
group.long 0x8A4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 "
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 "
|
|
group.long 0x8AC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 "
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 "
|
|
group.long 0x8B4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 "
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 "
|
|
group.long 0x8BC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 "
|
|
else
|
|
hgroup.long 0x8A0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
|
|
hgroup.long 0x8A4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
|
|
hgroup.long 0x8A8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
|
|
hgroup.long 0x8AC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
|
|
hgroup.long 0x8B0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
|
|
hgroup.long 0x8B4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
|
|
hgroup.long 0x8B8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
|
|
hgroup.long 0x8BC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 "
|
|
group.long 0x8C4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 "
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 "
|
|
group.long 0x8CC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 "
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 "
|
|
group.long 0x8D4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 "
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 "
|
|
group.long 0x8DC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 "
|
|
else
|
|
hgroup.long 0x8C0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
|
|
hgroup.long 0x8C4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
|
|
hgroup.long 0x8C8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
|
|
hgroup.long 0x8CC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
|
|
hgroup.long 0x8D0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
|
|
hgroup.long 0x8D4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
|
|
hgroup.long 0x8D8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
|
|
hgroup.long 0x8DC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 "
|
|
group.long 0x8E4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 "
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 "
|
|
group.long 0x8EC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 "
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 "
|
|
group.long 0x8F4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 "
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 "
|
|
group.long 0x8FC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 "
|
|
else
|
|
hgroup.long 0x8E0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
|
|
hgroup.long 0x8E4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
|
|
hgroup.long 0x8E8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
|
|
hgroup.long 0x8EC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
|
|
hgroup.long 0x8F0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
|
|
hgroup.long 0x8F4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
|
|
hgroup.long 0x8F8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
|
|
hgroup.long 0x8FC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 "
|
|
group.long 0x904++0x03
|
|
line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 "
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 "
|
|
group.long 0x90C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 "
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 "
|
|
group.long 0x914++0x03
|
|
line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 "
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 "
|
|
group.long 0x91C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 "
|
|
else
|
|
hgroup.long 0x900++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
|
|
hgroup.long 0x904++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
|
|
hgroup.long 0x908++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
|
|
hgroup.long 0x90C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
|
|
hgroup.long 0x910++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
|
|
hgroup.long 0x914++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
|
|
hgroup.long 0x918++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
|
|
hgroup.long 0x91C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 "
|
|
group.long 0x924++0x03
|
|
line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 "
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 "
|
|
group.long 0x92C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 "
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 "
|
|
group.long 0x934++0x03
|
|
line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 "
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 "
|
|
group.long 0x93C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 "
|
|
else
|
|
hgroup.long 0x920++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
|
|
hgroup.long 0x924++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
|
|
hgroup.long 0x928++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
|
|
hgroup.long 0x92C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
|
|
hgroup.long 0x930++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
|
|
hgroup.long 0x934++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
|
|
hgroup.long 0x938++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
|
|
hgroup.long 0x93C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 "
|
|
group.long 0x944++0x03
|
|
line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 "
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 "
|
|
group.long 0x94C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 "
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 "
|
|
group.long 0x954++0x03
|
|
line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 "
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 "
|
|
group.long 0x95C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 "
|
|
else
|
|
hgroup.long 0x940++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
|
|
hgroup.long 0x944++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
|
|
hgroup.long 0x948++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
|
|
hgroup.long 0x94C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
|
|
hgroup.long 0x950++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
|
|
hgroup.long 0x954++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
|
|
hgroup.long 0x958++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
|
|
hgroup.long 0x95C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 "
|
|
group.long 0x964++0x03
|
|
line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 "
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 "
|
|
group.long 0x96C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 "
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 "
|
|
group.long 0x974++0x03
|
|
line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 "
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 "
|
|
group.long 0x97C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 "
|
|
else
|
|
hgroup.long 0x960++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
|
|
hgroup.long 0x964++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
|
|
hgroup.long 0x968++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
|
|
hgroup.long 0x96C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
|
|
hgroup.long 0x970++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
|
|
hgroup.long 0x974++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
|
|
hgroup.long 0x978++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
|
|
hgroup.long 0x97C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 "
|
|
group.long 0x984++0x03
|
|
line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 "
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 "
|
|
group.long 0x98C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 "
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 "
|
|
group.long 0x994++0x03
|
|
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 "
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 "
|
|
group.long 0x99C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 "
|
|
else
|
|
hgroup.long 0x980++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
|
|
hgroup.long 0x984++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
|
|
hgroup.long 0x988++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
|
|
hgroup.long 0x98C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
|
|
hgroup.long 0x990++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
|
|
hgroup.long 0x994++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
|
|
hgroup.long 0x998++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
|
|
hgroup.long 0x99C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 "
|
|
group.long 0x9A4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 "
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 "
|
|
group.long 0x9AC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 "
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 "
|
|
group.long 0x9B4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 "
|
|
group.long 0x9B8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 "
|
|
group.long 0x9BC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 "
|
|
else
|
|
hgroup.long 0x9A0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
|
|
hgroup.long 0x9A4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
|
|
hgroup.long 0x9A8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
|
|
hgroup.long 0x9AC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
|
|
hgroup.long 0x9B0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
|
|
hgroup.long 0x9B4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
|
|
hgroup.long 0x9B8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
|
|
hgroup.long 0x9BC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 "
|
|
group.long 0x9C4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 "
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 "
|
|
group.long 0x9CC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 "
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 "
|
|
group.long 0x9D4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 "
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 "
|
|
group.long 0x9DC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 "
|
|
else
|
|
hgroup.long 0x9C0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
|
|
hgroup.long 0x9C4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
|
|
hgroup.long 0x9C8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
|
|
hgroup.long 0x9CC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
|
|
hgroup.long 0x9D0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
|
|
hgroup.long 0x9D4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
|
|
hgroup.long 0x9D8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
|
|
hgroup.long 0x9DC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 "
|
|
group.long 0x9E4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 "
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 "
|
|
group.long 0x9EC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 "
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 "
|
|
group.long 0x9F4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 "
|
|
group.long 0x9F8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 "
|
|
group.long 0x9FC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 "
|
|
else
|
|
hgroup.long 0x9E0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
|
|
hgroup.long 0x9E4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
|
|
hgroup.long 0x9E8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
|
|
hgroup.long 0x9EC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
|
|
hgroup.long 0x9F0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
|
|
hgroup.long 0x9F4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
|
|
hgroup.long 0x9F8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
|
|
hgroup.long 0x9FC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 "
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 "
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 "
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 "
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 "
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 "
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 "
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 "
|
|
else
|
|
hgroup.long 0xA00++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
|
|
hgroup.long 0xA04++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
|
|
hgroup.long 0xA08++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
|
|
hgroup.long 0xA0C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
|
|
hgroup.long 0xA10++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
|
|
hgroup.long 0xA14++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
|
|
hgroup.long 0xA18++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
|
|
hgroup.long 0xA1C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 "
|
|
group.long 0xA24++0x03
|
|
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 "
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 "
|
|
group.long 0xA2C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 "
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 "
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 "
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 "
|
|
group.long 0xA3C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 "
|
|
else
|
|
hgroup.long 0xA20++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
|
|
hgroup.long 0xA24++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
|
|
hgroup.long 0xA28++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
|
|
hgroup.long 0xA2C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
|
|
hgroup.long 0xA30++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
|
|
hgroup.long 0xA34++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
|
|
hgroup.long 0xA38++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
|
|
hgroup.long 0xA3C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 "
|
|
group.long 0xA44++0x03
|
|
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 "
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 "
|
|
group.long 0xA4C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 "
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 "
|
|
group.long 0xA54++0x03
|
|
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 "
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 "
|
|
group.long 0xA5C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 "
|
|
else
|
|
hgroup.long 0xA40++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
|
|
hgroup.long 0xA44++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
|
|
hgroup.long 0xA48++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
|
|
hgroup.long 0xA4C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
|
|
hgroup.long 0xA50++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
|
|
hgroup.long 0xA54++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
|
|
hgroup.long 0xA58++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
|
|
hgroup.long 0xA5C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 "
|
|
group.long 0xA64++0x03
|
|
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 "
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 "
|
|
group.long 0xA6C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 "
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 "
|
|
group.long 0xA74++0x03
|
|
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 "
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 "
|
|
group.long 0xA7C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 "
|
|
else
|
|
hgroup.long 0xA60++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
|
|
hgroup.long 0xA64++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
|
|
hgroup.long 0xA68++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
|
|
hgroup.long 0xA6C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
|
|
hgroup.long 0xA70++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
|
|
hgroup.long 0xA74++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
|
|
hgroup.long 0xA78++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
|
|
hgroup.long 0xA7C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 "
|
|
group.long 0xA84++0x03
|
|
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 "
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 "
|
|
group.long 0xA8C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 "
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 "
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 "
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 "
|
|
group.long 0xA9C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 "
|
|
else
|
|
hgroup.long 0xA80++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
|
|
hgroup.long 0xA84++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
|
|
hgroup.long 0xA88++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
|
|
hgroup.long 0xA8C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
|
|
hgroup.long 0xA90++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
|
|
hgroup.long 0xA94++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
|
|
hgroup.long 0xA98++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
|
|
hgroup.long 0xA9C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 "
|
|
group.long 0xAA4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 "
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 "
|
|
group.long 0xAAC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 "
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 "
|
|
group.long 0xAB4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 "
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 "
|
|
group.long 0xABC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 "
|
|
else
|
|
hgroup.long 0xAA0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
|
|
hgroup.long 0xAA4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
|
|
hgroup.long 0xAA8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
|
|
hgroup.long 0xAAC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
|
|
hgroup.long 0xAB0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
|
|
hgroup.long 0xAB4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
|
|
hgroup.long 0xAB8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
|
|
hgroup.long 0xABC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 "
|
|
group.long 0xAC4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 "
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 "
|
|
group.long 0xACC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 "
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 "
|
|
group.long 0xAD4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 "
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 "
|
|
group.long 0xADC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 "
|
|
else
|
|
hgroup.long 0xAC0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
|
|
hgroup.long 0xAC4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
|
|
hgroup.long 0xAC8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
|
|
hgroup.long 0xACC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
|
|
hgroup.long 0xAD0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
|
|
hgroup.long 0xAD4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
|
|
hgroup.long 0xAD8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
|
|
hgroup.long 0xADC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 "
|
|
group.long 0xAE4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 "
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 "
|
|
group.long 0xAEC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 "
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 "
|
|
group.long 0xAF4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 "
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 "
|
|
group.long 0xAFC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 "
|
|
else
|
|
hgroup.long 0xAE0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
|
|
hgroup.long 0xAE4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
|
|
hgroup.long 0xAE8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
|
|
hgroup.long 0xAEC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
|
|
hgroup.long 0xAF0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
|
|
hgroup.long 0xAF4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
|
|
hgroup.long 0xAF8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
|
|
hgroup.long 0xAFC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 "
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 "
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 "
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 "
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 "
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 "
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 "
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 "
|
|
else
|
|
hgroup.long 0xB00++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
|
|
hgroup.long 0xB04++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
|
|
hgroup.long 0xB08++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
|
|
hgroup.long 0xB0C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
|
|
hgroup.long 0xB10++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
|
|
hgroup.long 0xB14++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
|
|
hgroup.long 0xB18++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
|
|
hgroup.long 0xB1C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 "
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 "
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 "
|
|
group.long 0xB2C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 "
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 "
|
|
group.long 0xB34++0x03
|
|
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 "
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 "
|
|
group.long 0xB3C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 "
|
|
else
|
|
hgroup.long 0xB20++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
|
|
hgroup.long 0xB24++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
|
|
hgroup.long 0xB28++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
|
|
hgroup.long 0xB2C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
|
|
hgroup.long 0xB30++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
|
|
hgroup.long 0xB34++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
|
|
hgroup.long 0xB38++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
|
|
hgroup.long 0xB3C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 "
|
|
group.long 0xB44++0x03
|
|
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 "
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 "
|
|
group.long 0xB4C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 "
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 "
|
|
group.long 0xB54++0x03
|
|
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 "
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 "
|
|
group.long 0xB5C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 "
|
|
else
|
|
hgroup.long 0xB40++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
|
|
hgroup.long 0xB44++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
|
|
hgroup.long 0xB48++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
|
|
hgroup.long 0xB4C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
|
|
hgroup.long 0xB50++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
|
|
hgroup.long 0xB54++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
|
|
hgroup.long 0xB58++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
|
|
hgroup.long 0xB5C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 "
|
|
group.long 0xB64++0x03
|
|
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 "
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 "
|
|
group.long 0xB6C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 "
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 "
|
|
group.long 0xB74++0x03
|
|
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 "
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 "
|
|
group.long 0xB7C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 "
|
|
else
|
|
hgroup.long 0xB60++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
|
|
hgroup.long 0xB64++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
|
|
hgroup.long 0xB68++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
|
|
hgroup.long 0xB6C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
|
|
hgroup.long 0xB70++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
|
|
hgroup.long 0xB74++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
|
|
hgroup.long 0xB78++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
|
|
hgroup.long 0xB7C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 "
|
|
group.long 0xB84++0x03
|
|
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 "
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 "
|
|
group.long 0xB8C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 "
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 "
|
|
group.long 0xB94++0x03
|
|
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 "
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 "
|
|
group.long 0xB9C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 "
|
|
else
|
|
hgroup.long 0xB80++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
|
|
hgroup.long 0xB84++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
|
|
hgroup.long 0xB88++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
|
|
hgroup.long 0xB8C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
|
|
hgroup.long 0xB90++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
|
|
hgroup.long 0xB94++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
|
|
hgroup.long 0xB98++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
|
|
hgroup.long 0xB9C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 "
|
|
group.long 0xBA4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 "
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 "
|
|
group.long 0xBAC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 "
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 "
|
|
group.long 0xBB4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 "
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 "
|
|
group.long 0xBBC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 "
|
|
else
|
|
hgroup.long 0xBA0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
|
|
hgroup.long 0xBA4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
|
|
hgroup.long 0xBA8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
|
|
hgroup.long 0xBAC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
|
|
hgroup.long 0xBB0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
|
|
hgroup.long 0xBB4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
|
|
hgroup.long 0xBB8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
|
|
hgroup.long 0xBBC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 "
|
|
group.long 0xBC4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 "
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 "
|
|
group.long 0xBCC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 "
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 "
|
|
group.long 0xBD4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 "
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 "
|
|
group.long 0xBDC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 "
|
|
else
|
|
hgroup.long 0xBC0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
|
|
hgroup.long 0xBC4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
|
|
hgroup.long 0xBC8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
|
|
hgroup.long 0xBCC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
|
|
hgroup.long 0xBD0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
|
|
hgroup.long 0xBD4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
|
|
hgroup.long 0xBD8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
|
|
hgroup.long 0xBDC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
|
|
endif
|
|
else
|
|
hgroup.long 0x800++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 "
|
|
hgroup.long 0x804++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 "
|
|
hgroup.long 0x808++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 "
|
|
hgroup.long 0x80C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 "
|
|
hgroup.long 0x810++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 "
|
|
hgroup.long 0x814++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 "
|
|
hgroup.long 0x818++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 "
|
|
hgroup.long 0x81C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 "
|
|
hgroup.long 0x820++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 "
|
|
hgroup.long 0x824++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 "
|
|
hgroup.long 0x828++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 "
|
|
hgroup.long 0x82C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 "
|
|
hgroup.long 0x830++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 "
|
|
hgroup.long 0x834++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 "
|
|
hgroup.long 0x838++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 "
|
|
hgroup.long 0x83C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 "
|
|
hgroup.long 0x840++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 "
|
|
hgroup.long 0x844++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 "
|
|
hgroup.long 0x848++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 "
|
|
hgroup.long 0x84C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 "
|
|
hgroup.long 0x850++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 "
|
|
hgroup.long 0x854++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 "
|
|
hgroup.long 0x858++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 "
|
|
hgroup.long 0x85C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 "
|
|
hgroup.long 0x860++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 "
|
|
hgroup.long 0x864++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 "
|
|
hgroup.long 0x868++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 "
|
|
hgroup.long 0x86C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 "
|
|
hgroup.long 0x870++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 "
|
|
hgroup.long 0x874++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 "
|
|
hgroup.long 0x878++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 "
|
|
hgroup.long 0x87C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 "
|
|
hgroup.long 0x880++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 "
|
|
hgroup.long 0x884++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 "
|
|
hgroup.long 0x888++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 "
|
|
hgroup.long 0x88C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 "
|
|
hgroup.long 0x890++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 "
|
|
hgroup.long 0x894++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 "
|
|
hgroup.long 0x898++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 "
|
|
hgroup.long 0x89C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 "
|
|
hgroup.long 0x8A0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 "
|
|
hgroup.long 0x8A4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 "
|
|
hgroup.long 0x8A8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 "
|
|
hgroup.long 0x8AC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 "
|
|
hgroup.long 0x8B0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 "
|
|
hgroup.long 0x8B4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 "
|
|
hgroup.long 0x8B8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 "
|
|
hgroup.long 0x8BC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 "
|
|
hgroup.long 0x8C0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 "
|
|
hgroup.long 0x8C4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 "
|
|
hgroup.long 0x8C8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 "
|
|
hgroup.long 0x8CC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 "
|
|
hgroup.long 0x8D0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 "
|
|
hgroup.long 0x8D4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 "
|
|
hgroup.long 0x8D8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 "
|
|
hgroup.long 0x8DC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 "
|
|
hgroup.long 0x8E0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 "
|
|
hgroup.long 0x8E4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 "
|
|
hgroup.long 0x8E8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 "
|
|
hgroup.long 0x8EC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 "
|
|
hgroup.long 0x8F0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 "
|
|
hgroup.long 0x8F4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 "
|
|
hgroup.long 0x8F8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 "
|
|
hgroup.long 0x8FC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 "
|
|
hgroup.long 0x900++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 "
|
|
hgroup.long 0x904++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 "
|
|
hgroup.long 0x908++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 "
|
|
hgroup.long 0x90C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 "
|
|
hgroup.long 0x910++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 "
|
|
hgroup.long 0x914++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 "
|
|
hgroup.long 0x918++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 "
|
|
hgroup.long 0x91C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 "
|
|
hgroup.long 0x920++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 "
|
|
hgroup.long 0x924++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 "
|
|
hgroup.long 0x928++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 "
|
|
hgroup.long 0x92C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 "
|
|
hgroup.long 0x930++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 "
|
|
hgroup.long 0x934++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 "
|
|
hgroup.long 0x938++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 "
|
|
hgroup.long 0x93C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 "
|
|
hgroup.long 0x940++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 "
|
|
hgroup.long 0x944++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 "
|
|
hgroup.long 0x948++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 "
|
|
hgroup.long 0x94C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 "
|
|
hgroup.long 0x950++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 "
|
|
hgroup.long 0x954++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 "
|
|
hgroup.long 0x958++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 "
|
|
hgroup.long 0x95C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 "
|
|
hgroup.long 0x960++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 "
|
|
hgroup.long 0x964++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 "
|
|
hgroup.long 0x968++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 "
|
|
hgroup.long 0x96C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 "
|
|
hgroup.long 0x970++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 "
|
|
hgroup.long 0x974++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 "
|
|
hgroup.long 0x978++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 "
|
|
hgroup.long 0x97C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 "
|
|
hgroup.long 0x980++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 "
|
|
hgroup.long 0x984++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 "
|
|
hgroup.long 0x988++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 "
|
|
hgroup.long 0x98C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 "
|
|
hgroup.long 0x990++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
|
|
hgroup.long 0x994++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
|
|
hgroup.long 0x998++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
|
|
hgroup.long 0x99C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
|
|
hgroup.long 0x9A0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
|
|
hgroup.long 0x9A4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
|
|
hgroup.long 0x9A8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
|
|
hgroup.long 0x9AC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
|
|
hgroup.long 0x9B0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
|
|
hgroup.long 0x9B4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
|
|
hgroup.long 0x9B8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
|
|
hgroup.long 0x9BC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
|
|
hgroup.long 0x9C0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
|
|
hgroup.long 0x9C4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
|
|
hgroup.long 0x9C8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
|
|
hgroup.long 0x9CC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
|
|
hgroup.long 0x9D0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
|
|
hgroup.long 0x9D4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
|
|
hgroup.long 0x9D8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
|
|
hgroup.long 0x9DC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
|
|
hgroup.long 0x9E0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
|
|
hgroup.long 0x9E4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
|
|
hgroup.long 0x9E8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
|
|
hgroup.long 0x9EC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
|
|
hgroup.long 0x9F0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
|
|
hgroup.long 0x9F4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
|
|
hgroup.long 0x9F8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
|
|
hgroup.long 0x9FC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
|
|
hgroup.long 0xA00++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
|
|
hgroup.long 0xA04++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
|
|
hgroup.long 0xA08++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
|
|
hgroup.long 0xA0C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
|
|
hgroup.long 0xA10++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
|
|
hgroup.long 0xA14++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
|
|
hgroup.long 0xA18++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
|
|
hgroup.long 0xA1C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
|
|
hgroup.long 0xA20++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
|
|
hgroup.long 0xA24++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
|
|
hgroup.long 0xA28++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
|
|
hgroup.long 0xA2C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
|
|
hgroup.long 0xA30++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
|
|
hgroup.long 0xA34++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
|
|
hgroup.long 0xA38++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
|
|
hgroup.long 0xA3C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
|
|
hgroup.long 0xA40++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
|
|
hgroup.long 0xA44++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
|
|
hgroup.long 0xA48++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
|
|
hgroup.long 0xA4C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
|
|
hgroup.long 0xA50++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
|
|
hgroup.long 0xA54++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
|
|
hgroup.long 0xA58++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
|
|
hgroup.long 0xA5C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
|
|
hgroup.long 0xA60++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
|
|
hgroup.long 0xA64++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
|
|
hgroup.long 0xA68++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
|
|
hgroup.long 0xA6C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
|
|
hgroup.long 0xA70++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
|
|
hgroup.long 0xA74++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
|
|
hgroup.long 0xA78++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
|
|
hgroup.long 0xA7C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
|
|
hgroup.long 0xA80++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
|
|
hgroup.long 0xA84++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
|
|
hgroup.long 0xA88++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
|
|
hgroup.long 0xA8C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
|
|
hgroup.long 0xA90++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
|
|
hgroup.long 0xA94++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
|
|
hgroup.long 0xA98++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
|
|
hgroup.long 0xA9C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
|
|
hgroup.long 0xAA0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
|
|
hgroup.long 0xAA4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
|
|
hgroup.long 0xAA8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
|
|
hgroup.long 0xAAC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
|
|
hgroup.long 0xAB0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
|
|
hgroup.long 0xAB4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
|
|
hgroup.long 0xAB8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
|
|
hgroup.long 0xABC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
|
|
hgroup.long 0xAC0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
|
|
hgroup.long 0xAC4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
|
|
hgroup.long 0xAC8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
|
|
hgroup.long 0xACC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
|
|
hgroup.long 0xAD0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
|
|
hgroup.long 0xAD4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
|
|
hgroup.long 0xAD8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
|
|
hgroup.long 0xADC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
|
|
hgroup.long 0xAE0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
|
|
hgroup.long 0xAE4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
|
|
hgroup.long 0xAE8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
|
|
hgroup.long 0xAEC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
|
|
hgroup.long 0xAF0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
|
|
hgroup.long 0xAF4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
|
|
hgroup.long 0xAF8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
|
|
hgroup.long 0xAFC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
|
|
hgroup.long 0xB00++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
|
|
hgroup.long 0xB04++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
|
|
hgroup.long 0xB08++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
|
|
hgroup.long 0xB0C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
|
|
hgroup.long 0xB10++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
|
|
hgroup.long 0xB14++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
|
|
hgroup.long 0xB18++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
|
|
hgroup.long 0xB1C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
|
|
hgroup.long 0xB20++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
|
|
hgroup.long 0xB24++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
|
|
hgroup.long 0xB28++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
|
|
hgroup.long 0xB2C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
|
|
hgroup.long 0xB30++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
|
|
hgroup.long 0xB34++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
|
|
hgroup.long 0xB38++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
|
|
hgroup.long 0xB3C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
|
|
hgroup.long 0xB40++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
|
|
hgroup.long 0xB44++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
|
|
hgroup.long 0xB48++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
|
|
hgroup.long 0xB4C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
|
|
hgroup.long 0xB50++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
|
|
hgroup.long 0xB54++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
|
|
hgroup.long 0xB58++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
|
|
hgroup.long 0xB5C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
|
|
hgroup.long 0xB60++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
|
|
hgroup.long 0xB64++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
|
|
hgroup.long 0xB68++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
|
|
hgroup.long 0xB6C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
|
|
hgroup.long 0xB70++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
|
|
hgroup.long 0xB74++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
|
|
hgroup.long 0xB78++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
|
|
hgroup.long 0xB7C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
|
|
hgroup.long 0xB80++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
|
|
hgroup.long 0xB84++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
|
|
hgroup.long 0xB88++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
|
|
hgroup.long 0xB8C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
|
|
hgroup.long 0xB90++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
|
|
hgroup.long 0xB94++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
|
|
hgroup.long 0xB98++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
|
|
hgroup.long 0xB9C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
|
|
hgroup.long 0xBA0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
|
|
hgroup.long 0xBA4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
|
|
hgroup.long 0xBA8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
|
|
hgroup.long 0xBAC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
|
|
hgroup.long 0xBB0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
|
|
hgroup.long 0xBB4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
|
|
hgroup.long 0xBB8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
|
|
hgroup.long 0xBBC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
|
|
hgroup.long 0xBC0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
|
|
hgroup.long 0xBC4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
|
|
hgroup.long 0xBC8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
|
|
hgroup.long 0xBCC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
|
|
hgroup.long 0xBD0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
|
|
hgroup.long 0xBD4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
|
|
hgroup.long 0xBD8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
|
|
hgroup.long 0xBDC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
|
|
endif
|
|
tree.end
|
|
width 14.
|
|
tree "Configuration Registers"
|
|
rgroup.long 0xC00++0x03
|
|
line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SGI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SGI)" "Level,Edge"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (PPI)" "Level,Edge"
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC08++0x03
|
|
hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
|
|
hgroup.long 0xC0C++0x03
|
|
hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC14++0x03
|
|
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC10++0x03
|
|
hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
|
|
hgroup.long 0xC14++0x03
|
|
hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)
|
|
group.long 0xC18++0x03
|
|
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC1C++0x03
|
|
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC18++0x03
|
|
hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
|
|
hgroup.long 0xC1C++0x03
|
|
hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC24++0x03
|
|
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC20++0x03
|
|
hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
|
|
hgroup.long 0xC24++0x03
|
|
hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)
|
|
group.long 0xC28++0x03
|
|
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC2C++0x03
|
|
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC28++0x03
|
|
hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
|
|
hgroup.long 0xC2C++0x03
|
|
hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)
|
|
group.long 0xC30++0x03
|
|
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC34++0x03
|
|
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC30++0x03
|
|
hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
|
|
hgroup.long 0xC34++0x03
|
|
hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)
|
|
group.long 0xC38++0x03
|
|
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC3C++0x03
|
|
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC38++0x03
|
|
hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
|
|
hgroup.long 0xC3C++0x03
|
|
hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC44++0x03
|
|
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC40++0x03
|
|
hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
|
|
hgroup.long 0xC44++0x03
|
|
hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)
|
|
group.long 0xC48++0x03
|
|
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC4C++0x03
|
|
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC48++0x03
|
|
hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
|
|
hgroup.long 0xC4C++0x03
|
|
hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)
|
|
group.long 0xC50++0x03
|
|
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC54++0x03
|
|
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC50++0x03
|
|
hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
|
|
hgroup.long 0xC54++0x03
|
|
hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)
|
|
group.long 0xC58++0x03
|
|
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC5C++0x03
|
|
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC58++0x03
|
|
hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
|
|
hgroup.long 0xC5C++0x03
|
|
hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)
|
|
group.long 0xC60++0x03
|
|
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC64++0x03
|
|
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC60++0x03
|
|
hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
|
|
hgroup.long 0xC64++0x03
|
|
hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)
|
|
group.long 0xC68++0x03
|
|
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC6C++0x03
|
|
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC68++0x03
|
|
hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
|
|
hgroup.long 0xC6C++0x03
|
|
hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)
|
|
group.long 0xC70++0x03
|
|
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC74++0x03
|
|
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC70++0x03
|
|
hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
|
|
hgroup.long 0xC74++0x03
|
|
hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)
|
|
group.long 0xC78++0x03
|
|
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC7C++0x03
|
|
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC78++0x03
|
|
hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
|
|
hgroup.long 0xC7C++0x03
|
|
hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC84++0x03
|
|
line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC80++0x03
|
|
hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
|
|
hgroup.long 0xC84++0x03
|
|
hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
|
|
group.long 0xC88++0x03
|
|
line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC8C++0x03
|
|
line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC88++0x03
|
|
hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
|
|
hgroup.long 0xC8C++0x03
|
|
hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC94++0x03
|
|
line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC90++0x03
|
|
hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
|
|
hgroup.long 0xC94++0x03
|
|
hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
|
|
group.long 0xC98++0x03
|
|
line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xC9C++0x03
|
|
line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC98++0x03
|
|
hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
|
|
hgroup.long 0xC9C++0x03
|
|
hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
|
|
group.long 0xCA0++0x03
|
|
line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xCA4++0x03
|
|
line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCA0++0x03
|
|
hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
|
|
hgroup.long 0xCA4++0x03
|
|
hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
|
|
group.long 0xCA8++0x03
|
|
line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xCAC++0x03
|
|
line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCA8++0x03
|
|
hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
|
|
hgroup.long 0xCAC++0x03
|
|
hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
|
|
group.long 0xCB0++0x03
|
|
line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xCB4++0x03
|
|
line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCB0++0x03
|
|
hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
|
|
hgroup.long 0xCB4++0x03
|
|
hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
|
|
group.long 0xCB8++0x03
|
|
line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xCBC++0x03
|
|
line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCB8++0x03
|
|
hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
|
|
hgroup.long 0xCBC++0x03
|
|
hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
|
|
group.long 0xCC0++0x03
|
|
line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xCC4++0x03
|
|
line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCC0++0x03
|
|
hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
|
|
hgroup.long 0xCC4++0x03
|
|
hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
|
|
group.long 0xCC8++0x03
|
|
line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xCCC++0x03
|
|
line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCC8++0x03
|
|
hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
|
|
hgroup.long 0xCCC++0x03
|
|
hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0xCD0++0x03
|
|
line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xCD4++0x03
|
|
line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCD0++0x03
|
|
hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
|
|
hgroup.long 0xCD4++0x03
|
|
hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0xCD8++0x03
|
|
line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xCDC++0x03
|
|
line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCD8++0x03
|
|
hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
|
|
hgroup.long 0xCDC++0x03
|
|
hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0xCE0++0x03
|
|
line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xCE4++0x03
|
|
line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCE0++0x03
|
|
hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
|
|
hgroup.long 0xCE4++0x03
|
|
hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0xCE8++0x03
|
|
line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xCEC++0x03
|
|
line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCE8++0x03
|
|
hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
|
|
hgroup.long 0xCEC++0x03
|
|
hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0xCF0++0x03
|
|
line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
group.long 0xCF4++0x03
|
|
line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCF0++0x03
|
|
hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
|
|
hgroup.long 0xCF4++0x03
|
|
hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
|
|
endif
|
|
tree.end
|
|
width 17.
|
|
tree "Interrupt Group Modifier Registers"
|
|
hgroup.long 0x0D00++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01))
|
|
group.long 0x0D04++0x03
|
|
line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1"
|
|
bitfld.long 0x00 31. " GMB63 ,Group Modifier Bit 63" "0,1"
|
|
bitfld.long 0x00 30. " GMB62 ,Group Modifier Bit 62" "0,1"
|
|
bitfld.long 0x00 29. " GMB61 ,Group Modifier Bit 61" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB60 ,Group Modifier Bit 60" "0,1"
|
|
bitfld.long 0x00 27. " GMB59 ,Group Modifier Bit 59" "0,1"
|
|
bitfld.long 0x00 26. " GMB58 ,Group Modifier Bit 58" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB57 ,Group Modifier Bit 57" "0,1"
|
|
bitfld.long 0x00 24. " GMB56 ,Group Modifier Bit 56" "0,1"
|
|
bitfld.long 0x00 23. " GMB55 ,Group Modifier Bit 55" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB54 ,Group Modifier Bit 54" "0,1"
|
|
bitfld.long 0x00 21. " GMB53 ,Group Modifier Bit 53" "0,1"
|
|
bitfld.long 0x00 20. " GMB52 ,Group Modifier Bit 52" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB51 ,Group Modifier Bit 51" "0,1"
|
|
bitfld.long 0x00 18. " GMB50 ,Group Modifier Bit 50" "0,1"
|
|
bitfld.long 0x00 17. " GMB49 ,Group Modifier Bit 49" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB48 ,Group Modifier Bit 48" "0,1"
|
|
bitfld.long 0x00 15. " GMB47 ,Group Modifier Bit 47" "0,1"
|
|
bitfld.long 0x00 14. " GMB46 ,Group Modifier Bit 46" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB45 ,Group Modifier Bit 45" "0,1"
|
|
bitfld.long 0x00 12. " GMB44 ,Group Modifier Bit 44" "0,1"
|
|
bitfld.long 0x00 11. " GMB43 ,Group Modifier Bit 43" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB42 ,Group Modifier Bit 42" "0,1"
|
|
bitfld.long 0x00 9. " GMB41 ,Group Modifier Bit 41" "0,1"
|
|
bitfld.long 0x00 8. " GMB40 ,Group Modifier Bit 40" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB39 ,Group Modifier Bit 39" "0,1"
|
|
bitfld.long 0x00 6. " GMB38 ,Group Modifier Bit 38" "0,1"
|
|
bitfld.long 0x00 5. " GMB37 ,Group Modifier Bit 37" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB36 ,Group Modifier Bit 36" "0,1"
|
|
bitfld.long 0x00 3. " GMB35 ,Group Modifier Bit 35" "0,1"
|
|
bitfld.long 0x00 2. " GMB34 ,Group Modifier Bit 34" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB33 ,Group Modifier Bit 33" "0,1"
|
|
bitfld.long 0x00 0. " GMB32 ,Group Modifier Bit 32" "0,1"
|
|
else
|
|
hgroup.long 0x0D04++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02))
|
|
group.long 0x0D08++0x03
|
|
line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2"
|
|
bitfld.long 0x00 31. " GMB95 ,Group Modifier Bit 95" "0,1"
|
|
bitfld.long 0x00 30. " GMB94 ,Group Modifier Bit 94" "0,1"
|
|
bitfld.long 0x00 29. " GMB93 ,Group Modifier Bit 93" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB92 ,Group Modifier Bit 92" "0,1"
|
|
bitfld.long 0x00 27. " GMB91 ,Group Modifier Bit 91" "0,1"
|
|
bitfld.long 0x00 26. " GMB90 ,Group Modifier Bit 90" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB89 ,Group Modifier Bit 89" "0,1"
|
|
bitfld.long 0x00 24. " GMB88 ,Group Modifier Bit 88" "0,1"
|
|
bitfld.long 0x00 23. " GMB87 ,Group Modifier Bit 87" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB86 ,Group Modifier Bit 86" "0,1"
|
|
bitfld.long 0x00 21. " GMB85 ,Group Modifier Bit 85" "0,1"
|
|
bitfld.long 0x00 20. " GMB84 ,Group Modifier Bit 84" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB83 ,Group Modifier Bit 83" "0,1"
|
|
bitfld.long 0x00 18. " GMB82 ,Group Modifier Bit 82" "0,1"
|
|
bitfld.long 0x00 17. " GMB81 ,Group Modifier Bit 81" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB80 ,Group Modifier Bit 80" "0,1"
|
|
bitfld.long 0x00 15. " GMB79 ,Group Modifier Bit 79" "0,1"
|
|
bitfld.long 0x00 14. " GMB78 ,Group Modifier Bit 78" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB77 ,Group Modifier Bit 77" "0,1"
|
|
bitfld.long 0x00 12. " GMB76 ,Group Modifier Bit 76" "0,1"
|
|
bitfld.long 0x00 11. " GMB75 ,Group Modifier Bit 75" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB74 ,Group Modifier Bit 74" "0,1"
|
|
bitfld.long 0x00 9. " GMB73 ,Group Modifier Bit 73" "0,1"
|
|
bitfld.long 0x00 8. " GMB72 ,Group Modifier Bit 72" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB71 ,Group Modifier Bit 71" "0,1"
|
|
bitfld.long 0x00 6. " GMB70 ,Group Modifier Bit 70" "0,1"
|
|
bitfld.long 0x00 5. " GMB69 ,Group Modifier Bit 69" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB68 ,Group Modifier Bit 68" "0,1"
|
|
bitfld.long 0x00 3. " GMB67 ,Group Modifier Bit 67" "0,1"
|
|
bitfld.long 0x00 2. " GMB66 ,Group Modifier Bit 66" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB65 ,Group Modifier Bit 65" "0,1"
|
|
bitfld.long 0x00 0. " GMB64 ,Group Modifier Bit 64" "0,1"
|
|
else
|
|
hgroup.long 0x0D08++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03))
|
|
group.long 0x0D0C++0x03
|
|
line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3"
|
|
bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1"
|
|
bitfld.long 0x00 30. " GMB126 ,Group Modifier Bit 126" "0,1"
|
|
bitfld.long 0x00 29. " GMB125 ,Group Modifier Bit 125" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1"
|
|
bitfld.long 0x00 27. " GMB123 ,Group Modifier Bit 123" "0,1"
|
|
bitfld.long 0x00 26. " GMB122 ,Group Modifier Bit 122" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1"
|
|
bitfld.long 0x00 24. " GMB120 ,Group Modifier Bit 120" "0,1"
|
|
bitfld.long 0x00 23. " GMB119 ,Group Modifier Bit 119" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1"
|
|
bitfld.long 0x00 21. " GMB117 ,Group Modifier Bit 117" "0,1"
|
|
bitfld.long 0x00 20. " GMB116 ,Group Modifier Bit 116" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1"
|
|
bitfld.long 0x00 18. " GMB114 ,Group Modifier Bit 114" "0,1"
|
|
bitfld.long 0x00 17. " GMB113 ,Group Modifier Bit 113" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1"
|
|
bitfld.long 0x00 15. " GMB111 ,Group Modifier Bit 111" "0,1"
|
|
bitfld.long 0x00 14. " GMB110 ,Group Modifier Bit 110" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1"
|
|
bitfld.long 0x00 12. " GMB108 ,Group Modifier Bit 108" "0,1"
|
|
bitfld.long 0x00 11. " GMB107 ,Group Modifier Bit 107" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1"
|
|
bitfld.long 0x00 9. " GMB105 ,Group Modifier Bit 105" "0,1"
|
|
bitfld.long 0x00 8. " GMB104 ,Group Modifier Bit 104" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1"
|
|
bitfld.long 0x00 6. " GMB102 ,Group Modifier Bit 102" "0,1"
|
|
bitfld.long 0x00 5. " GMB101 ,Group Modifier Bit 101" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1"
|
|
bitfld.long 0x00 3. " GMB99 ,Group Modifier Bit 99" "0,1"
|
|
bitfld.long 0x00 2. " GMB98 ,Group Modifier Bit 98" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB97 ,Group Modifier Bit 97" "0,1"
|
|
bitfld.long 0x00 0. " GMB96 ,Group Modifier Bit 96" "0,1"
|
|
else
|
|
hgroup.long 0x0D0C++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04))
|
|
group.long 0x0D10++0x03
|
|
line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4"
|
|
bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1"
|
|
bitfld.long 0x00 30. " GMB158 ,Group Modifier Bit 158" "0,1"
|
|
bitfld.long 0x00 29. " GMB157 ,Group Modifier Bit 157" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1"
|
|
bitfld.long 0x00 27. " GMB155 ,Group Modifier Bit 155" "0,1"
|
|
bitfld.long 0x00 26. " GMB154 ,Group Modifier Bit 154" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1"
|
|
bitfld.long 0x00 24. " GMB152 ,Group Modifier Bit 152" "0,1"
|
|
bitfld.long 0x00 23. " GMB151 ,Group Modifier Bit 151" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1"
|
|
bitfld.long 0x00 21. " GMB149 ,Group Modifier Bit 149" "0,1"
|
|
bitfld.long 0x00 20. " GMB148 ,Group Modifier Bit 148" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1"
|
|
bitfld.long 0x00 18. " GMB146 ,Group Modifier Bit 146" "0,1"
|
|
bitfld.long 0x00 17. " GMB145 ,Group Modifier Bit 145" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1"
|
|
bitfld.long 0x00 15. " GMB143 ,Group Modifier Bit 143" "0,1"
|
|
bitfld.long 0x00 14. " GMB142 ,Group Modifier Bit 142" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1"
|
|
bitfld.long 0x00 12. " GMB140 ,Group Modifier Bit 140" "0,1"
|
|
bitfld.long 0x00 11. " GMB139 ,Group Modifier Bit 139" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1"
|
|
bitfld.long 0x00 9. " GMB137 ,Group Modifier Bit 137" "0,1"
|
|
bitfld.long 0x00 8. " GMB136 ,Group Modifier Bit 136" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1"
|
|
bitfld.long 0x00 6. " GMB134 ,Group Modifier Bit 134" "0,1"
|
|
bitfld.long 0x00 5. " GMB133 ,Group Modifier Bit 133" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1"
|
|
bitfld.long 0x00 3. " GMB131 ,Group Modifier Bit 131" "0,1"
|
|
bitfld.long 0x00 2. " GMB130 ,Group Modifier Bit 130" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1"
|
|
bitfld.long 0x00 0. " GMB128 ,Group Modifier Bit 128" "0,1"
|
|
else
|
|
hgroup.long 0x0D10++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05))
|
|
group.long 0x0D14++0x03
|
|
line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5"
|
|
bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1"
|
|
bitfld.long 0x00 30. " GMB190 ,Group Modifier Bit 190" "0,1"
|
|
bitfld.long 0x00 29. " GMB189 ,Group Modifier Bit 189" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1"
|
|
bitfld.long 0x00 27. " GMB187 ,Group Modifier Bit 187" "0,1"
|
|
bitfld.long 0x00 26. " GMB186 ,Group Modifier Bit 186" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1"
|
|
bitfld.long 0x00 24. " GMB184 ,Group Modifier Bit 184" "0,1"
|
|
bitfld.long 0x00 23. " GMB183 ,Group Modifier Bit 183" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1"
|
|
bitfld.long 0x00 21. " GMB181 ,Group Modifier Bit 181" "0,1"
|
|
bitfld.long 0x00 20. " GMB180 ,Group Modifier Bit 180" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1"
|
|
bitfld.long 0x00 18. " GMB178 ,Group Modifier Bit 178" "0,1"
|
|
bitfld.long 0x00 17. " GMB177 ,Group Modifier Bit 177" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1"
|
|
bitfld.long 0x00 15. " GMB175 ,Group Modifier Bit 175" "0,1"
|
|
bitfld.long 0x00 14. " GMB174 ,Group Modifier Bit 174" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1"
|
|
bitfld.long 0x00 12. " GMB172 ,Group Modifier Bit 172" "0,1"
|
|
bitfld.long 0x00 11. " GMB171 ,Group Modifier Bit 171" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1"
|
|
bitfld.long 0x00 9. " GMB169 ,Group Modifier Bit 169" "0,1"
|
|
bitfld.long 0x00 8. " GMB168 ,Group Modifier Bit 168" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1"
|
|
bitfld.long 0x00 6. " GMB166 ,Group Modifier Bit 166" "0,1"
|
|
bitfld.long 0x00 5. " GMB165 ,Group Modifier Bit 165" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1"
|
|
bitfld.long 0x00 3. " GMB163 ,Group Modifier Bit 163" "0,1"
|
|
bitfld.long 0x00 2. " GMB162 ,Group Modifier Bit 162" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1"
|
|
bitfld.long 0x00 0. " GMB160 ,Group Modifier Bit 160" "0,1"
|
|
else
|
|
hgroup.long 0x0D14++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06))
|
|
group.long 0x0D18++0x03
|
|
line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6"
|
|
bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1"
|
|
bitfld.long 0x00 30. " GMB222 ,Group Modifier Bit 222" "0,1"
|
|
bitfld.long 0x00 29. " GMB221 ,Group Modifier Bit 221" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1"
|
|
bitfld.long 0x00 27. " GMB219 ,Group Modifier Bit 219" "0,1"
|
|
bitfld.long 0x00 26. " GMB218 ,Group Modifier Bit 218" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1"
|
|
bitfld.long 0x00 24. " GMB216 ,Group Modifier Bit 216" "0,1"
|
|
bitfld.long 0x00 23. " GMB215 ,Group Modifier Bit 215" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1"
|
|
bitfld.long 0x00 21. " GMB213 ,Group Modifier Bit 213" "0,1"
|
|
bitfld.long 0x00 20. " GMB212 ,Group Modifier Bit 212" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1"
|
|
bitfld.long 0x00 18. " GMB210 ,Group Modifier Bit 210" "0,1"
|
|
bitfld.long 0x00 17. " GMB209 ,Group Modifier Bit 209" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1"
|
|
bitfld.long 0x00 15. " GMB207 ,Group Modifier Bit 207" "0,1"
|
|
bitfld.long 0x00 14. " GMB206 ,Group Modifier Bit 206" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1"
|
|
bitfld.long 0x00 12. " GMB204 ,Group Modifier Bit 204" "0,1"
|
|
bitfld.long 0x00 11. " GMB203 ,Group Modifier Bit 203" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1"
|
|
bitfld.long 0x00 9. " GMB201 ,Group Modifier Bit 201" "0,1"
|
|
bitfld.long 0x00 8. " GMB200 ,Group Modifier Bit 200" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1"
|
|
bitfld.long 0x00 6. " GMB198 ,Group Modifier Bit 198" "0,1"
|
|
bitfld.long 0x00 5. " GMB197 ,Group Modifier Bit 197" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1"
|
|
bitfld.long 0x00 3. " GMB195 ,Group Modifier Bit 195" "0,1"
|
|
bitfld.long 0x00 2. " GMB194 ,Group Modifier Bit 194" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1"
|
|
bitfld.long 0x00 0. " GMB192 ,Group Modifier Bit 192" "0,1"
|
|
else
|
|
hgroup.long 0x0D18++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07))
|
|
group.long 0x0D1C++0x03
|
|
line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7"
|
|
bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1"
|
|
bitfld.long 0x00 30. " GMB254 ,Group Modifier Bit 254" "0,1"
|
|
bitfld.long 0x00 29. " GMB253 ,Group Modifier Bit 253" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1"
|
|
bitfld.long 0x00 27. " GMB251 ,Group Modifier Bit 251" "0,1"
|
|
bitfld.long 0x00 26. " GMB250 ,Group Modifier Bit 250" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1"
|
|
bitfld.long 0x00 24. " GMB248 ,Group Modifier Bit 248" "0,1"
|
|
bitfld.long 0x00 23. " GMB247 ,Group Modifier Bit 247" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1"
|
|
bitfld.long 0x00 21. " GMB245 ,Group Modifier Bit 245" "0,1"
|
|
bitfld.long 0x00 20. " GMB244 ,Group Modifier Bit 244" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1"
|
|
bitfld.long 0x00 18. " GMB242 ,Group Modifier Bit 242" "0,1"
|
|
bitfld.long 0x00 17. " GMB241 ,Group Modifier Bit 241" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1"
|
|
bitfld.long 0x00 15. " GMB239 ,Group Modifier Bit 239" "0,1"
|
|
bitfld.long 0x00 14. " GMB238 ,Group Modifier Bit 238" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1"
|
|
bitfld.long 0x00 12. " GMB236 ,Group Modifier Bit 236" "0,1"
|
|
bitfld.long 0x00 11. " GMB235 ,Group Modifier Bit 235" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1"
|
|
bitfld.long 0x00 9. " GMB233 ,Group Modifier Bit 233" "0,1"
|
|
bitfld.long 0x00 8. " GMB232 ,Group Modifier Bit 232" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1"
|
|
bitfld.long 0x00 6. " GMB230 ,Group Modifier Bit 230" "0,1"
|
|
bitfld.long 0x00 5. " GMB229 ,Group Modifier Bit 229" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1"
|
|
bitfld.long 0x00 3. " GMB227 ,Group Modifier Bit 227" "0,1"
|
|
bitfld.long 0x00 2. " GMB226 ,Group Modifier Bit 226" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1"
|
|
bitfld.long 0x00 0. " GMB224 ,Group Modifier Bit 224" "0,1"
|
|
else
|
|
hgroup.long 0x0D1C++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08))
|
|
group.long 0x0D20++0x03
|
|
line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8"
|
|
bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1"
|
|
bitfld.long 0x00 30. " GMB286 ,Group Modifier Bit 286" "0,1"
|
|
bitfld.long 0x00 29. " GMB285 ,Group Modifier Bit 285" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1"
|
|
bitfld.long 0x00 27. " GMB283 ,Group Modifier Bit 283" "0,1"
|
|
bitfld.long 0x00 26. " GMB282 ,Group Modifier Bit 282" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1"
|
|
bitfld.long 0x00 24. " GMB280 ,Group Modifier Bit 280" "0,1"
|
|
bitfld.long 0x00 23. " GMB279 ,Group Modifier Bit 279" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1"
|
|
bitfld.long 0x00 21. " GMB277 ,Group Modifier Bit 277" "0,1"
|
|
bitfld.long 0x00 20. " GMB276 ,Group Modifier Bit 276" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1"
|
|
bitfld.long 0x00 18. " GMB274 ,Group Modifier Bit 274" "0,1"
|
|
bitfld.long 0x00 17. " GMB273 ,Group Modifier Bit 273" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1"
|
|
bitfld.long 0x00 15. " GMB271 ,Group Modifier Bit 271" "0,1"
|
|
bitfld.long 0x00 14. " GMB270 ,Group Modifier Bit 270" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1"
|
|
bitfld.long 0x00 12. " GMB268 ,Group Modifier Bit 268" "0,1"
|
|
bitfld.long 0x00 11. " GMB267 ,Group Modifier Bit 267" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1"
|
|
bitfld.long 0x00 9. " GMB265 ,Group Modifier Bit 265" "0,1"
|
|
bitfld.long 0x00 8. " GMB264 ,Group Modifier Bit 264" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1"
|
|
bitfld.long 0x00 6. " GMB262 ,Group Modifier Bit 262" "0,1"
|
|
bitfld.long 0x00 5. " GMB261 ,Group Modifier Bit 261" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1"
|
|
bitfld.long 0x00 3. " GMB259 ,Group Modifier Bit 259" "0,1"
|
|
bitfld.long 0x00 2. " GMB258 ,Group Modifier Bit 258" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1"
|
|
bitfld.long 0x00 0. " GMB256 ,Group Modifier Bit 256" "0,1"
|
|
else
|
|
hgroup.long 0x0D20++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09))
|
|
group.long 0x0D24++0x03
|
|
line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9"
|
|
bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1"
|
|
bitfld.long 0x00 30. " GMB318 ,Group Modifier Bit 318" "0,1"
|
|
bitfld.long 0x00 29. " GMB317 ,Group Modifier Bit 317" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1"
|
|
bitfld.long 0x00 27. " GMB315 ,Group Modifier Bit 315" "0,1"
|
|
bitfld.long 0x00 26. " GMB314 ,Group Modifier Bit 314" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1"
|
|
bitfld.long 0x00 24. " GMB312 ,Group Modifier Bit 312" "0,1"
|
|
bitfld.long 0x00 23. " GMB311 ,Group Modifier Bit 311" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1"
|
|
bitfld.long 0x00 21. " GMB309 ,Group Modifier Bit 309" "0,1"
|
|
bitfld.long 0x00 20. " GMB308 ,Group Modifier Bit 308" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1"
|
|
bitfld.long 0x00 18. " GMB306 ,Group Modifier Bit 306" "0,1"
|
|
bitfld.long 0x00 17. " GMB305 ,Group Modifier Bit 305" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1"
|
|
bitfld.long 0x00 15. " GMB303 ,Group Modifier Bit 303" "0,1"
|
|
bitfld.long 0x00 14. " GMB302 ,Group Modifier Bit 302" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1"
|
|
bitfld.long 0x00 12. " GMB300 ,Group Modifier Bit 300" "0,1"
|
|
bitfld.long 0x00 11. " GMB299 ,Group Modifier Bit 299" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1"
|
|
bitfld.long 0x00 9. " GMB297 ,Group Modifier Bit 297" "0,1"
|
|
bitfld.long 0x00 8. " GMB296 ,Group Modifier Bit 296" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1"
|
|
bitfld.long 0x00 6. " GMB294 ,Group Modifier Bit 294" "0,1"
|
|
bitfld.long 0x00 5. " GMB293 ,Group Modifier Bit 293" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1"
|
|
bitfld.long 0x00 3. " GMB291 ,Group Modifier Bit 291" "0,1"
|
|
bitfld.long 0x00 2. " GMB290 ,Group Modifier Bit 290" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1"
|
|
bitfld.long 0x00 0. " GMB288 ,Group Modifier Bit 288" "0,1"
|
|
else
|
|
hgroup.long 0x0D24++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A))
|
|
group.long 0x0D28++0x03
|
|
line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10"
|
|
bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1"
|
|
bitfld.long 0x00 30. " GMB350 ,Group Modifier Bit 350" "0,1"
|
|
bitfld.long 0x00 29. " GMB349 ,Group Modifier Bit 349" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1"
|
|
bitfld.long 0x00 27. " GMB347 ,Group Modifier Bit 347" "0,1"
|
|
bitfld.long 0x00 26. " GMB346 ,Group Modifier Bit 346" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1"
|
|
bitfld.long 0x00 24. " GMB344 ,Group Modifier Bit 344" "0,1"
|
|
bitfld.long 0x00 23. " GMB343 ,Group Modifier Bit 343" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1"
|
|
bitfld.long 0x00 21. " GMB341 ,Group Modifier Bit 341" "0,1"
|
|
bitfld.long 0x00 20. " GMB340 ,Group Modifier Bit 340" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1"
|
|
bitfld.long 0x00 18. " GMB338 ,Group Modifier Bit 338" "0,1"
|
|
bitfld.long 0x00 17. " GMB337 ,Group Modifier Bit 337" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1"
|
|
bitfld.long 0x00 15. " GMB335 ,Group Modifier Bit 335" "0,1"
|
|
bitfld.long 0x00 14. " GMB334 ,Group Modifier Bit 334" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1"
|
|
bitfld.long 0x00 12. " GMB332 ,Group Modifier Bit 332" "0,1"
|
|
bitfld.long 0x00 11. " GMB331 ,Group Modifier Bit 331" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1"
|
|
bitfld.long 0x00 9. " GMB329 ,Group Modifier Bit 329" "0,1"
|
|
bitfld.long 0x00 8. " GMB328 ,Group Modifier Bit 328" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1"
|
|
bitfld.long 0x00 6. " GMB326 ,Group Modifier Bit 326" "0,1"
|
|
bitfld.long 0x00 5. " GMB325 ,Group Modifier Bit 325" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1"
|
|
bitfld.long 0x00 3. " GMB323 ,Group Modifier Bit 323" "0,1"
|
|
bitfld.long 0x00 2. " GMB322 ,Group Modifier Bit 322" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1"
|
|
bitfld.long 0x00 0. " GMB320 ,Group Modifier Bit 320" "0,1"
|
|
else
|
|
hgroup.long 0x0D28++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B))
|
|
group.long 0x0D2C++0x03
|
|
line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11"
|
|
bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1"
|
|
bitfld.long 0x00 30. " GMB382 ,Group Modifier Bit 382" "0,1"
|
|
bitfld.long 0x00 29. " GMB381 ,Group Modifier Bit 381" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1"
|
|
bitfld.long 0x00 27. " GMB379 ,Group Modifier Bit 379" "0,1"
|
|
bitfld.long 0x00 26. " GMB378 ,Group Modifier Bit 378" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1"
|
|
bitfld.long 0x00 24. " GMB376 ,Group Modifier Bit 376" "0,1"
|
|
bitfld.long 0x00 23. " GMB375 ,Group Modifier Bit 375" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1"
|
|
bitfld.long 0x00 21. " GMB373 ,Group Modifier Bit 373" "0,1"
|
|
bitfld.long 0x00 20. " GMB372 ,Group Modifier Bit 372" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1"
|
|
bitfld.long 0x00 18. " GMB370 ,Group Modifier Bit 370" "0,1"
|
|
bitfld.long 0x00 17. " GMB369 ,Group Modifier Bit 369" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1"
|
|
bitfld.long 0x00 15. " GMB367 ,Group Modifier Bit 367" "0,1"
|
|
bitfld.long 0x00 14. " GMB366 ,Group Modifier Bit 366" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1"
|
|
bitfld.long 0x00 12. " GMB364 ,Group Modifier Bit 364" "0,1"
|
|
bitfld.long 0x00 11. " GMB363 ,Group Modifier Bit 363" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1"
|
|
bitfld.long 0x00 9. " GMB361 ,Group Modifier Bit 361" "0,1"
|
|
bitfld.long 0x00 8. " GMB360 ,Group Modifier Bit 360" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1"
|
|
bitfld.long 0x00 6. " GMB358 ,Group Modifier Bit 358" "0,1"
|
|
bitfld.long 0x00 5. " GMB357 ,Group Modifier Bit 357" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1"
|
|
bitfld.long 0x00 3. " GMB355 ,Group Modifier Bit 355" "0,1"
|
|
bitfld.long 0x00 2. " GMB354 ,Group Modifier Bit 354" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1"
|
|
bitfld.long 0x00 0. " GMB352 ,Group Modifier Bit 352" "0,1"
|
|
else
|
|
hgroup.long 0x0D2C++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C))
|
|
group.long 0x0D30++0x03
|
|
line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12"
|
|
bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1"
|
|
bitfld.long 0x00 30. " GMB414 ,Group Modifier Bit 414" "0,1"
|
|
bitfld.long 0x00 29. " GMB413 ,Group Modifier Bit 413" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1"
|
|
bitfld.long 0x00 27. " GMB411 ,Group Modifier Bit 411" "0,1"
|
|
bitfld.long 0x00 26. " GMB410 ,Group Modifier Bit 410" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1"
|
|
bitfld.long 0x00 24. " GMB408 ,Group Modifier Bit 408" "0,1"
|
|
bitfld.long 0x00 23. " GMB407 ,Group Modifier Bit 407" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1"
|
|
bitfld.long 0x00 21. " GMB405 ,Group Modifier Bit 405" "0,1"
|
|
bitfld.long 0x00 20. " GMB404 ,Group Modifier Bit 404" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1"
|
|
bitfld.long 0x00 18. " GMB402 ,Group Modifier Bit 402" "0,1"
|
|
bitfld.long 0x00 17. " GMB401 ,Group Modifier Bit 401" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1"
|
|
bitfld.long 0x00 15. " GMB399 ,Group Modifier Bit 399" "0,1"
|
|
bitfld.long 0x00 14. " GMB398 ,Group Modifier Bit 398" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1"
|
|
bitfld.long 0x00 12. " GMB396 ,Group Modifier Bit 396" "0,1"
|
|
bitfld.long 0x00 11. " GMB395 ,Group Modifier Bit 395" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1"
|
|
bitfld.long 0x00 9. " GMB393 ,Group Modifier Bit 393" "0,1"
|
|
bitfld.long 0x00 8. " GMB392 ,Group Modifier Bit 392" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1"
|
|
bitfld.long 0x00 6. " GMB390 ,Group Modifier Bit 390" "0,1"
|
|
bitfld.long 0x00 5. " GMB389 ,Group Modifier Bit 389" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1"
|
|
bitfld.long 0x00 3. " GMB387 ,Group Modifier Bit 387" "0,1"
|
|
bitfld.long 0x00 2. " GMB386 ,Group Modifier Bit 386" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1"
|
|
bitfld.long 0x00 0. " GMB384 ,Group Modifier Bit 384" "0,1"
|
|
else
|
|
hgroup.long 0x0D30++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D))
|
|
group.long 0x0D34++0x03
|
|
line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13"
|
|
bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1"
|
|
bitfld.long 0x00 30. " GMB446 ,Group Modifier Bit 446" "0,1"
|
|
bitfld.long 0x00 29. " GMB445 ,Group Modifier Bit 445" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1"
|
|
bitfld.long 0x00 27. " GMB443 ,Group Modifier Bit 443" "0,1"
|
|
bitfld.long 0x00 26. " GMB442 ,Group Modifier Bit 442" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1"
|
|
bitfld.long 0x00 24. " GMB440 ,Group Modifier Bit 440" "0,1"
|
|
bitfld.long 0x00 23. " GMB439 ,Group Modifier Bit 439" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1"
|
|
bitfld.long 0x00 21. " GMB437 ,Group Modifier Bit 437" "0,1"
|
|
bitfld.long 0x00 20. " GMB436 ,Group Modifier Bit 436" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1"
|
|
bitfld.long 0x00 18. " GMB434 ,Group Modifier Bit 434" "0,1"
|
|
bitfld.long 0x00 17. " GMB433 ,Group Modifier Bit 433" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1"
|
|
bitfld.long 0x00 15. " GMB431 ,Group Modifier Bit 431" "0,1"
|
|
bitfld.long 0x00 14. " GMB430 ,Group Modifier Bit 430" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1"
|
|
bitfld.long 0x00 12. " GMB428 ,Group Modifier Bit 428" "0,1"
|
|
bitfld.long 0x00 11. " GMB427 ,Group Modifier Bit 427" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1"
|
|
bitfld.long 0x00 9. " GMB425 ,Group Modifier Bit 425" "0,1"
|
|
bitfld.long 0x00 8. " GMB424 ,Group Modifier Bit 424" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1"
|
|
bitfld.long 0x00 6. " GMB422 ,Group Modifier Bit 422" "0,1"
|
|
bitfld.long 0x00 5. " GMB421 ,Group Modifier Bit 421" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1"
|
|
bitfld.long 0x00 3. " GMB419 ,Group Modifier Bit 419" "0,1"
|
|
bitfld.long 0x00 2. " GMB418 ,Group Modifier Bit 418" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1"
|
|
bitfld.long 0x00 0. " GMB416 ,Group Modifier Bit 416" "0,1"
|
|
else
|
|
hgroup.long 0x0D34++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E))
|
|
group.long 0x0D38++0x03
|
|
line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14"
|
|
bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1"
|
|
bitfld.long 0x00 30. " GMB478 ,Group Modifier Bit 478" "0,1"
|
|
bitfld.long 0x00 29. " GMB477 ,Group Modifier Bit 477" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1"
|
|
bitfld.long 0x00 27. " GMB475 ,Group Modifier Bit 475" "0,1"
|
|
bitfld.long 0x00 26. " GMB474 ,Group Modifier Bit 474" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1"
|
|
bitfld.long 0x00 24. " GMB472 ,Group Modifier Bit 472" "0,1"
|
|
bitfld.long 0x00 23. " GMB471 ,Group Modifier Bit 471" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1"
|
|
bitfld.long 0x00 21. " GMB469 ,Group Modifier Bit 469" "0,1"
|
|
bitfld.long 0x00 20. " GMB468 ,Group Modifier Bit 468" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1"
|
|
bitfld.long 0x00 18. " GMB466 ,Group Modifier Bit 466" "0,1"
|
|
bitfld.long 0x00 17. " GMB465 ,Group Modifier Bit 465" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1"
|
|
bitfld.long 0x00 15. " GMB463 ,Group Modifier Bit 463" "0,1"
|
|
bitfld.long 0x00 14. " GMB462 ,Group Modifier Bit 462" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1"
|
|
bitfld.long 0x00 12. " GMB460 ,Group Modifier Bit 460" "0,1"
|
|
bitfld.long 0x00 11. " GMB459 ,Group Modifier Bit 459" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1"
|
|
bitfld.long 0x00 9. " GMB457 ,Group Modifier Bit 457" "0,1"
|
|
bitfld.long 0x00 8. " GMB456 ,Group Modifier Bit 456" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1"
|
|
bitfld.long 0x00 6. " GMB454 ,Group Modifier Bit 454" "0,1"
|
|
bitfld.long 0x00 5. " GMB453 ,Group Modifier Bit 453" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1"
|
|
bitfld.long 0x00 3. " GMB451 ,Group Modifier Bit 451" "0,1"
|
|
bitfld.long 0x00 2. " GMB450 ,Group Modifier Bit 450" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1"
|
|
bitfld.long 0x00 0. " GMB448 ,Group Modifier Bit 448" "0,1"
|
|
else
|
|
hgroup.long 0x0D38++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F))
|
|
group.long 0x0D3C++0x03
|
|
line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15"
|
|
bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1"
|
|
bitfld.long 0x00 30. " GMB510 ,Group Modifier Bit 510" "0,1"
|
|
bitfld.long 0x00 29. " GMB509 ,Group Modifier Bit 509" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1"
|
|
bitfld.long 0x00 27. " GMB507 ,Group Modifier Bit 507" "0,1"
|
|
bitfld.long 0x00 26. " GMB506 ,Group Modifier Bit 506" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1"
|
|
bitfld.long 0x00 24. " GMB504 ,Group Modifier Bit 504" "0,1"
|
|
bitfld.long 0x00 23. " GMB503 ,Group Modifier Bit 503" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1"
|
|
bitfld.long 0x00 21. " GMB501 ,Group Modifier Bit 501" "0,1"
|
|
bitfld.long 0x00 20. " GMB500 ,Group Modifier Bit 500" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1"
|
|
bitfld.long 0x00 18. " GMB498 ,Group Modifier Bit 498" "0,1"
|
|
bitfld.long 0x00 17. " GMB497 ,Group Modifier Bit 497" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1"
|
|
bitfld.long 0x00 15. " GMB495 ,Group Modifier Bit 495" "0,1"
|
|
bitfld.long 0x00 14. " GMB494 ,Group Modifier Bit 494" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1"
|
|
bitfld.long 0x00 12. " GMB492 ,Group Modifier Bit 492" "0,1"
|
|
bitfld.long 0x00 11. " GMB491 ,Group Modifier Bit 491" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1"
|
|
bitfld.long 0x00 9. " GMB489 ,Group Modifier Bit 489" "0,1"
|
|
bitfld.long 0x00 8. " GMB488 ,Group Modifier Bit 488" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1"
|
|
bitfld.long 0x00 6. " GMB486 ,Group Modifier Bit 486" "0,1"
|
|
bitfld.long 0x00 5. " GMB485 ,Group Modifier Bit 485" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1"
|
|
bitfld.long 0x00 3. " GMB483 ,Group Modifier Bit 483" "0,1"
|
|
bitfld.long 0x00 2. " GMB482 ,Group Modifier Bit 482" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1"
|
|
bitfld.long 0x00 0. " GMB480 ,Group Modifier Bit 480" "0,1"
|
|
else
|
|
hgroup.long 0x0D3C++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
|
|
group.long 0x0D40++0x03
|
|
line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16"
|
|
bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1"
|
|
bitfld.long 0x00 30. " GMB542 ,Group Modifier Bit 542" "0,1"
|
|
bitfld.long 0x00 29. " GMB541 ,Group Modifier Bit 541" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1"
|
|
bitfld.long 0x00 27. " GMB539 ,Group Modifier Bit 539" "0,1"
|
|
bitfld.long 0x00 26. " GMB538 ,Group Modifier Bit 538" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1"
|
|
bitfld.long 0x00 24. " GMB536 ,Group Modifier Bit 536" "0,1"
|
|
bitfld.long 0x00 23. " GMB535 ,Group Modifier Bit 535" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1"
|
|
bitfld.long 0x00 21. " GMB533 ,Group Modifier Bit 533" "0,1"
|
|
bitfld.long 0x00 20. " GMB532 ,Group Modifier Bit 532" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1"
|
|
bitfld.long 0x00 18. " GMB530 ,Group Modifier Bit 530" "0,1"
|
|
bitfld.long 0x00 17. " GMB529 ,Group Modifier Bit 529" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1"
|
|
bitfld.long 0x00 15. " GMB527 ,Group Modifier Bit 527" "0,1"
|
|
bitfld.long 0x00 14. " GMB526 ,Group Modifier Bit 526" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1"
|
|
bitfld.long 0x00 12. " GMB524 ,Group Modifier Bit 524" "0,1"
|
|
bitfld.long 0x00 11. " GMB523 ,Group Modifier Bit 523" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1"
|
|
bitfld.long 0x00 9. " GMB521 ,Group Modifier Bit 521" "0,1"
|
|
bitfld.long 0x00 8. " GMB520 ,Group Modifier Bit 520" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1"
|
|
bitfld.long 0x00 6. " GMB518 ,Group Modifier Bit 518" "0,1"
|
|
bitfld.long 0x00 5. " GMB517 ,Group Modifier Bit 517" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1"
|
|
bitfld.long 0x00 3. " GMB515 ,Group Modifier Bit 515" "0,1"
|
|
bitfld.long 0x00 2. " GMB514 ,Group Modifier Bit 514" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1"
|
|
bitfld.long 0x00 0. " GMB512 ,Group Modifier Bit 512" "0,1"
|
|
else
|
|
hgroup.long 0x0D40++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
|
|
group.long 0x0D44++0x03
|
|
line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17"
|
|
bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1"
|
|
bitfld.long 0x00 30. " GMB574 ,Group Modifier Bit 574" "0,1"
|
|
bitfld.long 0x00 29. " GMB573 ,Group Modifier Bit 573" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1"
|
|
bitfld.long 0x00 27. " GMB571 ,Group Modifier Bit 571" "0,1"
|
|
bitfld.long 0x00 26. " GMB570 ,Group Modifier Bit 570" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1"
|
|
bitfld.long 0x00 24. " GMB568 ,Group Modifier Bit 568" "0,1"
|
|
bitfld.long 0x00 23. " GMB567 ,Group Modifier Bit 567" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1"
|
|
bitfld.long 0x00 21. " GMB565 ,Group Modifier Bit 565" "0,1"
|
|
bitfld.long 0x00 20. " GMB564 ,Group Modifier Bit 564" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1"
|
|
bitfld.long 0x00 18. " GMB562 ,Group Modifier Bit 562" "0,1"
|
|
bitfld.long 0x00 17. " GMB561 ,Group Modifier Bit 561" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1"
|
|
bitfld.long 0x00 15. " GMB559 ,Group Modifier Bit 559" "0,1"
|
|
bitfld.long 0x00 14. " GMB558 ,Group Modifier Bit 558" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1"
|
|
bitfld.long 0x00 12. " GMB556 ,Group Modifier Bit 556" "0,1"
|
|
bitfld.long 0x00 11. " GMB555 ,Group Modifier Bit 555" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1"
|
|
bitfld.long 0x00 9. " GMB553 ,Group Modifier Bit 553" "0,1"
|
|
bitfld.long 0x00 8. " GMB552 ,Group Modifier Bit 552" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1"
|
|
bitfld.long 0x00 6. " GMB550 ,Group Modifier Bit 550" "0,1"
|
|
bitfld.long 0x00 5. " GMB549 ,Group Modifier Bit 549" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1"
|
|
bitfld.long 0x00 3. " GMB547 ,Group Modifier Bit 547" "0,1"
|
|
bitfld.long 0x00 2. " GMB546 ,Group Modifier Bit 546" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1"
|
|
bitfld.long 0x00 0. " GMB544 ,Group Modifier Bit 544" "0,1"
|
|
else
|
|
hgroup.long 0x0D44++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
|
|
group.long 0x0D48++0x03
|
|
line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18"
|
|
bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1"
|
|
bitfld.long 0x00 30. " GMB606 ,Group Modifier Bit 606" "0,1"
|
|
bitfld.long 0x00 29. " GMB605 ,Group Modifier Bit 605" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1"
|
|
bitfld.long 0x00 27. " GMB603 ,Group Modifier Bit 603" "0,1"
|
|
bitfld.long 0x00 26. " GMB602 ,Group Modifier Bit 602" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1"
|
|
bitfld.long 0x00 24. " GMB600 ,Group Modifier Bit 600" "0,1"
|
|
bitfld.long 0x00 23. " GMB599 ,Group Modifier Bit 599" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1"
|
|
bitfld.long 0x00 21. " GMB597 ,Group Modifier Bit 597" "0,1"
|
|
bitfld.long 0x00 20. " GMB596 ,Group Modifier Bit 596" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1"
|
|
bitfld.long 0x00 18. " GMB594 ,Group Modifier Bit 594" "0,1"
|
|
bitfld.long 0x00 17. " GMB593 ,Group Modifier Bit 593" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1"
|
|
bitfld.long 0x00 15. " GMB591 ,Group Modifier Bit 591" "0,1"
|
|
bitfld.long 0x00 14. " GMB590 ,Group Modifier Bit 590" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1"
|
|
bitfld.long 0x00 12. " GMB588 ,Group Modifier Bit 588" "0,1"
|
|
bitfld.long 0x00 11. " GMB587 ,Group Modifier Bit 587" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1"
|
|
bitfld.long 0x00 9. " GMB585 ,Group Modifier Bit 585" "0,1"
|
|
bitfld.long 0x00 8. " GMB584 ,Group Modifier Bit 584" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1"
|
|
bitfld.long 0x00 6. " GMB582 ,Group Modifier Bit 582" "0,1"
|
|
bitfld.long 0x00 5. " GMB581 ,Group Modifier Bit 581" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1"
|
|
bitfld.long 0x00 3. " GMB579 ,Group Modifier Bit 579" "0,1"
|
|
bitfld.long 0x00 2. " GMB578 ,Group Modifier Bit 578" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1"
|
|
bitfld.long 0x00 0. " GMB576 ,Group Modifier Bit 576" "0,1"
|
|
else
|
|
hgroup.long 0x0D48++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
|
|
group.long 0x0D4C++0x03
|
|
line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19"
|
|
bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1"
|
|
bitfld.long 0x00 30. " GMB638 ,Group Modifier Bit 638" "0,1"
|
|
bitfld.long 0x00 29. " GMB637 ,Group Modifier Bit 637" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1"
|
|
bitfld.long 0x00 27. " GMB635 ,Group Modifier Bit 635" "0,1"
|
|
bitfld.long 0x00 26. " GMB634 ,Group Modifier Bit 634" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1"
|
|
bitfld.long 0x00 24. " GMB632 ,Group Modifier Bit 632" "0,1"
|
|
bitfld.long 0x00 23. " GMB631 ,Group Modifier Bit 631" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1"
|
|
bitfld.long 0x00 21. " GMB629 ,Group Modifier Bit 629" "0,1"
|
|
bitfld.long 0x00 20. " GMB628 ,Group Modifier Bit 628" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1"
|
|
bitfld.long 0x00 18. " GMB626 ,Group Modifier Bit 626" "0,1"
|
|
bitfld.long 0x00 17. " GMB625 ,Group Modifier Bit 625" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1"
|
|
bitfld.long 0x00 15. " GMB623 ,Group Modifier Bit 623" "0,1"
|
|
bitfld.long 0x00 14. " GMB622 ,Group Modifier Bit 622" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1"
|
|
bitfld.long 0x00 12. " GMB620 ,Group Modifier Bit 620" "0,1"
|
|
bitfld.long 0x00 11. " GMB619 ,Group Modifier Bit 619" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1"
|
|
bitfld.long 0x00 9. " GMB617 ,Group Modifier Bit 617" "0,1"
|
|
bitfld.long 0x00 8. " GMB616 ,Group Modifier Bit 616" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1"
|
|
bitfld.long 0x00 6. " GMB614 ,Group Modifier Bit 614" "0,1"
|
|
bitfld.long 0x00 5. " GMB613 ,Group Modifier Bit 613" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1"
|
|
bitfld.long 0x00 3. " GMB611 ,Group Modifier Bit 611" "0,1"
|
|
bitfld.long 0x00 2. " GMB610 ,Group Modifier Bit 610" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1"
|
|
bitfld.long 0x00 0. " GMB608 ,Group Modifier Bit 608" "0,1"
|
|
else
|
|
hgroup.long 0x0D4C++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
|
|
group.long 0x0D50++0x03
|
|
line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20"
|
|
bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1"
|
|
bitfld.long 0x00 30. " GMB670 ,Group Modifier Bit 670" "0,1"
|
|
bitfld.long 0x00 29. " GMB669 ,Group Modifier Bit 669" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1"
|
|
bitfld.long 0x00 27. " GMB667 ,Group Modifier Bit 667" "0,1"
|
|
bitfld.long 0x00 26. " GMB666 ,Group Modifier Bit 666" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1"
|
|
bitfld.long 0x00 24. " GMB664 ,Group Modifier Bit 664" "0,1"
|
|
bitfld.long 0x00 23. " GMB663 ,Group Modifier Bit 663" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1"
|
|
bitfld.long 0x00 21. " GMB661 ,Group Modifier Bit 661" "0,1"
|
|
bitfld.long 0x00 20. " GMB660 ,Group Modifier Bit 660" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1"
|
|
bitfld.long 0x00 18. " GMB658 ,Group Modifier Bit 658" "0,1"
|
|
bitfld.long 0x00 17. " GMB657 ,Group Modifier Bit 657" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1"
|
|
bitfld.long 0x00 15. " GMB655 ,Group Modifier Bit 655" "0,1"
|
|
bitfld.long 0x00 14. " GMB654 ,Group Modifier Bit 654" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1"
|
|
bitfld.long 0x00 12. " GMB652 ,Group Modifier Bit 652" "0,1"
|
|
bitfld.long 0x00 11. " GMB651 ,Group Modifier Bit 651" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1"
|
|
bitfld.long 0x00 9. " GMB649 ,Group Modifier Bit 649" "0,1"
|
|
bitfld.long 0x00 8. " GMB648 ,Group Modifier Bit 648" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1"
|
|
bitfld.long 0x00 6. " GMB646 ,Group Modifier Bit 646" "0,1"
|
|
bitfld.long 0x00 5. " GMB645 ,Group Modifier Bit 645" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1"
|
|
bitfld.long 0x00 3. " GMB643 ,Group Modifier Bit 643" "0,1"
|
|
bitfld.long 0x00 2. " GMB642 ,Group Modifier Bit 642" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1"
|
|
bitfld.long 0x00 0. " GMB640 ,Group Modifier Bit 640" "0,1"
|
|
else
|
|
hgroup.long 0x0D50++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
|
|
group.long 0x0D54++0x03
|
|
line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21"
|
|
bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1"
|
|
bitfld.long 0x00 30. " GMB702 ,Group Modifier Bit 702" "0,1"
|
|
bitfld.long 0x00 29. " GMB701 ,Group Modifier Bit 701" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1"
|
|
bitfld.long 0x00 27. " GMB699 ,Group Modifier Bit 699" "0,1"
|
|
bitfld.long 0x00 26. " GMB698 ,Group Modifier Bit 698" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1"
|
|
bitfld.long 0x00 24. " GMB696 ,Group Modifier Bit 696" "0,1"
|
|
bitfld.long 0x00 23. " GMB695 ,Group Modifier Bit 695" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1"
|
|
bitfld.long 0x00 21. " GMB693 ,Group Modifier Bit 693" "0,1"
|
|
bitfld.long 0x00 20. " GMB692 ,Group Modifier Bit 692" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1"
|
|
bitfld.long 0x00 18. " GMB690 ,Group Modifier Bit 690" "0,1"
|
|
bitfld.long 0x00 17. " GMB689 ,Group Modifier Bit 689" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1"
|
|
bitfld.long 0x00 15. " GMB687 ,Group Modifier Bit 687" "0,1"
|
|
bitfld.long 0x00 14. " GMB686 ,Group Modifier Bit 686" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1"
|
|
bitfld.long 0x00 12. " GMB684 ,Group Modifier Bit 684" "0,1"
|
|
bitfld.long 0x00 11. " GMB683 ,Group Modifier Bit 683" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1"
|
|
bitfld.long 0x00 9. " GMB681 ,Group Modifier Bit 681" "0,1"
|
|
bitfld.long 0x00 8. " GMB680 ,Group Modifier Bit 680" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1"
|
|
bitfld.long 0x00 6. " GMB678 ,Group Modifier Bit 678" "0,1"
|
|
bitfld.long 0x00 5. " GMB677 ,Group Modifier Bit 677" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1"
|
|
bitfld.long 0x00 3. " GMB675 ,Group Modifier Bit 675" "0,1"
|
|
bitfld.long 0x00 2. " GMB674 ,Group Modifier Bit 674" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1"
|
|
bitfld.long 0x00 0. " GMB672 ,Group Modifier Bit 672" "0,1"
|
|
else
|
|
hgroup.long 0x0D54++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
|
|
group.long 0x0D58++0x03
|
|
line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22"
|
|
bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1"
|
|
bitfld.long 0x00 30. " GMB734 ,Group Modifier Bit 734" "0,1"
|
|
bitfld.long 0x00 29. " GMB733 ,Group Modifier Bit 733" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1"
|
|
bitfld.long 0x00 27. " GMB731 ,Group Modifier Bit 731" "0,1"
|
|
bitfld.long 0x00 26. " GMB730 ,Group Modifier Bit 730" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1"
|
|
bitfld.long 0x00 24. " GMB728 ,Group Modifier Bit 728" "0,1"
|
|
bitfld.long 0x00 23. " GMB727 ,Group Modifier Bit 727" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1"
|
|
bitfld.long 0x00 21. " GMB725 ,Group Modifier Bit 725" "0,1"
|
|
bitfld.long 0x00 20. " GMB724 ,Group Modifier Bit 724" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1"
|
|
bitfld.long 0x00 18. " GMB722 ,Group Modifier Bit 722" "0,1"
|
|
bitfld.long 0x00 17. " GMB721 ,Group Modifier Bit 721" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1"
|
|
bitfld.long 0x00 15. " GMB719 ,Group Modifier Bit 719" "0,1"
|
|
bitfld.long 0x00 14. " GMB718 ,Group Modifier Bit 718" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1"
|
|
bitfld.long 0x00 12. " GMB716 ,Group Modifier Bit 716" "0,1"
|
|
bitfld.long 0x00 11. " GMB715 ,Group Modifier Bit 715" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1"
|
|
bitfld.long 0x00 9. " GMB713 ,Group Modifier Bit 713" "0,1"
|
|
bitfld.long 0x00 8. " GMB712 ,Group Modifier Bit 712" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1"
|
|
bitfld.long 0x00 6. " GMB710 ,Group Modifier Bit 710" "0,1"
|
|
bitfld.long 0x00 5. " GMB709 ,Group Modifier Bit 709" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1"
|
|
bitfld.long 0x00 3. " GMB707 ,Group Modifier Bit 707" "0,1"
|
|
bitfld.long 0x00 2. " GMB706 ,Group Modifier Bit 706" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1"
|
|
bitfld.long 0x00 0. " GMB704 ,Group Modifier Bit 704" "0,1"
|
|
else
|
|
hgroup.long 0x0D58++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
|
|
group.long 0x0D5C++0x03
|
|
line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23"
|
|
bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1"
|
|
bitfld.long 0x00 30. " GMB766 ,Group Modifier Bit 766" "0,1"
|
|
bitfld.long 0x00 29. " GMB765 ,Group Modifier Bit 765" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1"
|
|
bitfld.long 0x00 27. " GMB763 ,Group Modifier Bit 763" "0,1"
|
|
bitfld.long 0x00 26. " GMB762 ,Group Modifier Bit 762" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1"
|
|
bitfld.long 0x00 24. " GMB760 ,Group Modifier Bit 760" "0,1"
|
|
bitfld.long 0x00 23. " GMB759 ,Group Modifier Bit 759" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1"
|
|
bitfld.long 0x00 21. " GMB757 ,Group Modifier Bit 757" "0,1"
|
|
bitfld.long 0x00 20. " GMB756 ,Group Modifier Bit 756" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1"
|
|
bitfld.long 0x00 18. " GMB754 ,Group Modifier Bit 754" "0,1"
|
|
bitfld.long 0x00 17. " GMB753 ,Group Modifier Bit 753" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1"
|
|
bitfld.long 0x00 15. " GMB751 ,Group Modifier Bit 751" "0,1"
|
|
bitfld.long 0x00 14. " GMB750 ,Group Modifier Bit 750" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1"
|
|
bitfld.long 0x00 12. " GMB748 ,Group Modifier Bit 748" "0,1"
|
|
bitfld.long 0x00 11. " GMB747 ,Group Modifier Bit 747" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1"
|
|
bitfld.long 0x00 9. " GMB745 ,Group Modifier Bit 745" "0,1"
|
|
bitfld.long 0x00 8. " GMB744 ,Group Modifier Bit 744" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1"
|
|
bitfld.long 0x00 6. " GMB742 ,Group Modifier Bit 742" "0,1"
|
|
bitfld.long 0x00 5. " GMB741 ,Group Modifier Bit 741" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1"
|
|
bitfld.long 0x00 3. " GMB739 ,Group Modifier Bit 739" "0,1"
|
|
bitfld.long 0x00 2. " GMB738 ,Group Modifier Bit 738" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1"
|
|
bitfld.long 0x00 0. " GMB736 ,Group Modifier Bit 736" "0,1"
|
|
else
|
|
hgroup.long 0x0D5C++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
|
|
group.long 0x0D60++0x03
|
|
line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24"
|
|
bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1"
|
|
bitfld.long 0x00 30. " GMB798 ,Group Modifier Bit 798" "0,1"
|
|
bitfld.long 0x00 29. " GMB797 ,Group Modifier Bit 797" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1"
|
|
bitfld.long 0x00 27. " GMB795 ,Group Modifier Bit 795" "0,1"
|
|
bitfld.long 0x00 26. " GMB794 ,Group Modifier Bit 794" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1"
|
|
bitfld.long 0x00 24. " GMB792 ,Group Modifier Bit 792" "0,1"
|
|
bitfld.long 0x00 23. " GMB791 ,Group Modifier Bit 791" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1"
|
|
bitfld.long 0x00 21. " GMB789 ,Group Modifier Bit 789" "0,1"
|
|
bitfld.long 0x00 20. " GMB788 ,Group Modifier Bit 788" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1"
|
|
bitfld.long 0x00 18. " GMB786 ,Group Modifier Bit 786" "0,1"
|
|
bitfld.long 0x00 17. " GMB785 ,Group Modifier Bit 785" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1"
|
|
bitfld.long 0x00 15. " GMB783 ,Group Modifier Bit 783" "0,1"
|
|
bitfld.long 0x00 14. " GMB782 ,Group Modifier Bit 782" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1"
|
|
bitfld.long 0x00 12. " GMB780 ,Group Modifier Bit 780" "0,1"
|
|
bitfld.long 0x00 11. " GMB779 ,Group Modifier Bit 779" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1"
|
|
bitfld.long 0x00 9. " GMB777 ,Group Modifier Bit 777" "0,1"
|
|
bitfld.long 0x00 8. " GMB776 ,Group Modifier Bit 776" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1"
|
|
bitfld.long 0x00 6. " GMB774 ,Group Modifier Bit 774" "0,1"
|
|
bitfld.long 0x00 5. " GMB773 ,Group Modifier Bit 773" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1"
|
|
bitfld.long 0x00 3. " GMB771 ,Group Modifier Bit 771" "0,1"
|
|
bitfld.long 0x00 2. " GMB770 ,Group Modifier Bit 770" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1"
|
|
bitfld.long 0x00 0. " GMB768 ,Group Modifier Bit 768" "0,1"
|
|
else
|
|
hgroup.long 0x0D60++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
|
|
group.long 0x0D64++0x03
|
|
line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25"
|
|
bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1"
|
|
bitfld.long 0x00 30. " GMB830 ,Group Modifier Bit 830" "0,1"
|
|
bitfld.long 0x00 29. " GMB829 ,Group Modifier Bit 829" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1"
|
|
bitfld.long 0x00 27. " GMB827 ,Group Modifier Bit 827" "0,1"
|
|
bitfld.long 0x00 26. " GMB826 ,Group Modifier Bit 826" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1"
|
|
bitfld.long 0x00 24. " GMB824 ,Group Modifier Bit 824" "0,1"
|
|
bitfld.long 0x00 23. " GMB823 ,Group Modifier Bit 823" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1"
|
|
bitfld.long 0x00 21. " GMB821 ,Group Modifier Bit 821" "0,1"
|
|
bitfld.long 0x00 20. " GMB820 ,Group Modifier Bit 820" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1"
|
|
bitfld.long 0x00 18. " GMB818 ,Group Modifier Bit 818" "0,1"
|
|
bitfld.long 0x00 17. " GMB817 ,Group Modifier Bit 817" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1"
|
|
bitfld.long 0x00 15. " GMB815 ,Group Modifier Bit 815" "0,1"
|
|
bitfld.long 0x00 14. " GMB814 ,Group Modifier Bit 814" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1"
|
|
bitfld.long 0x00 12. " GMB812 ,Group Modifier Bit 812" "0,1"
|
|
bitfld.long 0x00 11. " GMB811 ,Group Modifier Bit 811" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1"
|
|
bitfld.long 0x00 9. " GMB809 ,Group Modifier Bit 809" "0,1"
|
|
bitfld.long 0x00 8. " GMB808 ,Group Modifier Bit 808" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1"
|
|
bitfld.long 0x00 6. " GMB806 ,Group Modifier Bit 806" "0,1"
|
|
bitfld.long 0x00 5. " GMB805 ,Group Modifier Bit 805" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1"
|
|
bitfld.long 0x00 3. " GMB803 ,Group Modifier Bit 803" "0,1"
|
|
bitfld.long 0x00 2. " GMB802 ,Group Modifier Bit 802" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1"
|
|
bitfld.long 0x00 0. " GMB800 ,Group Modifier Bit 800" "0,1"
|
|
else
|
|
hgroup.long 0x0D64++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A))
|
|
group.long 0x0D68++0x03
|
|
line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26"
|
|
bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1"
|
|
bitfld.long 0x00 30. " GMB862 ,Group Modifier Bit 862" "0,1"
|
|
bitfld.long 0x00 29. " GMB861 ,Group Modifier Bit 861" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1"
|
|
bitfld.long 0x00 27. " GMB859 ,Group Modifier Bit 859" "0,1"
|
|
bitfld.long 0x00 26. " GMB858 ,Group Modifier Bit 858" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1"
|
|
bitfld.long 0x00 24. " GMB856 ,Group Modifier Bit 856" "0,1"
|
|
bitfld.long 0x00 23. " GMB855 ,Group Modifier Bit 855" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1"
|
|
bitfld.long 0x00 21. " GMB853 ,Group Modifier Bit 853" "0,1"
|
|
bitfld.long 0x00 20. " GMB852 ,Group Modifier Bit 852" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1"
|
|
bitfld.long 0x00 18. " GMB850 ,Group Modifier Bit 850" "0,1"
|
|
bitfld.long 0x00 17. " GMB849 ,Group Modifier Bit 849" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1"
|
|
bitfld.long 0x00 15. " GMB847 ,Group Modifier Bit 847" "0,1"
|
|
bitfld.long 0x00 14. " GMB846 ,Group Modifier Bit 846" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1"
|
|
bitfld.long 0x00 12. " GMB844 ,Group Modifier Bit 844" "0,1"
|
|
bitfld.long 0x00 11. " GMB843 ,Group Modifier Bit 843" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1"
|
|
bitfld.long 0x00 9. " GMB841 ,Group Modifier Bit 841" "0,1"
|
|
bitfld.long 0x00 8. " GMB840 ,Group Modifier Bit 840" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1"
|
|
bitfld.long 0x00 6. " GMB838 ,Group Modifier Bit 838" "0,1"
|
|
bitfld.long 0x00 5. " GMB837 ,Group Modifier Bit 837" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1"
|
|
bitfld.long 0x00 3. " GMB835 ,Group Modifier Bit 835" "0,1"
|
|
bitfld.long 0x00 2. " GMB834 ,Group Modifier Bit 834" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1"
|
|
bitfld.long 0x00 0. " GMB832 ,Group Modifier Bit 832" "0,1"
|
|
else
|
|
hgroup.long 0x0D68++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
|
|
group.long 0x0D6C++0x03
|
|
line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27"
|
|
bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1"
|
|
bitfld.long 0x00 30. " GMB894 ,Group Modifier Bit 894" "0,1"
|
|
bitfld.long 0x00 29. " GMB893 ,Group Modifier Bit 893" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1"
|
|
bitfld.long 0x00 27. " GMB891 ,Group Modifier Bit 891" "0,1"
|
|
bitfld.long 0x00 26. " GMB890 ,Group Modifier Bit 890" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1"
|
|
bitfld.long 0x00 24. " GMB888 ,Group Modifier Bit 888" "0,1"
|
|
bitfld.long 0x00 23. " GMB887 ,Group Modifier Bit 887" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1"
|
|
bitfld.long 0x00 21. " GMB885 ,Group Modifier Bit 885" "0,1"
|
|
bitfld.long 0x00 20. " GMB884 ,Group Modifier Bit 884" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1"
|
|
bitfld.long 0x00 18. " GMB882 ,Group Modifier Bit 882" "0,1"
|
|
bitfld.long 0x00 17. " GMB881 ,Group Modifier Bit 881" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1"
|
|
bitfld.long 0x00 15. " GMB879 ,Group Modifier Bit 879" "0,1"
|
|
bitfld.long 0x00 14. " GMB878 ,Group Modifier Bit 878" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1"
|
|
bitfld.long 0x00 12. " GMB876 ,Group Modifier Bit 876" "0,1"
|
|
bitfld.long 0x00 11. " GMB875 ,Group Modifier Bit 875" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1"
|
|
bitfld.long 0x00 9. " GMB873 ,Group Modifier Bit 873" "0,1"
|
|
bitfld.long 0x00 8. " GMB872 ,Group Modifier Bit 872" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1"
|
|
bitfld.long 0x00 6. " GMB870 ,Group Modifier Bit 870" "0,1"
|
|
bitfld.long 0x00 5. " GMB869 ,Group Modifier Bit 869" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1"
|
|
bitfld.long 0x00 3. " GMB867 ,Group Modifier Bit 867" "0,1"
|
|
bitfld.long 0x00 2. " GMB866 ,Group Modifier Bit 866" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1"
|
|
bitfld.long 0x00 0. " GMB864 ,Group Modifier Bit 864" "0,1"
|
|
else
|
|
hgroup.long 0x0D6C++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
|
|
group.long 0x0D70++0x03
|
|
line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28"
|
|
bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1"
|
|
bitfld.long 0x00 30. " GMB926 ,Group Modifier Bit 926" "0,1"
|
|
bitfld.long 0x00 29. " GMB925 ,Group Modifier Bit 925" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1"
|
|
bitfld.long 0x00 27. " GMB923 ,Group Modifier Bit 923" "0,1"
|
|
bitfld.long 0x00 26. " GMB922 ,Group Modifier Bit 922" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1"
|
|
bitfld.long 0x00 24. " GMB920 ,Group Modifier Bit 920" "0,1"
|
|
bitfld.long 0x00 23. " GMB919 ,Group Modifier Bit 919" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1"
|
|
bitfld.long 0x00 21. " GMB917 ,Group Modifier Bit 917" "0,1"
|
|
bitfld.long 0x00 20. " GMB916 ,Group Modifier Bit 916" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1"
|
|
bitfld.long 0x00 18. " GMB914 ,Group Modifier Bit 914" "0,1"
|
|
bitfld.long 0x00 17. " GMB913 ,Group Modifier Bit 913" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1"
|
|
bitfld.long 0x00 15. " GMB911 ,Group Modifier Bit 911" "0,1"
|
|
bitfld.long 0x00 14. " GMB910 ,Group Modifier Bit 910" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1"
|
|
bitfld.long 0x00 12. " GMB908 ,Group Modifier Bit 908" "0,1"
|
|
bitfld.long 0x00 11. " GMB907 ,Group Modifier Bit 907" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1"
|
|
bitfld.long 0x00 9. " GMB905 ,Group Modifier Bit 905" "0,1"
|
|
bitfld.long 0x00 8. " GMB904 ,Group Modifier Bit 904" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1"
|
|
bitfld.long 0x00 6. " GMB902 ,Group Modifier Bit 902" "0,1"
|
|
bitfld.long 0x00 5. " GMB901 ,Group Modifier Bit 901" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1"
|
|
bitfld.long 0x00 3. " GMB899 ,Group Modifier Bit 899" "0,1"
|
|
bitfld.long 0x00 2. " GMB898 ,Group Modifier Bit 898" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1"
|
|
bitfld.long 0x00 0. " GMB896 ,Group Modifier Bit 896" "0,1"
|
|
else
|
|
hgroup.long 0x0D70++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
|
|
group.long 0x0D74++0x03
|
|
line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29"
|
|
bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1"
|
|
bitfld.long 0x00 30. " GMB958 ,Group Modifier Bit 958" "0,1"
|
|
bitfld.long 0x00 29. " GMB957 ,Group Modifier Bit 957" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1"
|
|
bitfld.long 0x00 27. " GMB955 ,Group Modifier Bit 955" "0,1"
|
|
bitfld.long 0x00 26. " GMB954 ,Group Modifier Bit 954" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1"
|
|
bitfld.long 0x00 24. " GMB952 ,Group Modifier Bit 952" "0,1"
|
|
bitfld.long 0x00 23. " GMB951 ,Group Modifier Bit 951" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1"
|
|
bitfld.long 0x00 21. " GMB949 ,Group Modifier Bit 949" "0,1"
|
|
bitfld.long 0x00 20. " GMB948 ,Group Modifier Bit 948" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1"
|
|
bitfld.long 0x00 18. " GMB946 ,Group Modifier Bit 946" "0,1"
|
|
bitfld.long 0x00 17. " GMB945 ,Group Modifier Bit 945" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1"
|
|
bitfld.long 0x00 15. " GMB943 ,Group Modifier Bit 943" "0,1"
|
|
bitfld.long 0x00 14. " GMB942 ,Group Modifier Bit 942" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1"
|
|
bitfld.long 0x00 12. " GMB940 ,Group Modifier Bit 940" "0,1"
|
|
bitfld.long 0x00 11. " GMB939 ,Group Modifier Bit 939" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1"
|
|
bitfld.long 0x00 9. " GMB937 ,Group Modifier Bit 937" "0,1"
|
|
bitfld.long 0x00 8. " GMB936 ,Group Modifier Bit 936" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1"
|
|
bitfld.long 0x00 6. " GMB934 ,Group Modifier Bit 934" "0,1"
|
|
bitfld.long 0x00 5. " GMB933 ,Group Modifier Bit 933" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1"
|
|
bitfld.long 0x00 3. " GMB931 ,Group Modifier Bit 931" "0,1"
|
|
bitfld.long 0x00 2. " GMB930 ,Group Modifier Bit 930" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1"
|
|
bitfld.long 0x00 0. " GMB928 ,Group Modifier Bit 928" "0,1"
|
|
else
|
|
hgroup.long 0x0D74++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
|
|
group.long 0x0D78++0x03
|
|
line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30"
|
|
bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1"
|
|
bitfld.long 0x00 30. " GMB990 ,Group Modifier Bit 990" "0,1"
|
|
bitfld.long 0x00 29. " GMB989 ,Group Modifier Bit 989" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1"
|
|
bitfld.long 0x00 27. " GMB987 ,Group Modifier Bit 987" "0,1"
|
|
bitfld.long 0x00 26. " GMB986 ,Group Modifier Bit 986" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1"
|
|
bitfld.long 0x00 24. " GMB984 ,Group Modifier Bit 984" "0,1"
|
|
bitfld.long 0x00 23. " GMB983 ,Group Modifier Bit 983" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1"
|
|
bitfld.long 0x00 21. " GMB981 ,Group Modifier Bit 981" "0,1"
|
|
bitfld.long 0x00 20. " GMB980 ,Group Modifier Bit 980" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1"
|
|
bitfld.long 0x00 18. " GMB978 ,Group Modifier Bit 978" "0,1"
|
|
bitfld.long 0x00 17. " GMB977 ,Group Modifier Bit 977" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1"
|
|
bitfld.long 0x00 15. " GMB975 ,Group Modifier Bit 975" "0,1"
|
|
bitfld.long 0x00 14. " GMB974 ,Group Modifier Bit 974" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1"
|
|
bitfld.long 0x00 12. " GMB972 ,Group Modifier Bit 972" "0,1"
|
|
bitfld.long 0x00 11. " GMB971 ,Group Modifier Bit 971" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1"
|
|
bitfld.long 0x00 9. " GMB969 ,Group Modifier Bit 969" "0,1"
|
|
bitfld.long 0x00 8. " GMB968 ,Group Modifier Bit 968" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1"
|
|
bitfld.long 0x00 6. " GMB966 ,Group Modifier Bit 966" "0,1"
|
|
bitfld.long 0x00 5. " GMB965 ,Group Modifier Bit 965" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1"
|
|
bitfld.long 0x00 3. " GMB963 ,Group Modifier Bit 963" "0,1"
|
|
bitfld.long 0x00 2. " GMB962 ,Group Modifier Bit 962" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1"
|
|
bitfld.long 0x00 0. " GMB960 ,Group Modifier Bit 960" "0,1"
|
|
else
|
|
hgroup.long 0x0D78++0x03
|
|
hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30"
|
|
endif
|
|
tree.end
|
|
width 14.
|
|
tree "Non-secure Access Control Registers"
|
|
hgroup.long 0x0E00++0x03
|
|
hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0"
|
|
hgroup.long 0xE04++0x03
|
|
hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1"
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08)))
|
|
group.long 0xE08++0x03
|
|
line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS47 ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS46 ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS45 ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS44 ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS43 ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS42 ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS41 ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS40 ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS39 ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS38 ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS37 ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS36 ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS35 ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS34 ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS33 ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS32 ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE08++0x03
|
|
hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C)))
|
|
group.long 0xE0C++0x03
|
|
line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS63 ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS62 ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS61 ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS60 ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS59 ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS58 ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS57 ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS56 ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS55 ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS54 ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS53 ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS52 ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS51 ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS50 ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS49 ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS48 ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE0C++0x03
|
|
hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10)))
|
|
group.long 0xE10++0x03
|
|
line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS79 ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS78 ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS77 ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS76 ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS75 ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS74 ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS73 ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS72 ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS71 ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS70 ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS69 ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS68 ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS67 ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS66 ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS65 ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS64 ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE10++0x03
|
|
hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14)))
|
|
group.long 0xE14++0x03
|
|
line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS95 ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS94 ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS93 ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS92 ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS91 ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS90 ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS89 ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS88 ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS87 ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS86 ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS85 ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS84 ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS83 ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS82 ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS81 ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS80 ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE14++0x03
|
|
hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18)))
|
|
group.long 0xE18++0x03
|
|
line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS99 ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS98 ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS97 ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS96 ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE18++0x03
|
|
hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C)))
|
|
group.long 0xE1C++0x03
|
|
line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE1C++0x03
|
|
hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20)))
|
|
group.long 0xE20++0x03
|
|
line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE20++0x03
|
|
hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24)))
|
|
group.long 0xE24++0x03
|
|
line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE24++0x03
|
|
hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28)))
|
|
group.long 0xE28++0x03
|
|
line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE28++0x03
|
|
hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C)))
|
|
group.long 0xE2C++0x03
|
|
line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE2C++0x03
|
|
hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30)))
|
|
group.long 0xE30++0x03
|
|
line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE30++0x03
|
|
hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34)))
|
|
group.long 0xE34++0x03
|
|
line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE34++0x03
|
|
hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38)))
|
|
group.long 0xE38++0x03
|
|
line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE38++0x03
|
|
hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C)))
|
|
group.long 0xE3C++0x03
|
|
line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE3C++0x03
|
|
hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40)))
|
|
group.long 0xE40++0x03
|
|
line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE40++0x03
|
|
hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44)))
|
|
group.long 0xE44++0x03
|
|
line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE44++0x03
|
|
hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48)))
|
|
group.long 0xE48++0x03
|
|
line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE48++0x03
|
|
hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C)))
|
|
group.long 0xE4C++0x03
|
|
line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE4C++0x03
|
|
hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50)))
|
|
group.long 0xE50++0x03
|
|
line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE50++0x03
|
|
hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54)))
|
|
group.long 0xE54++0x03
|
|
line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE54++0x03
|
|
hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58)))
|
|
group.long 0xE58++0x03
|
|
line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE58++0x03
|
|
hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C)))
|
|
group.long 0xE5C++0x03
|
|
line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE5C++0x03
|
|
hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60)))
|
|
group.long 0xE60++0x03
|
|
line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE60++0x03
|
|
hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64)))
|
|
group.long 0xE64++0x03
|
|
line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE64++0x03
|
|
hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68)))
|
|
group.long 0xE68++0x03
|
|
line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE68++0x03
|
|
hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C)))
|
|
group.long 0xE6C++0x03
|
|
line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE6C++0x03
|
|
hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70)))
|
|
group.long 0xE70++0x03
|
|
line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE70++0x03
|
|
hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74)))
|
|
group.long 0xE74++0x03
|
|
line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE74++0x03
|
|
hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78)))
|
|
group.long 0xE78++0x03
|
|
line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE78++0x03
|
|
hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C)))
|
|
group.long 0xE7C++0x03
|
|
line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE7C++0x03
|
|
hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80)))
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE80++0x03
|
|
hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84)))
|
|
group.long 0xE84++0x03
|
|
line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE84++0x03
|
|
hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88)))
|
|
group.long 0xE88++0x03
|
|
line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE88++0x03
|
|
hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C)))
|
|
group.long 0xE8C++0x03
|
|
line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE8C++0x03
|
|
hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90)))
|
|
group.long 0xE90++0x03
|
|
line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE90++0x03
|
|
hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94)))
|
|
group.long 0xE94++0x03
|
|
line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE94++0x03
|
|
hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98)))
|
|
group.long 0xE98++0x03
|
|
line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE98++0x03
|
|
hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C)))
|
|
group.long 0xE9C++0x03
|
|
line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xE9C++0x03
|
|
hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0)))
|
|
group.long 0xEA0++0x03
|
|
line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEA0++0x03
|
|
hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4)))
|
|
group.long 0xEA4++0x03
|
|
line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEA4++0x03
|
|
hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8)))
|
|
group.long 0xEA8++0x03
|
|
line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEA8++0x03
|
|
hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC)))
|
|
group.long 0xEAC++0x03
|
|
line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEAC++0x03
|
|
hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0)))
|
|
group.long 0xEB0++0x03
|
|
line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEB0++0x03
|
|
hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4)))
|
|
group.long 0xEB4++0x03
|
|
line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEB4++0x03
|
|
hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8)))
|
|
group.long 0xEB8++0x03
|
|
line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEB8++0x03
|
|
hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC)))
|
|
group.long 0xEBC++0x03
|
|
line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEBC++0x03
|
|
hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0)))
|
|
group.long 0xEC0++0x03
|
|
line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEC0++0x03
|
|
hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4)))
|
|
group.long 0xEC4++0x03
|
|
line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEC4++0x03
|
|
hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8)))
|
|
group.long 0xEC8++0x03
|
|
line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEC8++0x03
|
|
hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC)))
|
|
group.long 0xECC++0x03
|
|
line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xECC++0x03
|
|
hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0)))
|
|
group.long 0xED0++0x03
|
|
line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xED0++0x03
|
|
hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4)))
|
|
group.long 0xED4++0x03
|
|
line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xED4++0x03
|
|
hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8)))
|
|
group.long 0xED8++0x03
|
|
line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xED8++0x03
|
|
hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC)))
|
|
group.long 0xEDC++0x03
|
|
line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEDC++0x03
|
|
hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0)))
|
|
group.long 0xEE0++0x03
|
|
line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEE0++0x03
|
|
hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4)))
|
|
group.long 0xEE4++0x03
|
|
line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEE4++0x03
|
|
hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8)))
|
|
group.long 0xEE8++0x03
|
|
line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEE8++0x03
|
|
hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC)))
|
|
group.long 0xEEC++0x03
|
|
line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEEC++0x03
|
|
hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0)))
|
|
group.long 0xEF0++0x03
|
|
line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEF0++0x03
|
|
hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60"
|
|
endif
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4)))
|
|
group.long 0xEF4++0x03
|
|
line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
|
|
else
|
|
hgroup.long 0xEF4++0x03
|
|
hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61"
|
|
endif
|
|
tree.end
|
|
width 25.
|
|
tree "Software Generated Interrupt"
|
|
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
|
|
hgroup.long 0x0F00++0x03
|
|
hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
|
|
hgroup.long 0xF10++0x03
|
|
hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0"
|
|
hgroup.long 0xF14++0x03
|
|
hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1"
|
|
hgroup.long 0xF18++0x03
|
|
hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2"
|
|
hgroup.long 0xF1C++0x03
|
|
hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3"
|
|
hgroup.long 0xF20++0x03
|
|
hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0"
|
|
hgroup.long 0xF24++0x03
|
|
hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1"
|
|
hgroup.long 0xF28++0x03
|
|
hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2"
|
|
hgroup.long 0xF2C++0x03
|
|
hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3"
|
|
else
|
|
wgroup.long 0x0F00++0x03
|
|
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
|
|
group.long 0xF10++0x03
|
|
line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0"
|
|
group.long 0xF14++0x03
|
|
line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1"
|
|
group.long 0xF18++0x03
|
|
line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2"
|
|
group.long 0xF1C++0x03
|
|
line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3"
|
|
group.long 0xF20++0x03
|
|
line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0"
|
|
group.long 0xF24++0x03
|
|
line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1"
|
|
group.long 0xF28++0x03
|
|
line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2"
|
|
group.long 0xF2C++0x03
|
|
line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3"
|
|
endif
|
|
tree.end
|
|
width 24.
|
|
tree "Interrupt Routing Registers"
|
|
group.quad 0x6100++0x07
|
|
line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6108++0x07
|
|
line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6110++0x07
|
|
line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6118++0x07
|
|
line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6120++0x07
|
|
line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6128++0x07
|
|
line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6130++0x07
|
|
line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6138++0x07
|
|
line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6140++0x07
|
|
line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6148++0x07
|
|
line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6150++0x07
|
|
line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6158++0x07
|
|
line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6160++0x07
|
|
line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6168++0x07
|
|
line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6170++0x07
|
|
line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6178++0x07
|
|
line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6180++0x07
|
|
line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6188++0x07
|
|
line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6190++0x07
|
|
line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6198++0x07
|
|
line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x61A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x61A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x61B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x61B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x61C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x61C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x61D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x61D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x61E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x61E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x61F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x61F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6200++0x07
|
|
line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6208++0x07
|
|
line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6210++0x07
|
|
line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6218++0x07
|
|
line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6220++0x07
|
|
line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6228++0x07
|
|
line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6230++0x07
|
|
line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6238++0x07
|
|
line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6240++0x07
|
|
line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6248++0x07
|
|
line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6250++0x07
|
|
line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6258++0x07
|
|
line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6260++0x07
|
|
line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6268++0x07
|
|
line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6270++0x07
|
|
line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6278++0x07
|
|
line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6280++0x07
|
|
line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6288++0x07
|
|
line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6290++0x07
|
|
line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6298++0x07
|
|
line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x62A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x62A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x62B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x62B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x62C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x62C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x62D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x62D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x62E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x62E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x62F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x62F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6300++0x07
|
|
line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6308++0x07
|
|
line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6310++0x07
|
|
line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6318++0x07
|
|
line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6320++0x07
|
|
line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6328++0x07
|
|
line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6330++0x07
|
|
line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6338++0x07
|
|
line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6340++0x07
|
|
line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6348++0x07
|
|
line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6350++0x07
|
|
line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6358++0x07
|
|
line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6360++0x07
|
|
line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6368++0x07
|
|
line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6370++0x07
|
|
line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6378++0x07
|
|
line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6380++0x07
|
|
line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6388++0x07
|
|
line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6390++0x07
|
|
line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6398++0x07
|
|
line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x63A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x63A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x63B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x63B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x63C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x63C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x63D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x63D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x63E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x63E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x63F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x63F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6400++0x07
|
|
line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6408++0x07
|
|
line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6410++0x07
|
|
line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6418++0x07
|
|
line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6420++0x07
|
|
line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6428++0x07
|
|
line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6430++0x07
|
|
line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6438++0x07
|
|
line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6440++0x07
|
|
line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6448++0x07
|
|
line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6450++0x07
|
|
line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6458++0x07
|
|
line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6460++0x07
|
|
line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6468++0x07
|
|
line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6470++0x07
|
|
line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6478++0x07
|
|
line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6480++0x07
|
|
line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6488++0x07
|
|
line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6490++0x07
|
|
line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6498++0x07
|
|
line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x64A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x64A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x64B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x64B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x64C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x64C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x64D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x64D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x64E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x64E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x64F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x64F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6500++0x07
|
|
line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6508++0x07
|
|
line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6510++0x07
|
|
line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6518++0x07
|
|
line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6520++0x07
|
|
line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6528++0x07
|
|
line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6530++0x07
|
|
line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6538++0x07
|
|
line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6540++0x07
|
|
line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6548++0x07
|
|
line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6550++0x07
|
|
line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6558++0x07
|
|
line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6560++0x07
|
|
line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6568++0x07
|
|
line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6570++0x07
|
|
line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6578++0x07
|
|
line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6580++0x07
|
|
line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6588++0x07
|
|
line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6590++0x07
|
|
line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6598++0x07
|
|
line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x65A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x65A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x65B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x65B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x65C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x65C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x65D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x65D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x65E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x65E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x65F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x65F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6600++0x07
|
|
line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6608++0x07
|
|
line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6610++0x07
|
|
line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6618++0x07
|
|
line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6620++0x07
|
|
line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6628++0x07
|
|
line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6630++0x07
|
|
line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6638++0x07
|
|
line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6640++0x07
|
|
line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6648++0x07
|
|
line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6650++0x07
|
|
line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6658++0x07
|
|
line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6660++0x07
|
|
line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6668++0x07
|
|
line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6670++0x07
|
|
line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6678++0x07
|
|
line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6680++0x07
|
|
line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6688++0x07
|
|
line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6690++0x07
|
|
line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6698++0x07
|
|
line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x66A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x66A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x66B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x66B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x66C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x66C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x66D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x66D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x66E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x66E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x66F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x66F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6700++0x07
|
|
line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6708++0x07
|
|
line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6710++0x07
|
|
line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6718++0x07
|
|
line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6720++0x07
|
|
line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6728++0x07
|
|
line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6730++0x07
|
|
line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6738++0x07
|
|
line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6740++0x07
|
|
line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6748++0x07
|
|
line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6750++0x07
|
|
line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6758++0x07
|
|
line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6760++0x07
|
|
line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6768++0x07
|
|
line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6770++0x07
|
|
line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6778++0x07
|
|
line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6780++0x07
|
|
line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6788++0x07
|
|
line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6790++0x07
|
|
line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6798++0x07
|
|
line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x67A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x67A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x67B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x67B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x67C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x67C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x67D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x67D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x67E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x67E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x67F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x67F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6800++0x07
|
|
line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6808++0x07
|
|
line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6810++0x07
|
|
line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6818++0x07
|
|
line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6820++0x07
|
|
line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6828++0x07
|
|
line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6830++0x07
|
|
line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6838++0x07
|
|
line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6840++0x07
|
|
line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6848++0x07
|
|
line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6850++0x07
|
|
line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6858++0x07
|
|
line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6860++0x07
|
|
line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6868++0x07
|
|
line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6870++0x07
|
|
line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6878++0x07
|
|
line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6880++0x07
|
|
line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6888++0x07
|
|
line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6890++0x07
|
|
line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6898++0x07
|
|
line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x68A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x68A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x68B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x68B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x68C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x68C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x68D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x68D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x68E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x68E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x68F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x68F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6900++0x07
|
|
line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6908++0x07
|
|
line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6910++0x07
|
|
line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6918++0x07
|
|
line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6920++0x07
|
|
line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6928++0x07
|
|
line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6930++0x07
|
|
line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6938++0x07
|
|
line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6940++0x07
|
|
line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6948++0x07
|
|
line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6950++0x07
|
|
line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6958++0x07
|
|
line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6960++0x07
|
|
line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6968++0x07
|
|
line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6970++0x07
|
|
line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6978++0x07
|
|
line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6980++0x07
|
|
line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6988++0x07
|
|
line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6990++0x07
|
|
line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6998++0x07
|
|
line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x69A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x69A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x69B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x69B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x69C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x69C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x69D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x69D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x69E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x69E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x69F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x69F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A00++0x07
|
|
line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A08++0x07
|
|
line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A10++0x07
|
|
line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A18++0x07
|
|
line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A20++0x07
|
|
line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A28++0x07
|
|
line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A30++0x07
|
|
line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A38++0x07
|
|
line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A40++0x07
|
|
line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A48++0x07
|
|
line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A50++0x07
|
|
line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A58++0x07
|
|
line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A60++0x07
|
|
line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A68++0x07
|
|
line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A70++0x07
|
|
line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A78++0x07
|
|
line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A80++0x07
|
|
line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A88++0x07
|
|
line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A90++0x07
|
|
line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6A98++0x07
|
|
line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6AA0++0x07
|
|
line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6AA8++0x07
|
|
line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6AB0++0x07
|
|
line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6AB8++0x07
|
|
line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6AC0++0x07
|
|
line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6AC8++0x07
|
|
line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6AD0++0x07
|
|
line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6AD8++0x07
|
|
line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6AE0++0x07
|
|
line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6AE8++0x07
|
|
line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6AF0++0x07
|
|
line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6AF8++0x07
|
|
line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B00++0x07
|
|
line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B08++0x07
|
|
line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B10++0x07
|
|
line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B18++0x07
|
|
line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B20++0x07
|
|
line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B28++0x07
|
|
line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B30++0x07
|
|
line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B38++0x07
|
|
line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B40++0x07
|
|
line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B48++0x07
|
|
line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B50++0x07
|
|
line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B58++0x07
|
|
line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B60++0x07
|
|
line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B68++0x07
|
|
line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B70++0x07
|
|
line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B78++0x07
|
|
line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B80++0x07
|
|
line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B88++0x07
|
|
line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B90++0x07
|
|
line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6B98++0x07
|
|
line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6BA0++0x07
|
|
line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6BA8++0x07
|
|
line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6BB0++0x07
|
|
line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6BB8++0x07
|
|
line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6BC0++0x07
|
|
line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6BC8++0x07
|
|
line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6BD0++0x07
|
|
line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6BD8++0x07
|
|
line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6BE0++0x07
|
|
line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6BE8++0x07
|
|
line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6BF0++0x07
|
|
line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6BF8++0x07
|
|
line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C00++0x07
|
|
line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C08++0x07
|
|
line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C10++0x07
|
|
line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C18++0x07
|
|
line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C20++0x07
|
|
line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C28++0x07
|
|
line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C30++0x07
|
|
line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C38++0x07
|
|
line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C40++0x07
|
|
line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C48++0x07
|
|
line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C50++0x07
|
|
line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C58++0x07
|
|
line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C60++0x07
|
|
line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C68++0x07
|
|
line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C70++0x07
|
|
line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C78++0x07
|
|
line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C80++0x07
|
|
line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C88++0x07
|
|
line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C90++0x07
|
|
line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6C98++0x07
|
|
line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6CA0++0x07
|
|
line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6CA8++0x07
|
|
line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6CB0++0x07
|
|
line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6CB8++0x07
|
|
line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6CC0++0x07
|
|
line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6CC8++0x07
|
|
line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6CD0++0x07
|
|
line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6CD8++0x07
|
|
line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6CE0++0x07
|
|
line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6CE8++0x07
|
|
line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6CF0++0x07
|
|
line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6CF8++0x07
|
|
line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D00++0x07
|
|
line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D08++0x07
|
|
line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D10++0x07
|
|
line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D18++0x07
|
|
line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D20++0x07
|
|
line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D28++0x07
|
|
line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D30++0x07
|
|
line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D38++0x07
|
|
line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D40++0x07
|
|
line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D48++0x07
|
|
line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D50++0x07
|
|
line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D58++0x07
|
|
line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D60++0x07
|
|
line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D68++0x07
|
|
line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D70++0x07
|
|
line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D78++0x07
|
|
line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D80++0x07
|
|
line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D88++0x07
|
|
line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D90++0x07
|
|
line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6D98++0x07
|
|
line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6DA0++0x07
|
|
line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6DA8++0x07
|
|
line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6DB0++0x07
|
|
line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6DB8++0x07
|
|
line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6DC0++0x07
|
|
line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6DC8++0x07
|
|
line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6DD0++0x07
|
|
line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6DD8++0x07
|
|
line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6DE0++0x07
|
|
line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6DE8++0x07
|
|
line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6DF0++0x07
|
|
line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6DF8++0x07
|
|
line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E00++0x07
|
|
line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E08++0x07
|
|
line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E10++0x07
|
|
line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E18++0x07
|
|
line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E20++0x07
|
|
line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E28++0x07
|
|
line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E30++0x07
|
|
line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E38++0x07
|
|
line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E40++0x07
|
|
line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E48++0x07
|
|
line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E50++0x07
|
|
line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E58++0x07
|
|
line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E60++0x07
|
|
line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E68++0x07
|
|
line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E70++0x07
|
|
line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E78++0x07
|
|
line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E80++0x07
|
|
line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E88++0x07
|
|
line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E90++0x07
|
|
line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6E98++0x07
|
|
line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6EA0++0x07
|
|
line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6EA8++0x07
|
|
line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6EB0++0x07
|
|
line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6EB8++0x07
|
|
line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6EC0++0x07
|
|
line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6EC8++0x07
|
|
line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6ED0++0x07
|
|
line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6ED8++0x07
|
|
line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6EE0++0x07
|
|
line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6EE8++0x07
|
|
line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6EF0++0x07
|
|
line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6EF8++0x07
|
|
line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F00++0x07
|
|
line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F08++0x07
|
|
line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F10++0x07
|
|
line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F18++0x07
|
|
line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F20++0x07
|
|
line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F28++0x07
|
|
line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F30++0x07
|
|
line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F38++0x07
|
|
line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F40++0x07
|
|
line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F48++0x07
|
|
line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F50++0x07
|
|
line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F58++0x07
|
|
line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F60++0x07
|
|
line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F68++0x07
|
|
line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F70++0x07
|
|
line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F78++0x07
|
|
line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F80++0x07
|
|
line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F88++0x07
|
|
line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F90++0x07
|
|
line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6F98++0x07
|
|
line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6FA0++0x07
|
|
line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6FA8++0x07
|
|
line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6FB0++0x07
|
|
line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6FB8++0x07
|
|
line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6FC0++0x07
|
|
line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6FC8++0x07
|
|
line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6FD0++0x07
|
|
line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6FD8++0x07
|
|
line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6FE0++0x07
|
|
line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6FE8++0x07
|
|
line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6FF0++0x07
|
|
line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x6FF8++0x07
|
|
line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7000++0x07
|
|
line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7008++0x07
|
|
line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7010++0x07
|
|
line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7018++0x07
|
|
line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7020++0x07
|
|
line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7028++0x07
|
|
line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7030++0x07
|
|
line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7038++0x07
|
|
line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7040++0x07
|
|
line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7048++0x07
|
|
line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7050++0x07
|
|
line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7058++0x07
|
|
line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7060++0x07
|
|
line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7068++0x07
|
|
line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7070++0x07
|
|
line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7078++0x07
|
|
line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7080++0x07
|
|
line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7088++0x07
|
|
line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7090++0x07
|
|
line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7098++0x07
|
|
line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x70A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x70A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x70B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x70B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x70C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x70C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x70D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x70D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x70E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x70E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x70F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x70F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7100++0x07
|
|
line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7108++0x07
|
|
line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7110++0x07
|
|
line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7118++0x07
|
|
line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7120++0x07
|
|
line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7128++0x07
|
|
line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7130++0x07
|
|
line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7138++0x07
|
|
line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7140++0x07
|
|
line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7148++0x07
|
|
line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7150++0x07
|
|
line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7158++0x07
|
|
line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7160++0x07
|
|
line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7168++0x07
|
|
line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7170++0x07
|
|
line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7178++0x07
|
|
line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7180++0x07
|
|
line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7188++0x07
|
|
line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7190++0x07
|
|
line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7198++0x07
|
|
line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x71A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x71A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x71B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x71B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x71C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x71C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x71D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x71D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x71E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x71E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x71F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x71F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7200++0x07
|
|
line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7208++0x07
|
|
line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7210++0x07
|
|
line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7218++0x07
|
|
line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7220++0x07
|
|
line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7228++0x07
|
|
line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7230++0x07
|
|
line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7238++0x07
|
|
line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7240++0x07
|
|
line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7248++0x07
|
|
line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7250++0x07
|
|
line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7258++0x07
|
|
line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7260++0x07
|
|
line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7268++0x07
|
|
line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7270++0x07
|
|
line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7278++0x07
|
|
line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7280++0x07
|
|
line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7288++0x07
|
|
line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7290++0x07
|
|
line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7298++0x07
|
|
line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x72A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x72A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x72B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x72B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x72C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x72C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x72D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x72D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x72E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x72E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x72F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x72F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7300++0x07
|
|
line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7308++0x07
|
|
line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7310++0x07
|
|
line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7318++0x07
|
|
line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7320++0x07
|
|
line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7328++0x07
|
|
line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7330++0x07
|
|
line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7338++0x07
|
|
line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7340++0x07
|
|
line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7348++0x07
|
|
line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7350++0x07
|
|
line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7358++0x07
|
|
line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7360++0x07
|
|
line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7368++0x07
|
|
line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7370++0x07
|
|
line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7378++0x07
|
|
line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7380++0x07
|
|
line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7388++0x07
|
|
line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7390++0x07
|
|
line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7398++0x07
|
|
line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x73A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x73A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x73B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x73B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x73C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x73C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x73D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x73D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x73E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x73E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x73F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x73F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7400++0x07
|
|
line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7408++0x07
|
|
line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7410++0x07
|
|
line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7418++0x07
|
|
line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7420++0x07
|
|
line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7428++0x07
|
|
line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7430++0x07
|
|
line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7438++0x07
|
|
line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7440++0x07
|
|
line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7448++0x07
|
|
line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7450++0x07
|
|
line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7458++0x07
|
|
line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7460++0x07
|
|
line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7468++0x07
|
|
line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7470++0x07
|
|
line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7478++0x07
|
|
line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7480++0x07
|
|
line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7488++0x07
|
|
line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7490++0x07
|
|
line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7498++0x07
|
|
line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x74A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x74A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x74B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x74B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x74C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x74C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x74D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x74D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x74E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x74E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x74F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x74F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7500++0x07
|
|
line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7508++0x07
|
|
line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7510++0x07
|
|
line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7518++0x07
|
|
line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7520++0x07
|
|
line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7528++0x07
|
|
line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7530++0x07
|
|
line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7538++0x07
|
|
line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7540++0x07
|
|
line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7548++0x07
|
|
line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7550++0x07
|
|
line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7558++0x07
|
|
line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7560++0x07
|
|
line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7568++0x07
|
|
line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7570++0x07
|
|
line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7578++0x07
|
|
line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7580++0x07
|
|
line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7588++0x07
|
|
line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7590++0x07
|
|
line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7598++0x07
|
|
line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x75A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x75A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x75B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x75B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x75C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x75C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x75D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x75D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x75E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x75E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x75F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x75F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7600++0x07
|
|
line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7608++0x07
|
|
line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7610++0x07
|
|
line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7618++0x07
|
|
line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7620++0x07
|
|
line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7628++0x07
|
|
line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7630++0x07
|
|
line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7638++0x07
|
|
line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7640++0x07
|
|
line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7648++0x07
|
|
line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7650++0x07
|
|
line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7658++0x07
|
|
line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7660++0x07
|
|
line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7668++0x07
|
|
line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7670++0x07
|
|
line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7678++0x07
|
|
line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7680++0x07
|
|
line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7688++0x07
|
|
line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7690++0x07
|
|
line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7698++0x07
|
|
line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x76A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x76A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x76B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x76B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x76C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x76C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x76D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x76D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x76E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x76E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x76F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x76F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7700++0x07
|
|
line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7708++0x07
|
|
line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7710++0x07
|
|
line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7718++0x07
|
|
line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7720++0x07
|
|
line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7728++0x07
|
|
line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7730++0x07
|
|
line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7738++0x07
|
|
line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7740++0x07
|
|
line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7748++0x07
|
|
line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7750++0x07
|
|
line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7758++0x07
|
|
line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7760++0x07
|
|
line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7768++0x07
|
|
line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7770++0x07
|
|
line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7778++0x07
|
|
line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7780++0x07
|
|
line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7788++0x07
|
|
line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7790++0x07
|
|
line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7798++0x07
|
|
line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x77A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x77A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x77B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x77B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x77C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x77C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x77D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x77D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x77E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x77E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x77F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x77F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7800++0x07
|
|
line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7808++0x07
|
|
line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7810++0x07
|
|
line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7818++0x07
|
|
line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7820++0x07
|
|
line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7828++0x07
|
|
line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7830++0x07
|
|
line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7838++0x07
|
|
line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7840++0x07
|
|
line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7848++0x07
|
|
line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7850++0x07
|
|
line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7858++0x07
|
|
line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7860++0x07
|
|
line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7868++0x07
|
|
line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7870++0x07
|
|
line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7878++0x07
|
|
line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7880++0x07
|
|
line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7888++0x07
|
|
line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7890++0x07
|
|
line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7898++0x07
|
|
line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x78A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x78A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x78B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x78B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x78C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x78C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x78D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x78D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x78E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x78E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x78F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x78F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7900++0x07
|
|
line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7908++0x07
|
|
line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7910++0x07
|
|
line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7918++0x07
|
|
line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7920++0x07
|
|
line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7928++0x07
|
|
line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7930++0x07
|
|
line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7938++0x07
|
|
line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7940++0x07
|
|
line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7948++0x07
|
|
line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7950++0x07
|
|
line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7958++0x07
|
|
line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7960++0x07
|
|
line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7968++0x07
|
|
line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7970++0x07
|
|
line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7978++0x07
|
|
line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7980++0x07
|
|
line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7988++0x07
|
|
line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7990++0x07
|
|
line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7998++0x07
|
|
line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x79A0++0x07
|
|
line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x79A8++0x07
|
|
line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x79B0++0x07
|
|
line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x79B8++0x07
|
|
line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x79C0++0x07
|
|
line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x79C8++0x07
|
|
line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x79D0++0x07
|
|
line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x79D8++0x07
|
|
line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x79E0++0x07
|
|
line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x79E8++0x07
|
|
line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x79F0++0x07
|
|
line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x79F8++0x07
|
|
line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A00++0x07
|
|
line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A08++0x07
|
|
line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A10++0x07
|
|
line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A18++0x07
|
|
line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A20++0x07
|
|
line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A28++0x07
|
|
line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A30++0x07
|
|
line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A38++0x07
|
|
line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A40++0x07
|
|
line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A48++0x07
|
|
line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A50++0x07
|
|
line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A58++0x07
|
|
line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A60++0x07
|
|
line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A68++0x07
|
|
line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A70++0x07
|
|
line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A78++0x07
|
|
line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A80++0x07
|
|
line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A88++0x07
|
|
line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A90++0x07
|
|
line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7A98++0x07
|
|
line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7AA0++0x07
|
|
line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7AA8++0x07
|
|
line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7AB0++0x07
|
|
line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7AB8++0x07
|
|
line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7AC0++0x07
|
|
line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7AC8++0x07
|
|
line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7AD0++0x07
|
|
line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7AD8++0x07
|
|
line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7AE0++0x07
|
|
line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7AE8++0x07
|
|
line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7AF0++0x07
|
|
line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7AF8++0x07
|
|
line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B00++0x07
|
|
line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B08++0x07
|
|
line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B10++0x07
|
|
line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B18++0x07
|
|
line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B20++0x07
|
|
line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B28++0x07
|
|
line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B30++0x07
|
|
line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B38++0x07
|
|
line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B40++0x07
|
|
line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B48++0x07
|
|
line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B50++0x07
|
|
line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B58++0x07
|
|
line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B60++0x07
|
|
line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B68++0x07
|
|
line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B70++0x07
|
|
line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B78++0x07
|
|
line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B80++0x07
|
|
line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B88++0x07
|
|
line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B90++0x07
|
|
line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7B98++0x07
|
|
line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7BA0++0x07
|
|
line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7BA8++0x07
|
|
line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7BB0++0x07
|
|
line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7BB8++0x07
|
|
line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7BC0++0x07
|
|
line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7BC8++0x07
|
|
line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7BD0++0x07
|
|
line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7BD8++0x07
|
|
line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7BE0++0x07
|
|
line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7BE8++0x07
|
|
line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7BF0++0x07
|
|
line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7BF8++0x07
|
|
line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C00++0x07
|
|
line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C08++0x07
|
|
line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C10++0x07
|
|
line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C18++0x07
|
|
line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C20++0x07
|
|
line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C28++0x07
|
|
line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C30++0x07
|
|
line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C38++0x07
|
|
line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C40++0x07
|
|
line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C48++0x07
|
|
line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C50++0x07
|
|
line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C58++0x07
|
|
line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C60++0x07
|
|
line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C68++0x07
|
|
line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C70++0x07
|
|
line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C78++0x07
|
|
line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C80++0x07
|
|
line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C88++0x07
|
|
line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C90++0x07
|
|
line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7C98++0x07
|
|
line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7CA0++0x07
|
|
line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7CA8++0x07
|
|
line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7CB0++0x07
|
|
line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7CB8++0x07
|
|
line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7CC0++0x07
|
|
line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7CC8++0x07
|
|
line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7CD0++0x07
|
|
line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7CD8++0x07
|
|
line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7CE0++0x07
|
|
line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7CE8++0x07
|
|
line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7CF0++0x07
|
|
line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7CF8++0x07
|
|
line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D00++0x07
|
|
line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D08++0x07
|
|
line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D10++0x07
|
|
line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D18++0x07
|
|
line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D20++0x07
|
|
line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D28++0x07
|
|
line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D30++0x07
|
|
line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D38++0x07
|
|
line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D40++0x07
|
|
line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D48++0x07
|
|
line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D50++0x07
|
|
line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D58++0x07
|
|
line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D60++0x07
|
|
line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D68++0x07
|
|
line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D70++0x07
|
|
line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D78++0x07
|
|
line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D80++0x07
|
|
line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D88++0x07
|
|
line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D90++0x07
|
|
line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7D98++0x07
|
|
line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7DA0++0x07
|
|
line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7DA8++0x07
|
|
line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7DB0++0x07
|
|
line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7DB8++0x07
|
|
line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7DC0++0x07
|
|
line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7DC8++0x07
|
|
line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7DD0++0x07
|
|
line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7DD8++0x07
|
|
line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7DE0++0x07
|
|
line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7DE8++0x07
|
|
line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7DF0++0x07
|
|
line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7DF8++0x07
|
|
line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E00++0x07
|
|
line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E08++0x07
|
|
line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E10++0x07
|
|
line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E18++0x07
|
|
line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E20++0x07
|
|
line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E28++0x07
|
|
line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E30++0x07
|
|
line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E38++0x07
|
|
line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E40++0x07
|
|
line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E48++0x07
|
|
line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E50++0x07
|
|
line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E58++0x07
|
|
line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E60++0x07
|
|
line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E68++0x07
|
|
line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E70++0x07
|
|
line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E78++0x07
|
|
line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E80++0x07
|
|
line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E88++0x07
|
|
line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E90++0x07
|
|
line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7E98++0x07
|
|
line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7EA0++0x07
|
|
line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7EA8++0x07
|
|
line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7EB0++0x07
|
|
line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7EB8++0x07
|
|
line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7EC0++0x07
|
|
line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7EC8++0x07
|
|
line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7ED0++0x07
|
|
line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7ED8++0x07
|
|
line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7EE0++0x07
|
|
line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7EE8++0x07
|
|
line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7EF0++0x07
|
|
line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
group.quad 0x7EF8++0x07
|
|
line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
|
|
bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
|
|
hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
|
|
tree.end
|
|
width 22.
|
|
tree "Implementation Defined Test Registers"
|
|
rgroup.long 0xC000++0x03
|
|
line.long 0x00 "GICD_ESTATUSR,GICD_ESTATUSR"
|
|
bitfld.long 0x00 31. " SRWP ,Super Register Write Pending" "Not pending,Pending"
|
|
wgroup.long 0xC004++0x03
|
|
line.long 0x00 "GICD_ERRTESTR,Error Test Register"
|
|
bitfld.long 0x00 1. " AXIM_ERR ,Drives the axim_err pin to 0b1 for 1 cycle" "Low,High"
|
|
bitfld.long 0x00 0. " ECC_FATAL ,Drives the ecc_fatal pin to 0b1 for 1 cycle" "Low,High"
|
|
textline " "
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
|
|
rgroup.long 0xC084++0x03
|
|
line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
|
|
bitfld.long 0x00 31. " SPIS63 ,SPI Status Bit 63" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS62 ,SPI Status Bit 62" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS61 ,SPI Status Bit 61" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS60 ,SPI Status Bit 60" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS59 ,SPI Status Bit 59" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS58 ,SPI Status Bit 58" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS57 ,SPI Status Bit 57" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS56 ,SPI Status Bit 56" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS55 ,SPI Status Bit 55" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS54 ,SPI Status Bit 54" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS53 ,SPI Status Bit 53" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS52 ,SPI Status Bit 52" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS51 ,SPI Status Bit 51" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS50 ,SPI Status Bit 50" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS49 ,SPI Status Bit 49" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS48 ,SPI Status Bit 48" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS47 ,SPI Status Bit 47" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS46 ,SPI Status Bit 46" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS45 ,SPI Status Bit 45" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS44 ,SPI Status Bit 44" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS43 ,SPI Status Bit 43" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS42 ,SPI Status Bit 42" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS41 ,SPI Status Bit 41" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS40 ,SPI Status Bit 40" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS39 ,SPI Status Bit 39" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS38 ,SPI Status Bit 38" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS37 ,SPI Status Bit 37" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS36 ,SPI Status Bit 36" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS35 ,SPI Status Bit 35" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS34 ,SPI Status Bit 34" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS33 ,SPI Status Bit 33" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS32 ,SPI Status Bit 32" "Low,High"
|
|
else
|
|
hgroup.long 0xC084++0x03
|
|
hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
|
|
rgroup.long 0xC088++0x03
|
|
line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
|
|
bitfld.long 0x00 31. " SPIS95 ,SPI Status Bit 95" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS94 ,SPI Status Bit 94" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS93 ,SPI Status Bit 93" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS92 ,SPI Status Bit 92" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS91 ,SPI Status Bit 91" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS90 ,SPI Status Bit 90" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS89 ,SPI Status Bit 89" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS88 ,SPI Status Bit 88" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS87 ,SPI Status Bit 87" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS86 ,SPI Status Bit 86" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS85 ,SPI Status Bit 85" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS84 ,SPI Status Bit 84" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS83 ,SPI Status Bit 83" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS82 ,SPI Status Bit 82" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS81 ,SPI Status Bit 81" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS80 ,SPI Status Bit 80" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS79 ,SPI Status Bit 79" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS78 ,SPI Status Bit 78" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS77 ,SPI Status Bit 77" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS76 ,SPI Status Bit 76" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS75 ,SPI Status Bit 75" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS74 ,SPI Status Bit 74" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS73 ,SPI Status Bit 73" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS72 ,SPI Status Bit 72" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS71 ,SPI Status Bit 71" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS70 ,SPI Status Bit 70" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS69 ,SPI Status Bit 69" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS68 ,SPI Status Bit 68" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS67 ,SPI Status Bit 67" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS66 ,SPI Status Bit 66" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS65 ,SPI Status Bit 65" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS64 ,SPI Status Bit 64" "Low,High"
|
|
else
|
|
hgroup.long 0xC088++0x03
|
|
hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
|
|
rgroup.long 0xC08C++0x03
|
|
line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
|
|
bitfld.long 0x00 31. " SPIS127 ,SPI Status Bit 127" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS126 ,SPI Status Bit 126" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS125 ,SPI Status Bit 125" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS124 ,SPI Status Bit 124" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS123 ,SPI Status Bit 123" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS122 ,SPI Status Bit 122" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS121 ,SPI Status Bit 121" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS120 ,SPI Status Bit 120" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS119 ,SPI Status Bit 119" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS118 ,SPI Status Bit 118" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS117 ,SPI Status Bit 117" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS116 ,SPI Status Bit 116" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS115 ,SPI Status Bit 115" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS114 ,SPI Status Bit 114" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS113 ,SPI Status Bit 113" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS112 ,SPI Status Bit 112" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS111 ,SPI Status Bit 111" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS110 ,SPI Status Bit 110" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS109 ,SPI Status Bit 109" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS108 ,SPI Status Bit 108" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS107 ,SPI Status Bit 107" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS106 ,SPI Status Bit 106" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS105 ,SPI Status Bit 105" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS104 ,SPI Status Bit 104" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS103 ,SPI Status Bit 103" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS102 ,SPI Status Bit 102" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS101 ,SPI Status Bit 101" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS100 ,SPI Status Bit 100" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS99 ,SPI Status Bit 99" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS98 ,SPI Status Bit 98" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS97 ,SPI Status Bit 97" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS96 ,SPI Status Bit 96" "Low,High"
|
|
else
|
|
hgroup.long 0xC08C++0x03
|
|
hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
|
|
rgroup.long 0xC090++0x03
|
|
line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
|
|
bitfld.long 0x00 31. " SPIS159 ,SPI Status Bit 159" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS158 ,SPI Status Bit 158" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS157 ,SPI Status Bit 157" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS156 ,SPI Status Bit 156" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS155 ,SPI Status Bit 155" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS154 ,SPI Status Bit 154" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS153 ,SPI Status Bit 153" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS152 ,SPI Status Bit 152" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS151 ,SPI Status Bit 151" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS150 ,SPI Status Bit 150" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS149 ,SPI Status Bit 149" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS148 ,SPI Status Bit 148" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS147 ,SPI Status Bit 147" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS146 ,SPI Status Bit 146" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS145 ,SPI Status Bit 145" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS144 ,SPI Status Bit 144" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS143 ,SPI Status Bit 143" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS142 ,SPI Status Bit 142" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS141 ,SPI Status Bit 141" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS140 ,SPI Status Bit 140" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS139 ,SPI Status Bit 139" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS138 ,SPI Status Bit 138" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS137 ,SPI Status Bit 137" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS136 ,SPI Status Bit 136" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS135 ,SPI Status Bit 135" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS134 ,SPI Status Bit 134" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS133 ,SPI Status Bit 133" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS132 ,SPI Status Bit 132" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS131 ,SPI Status Bit 131" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS130 ,SPI Status Bit 130" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS129 ,SPI Status Bit 129" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS128 ,SPI Status Bit 128" "Low,High"
|
|
else
|
|
hgroup.long 0xC090++0x03
|
|
hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
|
|
rgroup.long 0xC094++0x03
|
|
line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
|
|
bitfld.long 0x00 31. " SPIS191 ,SPI Status Bit 191" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS190 ,SPI Status Bit 190" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS189 ,SPI Status Bit 189" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS188 ,SPI Status Bit 188" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS187 ,SPI Status Bit 187" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS186 ,SPI Status Bit 186" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS185 ,SPI Status Bit 185" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS184 ,SPI Status Bit 184" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS183 ,SPI Status Bit 183" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS182 ,SPI Status Bit 182" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS181 ,SPI Status Bit 181" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS180 ,SPI Status Bit 180" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS179 ,SPI Status Bit 179" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS178 ,SPI Status Bit 178" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS177 ,SPI Status Bit 177" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS176 ,SPI Status Bit 176" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS175 ,SPI Status Bit 175" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS174 ,SPI Status Bit 174" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS173 ,SPI Status Bit 173" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS172 ,SPI Status Bit 172" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS171 ,SPI Status Bit 171" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS170 ,SPI Status Bit 170" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS169 ,SPI Status Bit 169" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS168 ,SPI Status Bit 168" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS167 ,SPI Status Bit 167" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS166 ,SPI Status Bit 166" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS165 ,SPI Status Bit 165" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS164 ,SPI Status Bit 164" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS163 ,SPI Status Bit 163" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS162 ,SPI Status Bit 162" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS161 ,SPI Status Bit 161" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS160 ,SPI Status Bit 160" "Low,High"
|
|
else
|
|
hgroup.long 0xC094++0x03
|
|
hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
|
|
rgroup.long 0xC098++0x03
|
|
line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
|
|
bitfld.long 0x00 31. " SPIS223 ,SPI Status Bit 223" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS222 ,SPI Status Bit 222" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS221 ,SPI Status Bit 221" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS220 ,SPI Status Bit 220" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS219 ,SPI Status Bit 219" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS218 ,SPI Status Bit 218" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS217 ,SPI Status Bit 217" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS216 ,SPI Status Bit 216" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS215 ,SPI Status Bit 215" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS214 ,SPI Status Bit 214" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS213 ,SPI Status Bit 213" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS212 ,SPI Status Bit 212" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS211 ,SPI Status Bit 211" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS210 ,SPI Status Bit 210" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS209 ,SPI Status Bit 209" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS208 ,SPI Status Bit 208" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS207 ,SPI Status Bit 207" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS206 ,SPI Status Bit 206" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS205 ,SPI Status Bit 205" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS204 ,SPI Status Bit 204" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS203 ,SPI Status Bit 203" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS202 ,SPI Status Bit 202" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS201 ,SPI Status Bit 201" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS200 ,SPI Status Bit 200" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS199 ,SPI Status Bit 199" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS198 ,SPI Status Bit 198" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS197 ,SPI Status Bit 197" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS196 ,SPI Status Bit 196" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS195 ,SPI Status Bit 195" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS194 ,SPI Status Bit 194" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS193 ,SPI Status Bit 193" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS192 ,SPI Status Bit 192" "Low,High"
|
|
else
|
|
hgroup.long 0xC098++0x03
|
|
hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
|
|
rgroup.long 0xC09C++0x03
|
|
line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
|
|
bitfld.long 0x00 31. " SPIS255 ,SPI Status Bit 255" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS254 ,SPI Status Bit 254" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS253 ,SPI Status Bit 253" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS252 ,SPI Status Bit 252" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS251 ,SPI Status Bit 251" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS250 ,SPI Status Bit 250" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS249 ,SPI Status Bit 249" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS248 ,SPI Status Bit 248" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS247 ,SPI Status Bit 247" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS246 ,SPI Status Bit 246" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS245 ,SPI Status Bit 245" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS244 ,SPI Status Bit 244" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS243 ,SPI Status Bit 243" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS242 ,SPI Status Bit 242" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS241 ,SPI Status Bit 241" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS240 ,SPI Status Bit 240" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS239 ,SPI Status Bit 239" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS238 ,SPI Status Bit 238" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS237 ,SPI Status Bit 237" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS236 ,SPI Status Bit 236" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS235 ,SPI Status Bit 235" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS234 ,SPI Status Bit 234" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS233 ,SPI Status Bit 233" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS232 ,SPI Status Bit 232" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS231 ,SPI Status Bit 231" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS230 ,SPI Status Bit 230" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS229 ,SPI Status Bit 229" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS228 ,SPI Status Bit 228" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS227 ,SPI Status Bit 227" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS226 ,SPI Status Bit 226" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS225 ,SPI Status Bit 225" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS224 ,SPI Status Bit 224" "Low,High"
|
|
else
|
|
hgroup.long 0xC09C++0x03
|
|
hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
|
|
rgroup.long 0xC0A0++0x03
|
|
line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
|
|
bitfld.long 0x00 31. " SPIS287 ,SPI Status Bit 287" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS286 ,SPI Status Bit 286" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS285 ,SPI Status Bit 285" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS284 ,SPI Status Bit 284" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS283 ,SPI Status Bit 283" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS282 ,SPI Status Bit 282" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS281 ,SPI Status Bit 281" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS280 ,SPI Status Bit 280" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS279 ,SPI Status Bit 279" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS278 ,SPI Status Bit 278" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS277 ,SPI Status Bit 277" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS276 ,SPI Status Bit 276" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS275 ,SPI Status Bit 275" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS274 ,SPI Status Bit 274" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS273 ,SPI Status Bit 273" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS272 ,SPI Status Bit 272" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS271 ,SPI Status Bit 271" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS270 ,SPI Status Bit 270" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS269 ,SPI Status Bit 269" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS268 ,SPI Status Bit 268" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS267 ,SPI Status Bit 267" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS266 ,SPI Status Bit 266" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS265 ,SPI Status Bit 265" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS264 ,SPI Status Bit 264" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS263 ,SPI Status Bit 263" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS262 ,SPI Status Bit 262" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS261 ,SPI Status Bit 261" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS260 ,SPI Status Bit 260" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS259 ,SPI Status Bit 259" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS258 ,SPI Status Bit 258" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS257 ,SPI Status Bit 257" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS256 ,SPI Status Bit 256" "Low,High"
|
|
else
|
|
hgroup.long 0xC0A0++0x03
|
|
hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
|
|
rgroup.long 0xC0A4++0x03
|
|
line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
|
|
bitfld.long 0x00 31. " SPIS319 ,SPI Status Bit 319" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS318 ,SPI Status Bit 318" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS317 ,SPI Status Bit 317" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS316 ,SPI Status Bit 316" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS315 ,SPI Status Bit 315" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS314 ,SPI Status Bit 314" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS313 ,SPI Status Bit 313" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS312 ,SPI Status Bit 312" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS311 ,SPI Status Bit 311" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS310 ,SPI Status Bit 310" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS309 ,SPI Status Bit 309" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS308 ,SPI Status Bit 308" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS307 ,SPI Status Bit 307" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS306 ,SPI Status Bit 306" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS305 ,SPI Status Bit 305" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS304 ,SPI Status Bit 304" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS303 ,SPI Status Bit 303" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS302 ,SPI Status Bit 302" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS301 ,SPI Status Bit 301" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS300 ,SPI Status Bit 300" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS299 ,SPI Status Bit 299" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS298 ,SPI Status Bit 298" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS297 ,SPI Status Bit 297" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS296 ,SPI Status Bit 296" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS295 ,SPI Status Bit 295" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS294 ,SPI Status Bit 294" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS293 ,SPI Status Bit 293" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS292 ,SPI Status Bit 292" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS291 ,SPI Status Bit 291" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS290 ,SPI Status Bit 290" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS289 ,SPI Status Bit 289" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS288 ,SPI Status Bit 288" "Low,High"
|
|
else
|
|
hgroup.long 0xC0A4++0x03
|
|
hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
|
|
rgroup.long 0xC0A8++0x03
|
|
line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
|
|
bitfld.long 0x00 31. " SPIS351 ,SPI Status Bit 351" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS350 ,SPI Status Bit 350" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS349 ,SPI Status Bit 349" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS348 ,SPI Status Bit 348" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS347 ,SPI Status Bit 347" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS346 ,SPI Status Bit 346" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS345 ,SPI Status Bit 345" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS344 ,SPI Status Bit 344" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS343 ,SPI Status Bit 343" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS342 ,SPI Status Bit 342" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS341 ,SPI Status Bit 341" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS340 ,SPI Status Bit 340" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS339 ,SPI Status Bit 339" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS338 ,SPI Status Bit 338" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS337 ,SPI Status Bit 337" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS336 ,SPI Status Bit 336" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS335 ,SPI Status Bit 335" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS334 ,SPI Status Bit 334" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS333 ,SPI Status Bit 333" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS332 ,SPI Status Bit 332" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS331 ,SPI Status Bit 331" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS330 ,SPI Status Bit 330" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS329 ,SPI Status Bit 329" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS328 ,SPI Status Bit 328" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS327 ,SPI Status Bit 327" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS326 ,SPI Status Bit 326" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS325 ,SPI Status Bit 325" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS324 ,SPI Status Bit 324" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS323 ,SPI Status Bit 323" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS322 ,SPI Status Bit 322" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS321 ,SPI Status Bit 321" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS320 ,SPI Status Bit 320" "Low,High"
|
|
else
|
|
hgroup.long 0xC0A8++0x03
|
|
hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
|
|
rgroup.long 0xC0AC++0x03
|
|
line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
|
|
bitfld.long 0x00 31. " SPIS383 ,SPI Status Bit 383" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS382 ,SPI Status Bit 382" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS381 ,SPI Status Bit 381" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS380 ,SPI Status Bit 380" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS379 ,SPI Status Bit 379" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS378 ,SPI Status Bit 378" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS377 ,SPI Status Bit 377" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS376 ,SPI Status Bit 376" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS375 ,SPI Status Bit 375" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS374 ,SPI Status Bit 374" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS373 ,SPI Status Bit 373" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS372 ,SPI Status Bit 372" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS371 ,SPI Status Bit 371" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS370 ,SPI Status Bit 370" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS369 ,SPI Status Bit 369" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS368 ,SPI Status Bit 368" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS367 ,SPI Status Bit 367" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS366 ,SPI Status Bit 366" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS365 ,SPI Status Bit 365" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS364 ,SPI Status Bit 364" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS363 ,SPI Status Bit 363" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS362 ,SPI Status Bit 362" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS361 ,SPI Status Bit 361" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS360 ,SPI Status Bit 360" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS359 ,SPI Status Bit 359" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS358 ,SPI Status Bit 358" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS357 ,SPI Status Bit 357" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS356 ,SPI Status Bit 356" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS355 ,SPI Status Bit 355" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS354 ,SPI Status Bit 354" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS353 ,SPI Status Bit 353" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS352 ,SPI Status Bit 352" "Low,High"
|
|
else
|
|
hgroup.long 0xC0AC++0x03
|
|
hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
|
|
rgroup.long 0xC0B0++0x03
|
|
line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
|
|
bitfld.long 0x00 31. " SPIS415 ,SPI Status Bit 415" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS414 ,SPI Status Bit 414" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS413 ,SPI Status Bit 413" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS412 ,SPI Status Bit 412" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS411 ,SPI Status Bit 411" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS410 ,SPI Status Bit 410" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS409 ,SPI Status Bit 409" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS408 ,SPI Status Bit 408" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS407 ,SPI Status Bit 407" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS406 ,SPI Status Bit 406" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS405 ,SPI Status Bit 405" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS404 ,SPI Status Bit 404" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS403 ,SPI Status Bit 403" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS402 ,SPI Status Bit 402" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS401 ,SPI Status Bit 401" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS400 ,SPI Status Bit 400" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS399 ,SPI Status Bit 399" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS398 ,SPI Status Bit 398" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS397 ,SPI Status Bit 397" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS396 ,SPI Status Bit 396" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS395 ,SPI Status Bit 395" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS394 ,SPI Status Bit 394" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS393 ,SPI Status Bit 393" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS392 ,SPI Status Bit 392" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS391 ,SPI Status Bit 391" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS390 ,SPI Status Bit 390" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS389 ,SPI Status Bit 389" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS388 ,SPI Status Bit 388" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS387 ,SPI Status Bit 387" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS386 ,SPI Status Bit 386" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS385 ,SPI Status Bit 385" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS384 ,SPI Status Bit 384" "Low,High"
|
|
else
|
|
hgroup.long 0xC0B0++0x03
|
|
hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
|
|
rgroup.long 0xC0B4++0x03
|
|
line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
|
|
bitfld.long 0x00 31. " SPIS447 ,SPI Status Bit 447" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS446 ,SPI Status Bit 446" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS445 ,SPI Status Bit 445" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS444 ,SPI Status Bit 444" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS443 ,SPI Status Bit 443" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS442 ,SPI Status Bit 442" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS441 ,SPI Status Bit 441" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS440 ,SPI Status Bit 440" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS439 ,SPI Status Bit 439" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS438 ,SPI Status Bit 438" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS437 ,SPI Status Bit 437" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS436 ,SPI Status Bit 436" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS435 ,SPI Status Bit 435" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS434 ,SPI Status Bit 434" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS433 ,SPI Status Bit 433" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS432 ,SPI Status Bit 432" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS431 ,SPI Status Bit 431" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS430 ,SPI Status Bit 430" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS429 ,SPI Status Bit 429" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS428 ,SPI Status Bit 428" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS427 ,SPI Status Bit 427" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS426 ,SPI Status Bit 426" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS425 ,SPI Status Bit 425" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS424 ,SPI Status Bit 424" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS423 ,SPI Status Bit 423" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS422 ,SPI Status Bit 422" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS421 ,SPI Status Bit 421" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS420 ,SPI Status Bit 420" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS419 ,SPI Status Bit 419" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS418 ,SPI Status Bit 418" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS417 ,SPI Status Bit 417" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS416 ,SPI Status Bit 416" "Low,High"
|
|
else
|
|
hgroup.long 0xC0B4++0x03
|
|
hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
|
|
rgroup.long 0xC0B8++0x03
|
|
line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
|
|
bitfld.long 0x00 31. " SPIS479 ,SPI Status Bit 479" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS478 ,SPI Status Bit 478" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS477 ,SPI Status Bit 477" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS476 ,SPI Status Bit 476" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS475 ,SPI Status Bit 475" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS474 ,SPI Status Bit 474" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS473 ,SPI Status Bit 473" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS472 ,SPI Status Bit 472" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS471 ,SPI Status Bit 471" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS470 ,SPI Status Bit 470" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS469 ,SPI Status Bit 469" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS468 ,SPI Status Bit 468" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS467 ,SPI Status Bit 467" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS466 ,SPI Status Bit 466" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS465 ,SPI Status Bit 465" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS464 ,SPI Status Bit 464" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS463 ,SPI Status Bit 463" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS462 ,SPI Status Bit 462" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS461 ,SPI Status Bit 461" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS460 ,SPI Status Bit 460" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS459 ,SPI Status Bit 459" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS458 ,SPI Status Bit 458" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS457 ,SPI Status Bit 457" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS456 ,SPI Status Bit 456" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS455 ,SPI Status Bit 455" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS454 ,SPI Status Bit 454" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS453 ,SPI Status Bit 453" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS452 ,SPI Status Bit 452" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS451 ,SPI Status Bit 451" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS450 ,SPI Status Bit 450" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS449 ,SPI Status Bit 449" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS448 ,SPI Status Bit 448" "Low,High"
|
|
else
|
|
hgroup.long 0xC0B8++0x03
|
|
hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
|
|
rgroup.long 0xC0BC++0x03
|
|
line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
|
|
bitfld.long 0x00 31. " SPIS511 ,SPI Status Bit 511" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS510 ,SPI Status Bit 510" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS509 ,SPI Status Bit 509" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS508 ,SPI Status Bit 508" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS507 ,SPI Status Bit 507" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS506 ,SPI Status Bit 506" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS505 ,SPI Status Bit 505" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS504 ,SPI Status Bit 504" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS503 ,SPI Status Bit 503" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS502 ,SPI Status Bit 502" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS501 ,SPI Status Bit 501" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS500 ,SPI Status Bit 500" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS499 ,SPI Status Bit 499" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS498 ,SPI Status Bit 498" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS497 ,SPI Status Bit 497" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS496 ,SPI Status Bit 496" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS495 ,SPI Status Bit 495" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS494 ,SPI Status Bit 494" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS493 ,SPI Status Bit 493" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS492 ,SPI Status Bit 492" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS491 ,SPI Status Bit 491" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS490 ,SPI Status Bit 490" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS489 ,SPI Status Bit 489" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS488 ,SPI Status Bit 488" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS487 ,SPI Status Bit 487" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS486 ,SPI Status Bit 486" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS485 ,SPI Status Bit 485" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS484 ,SPI Status Bit 484" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS483 ,SPI Status Bit 483" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS482 ,SPI Status Bit 482" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS481 ,SPI Status Bit 481" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS480 ,SPI Status Bit 480" "Low,High"
|
|
else
|
|
hgroup.long 0xC0BC++0x03
|
|
hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
|
|
rgroup.long 0xC0C0++0x03
|
|
line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
|
|
bitfld.long 0x00 31. " SPIS543 ,SPI Status Bit 543" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS542 ,SPI Status Bit 542" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS541 ,SPI Status Bit 541" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS540 ,SPI Status Bit 540" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS539 ,SPI Status Bit 539" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS538 ,SPI Status Bit 538" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS537 ,SPI Status Bit 537" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS536 ,SPI Status Bit 536" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS535 ,SPI Status Bit 535" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS534 ,SPI Status Bit 534" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS533 ,SPI Status Bit 533" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS532 ,SPI Status Bit 532" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS531 ,SPI Status Bit 531" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS530 ,SPI Status Bit 530" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS529 ,SPI Status Bit 529" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS528 ,SPI Status Bit 528" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS527 ,SPI Status Bit 527" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS526 ,SPI Status Bit 526" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS525 ,SPI Status Bit 525" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS524 ,SPI Status Bit 524" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS523 ,SPI Status Bit 523" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS522 ,SPI Status Bit 522" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS521 ,SPI Status Bit 521" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS520 ,SPI Status Bit 520" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS519 ,SPI Status Bit 519" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS518 ,SPI Status Bit 518" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS517 ,SPI Status Bit 517" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS516 ,SPI Status Bit 516" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS515 ,SPI Status Bit 515" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS514 ,SPI Status Bit 514" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS513 ,SPI Status Bit 513" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS512 ,SPI Status Bit 512" "Low,High"
|
|
else
|
|
hgroup.long 0xC0C0++0x03
|
|
hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
|
|
rgroup.long 0xC0C4++0x03
|
|
line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
|
|
bitfld.long 0x00 31. " SPIS575 ,SPI Status Bit 575" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS574 ,SPI Status Bit 574" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS573 ,SPI Status Bit 573" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS572 ,SPI Status Bit 572" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS571 ,SPI Status Bit 571" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS570 ,SPI Status Bit 570" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS569 ,SPI Status Bit 569" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS568 ,SPI Status Bit 568" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS567 ,SPI Status Bit 567" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS566 ,SPI Status Bit 566" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS565 ,SPI Status Bit 565" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS564 ,SPI Status Bit 564" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS563 ,SPI Status Bit 563" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS562 ,SPI Status Bit 562" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS561 ,SPI Status Bit 561" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS560 ,SPI Status Bit 560" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS559 ,SPI Status Bit 559" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS558 ,SPI Status Bit 558" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS557 ,SPI Status Bit 557" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS556 ,SPI Status Bit 556" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS555 ,SPI Status Bit 555" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS554 ,SPI Status Bit 554" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS553 ,SPI Status Bit 553" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS552 ,SPI Status Bit 552" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS551 ,SPI Status Bit 551" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS550 ,SPI Status Bit 550" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS549 ,SPI Status Bit 549" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS548 ,SPI Status Bit 548" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS547 ,SPI Status Bit 547" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS546 ,SPI Status Bit 546" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS545 ,SPI Status Bit 545" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS544 ,SPI Status Bit 544" "Low,High"
|
|
else
|
|
hgroup.long 0xC0C4++0x03
|
|
hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
|
|
rgroup.long 0xC0C8++0x03
|
|
line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
|
|
bitfld.long 0x00 31. " SPIS607 ,SPI Status Bit 607" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS606 ,SPI Status Bit 606" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS605 ,SPI Status Bit 605" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS604 ,SPI Status Bit 604" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS603 ,SPI Status Bit 603" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS602 ,SPI Status Bit 602" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS601 ,SPI Status Bit 601" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS600 ,SPI Status Bit 600" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS599 ,SPI Status Bit 599" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS598 ,SPI Status Bit 598" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS597 ,SPI Status Bit 597" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS596 ,SPI Status Bit 596" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS595 ,SPI Status Bit 595" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS594 ,SPI Status Bit 594" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS593 ,SPI Status Bit 593" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS592 ,SPI Status Bit 592" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS591 ,SPI Status Bit 591" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS590 ,SPI Status Bit 590" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS589 ,SPI Status Bit 589" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS588 ,SPI Status Bit 588" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS587 ,SPI Status Bit 587" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS586 ,SPI Status Bit 586" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS585 ,SPI Status Bit 585" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS584 ,SPI Status Bit 584" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS583 ,SPI Status Bit 583" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS582 ,SPI Status Bit 582" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS581 ,SPI Status Bit 581" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS580 ,SPI Status Bit 580" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS579 ,SPI Status Bit 579" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS578 ,SPI Status Bit 578" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS577 ,SPI Status Bit 577" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS576 ,SPI Status Bit 576" "Low,High"
|
|
else
|
|
hgroup.long 0xC0C8++0x03
|
|
hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
|
|
rgroup.long 0xC0CC++0x03
|
|
line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
|
|
bitfld.long 0x00 31. " SPIS639 ,SPI Status Bit 639" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS638 ,SPI Status Bit 638" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS637 ,SPI Status Bit 637" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS636 ,SPI Status Bit 636" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS635 ,SPI Status Bit 635" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS634 ,SPI Status Bit 634" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS633 ,SPI Status Bit 633" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS632 ,SPI Status Bit 632" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS631 ,SPI Status Bit 631" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS630 ,SPI Status Bit 630" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS629 ,SPI Status Bit 629" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS628 ,SPI Status Bit 628" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS627 ,SPI Status Bit 627" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS626 ,SPI Status Bit 626" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS625 ,SPI Status Bit 625" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS624 ,SPI Status Bit 624" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS623 ,SPI Status Bit 623" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS622 ,SPI Status Bit 622" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS621 ,SPI Status Bit 621" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS620 ,SPI Status Bit 620" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS619 ,SPI Status Bit 619" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS618 ,SPI Status Bit 618" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS617 ,SPI Status Bit 617" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS616 ,SPI Status Bit 616" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS615 ,SPI Status Bit 615" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS614 ,SPI Status Bit 614" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS613 ,SPI Status Bit 613" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS612 ,SPI Status Bit 612" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS611 ,SPI Status Bit 611" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS610 ,SPI Status Bit 610" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS609 ,SPI Status Bit 609" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS608 ,SPI Status Bit 608" "Low,High"
|
|
else
|
|
hgroup.long 0xC0CC++0x03
|
|
hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
|
|
rgroup.long 0xC0D0++0x03
|
|
line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
|
|
bitfld.long 0x00 31. " SPIS671 ,SPI Status Bit 671" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS670 ,SPI Status Bit 670" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS669 ,SPI Status Bit 669" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS668 ,SPI Status Bit 668" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS667 ,SPI Status Bit 667" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS666 ,SPI Status Bit 666" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS665 ,SPI Status Bit 665" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS664 ,SPI Status Bit 664" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS663 ,SPI Status Bit 663" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS662 ,SPI Status Bit 662" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS661 ,SPI Status Bit 661" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS660 ,SPI Status Bit 660" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS659 ,SPI Status Bit 659" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS658 ,SPI Status Bit 658" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS657 ,SPI Status Bit 657" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS656 ,SPI Status Bit 656" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS655 ,SPI Status Bit 655" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS654 ,SPI Status Bit 654" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS653 ,SPI Status Bit 653" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS652 ,SPI Status Bit 652" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS651 ,SPI Status Bit 651" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS650 ,SPI Status Bit 650" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS649 ,SPI Status Bit 649" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS648 ,SPI Status Bit 648" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS647 ,SPI Status Bit 647" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS646 ,SPI Status Bit 646" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS645 ,SPI Status Bit 645" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS644 ,SPI Status Bit 644" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS643 ,SPI Status Bit 643" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS642 ,SPI Status Bit 642" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS641 ,SPI Status Bit 641" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS640 ,SPI Status Bit 640" "Low,High"
|
|
else
|
|
hgroup.long 0xC0D0++0x03
|
|
hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
|
|
rgroup.long 0xC0D4++0x03
|
|
line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
|
|
bitfld.long 0x00 31. " SPIS703 ,SPI Status Bit 703" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS702 ,SPI Status Bit 702" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS701 ,SPI Status Bit 701" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS700 ,SPI Status Bit 700" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS699 ,SPI Status Bit 699" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS698 ,SPI Status Bit 698" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS697 ,SPI Status Bit 697" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS696 ,SPI Status Bit 696" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS695 ,SPI Status Bit 695" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS694 ,SPI Status Bit 694" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS693 ,SPI Status Bit 693" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS692 ,SPI Status Bit 692" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS691 ,SPI Status Bit 691" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS690 ,SPI Status Bit 690" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS689 ,SPI Status Bit 689" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS688 ,SPI Status Bit 688" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS687 ,SPI Status Bit 687" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS686 ,SPI Status Bit 686" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS685 ,SPI Status Bit 685" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS684 ,SPI Status Bit 684" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS683 ,SPI Status Bit 683" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS682 ,SPI Status Bit 682" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS681 ,SPI Status Bit 681" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS680 ,SPI Status Bit 680" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS679 ,SPI Status Bit 679" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS678 ,SPI Status Bit 678" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS677 ,SPI Status Bit 677" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS676 ,SPI Status Bit 676" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS675 ,SPI Status Bit 675" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS674 ,SPI Status Bit 674" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS673 ,SPI Status Bit 673" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS672 ,SPI Status Bit 672" "Low,High"
|
|
else
|
|
hgroup.long 0xC0D4++0x03
|
|
hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
|
|
rgroup.long 0xC0D8++0x03
|
|
line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
|
|
bitfld.long 0x00 31. " SPIS735 ,SPI Status Bit 735" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS734 ,SPI Status Bit 734" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS733 ,SPI Status Bit 733" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS732 ,SPI Status Bit 732" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS731 ,SPI Status Bit 731" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS730 ,SPI Status Bit 730" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS729 ,SPI Status Bit 729" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS728 ,SPI Status Bit 728" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS727 ,SPI Status Bit 727" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS726 ,SPI Status Bit 726" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS725 ,SPI Status Bit 725" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS724 ,SPI Status Bit 724" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS723 ,SPI Status Bit 723" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS722 ,SPI Status Bit 722" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS721 ,SPI Status Bit 721" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS720 ,SPI Status Bit 720" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS719 ,SPI Status Bit 719" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS718 ,SPI Status Bit 718" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS717 ,SPI Status Bit 717" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS716 ,SPI Status Bit 716" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS715 ,SPI Status Bit 715" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS714 ,SPI Status Bit 714" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS713 ,SPI Status Bit 713" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS712 ,SPI Status Bit 712" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS711 ,SPI Status Bit 711" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS710 ,SPI Status Bit 710" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS709 ,SPI Status Bit 709" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS708 ,SPI Status Bit 708" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS707 ,SPI Status Bit 707" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS706 ,SPI Status Bit 706" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS705 ,SPI Status Bit 705" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS704 ,SPI Status Bit 704" "Low,High"
|
|
else
|
|
hgroup.long 0xC0D8++0x03
|
|
hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
|
|
rgroup.long 0xC0DC++0x03
|
|
line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
|
|
bitfld.long 0x00 31. " SPIS767 ,SPI Status Bit 767" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS766 ,SPI Status Bit 766" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS765 ,SPI Status Bit 765" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS764 ,SPI Status Bit 764" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS763 ,SPI Status Bit 763" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS762 ,SPI Status Bit 762" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS761 ,SPI Status Bit 761" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS760 ,SPI Status Bit 760" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS759 ,SPI Status Bit 759" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS758 ,SPI Status Bit 758" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS757 ,SPI Status Bit 757" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS756 ,SPI Status Bit 756" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS755 ,SPI Status Bit 755" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS754 ,SPI Status Bit 754" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS753 ,SPI Status Bit 753" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS752 ,SPI Status Bit 752" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS751 ,SPI Status Bit 751" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS750 ,SPI Status Bit 750" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS749 ,SPI Status Bit 749" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS748 ,SPI Status Bit 748" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS747 ,SPI Status Bit 747" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS746 ,SPI Status Bit 746" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS745 ,SPI Status Bit 745" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS744 ,SPI Status Bit 744" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS743 ,SPI Status Bit 743" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS742 ,SPI Status Bit 742" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS741 ,SPI Status Bit 741" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS740 ,SPI Status Bit 740" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS739 ,SPI Status Bit 739" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS738 ,SPI Status Bit 738" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS737 ,SPI Status Bit 737" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS736 ,SPI Status Bit 736" "Low,High"
|
|
else
|
|
hgroup.long 0xC0DC++0x03
|
|
hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
|
|
rgroup.long 0xC0E0++0x03
|
|
line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
|
|
bitfld.long 0x00 31. " SPIS799 ,SPI Status Bit 799" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS798 ,SPI Status Bit 798" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS797 ,SPI Status Bit 797" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS796 ,SPI Status Bit 796" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS795 ,SPI Status Bit 795" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS794 ,SPI Status Bit 794" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS793 ,SPI Status Bit 793" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS792 ,SPI Status Bit 792" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS791 ,SPI Status Bit 791" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS790 ,SPI Status Bit 790" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS789 ,SPI Status Bit 789" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS788 ,SPI Status Bit 788" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS787 ,SPI Status Bit 787" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS786 ,SPI Status Bit 786" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS785 ,SPI Status Bit 785" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS784 ,SPI Status Bit 784" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS783 ,SPI Status Bit 783" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS782 ,SPI Status Bit 782" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS781 ,SPI Status Bit 781" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS780 ,SPI Status Bit 780" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS779 ,SPI Status Bit 779" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS778 ,SPI Status Bit 778" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS777 ,SPI Status Bit 777" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS776 ,SPI Status Bit 776" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS775 ,SPI Status Bit 775" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS774 ,SPI Status Bit 774" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS773 ,SPI Status Bit 773" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS772 ,SPI Status Bit 772" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS771 ,SPI Status Bit 771" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS770 ,SPI Status Bit 770" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS769 ,SPI Status Bit 769" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS768 ,SPI Status Bit 768" "Low,High"
|
|
else
|
|
hgroup.long 0xC0E0++0x03
|
|
hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
|
|
rgroup.long 0xC0E4++0x03
|
|
line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
|
|
bitfld.long 0x00 31. " SPIS831 ,SPI Status Bit 831" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS830 ,SPI Status Bit 830" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS829 ,SPI Status Bit 829" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS828 ,SPI Status Bit 828" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS827 ,SPI Status Bit 827" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS826 ,SPI Status Bit 826" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS825 ,SPI Status Bit 825" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS824 ,SPI Status Bit 824" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS823 ,SPI Status Bit 823" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS822 ,SPI Status Bit 822" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS821 ,SPI Status Bit 821" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS820 ,SPI Status Bit 820" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS819 ,SPI Status Bit 819" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS818 ,SPI Status Bit 818" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS817 ,SPI Status Bit 817" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS816 ,SPI Status Bit 816" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS815 ,SPI Status Bit 815" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS814 ,SPI Status Bit 814" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS813 ,SPI Status Bit 813" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS812 ,SPI Status Bit 812" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS811 ,SPI Status Bit 811" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS810 ,SPI Status Bit 810" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS809 ,SPI Status Bit 809" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS808 ,SPI Status Bit 808" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS807 ,SPI Status Bit 807" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS806 ,SPI Status Bit 806" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS805 ,SPI Status Bit 805" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS804 ,SPI Status Bit 804" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS803 ,SPI Status Bit 803" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS802 ,SPI Status Bit 802" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS801 ,SPI Status Bit 801" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS800 ,SPI Status Bit 800" "Low,High"
|
|
else
|
|
hgroup.long 0xC0E4++0x03
|
|
hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
|
|
rgroup.long 0xC0E8++0x03
|
|
line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
|
|
bitfld.long 0x00 31. " SPIS863 ,SPI Status Bit 863" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS862 ,SPI Status Bit 862" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS861 ,SPI Status Bit 861" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS860 ,SPI Status Bit 860" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS859 ,SPI Status Bit 859" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS858 ,SPI Status Bit 858" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS857 ,SPI Status Bit 857" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS856 ,SPI Status Bit 856" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS855 ,SPI Status Bit 855" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS854 ,SPI Status Bit 854" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS853 ,SPI Status Bit 853" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS852 ,SPI Status Bit 852" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS851 ,SPI Status Bit 851" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS850 ,SPI Status Bit 850" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS849 ,SPI Status Bit 849" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS848 ,SPI Status Bit 848" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS847 ,SPI Status Bit 847" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS846 ,SPI Status Bit 846" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS845 ,SPI Status Bit 845" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS844 ,SPI Status Bit 844" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS843 ,SPI Status Bit 843" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS842 ,SPI Status Bit 842" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS841 ,SPI Status Bit 841" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS840 ,SPI Status Bit 840" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS839 ,SPI Status Bit 839" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS838 ,SPI Status Bit 838" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS837 ,SPI Status Bit 837" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS836 ,SPI Status Bit 836" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS835 ,SPI Status Bit 835" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS834 ,SPI Status Bit 834" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS833 ,SPI Status Bit 833" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS832 ,SPI Status Bit 832" "Low,High"
|
|
else
|
|
hgroup.long 0xC0E8++0x03
|
|
hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
|
|
rgroup.long 0xC0EC++0x03
|
|
line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
|
|
bitfld.long 0x00 31. " SPIS895 ,SPI Status Bit 895" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS894 ,SPI Status Bit 894" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS893 ,SPI Status Bit 893" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS892 ,SPI Status Bit 892" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS891 ,SPI Status Bit 891" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS890 ,SPI Status Bit 890" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS889 ,SPI Status Bit 889" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS888 ,SPI Status Bit 888" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS887 ,SPI Status Bit 887" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS886 ,SPI Status Bit 886" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS885 ,SPI Status Bit 885" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS884 ,SPI Status Bit 884" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS883 ,SPI Status Bit 883" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS882 ,SPI Status Bit 882" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS881 ,SPI Status Bit 881" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS880 ,SPI Status Bit 880" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS879 ,SPI Status Bit 879" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS878 ,SPI Status Bit 878" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS877 ,SPI Status Bit 877" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS876 ,SPI Status Bit 876" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS875 ,SPI Status Bit 875" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS874 ,SPI Status Bit 874" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS873 ,SPI Status Bit 873" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS872 ,SPI Status Bit 872" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS871 ,SPI Status Bit 871" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS870 ,SPI Status Bit 870" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS869 ,SPI Status Bit 869" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS868 ,SPI Status Bit 868" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS867 ,SPI Status Bit 867" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS866 ,SPI Status Bit 866" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS865 ,SPI Status Bit 865" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS864 ,SPI Status Bit 864" "Low,High"
|
|
else
|
|
hgroup.long 0xC0EC++0x03
|
|
hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
|
|
rgroup.long 0xC0F0++0x03
|
|
line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
|
|
bitfld.long 0x00 31. " SPIS927 ,SPI Status Bit 927" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS926 ,SPI Status Bit 926" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS925 ,SPI Status Bit 925" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS924 ,SPI Status Bit 924" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS923 ,SPI Status Bit 923" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS922 ,SPI Status Bit 922" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS921 ,SPI Status Bit 921" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS920 ,SPI Status Bit 920" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS919 ,SPI Status Bit 919" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS918 ,SPI Status Bit 918" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS917 ,SPI Status Bit 917" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS916 ,SPI Status Bit 916" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS915 ,SPI Status Bit 915" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS914 ,SPI Status Bit 914" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS913 ,SPI Status Bit 913" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS912 ,SPI Status Bit 912" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS911 ,SPI Status Bit 911" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS910 ,SPI Status Bit 910" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS909 ,SPI Status Bit 909" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS908 ,SPI Status Bit 908" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS907 ,SPI Status Bit 907" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS906 ,SPI Status Bit 906" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS905 ,SPI Status Bit 905" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS904 ,SPI Status Bit 904" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS903 ,SPI Status Bit 903" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS902 ,SPI Status Bit 902" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS901 ,SPI Status Bit 901" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS900 ,SPI Status Bit 900" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS899 ,SPI Status Bit 899" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS898 ,SPI Status Bit 898" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS897 ,SPI Status Bit 897" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS896 ,SPI Status Bit 896" "Low,High"
|
|
else
|
|
hgroup.long 0xC0F0++0x03
|
|
hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
|
|
rgroup.long 0xC0F4++0x03
|
|
line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
|
|
bitfld.long 0x00 31. " SPIS959 ,SPI Status Bit 959" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS958 ,SPI Status Bit 958" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS957 ,SPI Status Bit 957" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS956 ,SPI Status Bit 956" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS955 ,SPI Status Bit 955" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS954 ,SPI Status Bit 954" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS953 ,SPI Status Bit 953" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS952 ,SPI Status Bit 952" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS951 ,SPI Status Bit 951" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS950 ,SPI Status Bit 950" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS949 ,SPI Status Bit 949" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS948 ,SPI Status Bit 948" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS947 ,SPI Status Bit 947" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS946 ,SPI Status Bit 946" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS945 ,SPI Status Bit 945" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS944 ,SPI Status Bit 944" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS943 ,SPI Status Bit 943" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS942 ,SPI Status Bit 942" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS941 ,SPI Status Bit 941" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS940 ,SPI Status Bit 940" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS939 ,SPI Status Bit 939" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS938 ,SPI Status Bit 938" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS937 ,SPI Status Bit 937" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS936 ,SPI Status Bit 936" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS935 ,SPI Status Bit 935" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS934 ,SPI Status Bit 934" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS933 ,SPI Status Bit 933" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS932 ,SPI Status Bit 932" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS931 ,SPI Status Bit 931" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS930 ,SPI Status Bit 930" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS929 ,SPI Status Bit 929" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS928 ,SPI Status Bit 928" "Low,High"
|
|
else
|
|
hgroup.long 0xC0F4++0x03
|
|
hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
|
|
rgroup.long 0xC0F8++0x03
|
|
line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
|
|
bitfld.long 0x00 31. " SPIS991 ,SPI Status Bit 991" "Low,High"
|
|
bitfld.long 0x00 30. " SPIS990 ,SPI Status Bit 990" "Low,High"
|
|
bitfld.long 0x00 29. " SPIS989 ,SPI Status Bit 989" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPIS988 ,SPI Status Bit 988" "Low,High"
|
|
bitfld.long 0x00 27. " SPIS987 ,SPI Status Bit 987" "Low,High"
|
|
bitfld.long 0x00 26. " SPIS986 ,SPI Status Bit 986" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPIS985 ,SPI Status Bit 985" "Low,High"
|
|
bitfld.long 0x00 24. " SPIS984 ,SPI Status Bit 984" "Low,High"
|
|
bitfld.long 0x00 23. " SPIS983 ,SPI Status Bit 983" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPIS982 ,SPI Status Bit 982" "Low,High"
|
|
bitfld.long 0x00 21. " SPIS981 ,SPI Status Bit 981" "Low,High"
|
|
bitfld.long 0x00 20. " SPIS980 ,SPI Status Bit 980" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPIS979 ,SPI Status Bit 979" "Low,High"
|
|
bitfld.long 0x00 18. " SPIS978 ,SPI Status Bit 978" "Low,High"
|
|
bitfld.long 0x00 17. " SPIS977 ,SPI Status Bit 977" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPIS976 ,SPI Status Bit 976" "Low,High"
|
|
bitfld.long 0x00 15. " SPIS975 ,SPI Status Bit 975" "Low,High"
|
|
bitfld.long 0x00 14. " SPIS974 ,SPI Status Bit 974" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPIS973 ,SPI Status Bit 973" "Low,High"
|
|
bitfld.long 0x00 12. " SPIS972 ,SPI Status Bit 972" "Low,High"
|
|
bitfld.long 0x00 11. " SPIS971 ,SPI Status Bit 971" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPIS970 ,SPI Status Bit 970" "Low,High"
|
|
bitfld.long 0x00 9. " SPIS969 ,SPI Status Bit 969" "Low,High"
|
|
bitfld.long 0x00 8. " SPIS968 ,SPI Status Bit 968" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPIS967 ,SPI Status Bit 967" "Low,High"
|
|
bitfld.long 0x00 6. " SPIS966 ,SPI Status Bit 966" "Low,High"
|
|
bitfld.long 0x00 5. " SPIS965 ,SPI Status Bit 965" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIS964 ,SPI Status Bit 964" "Low,High"
|
|
bitfld.long 0x00 3. " SPIS963 ,SPI Status Bit 963" "Low,High"
|
|
bitfld.long 0x00 2. " SPIS962 ,SPI Status Bit 962" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIS961 ,SPI Status Bit 961" "Low,High"
|
|
bitfld.long 0x00 0. " SPIS960 ,SPI Status Bit 960" "Low,High"
|
|
else
|
|
hgroup.long 0xC0F8++0x03
|
|
hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "Peripheral/Component ID Registers"
|
|
rgroup.long 0xFFE0++0x03
|
|
line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]"
|
|
rgroup.long 0xFFE4++0x03
|
|
line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register"
|
|
bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFFE8++0x03
|
|
line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register"
|
|
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
|
|
bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used"
|
|
bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xFFEC++0x03
|
|
line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register"
|
|
bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFFD0++0x03
|
|
line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register"
|
|
bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long 0xFFD4++0x03
|
|
hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register"
|
|
hgroup.long 0xFFD8++0x03
|
|
hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register"
|
|
hgroup.long 0xFFDC++0x03
|
|
hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register"
|
|
rgroup.long 0xFFF0++0x03
|
|
line.long 0x00 "GICD_CIDR0,Component ID0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.long 0xFFF4++0x03
|
|
line.long 0x00 "GICD_CIDR1,Component ID1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.long 0xFFF8++0x03
|
|
line.long 0x00 "GICD_CIDR2,Component ID2 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.long 0xFFFC++0x03
|
|
line.long 0x00 "GICD_CIDR3,Component ID3 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
base (COMP.BASE("GICD",-1.)+0x20000)
|
|
width 24.
|
|
tree "Interrupt Translation Service"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GITS_CTLR,ITS Control Register"
|
|
rbitfld.long 0x00 31. " QUIESCENT ,Indicates completion of all ITS operations" "Not quiescent,Quiescent"
|
|
bitfld.long 0x00 0. " ENABLED ,Controls whether the ITS is enabled" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register"
|
|
bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..."
|
|
bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00)
|
|
rgroup.quad 0x08++0x07
|
|
line.quad 0x00 "GITS_TYPER,ITS Type Register"
|
|
bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
|
|
bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
|
|
textline " "
|
|
bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count"
|
|
textline " "
|
|
bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
|
|
bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
|
|
textline " "
|
|
bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1"
|
|
elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)
|
|
rgroup.quad 0x08++0x07
|
|
line.quad 0x00 "GITS_TYPER,ITS Type Register"
|
|
bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
|
|
bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
|
|
textline " "
|
|
bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count"
|
|
textline " "
|
|
bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
|
|
bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
|
|
textline " "
|
|
bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00)
|
|
rgroup.quad 0x08++0x07
|
|
line.quad 0x00 "GITS_TYPER,ITS Type Register"
|
|
bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
|
|
bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count"
|
|
bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
|
|
textline " "
|
|
bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
|
|
bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1"
|
|
else
|
|
rgroup.quad 0x08++0x07
|
|
line.quad 0x00 "GITS_TYPER,ITS Type Register"
|
|
bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
|
|
bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count"
|
|
bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
|
|
textline " "
|
|
bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
|
|
bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.quad 0x80++0x07
|
|
line.quad 0x00 "GITS_CBASER,The command queue control register"
|
|
bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated"
|
|
bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
|
|
textline " "
|
|
bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
|
|
hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the base physical address of the command queue"
|
|
textline " "
|
|
bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..."
|
|
hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of 4KB pages of physical memory allocated to the command queue minus one"
|
|
group.quad 0x88++0x7
|
|
line.quad 0x00 "GITS_CWRITER,The command queue write pointer"
|
|
hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER"
|
|
bitfld.quad 0x00 0. " RETRY ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted"
|
|
group.quad 0x90++0x07
|
|
line.quad 0x00 "GITS_CREADR,The command queue read pointer"
|
|
hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER"
|
|
bitfld.quad 0x00 0. " STALLED ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled"
|
|
if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0100))&0x700000000000000)==0x00)
|
|
group.quad 0x100++0x07
|
|
line.quad 0x00 "GITS_BASER0,ITS table control register"
|
|
bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
|
|
bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
|
|
textline " "
|
|
bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
|
|
rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
|
|
rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS ,Physical Address"
|
|
bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
|
|
else
|
|
group.quad 0x100++0x07
|
|
line.quad 0x00 "GITS_BASER0,ITS table control register"
|
|
bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
|
|
bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
|
|
textline " "
|
|
bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
|
|
rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
|
|
rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS ,Physical Address"
|
|
bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
|
|
hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of pages of physical memory allocated to the table minus one"
|
|
endif
|
|
textline " "
|
|
wgroup.long 0xC000++0x03
|
|
line.long 0x00 "GITS_TRKCTLR,Tracking Control Register"
|
|
bitfld.long 0x00 1. " LPI_TRACK ,Write 0b1 to capture information about the next interrupt that the ITS generated or failed to generate because of misprogramming" "No effect,Capture"
|
|
bitfld.long 0x00 0. " CACHE_COUNT_RESET ,Write 0b1 to reset the cache hit and miss counters in GITS_TRKICR and GITS_TRKLCR" "No effect,Reset"
|
|
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x1F)==0x01)
|
|
rgroup.long 0xC004++0x03
|
|
line.long 0x00 "GITS_TRKR,Tracking Status Register"
|
|
bitfld.long 0x00 6. " PID_OUT_OF_RANGE ,Indicates that the LPI PID is larger than that allowed by the IDbits field in the GICR_PROPBASER" "0,1"
|
|
bitfld.long 0x00 5. " TARGET_OUT_OF_RANGE ,Indicates that target collection has not been successfully mapped using MAPC or that the target core does not have LPIs enabled in GICR_CTLR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1"
|
|
bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
|
|
bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
|
|
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0xF)==0x01)
|
|
rgroup.long 0xC004++0x03
|
|
line.long 0x00 "GITS_TRKR,Tracking Status Register"
|
|
bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1"
|
|
bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
|
|
bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
|
|
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7)==0x01)
|
|
rgroup.long 0xC004++0x03
|
|
line.long 0x00 "GITS_TRKR,Tracking Status Register"
|
|
bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
|
|
bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
|
|
bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
|
|
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x3)==0x01)
|
|
rgroup.long 0xC004++0x03
|
|
line.long 0x00 "GITS_TRKR,Tracking Status Register"
|
|
bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
|
|
bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
|
|
else
|
|
rgroup.long 0xC004++0x03
|
|
line.long 0x00 "GITS_TRKR,Tracking Status Register"
|
|
bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
|
|
bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
|
|
endif
|
|
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01)
|
|
rgroup.long 0xC008++0x03
|
|
line.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " LPI_DID ,The Device ID for the interrupt that was tracked"
|
|
else
|
|
hgroup.long 0xC008++0x03
|
|
hide.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register"
|
|
endif
|
|
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01)
|
|
rgroup.long 0xC00C++0x03
|
|
line.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LPI_PID ,The ID after translation for an interrupt that was tracked and generated an LPI successfully"
|
|
else
|
|
hgroup.long 0xC00C++0x03
|
|
hide.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register"
|
|
endif
|
|
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01)
|
|
rgroup.long 0xC010++0x03
|
|
line.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LPI_ID ,The ID before translation of the interrupt that was tracked"
|
|
else
|
|
hgroup.long 0xC010++0x03
|
|
hide.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register"
|
|
endif
|
|
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01)
|
|
rgroup.long 0xC014++0x03
|
|
line.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " LPI_TARGET_CORE ,The target core for an interrupt that was tracked and generated an LPI successfully"
|
|
else
|
|
hgroup.long 0xC014++0x03
|
|
hide.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register"
|
|
endif
|
|
rgroup.long 0xC018++0x03
|
|
line.long 0x00 "GITS_TRKICR,Debug ITE Cache Statistics"
|
|
hexmask.long.word 0x00 16.--31. 1. " ITE_CACHE_HITS ,Number of hits in the ITE cache"
|
|
hexmask.long.word 0x00 0.--15. 1. " ITE_CACHE_MISSES ,Number of misses in the ITE cache"
|
|
rgroup.long 0xC01C++0x03
|
|
line.long 0x00 "GITS_TRKLCR,Debug LPI Cache Statistics"
|
|
hexmask.long.word 0x00 16.--31. 1. " LPI_CACHE_HITS ,Number of hits in the LPI cache"
|
|
hexmask.long.word 0x00 0.--15. 1. " LPI_CACHE_MISSES ,Number of misses in the LPI cache"
|
|
rgroup.long 0xFFE0++0x03
|
|
line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]"
|
|
rgroup.long 0xFFE4++0x03
|
|
line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register"
|
|
bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFFE8++0x03
|
|
line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register"
|
|
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
|
|
bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xFFEC++0x03
|
|
line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register"
|
|
bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFFD0++0x03
|
|
line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register"
|
|
bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long 0xFFD4++0x03
|
|
hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register"
|
|
hgroup.long 0xFFD8++0x03
|
|
hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register"
|
|
hgroup.long 0xFFDC++0x03
|
|
hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register"
|
|
rgroup.long 0xFFF0++0x03
|
|
line.long 0x00 "GITS_CIDR0,Component ID0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.long 0xFFF4++0x03
|
|
line.long 0x00 "GITS_CIDR1,Component ID1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.long 0xFFF8++0x03
|
|
line.long 0x00 "GITS_CIDR2,Component ID2 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.long 0xFFFC++0x03
|
|
line.long 0x00 "GITS_CIDR3,Component ID3 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
textline " "
|
|
base (COMP.BASE("GICD",-1.)+0x20000)+0x10000
|
|
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)))&0x01)==0x01)
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "GITS_TRANSLATER,ITS Translation Register"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
base COMP.BASE("GICR",-1.)
|
|
width 17.
|
|
tree "Redistributor Interface"
|
|
tree "Control Registers"
|
|
if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21)
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
|
|
rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes"
|
|
bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes"
|
|
bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled"
|
|
elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20)
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
|
|
rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes"
|
|
bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes"
|
|
bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
|
|
elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01)
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
|
|
rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
|
|
rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
|
|
endif
|
|
rgroup.long 0x0004++0x03
|
|
line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register"
|
|
bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..."
|
|
bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
rgroup.quad 0x0008++0x07
|
|
line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register"
|
|
hexmask.quad.byte 0x00 56.--63. 1. " AFF3 ,Affinity level 3 value for the Redistributor"
|
|
hexmask.quad.byte 0x00 48.--55. 1. " AFF2 ,Affinity level 2 value for the Redistributor"
|
|
hexmask.quad.byte 0x00 40.--47. 1. " AFF1 ,Affinity level 1 value for the Redistributor"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 32.--39. 1. " AFF0 ,Affinity level 0 value for the Redistributor"
|
|
bitfld.quad 0x00 24.--25. " COMMONLPIAFF ,The affinity level at which Redistributors share a LPI Configuration table" "All levels,AFF3,AFF3/AFF2,AFF3/AFF2/AFF1"
|
|
hexmask.quad.word 0x00 8.--23. 1. " PROCESSOR_NUMBER ,A unique identifier for the PE"
|
|
textline " "
|
|
bitfld.quad 0x00 5. " DPGS ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported"
|
|
bitfld.quad 0x00 4. " LAST ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest"
|
|
bitfld.quad 0x00 3. " DIRECTLPI ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " PLPIS ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported"
|
|
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014))))
|
|
group.long 0x0014++0x03
|
|
line.long 0x00 "GICR_WAKER,Power Management Control Register"
|
|
bitfld.long 0x00 31. " QUIESCENT ,This bit shows that the GIC-500 is idle and can be powered down if required" "Not quiescent,Quiescent"
|
|
bitfld.long 0x00 2. " CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent"
|
|
bitfld.long 0x00 1. " PROCESSORASLEEP ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SLEEP ,Indicates if GIC-500 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes"
|
|
textline " "
|
|
else
|
|
hgroup.long 0x0014++0x03
|
|
hide.long 0x00 "GICR_WAKER,Power Management Control Register"
|
|
endif
|
|
group.quad 0x070++0x07
|
|
line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register"
|
|
bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
|
|
hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table"
|
|
textline " "
|
|
bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
|
|
bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
|
|
textline " "
|
|
bitfld.quad 0x00 0.--4. " IDBITS ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address"
|
|
group.quad 0x78++0x07
|
|
line.quad 0x00 "GICR_PENDBASER,LPI pending table base register"
|
|
bitfld.quad 0x00 62. " PTZ ,Pending Table Zero" "Not zero,Zero"
|
|
bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
|
|
textline " "
|
|
hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table"
|
|
bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
|
|
textline " "
|
|
bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
|
|
textline " "
|
|
tree.end
|
|
tree "SGI and PPI Registers"
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080))
|
|
group.long 0x10080++0x03
|
|
line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0"
|
|
bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1"
|
|
bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1"
|
|
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000)
|
|
group.long 0x10080++0x03
|
|
line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0"
|
|
bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x10080++0x03
|
|
hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
width 24.
|
|
group.long 0x10100++0x03
|
|
line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled"
|
|
group.long 0x10200++0x03
|
|
line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending"
|
|
group.long 0x10300++0x03
|
|
line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active"
|
|
textline " "
|
|
width 18.
|
|
group.long 0x10400++0x03
|
|
line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 "
|
|
group.long 0x10404++0x03
|
|
line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 "
|
|
group.long 0x10408++0x03
|
|
line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 "
|
|
group.long 0x1040C++0x03
|
|
line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 "
|
|
group.long 0x10410++0x03
|
|
line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 "
|
|
group.long 0x10414++0x03
|
|
line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 "
|
|
group.long 0x10418++0x03
|
|
line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 "
|
|
group.long 0x1041C++0x03
|
|
line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 "
|
|
textline " "
|
|
rgroup.long 0x10C00++0x03
|
|
line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge"
|
|
group.long 0x10C04++0x03
|
|
line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge"
|
|
textline " "
|
|
width 18.
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00))
|
|
group.long 0x10D00++0x03
|
|
line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0"
|
|
bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1"
|
|
bitfld.long 0x00 30. " GMB30 ,Group Modifier Bit 30" "0,1"
|
|
bitfld.long 0x00 29. " GMB29 ,Group Modifier Bit 29" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1"
|
|
bitfld.long 0x00 27. " GMB27 ,Group Modifier Bit 27" "0,1"
|
|
bitfld.long 0x00 26. " GMB26 ,Group Modifier Bit 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1"
|
|
bitfld.long 0x00 24. " GMB24 ,Group Modifier Bit 24" "0,1"
|
|
bitfld.long 0x00 23. " GMB23 ,Group Modifier Bit 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1"
|
|
bitfld.long 0x00 21. " GMB21 ,Group Modifier Bit 21" "0,1"
|
|
bitfld.long 0x00 20. " GMB20 ,Group Modifier Bit 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1"
|
|
bitfld.long 0x00 18. " GMB18 ,Group Modifier Bit 18" "0,1"
|
|
bitfld.long 0x00 17. " GMB17 ,Group Modifier Bit 17" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1"
|
|
bitfld.long 0x00 15. " GMB15 ,Group Modifier Bit 15" "0,1"
|
|
bitfld.long 0x00 14. " GMB14 ,Group Modifier Bit 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1"
|
|
bitfld.long 0x00 12. " GMB12 ,Group Modifier Bit 12" "0,1"
|
|
bitfld.long 0x00 11. " GMB11 ,Group Modifier Bit 11" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1"
|
|
bitfld.long 0x00 9. " GMB9 ,Group Modifier Bit 9" "0,1"
|
|
bitfld.long 0x00 8. " GMB8 ,Group Modifier Bit 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GMB7 ,Group Modifier Bit 7" "0,1"
|
|
bitfld.long 0x00 6. " GMB6 ,Group Modifier Bit 6" "0,1"
|
|
bitfld.long 0x00 5. " GMB5 ,Group Modifier Bit 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GMB4 ,Group Modifier Bit 4" "0,1"
|
|
bitfld.long 0x00 3. " GMB3 ,Group Modifier Bit 3" "0,1"
|
|
bitfld.long 0x00 2. " GMB2 ,Group Modifier Bit 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GMB1 ,Group Modifier Bit 1" "0,1"
|
|
bitfld.long 0x00 0. " GMB0 ,Group Modifier Bit 0" "0,1"
|
|
textline " "
|
|
else
|
|
hgroup.long 0x10D00++0x03
|
|
hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00))
|
|
group.long 0x10E00++0x03
|
|
line.long 0x00 "GICR_NSACR,Non-secure Access Control Register"
|
|
bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..."
|
|
bitfld.long 0x00 28.--29. " NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..."
|
|
bitfld.long 0x00 26.--27. " NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..."
|
|
bitfld.long 0x00 22.--23. " NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..."
|
|
bitfld.long 0x00 20.--21. " NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " NS_ACCESS9 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..."
|
|
bitfld.long 0x00 16.--17. " NS_ACCESS8 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..."
|
|
bitfld.long 0x00 14.--15. " NS_ACCESS7 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NS_ACCESS6 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..."
|
|
bitfld.long 0x00 10.--11. " NS_ACCESS5 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..."
|
|
bitfld.long 0x00 8.--9. " NS_ACCESS4 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " NS_ACCESS3 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..."
|
|
bitfld.long 0x00 4.--5. " NS_ACCESS2 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..."
|
|
bitfld.long 0x00 2.--3. " NS_ACCESS1 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NS_ACCESS0 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..."
|
|
textline " "
|
|
else
|
|
hgroup.long 0x10E00++0x03
|
|
hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
rgroup.long 0x1C000++0x03
|
|
line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register"
|
|
bitfld.long 0x00 31. " CPU_AS ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High"
|
|
bitfld.long 0x00 2. " ENABLEGRP1_S ,EnableGrp1 Secure" "0,1"
|
|
bitfld.long 0x00 1. " ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1"
|
|
rgroup.long 0x1C080++0x03
|
|
line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " PPI31S ,Actual status of the PPI31 input signal" "Low,High"
|
|
bitfld.long 0x00 30. " PPI30S ,Actual status of the PPI30 input signal" "Low,High"
|
|
bitfld.long 0x00 29. " PPI29S ,Actual status of the PPI29 input signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PPI28S ,Actual status of the PPI28 input signal" "Low,High"
|
|
bitfld.long 0x00 27. " PPI27S ,Actual status of the PPI27 input signal" "Low,High"
|
|
bitfld.long 0x00 26. " PPI26S ,Actual status of the PPI26 input signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PPI25S ,Actual status of the PPI25 input signal" "Low,High"
|
|
bitfld.long 0x00 24. " PPI24S ,Actual status of the PPI24 input signal" "Low,High"
|
|
bitfld.long 0x00 23. " PPI23S ,Actual status of the PPI23 input signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PPI22S ,Actual status of the PPI22 input signal" "Low,High"
|
|
bitfld.long 0x00 21. " PPI21S ,Actual status of the PPI21 input signal" "Low,High"
|
|
bitfld.long 0x00 20. " PPI20S ,Actual status of the PPI20 input signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPI19S ,Actual status of the PPI19 input signal" "Low,High"
|
|
bitfld.long 0x00 18. " PPI18S ,Actual status of the PPI18 input signal" "Low,High"
|
|
bitfld.long 0x00 17. " PPI17S ,Actual status of the PPI17 input signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPI16S ,Actual status of the PPI16 input signal" "Low,High"
|
|
tree.end
|
|
width 12.
|
|
tree "Peripheral/Component ID Registers"
|
|
rgroup.long 0xFFE0++0x03
|
|
line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]"
|
|
rgroup.long 0xFFE4++0x03
|
|
line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register"
|
|
bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFFE8++0x03
|
|
line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register"
|
|
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
|
|
bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
|
|
bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xFFEC++0x03
|
|
line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register"
|
|
bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFFD0++0x03
|
|
line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register"
|
|
bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long 0xFFD4++0x03
|
|
hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register"
|
|
hgroup.long 0xFFD8++0x03
|
|
hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register"
|
|
hgroup.long 0xFFDC++0x03
|
|
hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register"
|
|
rgroup.long 0xFFF0++0x03
|
|
line.long 0x00 "GICR_CIDR0,Component ID0 Register"
|
|
hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.long 0xFFF4++0x03
|
|
line.long 0x00 "GICR_CIDR1,Component ID1 Register"
|
|
hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.long 0xFFF8++0x03
|
|
line.long 0x00 "GICR_CIDR2,Component ID2 Register"
|
|
hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.long 0xFFFC++0x03
|
|
line.long 0x00 "GICR_CIDR3,Component ID3 Register"
|
|
hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
sif COMP.AVAILABLE("GICC")
|
|
base COMP.BASE("GICC",-1.)
|
|
width 14.
|
|
tree "CPU Interface"
|
|
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.)))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
|
|
bitfld.long 0x00 10. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
|
|
bitfld.long 0x00 9. " EOIMODES ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
|
|
bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
|
|
bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
|
|
bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both"
|
|
bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ"
|
|
bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
|
|
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
|
|
bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
|
|
bitfld.long 0x00 6. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
|
|
bitfld.long 0x00 5. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
|
|
bitfld.long 0x00 9. " EOIMODE ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
|
|
bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
|
|
bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
|
|
bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
|
|
bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ"
|
|
bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GICC_BPR,Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7"
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register"
|
|
in
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "GICC_EOIR,End Of Interrupt Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "GICC_RPR,Running Priority Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register"
|
|
in
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "GICC_STATUSR,CPU Interface Status Register"
|
|
bitfld.long 0x00 4. " ASV ,Attempted security violation" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " WROD ,Write to an RO location" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " RWOD ,Read of a WO location" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRD ,Write to a reserved location" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " RRD ,Read of a reserved location" "Not detected,Detected"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "GICC_APR0,Active Priorities Register 0"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GICC_APR1,Active Priorities Register 1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "GICC_APR2,Active Priorities Register 2"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "GICC_APR3,Active Priorities Register 3"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "GICC_IIDR,CPU Interface Identification Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID"
|
|
bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..."
|
|
bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
wgroup.long 0x1000++0x03
|
|
line.long 0x00 "GICC_DIR,Deactivate Interrupt Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID"
|
|
tree.end
|
|
width 0x0b
|
|
endif
|
|
sif COMP.AVAILABLE("GICH")
|
|
base COMP.BASE("GICH",-1.)
|
|
width 13.
|
|
tree "Virtual CPU Control Interface"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GICH_HCR,Hypervisor Control Register"
|
|
bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Virtual CPU interface Enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "GICH_VTR,Virtual Type Register"
|
|
bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 23.--25. " IDBITS ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " A3V ,Affinity 3 valid" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--4. " LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GICH_VMCR,Virtual Machine Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VPMR ,Virtual priority mask"
|
|
bitfld.long 0x00 21.--23. " VBPR0 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " VBPR1 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. " VEOIM ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VCBPR ,Virtual Common Binary Point Register" "ABPR,BPR"
|
|
bitfld.long 0x00 3. " VFIQEN ,Virtual FIQ enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VACKCTL ,Virtual AckCtl" "INTID=1022,INTID=corresponding"
|
|
bitfld.long 0x00 1. " VENG1 ,Virtual interrupt enable for group 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VENG0 ,Virtual interrupt enable for group 0" "Disabled,Enabled"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register"
|
|
bitfld.long 0x00 7. " VGRP1D ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 6. " VGRP1E ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 5. " VGRP0D ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 4. " VGRP0E ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 1. " U ,Underflow maintenance interrupt assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " EOI ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "GICH_EISR0,End of Interrupt Status Register"
|
|
bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STATUS9 ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " STATUS8 ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " STATUS7 ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STATUS6 ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " STATUS5 ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " STATUS4 ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "GICH_ELRSR0,Empty List register Status Register"
|
|
bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STATUS9 ,Status bit for List register 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " STATUS8 ,Status bit for List register 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " STATUS7 ,Status bit for List register 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " STATUS6 ,Status bit for List register 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " STATUS5 ,Status bit for List register 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " STATUS4 ,Status bit for List register 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STATUS3 ,Status bit for List register 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " STATUS2 ,Status bit for List register 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " STATUS1 ,Status bit for List register 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STATUS0 ,Status bit for List register 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "GICH_APR0,Active Priorities Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1"
|
|
bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "GICH_APR1,Active Priorities Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1"
|
|
bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "GICH_APR2,Active Priorities Register 2"
|
|
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1"
|
|
bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "GICH_APR3,Active Priorities Register 3"
|
|
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1"
|
|
bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1"
|
|
textline " "
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "GICH_LR0,List Register 0"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "GICH_LR1,List Register 1"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "GICH_LR2,List Register 2"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "GICH_LR3,List Register 3"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "GICH_LR4,List Register 4"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "GICH_LR5,List Register 5"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "GICH_LR6,List Register 6"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "GICH_LR7,List Register 7"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "GICH_LR8,List Register 8"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "GICH_LR9,List Register 9"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "GICH_LR10,List Register 10"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "GICH_LR11,List Register 11"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "GICH_LR12,List Register 12"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "GICH_LR13,List Register 13"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "GICH_LR14,List Register 14"
|
|
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID"
|
|
tree.end
|
|
width 0x0b
|
|
endif
|
|
sif COMP.AVAILABLE("GICV")
|
|
base COMP.BASE("GICV",-1.)
|
|
width 14.
|
|
tree "Virtual CPU Interface"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GICV_CTLR,VM Control Register"
|
|
bitfld.long 0x00 9. " EOIMODE ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
|
|
bitfld.long 0x00 4. " CBPR ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both"
|
|
bitfld.long 0x00 3. " FIQEN ,FIQ Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GICV_PMR,VM Priority Mask Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for the virtual CPU interface"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GICV_BPR,VM Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register"
|
|
hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register"
|
|
hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "GICV_RPR,VM Running Priority Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register"
|
|
hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register"
|
|
hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register"
|
|
hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register"
|
|
hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID"
|
|
textline ""
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "GICV_APR0,VM Active Priority Register 0"
|
|
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1"
|
|
bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "GICV_APR1,VM Active Priority Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1"
|
|
bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "GICV_APR2,VM Active Priority Register 2"
|
|
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1"
|
|
bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "GICV_APR3,VM Active Priority Register 3"
|
|
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
|
|
bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1"
|
|
bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1"
|
|
bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
|
|
bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1"
|
|
bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1"
|
|
bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
|
|
bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1"
|
|
bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1"
|
|
bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
|
|
bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1"
|
|
bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1"
|
|
bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
|
|
bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1"
|
|
bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1"
|
|
bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
|
|
bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1"
|
|
bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1"
|
|
bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1"
|
|
bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1"
|
|
bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1"
|
|
bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1"
|
|
bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1"
|
|
bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1"
|
|
bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1"
|
|
textline " "
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID"
|
|
bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" ",,,GICv3,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
wgroup.long 0x1000++0x03
|
|
line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register"
|
|
hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID"
|
|
tree.end
|
|
width 0x0b
|
|
endif
|
|
width 0x0B
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree.end
|
|
elif (CORENAME()=="CORTEXM4F")
|
|
tree.close "Core Registers (Cortex-M4F)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
|
|
bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
|
|
bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
|
|
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
|
|
rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
|
|
bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
|
|
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
|
|
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
|
|
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,ARMv7-M"
|
|
newline
|
|
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC24=Cortex-M4"
|
|
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
|
|
group.long 0xD04++0x23
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
|
|
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
|
|
bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
|
|
line.long 0x04 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
|
|
rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
|
|
bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
|
|
bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
|
|
bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
|
|
line.long 0x0C "SCR,System Control Register"
|
|
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
line.long 0x10 "CCR,Configuration Control Register"
|
|
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
|
|
bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
|
|
bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
|
|
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
|
|
textline " "
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
|
|
line.long 0x20 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
|
|
bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
|
|
bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
|
|
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
|
|
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
|
|
group.byte 0xD28++0x1
|
|
line.byte 0x00 "MMFSR,MemManage Status Register"
|
|
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
|
|
line.byte 0x01 "BFSR,Bus Fault Status Register"
|
|
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
|
|
group.word 0xD2A++0x1
|
|
line.word 0x00 "USAFAULT,Usage Fault Status Register"
|
|
bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
|
|
bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
|
|
bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
|
|
bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
|
|
bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
|
|
group.long 0xD2C++0x07
|
|
line.long 0x00 "HFSR,Hard Fault Status Register"
|
|
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
|
|
line.long 0x04 "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
|
|
bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
|
|
bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
|
|
group.long 0xD34++0x0B
|
|
line.long 0x00 "MMFAR,MemManage Fault Address Register"
|
|
line.long 0x04 "BFAR,BusFault Address Register"
|
|
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
|
|
width 10.
|
|
tree "Feature Registers"
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
autoindent.on center tree
|
|
tree "ADC"
|
|
base ad:0x5A880000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
bitfld.long 0x00 10. "CALOFSI,Calibration Offset Function Implemented" "0: Offset calibration and offset trimming not..,1: Offset calibration and offset trimming.."
|
|
bitfld.long 0x00 9. "IADCKI,Internal ADC Clock implemented" "0: Internal clock source not implemented,1: Internal clock source (and CFG[ADCKEN]).."
|
|
newline
|
|
bitfld.long 0x00 8. "VR1RNGI,Voltage Reference 1 Range Control Bit Implemented" "0: Range control not required,1: Range control required"
|
|
bitfld.long 0x00 4.--6. "CSW,Channel Scale Width" "0: Channel scaling not supported,1: Channel scaling supported,?,?,?,?,6: Channel scaling supported,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "MVI,Multi Vref Implemented" "0: Single voltage reference high (VREFH) input..,1: Multiple voltage reference high (VREFH).."
|
|
bitfld.long 0x00 1. "DIFFEN,Differential Supported" "0: Differential operation not supported,1: Differential operation supported"
|
|
newline
|
|
bitfld.long 0x00 0. "RES,Resolution" "0: Up to 13-bit differential/12-bit single ended..,1: Up to 16-bit differential/15-bit single ended.."
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CMD_NUM,Command Buffer Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CV_NUM,Compare Value Number"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "FIFOSIZE,Result FIFO Depth"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TRIG_NUM,Trigger Number"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTRL,ADC Control Register"
|
|
bitfld.long 0x00 8. "RSTFIFO,Reset FIFO" "0: No effect,1: FIFO is reset"
|
|
bitfld.long 0x00 2. "DOZEN,Doze Enable" "0: ADC is enabled in Doze mode,1: ADC is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: ADC logic is not reset,1: ADC logic is reset"
|
|
bitfld.long 0x00 0. "ADCEN,ADC Enable" "0: ADC is disabled,1: ADC is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,ADC Status Register"
|
|
rbitfld.long 0x00 24.--27. "CMDACT,Command Active" "0: No command is currently in progress,1: Command 1 currently being executed,2: Command 2 currently being executed,3: Associated command number is currently being..,4: Associated command number is currently being..,5: Associated command number is currently being..,6: Associated command number is currently being..,7: Associated command number is currently being..,8: Associated command number is currently being..,9: Associated command number is currently being..,?..."
|
|
rbitfld.long 0x00 16.--18. "TRGACT,Trigger Active" "0: Command (sequence) associated with Trigger 0..,1: Command (sequence) associated with Trigger 1..,2: Command (sequence) associated with Trigger 2..,3: Command (sequence) from the associated..,4: Command (sequence) from the associated..,5: Command (sequence) from the associated..,6: Command (sequence) from the associated..,7: Command (sequence) from the associated.."
|
|
newline
|
|
rbitfld.long 0x00 8. "ADC_ACTIVE,ADC Active" "0: The ADC is IDLE,1: The ADC is processing a conversion running.."
|
|
eventfld.long 0x00 1. "FOF,Result FIFO Overflow Flag" "0: No result FIFO overflow has occurred since..,1: At least one result FIFO overflow has.."
|
|
newline
|
|
rbitfld.long 0x00 0. "RDY,Result FIFO Ready Flag" "0: Result FIFO data level not above watermark..,1: Result FIFO holding data above watermark level"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x00 1. "FOFIE,Result FIFO Overflow Interrupt Enable" "0: FIFO overflow interrupts are not enabled,1: FIFO overflow interrupts are enabled"
|
|
bitfld.long 0x00 0. "FWMIE,FIFO Watermark Interrupt Enable" "0: FIFO watermark interrupts are not enabled,1: FIFO watermark interrupts are enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DE,DMA Enable Register"
|
|
bitfld.long 0x00 0. "FWMDE,FIFO Watermark DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFG,ADC Configuration Register"
|
|
bitfld.long 0x00 28. "PWREN,ADC Analog Pre-Enable" "0: ADC analog circuits are only enabled while..,1: ADC analog circuits are pre-enabled and ready.."
|
|
hexmask.long.byte 0x00 16.--23. 1. "PUDLY,Power Up Delay"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "REFSEL,Voltage Reference Selection" "0: (Default) Option 1 setting,1: Option 2 setting,2: Option 3 setting,?..."
|
|
bitfld.long 0x00 4.--5. "PWRSEL,Power Configuration Select" "0: Level 1 (Lowest power setting),1: PWRSEL_1,2: PWRSEL_2,3: Level 4 (Highest power setting)"
|
|
newline
|
|
bitfld.long 0x00 0. "TPRICTRL,ADC trigger priority control" "0: If a higher priority trigger is detected..,1: If a higher priority trigger is received.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PAUSE,ADC Pause Register"
|
|
bitfld.long 0x00 31. "PAUSEEN,PAUSE Option Enable" "0: Pause operation disabled,1: Pause operation enabled"
|
|
hexmask.long.word 0x00 0.--8. 1. "PAUSEDLY,Pause Delay"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FCTRL,ADC FIFO Control Register"
|
|
bitfld.long 0x00 16.--19. "FWMARK,Watermark level selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 0.--4. "FCOUNT,Result FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SWTRIG,Software Trigger Register"
|
|
bitfld.long 0x00 7. "SWT7,Software trigger 7 event" "0: No trigger 7 event generated,1: Trigger 7 event generated"
|
|
bitfld.long 0x00 6. "SWT6,Software trigger 6 event" "0: No trigger 6 event generated,1: Trigger 6 event generated"
|
|
newline
|
|
bitfld.long 0x00 5. "SWT5,Software trigger 5 event" "0: No trigger 5 event generated,1: Trigger 5 event generated"
|
|
bitfld.long 0x00 4. "SWT4,Software trigger 4 event" "0: No trigger 4 event generated,1: Trigger 4 event generated"
|
|
newline
|
|
bitfld.long 0x00 3. "SWT3,Software trigger 3 event" "0: No trigger 3 event generated,1: Trigger 3 event generated"
|
|
bitfld.long 0x00 2. "SWT2,Software trigger 2 event" "0: No trigger 2 event generated,1: Trigger 2 event generated"
|
|
newline
|
|
bitfld.long 0x00 1. "SWT1,Software trigger 1 event" "0: No trigger 1 event generated,1: Trigger 1 event generated"
|
|
bitfld.long 0x00 0. "SWT0,Software trigger 0 event" "0: No trigger 0 event generated,1: Trigger 0 event generated"
|
|
repeat 8. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0xC0)++0x03
|
|
line.long 0x00 "TCTRL[$1],Trigger Control Register $1"
|
|
bitfld.long 0x00 24.--27. "TCMD,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,?,?,?,?,?,15: CMD15 is executed"
|
|
bitfld.long 0x00 16.--19. "TDLY,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TPRI,Trigger priority setting" "0: Set to highest priority Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to lowest priority Level 8"
|
|
bitfld.long 0x00 0. "HTEN,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
|
|
repeat.end
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CMDL1,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "CMDH1,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CMDL2,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "CMDH2,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CMDL3,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CMDH3,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CMDL4,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CMDH4,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CMDL5,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CMDH5,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CMDL6,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CMDH6,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CMDL7,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CMDH7,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CMDL8,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "CMDH8,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CMDL9,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CMDH9,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "CMDL10,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "CMDH10,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CMDL11,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "CMDH11,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "CMDL12,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CMDH12,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "CMDL13,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CMDH13,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CMDL14,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "CMDH14,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CMDL15,ADC Command Low Buffer Register"
|
|
bitfld.long 0x00 13. "CSCALE,Channel Scale" "0: Scale selected analog channel (Factor of 30/64),1: (Default) Full scale (Factor of 1)"
|
|
bitfld.long 0x00 6. "DIFF,Differential Mode Enable" "0: Single-ended mode,1: Differential mode"
|
|
newline
|
|
bitfld.long 0x00 5. "ABSEL,A-side vs" "0: When DIFF=0b0 the associated A-side channel..,1: When DIFF=0b0 the associated B-side channel.."
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CMDH15,ADC Command High Buffer Register"
|
|
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
|
|
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
|
|
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
|
|
newline
|
|
bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
|
|
repeat 4. (strings "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "CV$1,Compare Value Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "CVH,Compare Value High"
|
|
hexmask.long.word 0x00 0.--15. 1. "CVL,Compare Value Low"
|
|
repeat.end
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "RESFIFO,ADC Data Result FIFO Register"
|
|
bitfld.long 0x00 31. "VALID,FIFO entry is valid" "0: FIFO is empty,1: FIFO record read from RESFIFO is valid"
|
|
bitfld.long 0x00 24.--27. "CMDSRC,Command Buffer Source" "0: Not a valid value CMDSRC value for a dataword..,1: CMD1 buffer used as control settings for this..,2: Corresponding command buffer used as control..,3: Corresponding command buffer used as control..,4: Corresponding command buffer used as control..,5: Corresponding command buffer used as control..,6: Corresponding command buffer used as control..,7: Corresponding command buffer used as control..,8: Corresponding command buffer used as control..,9: Corresponding command buffer used as control..,?,?,?,?,?,15: CMD15 buffer used as control settings for.."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "LOOPCNT,Loop count value" "0: Result is from initial conversion in command,1: Result is from second conversion in command,2: Result is from LOOPCNT+1 conversion in command,3: Result is from LOOPCNT+1 conversion in command,4: Result is from LOOPCNT+1 conversion in command,5: Result is from LOOPCNT+1 conversion in command,6: Result is from LOOPCNT+1 conversion in command,7: Result is from LOOPCNT+1 conversion in command,8: Result is from LOOPCNT+1 conversion in command,9: Result is from LOOPCNT+1 conversion in command,?,?,?,?,?,15: Result is from 16th conversion in command"
|
|
bitfld.long 0x00 16.--18. "TSRC,Trigger Source" "0: Trigger source 0 initiated this conversion,1: Trigger source 1 initiated this conversion,2: Corresponding trigger source initiated this..,3: Corresponding trigger source initiated this..,4: Corresponding trigger source initiated this..,5: Corresponding trigger source initiated this..,6: Corresponding trigger source initiated this..,7: Trigger source 7 initiated this conversion"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "D,Data result"
|
|
tree.end
|
|
sif cpuis("IMX8D?L-CM4")
|
|
tree "AHB_LMEM64_REV2 (LMEM64)"
|
|
base ad:0xE0082000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCCCR,PC bus Cache control register"
|
|
bitfld.long 0x00 31. "GO,Initiate Cache Command" "0: Write: no effect,1: Write: initiate command indicated by bits 27-24"
|
|
bitfld.long 0x00 27. "PUSHW1,Push Way 1" "0: no_operation,1: When setting the GO bit push all modified.."
|
|
newline
|
|
bitfld.long 0x00 26. "INVW1,Invalidate Way 1" "0: no_operation,1: When setting the GO bit invalidate all lines.."
|
|
bitfld.long 0x00 25. "PUSHW0,Push Way 0" "0: no_operation,1: When setting the GO bit push all modified.."
|
|
newline
|
|
bitfld.long 0x00 24. "INVW0,Invalidate Way 0" "0: no_operation,1: When setting the GO bit invalidate all lines.."
|
|
bitfld.long 0x00 3. "PCCR3,Forces no allocation on cache misses" "0: Allocation on cache misses,1: Forces no allocation on cache misses (must.."
|
|
newline
|
|
bitfld.long 0x00 2. "PCCR2,Forces all cacheable spaces to write through" "0: Does NOT force all cacheable spaces to write..,1: Forces all cacheable spaces to write through"
|
|
bitfld.long 0x00 1. "ENWRBUF,Enable Write Buffer" "0: Write buffer disabled,1: Write buffer enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ENCACHE,Cache enable" "0: Cache disabled,1: Cache enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCCLCR,PC bus Cache line control register"
|
|
bitfld.long 0x00 27. "LACC,Line access type" "0: read,1: write"
|
|
bitfld.long 0x00 26. "LADSEL,Line Address Select" "0: Cache address,1: Physical address"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "LCMD,Line Command" "0: Search and read or write,1: invalidate,2: push,3: clear"
|
|
bitfld.long 0x00 22. "LCWAY,Line Command Way" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "LCIMB,Line Command Initial Modified Bit" "0,1"
|
|
bitfld.long 0x00 20. "LCIVB,Line Command Initial Valid Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "TDSEL,Tag/Data Select" "0: data,1: tag"
|
|
bitfld.long 0x00 14. "WSEL,Way select" "0: Way 0,1: Way 1"
|
|
newline
|
|
hexmask.long.word 0x00 2.--13. 1. "CACHEADDR,Cache address"
|
|
bitfld.long 0x00 0. "LGO,Initiate Cache Line Command" "0: Write: no effect,1: Write: initiate line command indicated by.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCCSAR,PC bus Cache search address register"
|
|
hexmask.long 0x00 1.--31. 1. "PHYADDR,Physical Address"
|
|
bitfld.long 0x00 0. "LGO,Initiate Cache Line Command" "0: Write: no effect,1: Write: initiate line command indicated by.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCCCVR,PC bus Cache read/write value register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Cache read/write Data"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "PSCCR,PS bus Cache control register"
|
|
bitfld.long 0x00 31. "GO,Initiate Cache Command" "0: Write: no effect,1: Write: initiate command indicated by bits 27-24"
|
|
bitfld.long 0x00 27. "PUSHW1,Push Way 1" "0: no_operation,1: When setting the GO bit push all modified.."
|
|
newline
|
|
bitfld.long 0x00 26. "INVW1,Invalidate Way 1" "0: no_operation,1: When setting the GO bit invalidate all lines.."
|
|
bitfld.long 0x00 25. "PUSHW0,Push Way 0" "0: no_operation,1: When setting the GO bit push all modified.."
|
|
newline
|
|
bitfld.long 0x00 24. "INVW0,Invalidate Way 0" "0: no_operation,1: When setting the GO bit invalidate all lines.."
|
|
bitfld.long 0x00 3. "PSCR3,Forces no allocation on cache misses" "0: Allocation on cache misses,1: Forces no allocation on cache misses (must.."
|
|
newline
|
|
bitfld.long 0x00 2. "PSCR2,Forces all cacheable spaces to write through" "0: Does NOT force all cacheable spaces to write..,1: Forces all cacheable spaces to write through"
|
|
bitfld.long 0x00 1. "ENWRBUF,Enable Write Buffer" "0: Write buffer disabled,1: Write buffer enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ENCACHE,Cache enable" "0: Cache disabled,1: Cache enabled"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "PSCLCR,PS bus Cache line control register"
|
|
bitfld.long 0x00 27. "LACC,Line access type" "0: read,1: write"
|
|
bitfld.long 0x00 26. "LADSEL,Line Address Select" "0: Cache address,1: Physical address"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "LCMD,Line Command" "0: Search and read or write,1: invalidate,2: push,3: clear"
|
|
bitfld.long 0x00 22. "LCWAY,Line Command Way" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "LCIMB,Line Command Initial Modified Bit" "0,1"
|
|
bitfld.long 0x00 20. "LCIVB,Line Command Initial Valid Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "TDSEL,Tag/Data Select" "0: data,1: tag"
|
|
bitfld.long 0x00 14. "WSEL,Way select" "0: Way 0,1: Way 1"
|
|
newline
|
|
hexmask.long.word 0x00 2.--13. 1. "CACHEADDR,Cache address"
|
|
bitfld.long 0x00 0. "LGO,Initiate Cache Line Command" "0: Write: no effect,1: Write: initiate line command indicated by.."
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "PSCSAR,PS bus Cache search address register"
|
|
hexmask.long 0x00 1.--31. 1. "PHYADDR,Physical Address"
|
|
bitfld.long 0x00 0. "LGO,Initiate Cache Line Command" "0: Write: no effect,1: Write: initiate line command indicated by.."
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "PSCCVR,PS bus Cache read/write value register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Cache read/write Data"
|
|
tree.end
|
|
endif
|
|
tree "APBHDMA (APBH)"
|
|
base ad:0x5B810000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL0,AHB to APBH Bridge Control and Status Register 0"
|
|
bitfld.long 0x00 31. "SFTRST,SFTRST" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,CLKGATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "AHB_BURST8_EN,AHB_BURST8_EN" "0,1"
|
|
bitfld.long 0x00 28. "APB_BURST_EN,APB_BURST_EN" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "CLKGATE_CHANNEL,CLKGATE_CHANNEL"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL0_SET,AHB to APBH Bridge Control and Status Register 0"
|
|
bitfld.long 0x00 31. "SFTRST,SFTRST" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,CLKGATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "AHB_BURST8_EN,AHB_BURST8_EN" "0,1"
|
|
bitfld.long 0x00 28. "APB_BURST_EN,APB_BURST_EN" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "CLKGATE_CHANNEL,CLKGATE_CHANNEL"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL0_CLR,AHB to APBH Bridge Control and Status Register 0"
|
|
eventfld.long 0x00 31. "SFTRST,SFTRST" "0,1"
|
|
eventfld.long 0x00 30. "CLKGATE,CLKGATE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 29. "AHB_BURST8_EN,AHB_BURST8_EN" "0,1"
|
|
eventfld.long 0x00 28. "APB_BURST_EN,APB_BURST_EN" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "CLKGATE_CHANNEL,CLKGATE_CHANNEL"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTRL0_TOG,AHB to APBH Bridge Control and Status Register 0"
|
|
bitfld.long 0x00 31. "SFTRST,SFTRST" "0,1"
|
|
bitfld.long 0x00 30. "CLKGATE,CLKGATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "AHB_BURST8_EN,AHB_BURST8_EN" "0,1"
|
|
bitfld.long 0x00 28. "APB_BURST_EN,APB_BURST_EN" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "CLKGATE_CHANNEL,CLKGATE_CHANNEL"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTRL1,AHB to APBH Bridge Control and Status Register 1"
|
|
bitfld.long 0x00 31. "CH15_CMDCMPLT_IRQ_EN,CH15_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 30. "CH14_CMDCMPLT_IRQ_EN,CH14_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "CH13_CMDCMPLT_IRQ_EN,CH13_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 28. "CH12_CMDCMPLT_IRQ_EN,CH12_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "CH11_CMDCMPLT_IRQ_EN,CH11_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 26. "CH10_CMDCMPLT_IRQ_EN,CH10_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "CH9_CMDCMPLT_IRQ_EN,CH9_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 24. "CH8_CMDCMPLT_IRQ_EN,CH8_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "CH7_CMDCMPLT_IRQ_EN,CH7_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 22. "CH6_CMDCMPLT_IRQ_EN,CH6_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "CH5_CMDCMPLT_IRQ_EN,CH5_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 20. "CH4_CMDCMPLT_IRQ_EN,CH4_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CH3_CMDCMPLT_IRQ_EN,CH3_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 18. "CH2_CMDCMPLT_IRQ_EN,CH2_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CH1_CMDCMPLT_IRQ_EN,CH1_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 16. "CH0_CMDCMPLT_IRQ_EN,CH0_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "CH15_CMDCMPLT_IRQ,CH15_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 14. "CH14_CMDCMPLT_IRQ,CH14_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CH13_CMDCMPLT_IRQ,CH13_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 12. "CH12_CMDCMPLT_IRQ,CH12_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CH11_CMDCMPLT_IRQ,CH11_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 10. "CH10_CMDCMPLT_IRQ,CH10_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH9_CMDCMPLT_IRQ,CH9_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 8. "CH8_CMDCMPLT_IRQ,CH8_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CH7_CMDCMPLT_IRQ,CH7_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 6. "CH6_CMDCMPLT_IRQ,CH6_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5_CMDCMPLT_IRQ,CH5_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 4. "CH4_CMDCMPLT_IRQ,CH4_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3_CMDCMPLT_IRQ,CH3_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 2. "CH2_CMDCMPLT_IRQ,CH2_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1_CMDCMPLT_IRQ,CH1_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 0. "CH0_CMDCMPLT_IRQ,CH0_CMDCMPLT_IRQ" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTRL1_SET,AHB to APBH Bridge Control and Status Register 1"
|
|
bitfld.long 0x00 31. "CH15_CMDCMPLT_IRQ_EN,CH15_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 30. "CH14_CMDCMPLT_IRQ_EN,CH14_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "CH13_CMDCMPLT_IRQ_EN,CH13_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 28. "CH12_CMDCMPLT_IRQ_EN,CH12_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "CH11_CMDCMPLT_IRQ_EN,CH11_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 26. "CH10_CMDCMPLT_IRQ_EN,CH10_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "CH9_CMDCMPLT_IRQ_EN,CH9_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 24. "CH8_CMDCMPLT_IRQ_EN,CH8_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "CH7_CMDCMPLT_IRQ_EN,CH7_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 22. "CH6_CMDCMPLT_IRQ_EN,CH6_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "CH5_CMDCMPLT_IRQ_EN,CH5_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 20. "CH4_CMDCMPLT_IRQ_EN,CH4_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CH3_CMDCMPLT_IRQ_EN,CH3_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 18. "CH2_CMDCMPLT_IRQ_EN,CH2_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CH1_CMDCMPLT_IRQ_EN,CH1_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 16. "CH0_CMDCMPLT_IRQ_EN,CH0_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "CH15_CMDCMPLT_IRQ,CH15_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 14. "CH14_CMDCMPLT_IRQ,CH14_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CH13_CMDCMPLT_IRQ,CH13_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 12. "CH12_CMDCMPLT_IRQ,CH12_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CH11_CMDCMPLT_IRQ,CH11_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 10. "CH10_CMDCMPLT_IRQ,CH10_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH9_CMDCMPLT_IRQ,CH9_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 8. "CH8_CMDCMPLT_IRQ,CH8_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CH7_CMDCMPLT_IRQ,CH7_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 6. "CH6_CMDCMPLT_IRQ,CH6_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5_CMDCMPLT_IRQ,CH5_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 4. "CH4_CMDCMPLT_IRQ,CH4_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3_CMDCMPLT_IRQ,CH3_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 2. "CH2_CMDCMPLT_IRQ,CH2_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1_CMDCMPLT_IRQ,CH1_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 0. "CH0_CMDCMPLT_IRQ,CH0_CMDCMPLT_IRQ" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL1_CLR,AHB to APBH Bridge Control and Status Register 1"
|
|
eventfld.long 0x00 31. "CH15_CMDCMPLT_IRQ_EN,CH15_CMDCMPLT_IRQ_EN" "0,1"
|
|
eventfld.long 0x00 30. "CH14_CMDCMPLT_IRQ_EN,CH14_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 29. "CH13_CMDCMPLT_IRQ_EN,CH13_CMDCMPLT_IRQ_EN" "0,1"
|
|
eventfld.long 0x00 28. "CH12_CMDCMPLT_IRQ_EN,CH12_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 27. "CH11_CMDCMPLT_IRQ_EN,CH11_CMDCMPLT_IRQ_EN" "0,1"
|
|
eventfld.long 0x00 26. "CH10_CMDCMPLT_IRQ_EN,CH10_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 25. "CH9_CMDCMPLT_IRQ_EN,CH9_CMDCMPLT_IRQ_EN" "0,1"
|
|
eventfld.long 0x00 24. "CH8_CMDCMPLT_IRQ_EN,CH8_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 23. "CH7_CMDCMPLT_IRQ_EN,CH7_CMDCMPLT_IRQ_EN" "0,1"
|
|
eventfld.long 0x00 22. "CH6_CMDCMPLT_IRQ_EN,CH6_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 21. "CH5_CMDCMPLT_IRQ_EN,CH5_CMDCMPLT_IRQ_EN" "0,1"
|
|
eventfld.long 0x00 20. "CH4_CMDCMPLT_IRQ_EN,CH4_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 19. "CH3_CMDCMPLT_IRQ_EN,CH3_CMDCMPLT_IRQ_EN" "0,1"
|
|
eventfld.long 0x00 18. "CH2_CMDCMPLT_IRQ_EN,CH2_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 17. "CH1_CMDCMPLT_IRQ_EN,CH1_CMDCMPLT_IRQ_EN" "0,1"
|
|
eventfld.long 0x00 16. "CH0_CMDCMPLT_IRQ_EN,CH0_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 15. "CH15_CMDCMPLT_IRQ,CH15_CMDCMPLT_IRQ" "0,1"
|
|
eventfld.long 0x00 14. "CH14_CMDCMPLT_IRQ,CH14_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 13. "CH13_CMDCMPLT_IRQ,CH13_CMDCMPLT_IRQ" "0,1"
|
|
eventfld.long 0x00 12. "CH12_CMDCMPLT_IRQ,CH12_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 11. "CH11_CMDCMPLT_IRQ,CH11_CMDCMPLT_IRQ" "0,1"
|
|
eventfld.long 0x00 10. "CH10_CMDCMPLT_IRQ,CH10_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 9. "CH9_CMDCMPLT_IRQ,CH9_CMDCMPLT_IRQ" "0,1"
|
|
eventfld.long 0x00 8. "CH8_CMDCMPLT_IRQ,CH8_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 7. "CH7_CMDCMPLT_IRQ,CH7_CMDCMPLT_IRQ" "0,1"
|
|
eventfld.long 0x00 6. "CH6_CMDCMPLT_IRQ,CH6_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 5. "CH5_CMDCMPLT_IRQ,CH5_CMDCMPLT_IRQ" "0,1"
|
|
eventfld.long 0x00 4. "CH4_CMDCMPLT_IRQ,CH4_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 3. "CH3_CMDCMPLT_IRQ,CH3_CMDCMPLT_IRQ" "0,1"
|
|
eventfld.long 0x00 2. "CH2_CMDCMPLT_IRQ,CH2_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 1. "CH1_CMDCMPLT_IRQ,CH1_CMDCMPLT_IRQ" "0,1"
|
|
eventfld.long 0x00 0. "CH0_CMDCMPLT_IRQ,CH0_CMDCMPLT_IRQ" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CTRL1_TOG,AHB to APBH Bridge Control and Status Register 1"
|
|
bitfld.long 0x00 31. "CH15_CMDCMPLT_IRQ_EN,CH15_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 30. "CH14_CMDCMPLT_IRQ_EN,CH14_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "CH13_CMDCMPLT_IRQ_EN,CH13_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 28. "CH12_CMDCMPLT_IRQ_EN,CH12_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "CH11_CMDCMPLT_IRQ_EN,CH11_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 26. "CH10_CMDCMPLT_IRQ_EN,CH10_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "CH9_CMDCMPLT_IRQ_EN,CH9_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 24. "CH8_CMDCMPLT_IRQ_EN,CH8_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "CH7_CMDCMPLT_IRQ_EN,CH7_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 22. "CH6_CMDCMPLT_IRQ_EN,CH6_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "CH5_CMDCMPLT_IRQ_EN,CH5_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 20. "CH4_CMDCMPLT_IRQ_EN,CH4_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CH3_CMDCMPLT_IRQ_EN,CH3_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 18. "CH2_CMDCMPLT_IRQ_EN,CH2_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CH1_CMDCMPLT_IRQ_EN,CH1_CMDCMPLT_IRQ_EN" "0,1"
|
|
bitfld.long 0x00 16. "CH0_CMDCMPLT_IRQ_EN,CH0_CMDCMPLT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "CH15_CMDCMPLT_IRQ,CH15_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 14. "CH14_CMDCMPLT_IRQ,CH14_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CH13_CMDCMPLT_IRQ,CH13_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 12. "CH12_CMDCMPLT_IRQ,CH12_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CH11_CMDCMPLT_IRQ,CH11_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 10. "CH10_CMDCMPLT_IRQ,CH10_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH9_CMDCMPLT_IRQ,CH9_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 8. "CH8_CMDCMPLT_IRQ,CH8_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CH7_CMDCMPLT_IRQ,CH7_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 6. "CH6_CMDCMPLT_IRQ,CH6_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5_CMDCMPLT_IRQ,CH5_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 4. "CH4_CMDCMPLT_IRQ,CH4_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3_CMDCMPLT_IRQ,CH3_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 2. "CH2_CMDCMPLT_IRQ,CH2_CMDCMPLT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1_CMDCMPLT_IRQ,CH1_CMDCMPLT_IRQ" "0,1"
|
|
bitfld.long 0x00 0. "CH0_CMDCMPLT_IRQ,CH0_CMDCMPLT_IRQ" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CTRL2,AHB to APBH Bridge Control and Status Register 2"
|
|
rbitfld.long 0x00 31. "CH15_ERROR_STATUS,CH15_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
rbitfld.long 0x00 30. "CH14_ERROR_STATUS,CH14_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
newline
|
|
rbitfld.long 0x00 29. "CH13_ERROR_STATUS,CH13_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
rbitfld.long 0x00 28. "CH12_ERROR_STATUS,CH12_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
newline
|
|
rbitfld.long 0x00 27. "CH11_ERROR_STATUS,CH11_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
rbitfld.long 0x00 26. "CH10_ERROR_STATUS,CH10_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
newline
|
|
rbitfld.long 0x00 25. "CH9_ERROR_STATUS,CH9_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
rbitfld.long 0x00 24. "CH8_ERROR_STATUS,CH8_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
newline
|
|
rbitfld.long 0x00 23. "CH7_ERROR_STATUS,CH7_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
rbitfld.long 0x00 22. "CH6_ERROR_STATUS,CH6_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
newline
|
|
rbitfld.long 0x00 21. "CH5_ERROR_STATUS,CH5_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
rbitfld.long 0x00 20. "CH4_ERROR_STATUS,CH4_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
newline
|
|
rbitfld.long 0x00 19. "CH3_ERROR_STATUS,CH3_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
rbitfld.long 0x00 18. "CH2_ERROR_STATUS,CH2_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
newline
|
|
rbitfld.long 0x00 17. "CH1_ERROR_STATUS,CH1_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
rbitfld.long 0x00 16. "CH0_ERROR_STATUS,CH0_ERROR_STATUS" "0: An early termination from the device causes..,1: An AHB bus error causes error IRQ"
|
|
newline
|
|
bitfld.long 0x00 15. "CH15_ERROR_IRQ,CH15_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 14. "CH14_ERROR_IRQ,CH14_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CH13_ERROR_IRQ,CH13_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 12. "CH12_ERROR_IRQ,CH12_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CH11_ERROR_IRQ,CH11_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 10. "CH10_ERROR_IRQ,CH10_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH9_ERROR_IRQ,CH9_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 8. "CH8_ERROR_IRQ,CH8_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CH7_ERROR_IRQ,CH7_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 6. "CH6_ERROR_IRQ,CH6_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5_ERROR_IRQ,CH5_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 4. "CH4_ERROR_IRQ,CH4_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3_ERROR_IRQ,CH3_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 2. "CH2_ERROR_IRQ,CH2_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1_ERROR_IRQ,CH1_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 0. "CH0_ERROR_IRQ,CH0_ERROR_IRQ" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CTRL2_SET,AHB to APBH Bridge Control and Status Register 2"
|
|
rbitfld.long 0x00 31. "CH15_ERROR_STATUS,CH15_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 30. "CH14_ERROR_STATUS,CH14_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "CH13_ERROR_STATUS,CH13_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 28. "CH12_ERROR_STATUS,CH12_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 27. "CH11_ERROR_STATUS,CH11_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 26. "CH10_ERROR_STATUS,CH10_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 25. "CH9_ERROR_STATUS,CH9_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 24. "CH8_ERROR_STATUS,CH8_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23. "CH7_ERROR_STATUS,CH7_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 22. "CH6_ERROR_STATUS,CH6_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 21. "CH5_ERROR_STATUS,CH5_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 20. "CH4_ERROR_STATUS,CH4_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. "CH3_ERROR_STATUS,CH3_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 18. "CH2_ERROR_STATUS,CH2_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 17. "CH1_ERROR_STATUS,CH1_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 16. "CH0_ERROR_STATUS,CH0_ERROR_STATUS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "CH15_ERROR_IRQ,CH15_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 14. "CH14_ERROR_IRQ,CH14_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CH13_ERROR_IRQ,CH13_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 12. "CH12_ERROR_IRQ,CH12_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CH11_ERROR_IRQ,CH11_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 10. "CH10_ERROR_IRQ,CH10_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH9_ERROR_IRQ,CH9_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 8. "CH8_ERROR_IRQ,CH8_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CH7_ERROR_IRQ,CH7_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 6. "CH6_ERROR_IRQ,CH6_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5_ERROR_IRQ,CH5_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 4. "CH4_ERROR_IRQ,CH4_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3_ERROR_IRQ,CH3_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 2. "CH2_ERROR_IRQ,CH2_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1_ERROR_IRQ,CH1_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 0. "CH0_ERROR_IRQ,CH0_ERROR_IRQ" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CTRL2_CLR,AHB to APBH Bridge Control and Status Register 2"
|
|
eventfld.long 0x00 31. "CH15_ERROR_STATUS,CH15_ERROR_STATUS" "0,1"
|
|
eventfld.long 0x00 30. "CH14_ERROR_STATUS,CH14_ERROR_STATUS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 29. "CH13_ERROR_STATUS,CH13_ERROR_STATUS" "0,1"
|
|
eventfld.long 0x00 28. "CH12_ERROR_STATUS,CH12_ERROR_STATUS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 27. "CH11_ERROR_STATUS,CH11_ERROR_STATUS" "0,1"
|
|
eventfld.long 0x00 26. "CH10_ERROR_STATUS,CH10_ERROR_STATUS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 25. "CH9_ERROR_STATUS,CH9_ERROR_STATUS" "0,1"
|
|
eventfld.long 0x00 24. "CH8_ERROR_STATUS,CH8_ERROR_STATUS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 23. "CH7_ERROR_STATUS,CH7_ERROR_STATUS" "0,1"
|
|
eventfld.long 0x00 22. "CH6_ERROR_STATUS,CH6_ERROR_STATUS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 21. "CH5_ERROR_STATUS,CH5_ERROR_STATUS" "0,1"
|
|
eventfld.long 0x00 20. "CH4_ERROR_STATUS,CH4_ERROR_STATUS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 19. "CH3_ERROR_STATUS,CH3_ERROR_STATUS" "0,1"
|
|
eventfld.long 0x00 18. "CH2_ERROR_STATUS,CH2_ERROR_STATUS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 17. "CH1_ERROR_STATUS,CH1_ERROR_STATUS" "0,1"
|
|
eventfld.long 0x00 16. "CH0_ERROR_STATUS,CH0_ERROR_STATUS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 15. "CH15_ERROR_IRQ,CH15_ERROR_IRQ" "0,1"
|
|
eventfld.long 0x00 14. "CH14_ERROR_IRQ,CH14_ERROR_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 13. "CH13_ERROR_IRQ,CH13_ERROR_IRQ" "0,1"
|
|
eventfld.long 0x00 12. "CH12_ERROR_IRQ,CH12_ERROR_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 11. "CH11_ERROR_IRQ,CH11_ERROR_IRQ" "0,1"
|
|
eventfld.long 0x00 10. "CH10_ERROR_IRQ,CH10_ERROR_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 9. "CH9_ERROR_IRQ,CH9_ERROR_IRQ" "0,1"
|
|
eventfld.long 0x00 8. "CH8_ERROR_IRQ,CH8_ERROR_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 7. "CH7_ERROR_IRQ,CH7_ERROR_IRQ" "0,1"
|
|
eventfld.long 0x00 6. "CH6_ERROR_IRQ,CH6_ERROR_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 5. "CH5_ERROR_IRQ,CH5_ERROR_IRQ" "0,1"
|
|
eventfld.long 0x00 4. "CH4_ERROR_IRQ,CH4_ERROR_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 3. "CH3_ERROR_IRQ,CH3_ERROR_IRQ" "0,1"
|
|
eventfld.long 0x00 2. "CH2_ERROR_IRQ,CH2_ERROR_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 1. "CH1_ERROR_IRQ,CH1_ERROR_IRQ" "0,1"
|
|
eventfld.long 0x00 0. "CH0_ERROR_IRQ,CH0_ERROR_IRQ" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CTRL2_TOG,AHB to APBH Bridge Control and Status Register 2"
|
|
rbitfld.long 0x00 31. "CH15_ERROR_STATUS,CH15_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 30. "CH14_ERROR_STATUS,CH14_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "CH13_ERROR_STATUS,CH13_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 28. "CH12_ERROR_STATUS,CH12_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 27. "CH11_ERROR_STATUS,CH11_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 26. "CH10_ERROR_STATUS,CH10_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 25. "CH9_ERROR_STATUS,CH9_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 24. "CH8_ERROR_STATUS,CH8_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23. "CH7_ERROR_STATUS,CH7_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 22. "CH6_ERROR_STATUS,CH6_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 21. "CH5_ERROR_STATUS,CH5_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 20. "CH4_ERROR_STATUS,CH4_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. "CH3_ERROR_STATUS,CH3_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 18. "CH2_ERROR_STATUS,CH2_ERROR_STATUS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 17. "CH1_ERROR_STATUS,CH1_ERROR_STATUS" "0,1"
|
|
rbitfld.long 0x00 16. "CH0_ERROR_STATUS,CH0_ERROR_STATUS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "CH15_ERROR_IRQ,CH15_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 14. "CH14_ERROR_IRQ,CH14_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CH13_ERROR_IRQ,CH13_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 12. "CH12_ERROR_IRQ,CH12_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CH11_ERROR_IRQ,CH11_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 10. "CH10_ERROR_IRQ,CH10_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "CH9_ERROR_IRQ,CH9_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 8. "CH8_ERROR_IRQ,CH8_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "CH7_ERROR_IRQ,CH7_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 6. "CH6_ERROR_IRQ,CH6_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5_ERROR_IRQ,CH5_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 4. "CH4_ERROR_IRQ,CH4_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3_ERROR_IRQ,CH3_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 2. "CH2_ERROR_IRQ,CH2_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1_ERROR_IRQ,CH1_ERROR_IRQ" "0,1"
|
|
bitfld.long 0x00 0. "CH0_ERROR_IRQ,CH0_ERROR_IRQ" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CHANNEL_CTRL,AHB to APBH Bridge Channel Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESET_CHANNEL,RESET_CHANNEL"
|
|
hexmask.long.word 0x00 0.--15. 1. "FREEZE_CHANNEL,FREEZE_CHANNEL"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CHANNEL_CTRL_SET,AHB to APBH Bridge Channel Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESET_CHANNEL,RESET_CHANNEL"
|
|
hexmask.long.word 0x00 0.--15. 1. "FREEZE_CHANNEL,FREEZE_CHANNEL"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CHANNEL_CTRL_CLR,AHB to APBH Bridge Channel Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESET_CHANNEL,RESET_CHANNEL"
|
|
hexmask.long.word 0x00 0.--15. 1. "FREEZE_CHANNEL,FREEZE_CHANNEL"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CHANNEL_CTRL_TOG,AHB to APBH Bridge Channel Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESET_CHANNEL,RESET_CHANNEL"
|
|
hexmask.long.word 0x00 0.--15. 1. "FREEZE_CHANNEL,FREEZE_CHANNEL"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "DEVSEL,AHB to APBH DMA Device Assignment Register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DMA_BURST_SIZE,AHB to APBH DMA burst size"
|
|
bitfld.long 0x00 16.--17. "CH8,CH8" "0: no description available,1: no description available,2: no description available,?..."
|
|
bitfld.long 0x00 14.--15. "CH7,CH7" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "CH6,CH6" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "CH5,CH5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CH4,CH4" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "CH3,CH3" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "CH2,CH2" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "CH1,CH1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CH0,CH0" "0,1,2,3"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DEBUG,AHB to APBH DMA Debug Register"
|
|
bitfld.long 0x00 0. "GPMI_ONE_FIFO,GPMI_ONE_FIFO" "0,1"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CH0_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CH0_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "CH0_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "CH0_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CH0_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "CH0_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "CH0_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "CH1_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CH1_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "CH1_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "CH1_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CH1_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "CH1_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x1D0++0x03
|
|
line.long 0x00 "CH1_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "CH2_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "CH2_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x200++0x03
|
|
line.long 0x00 "CH2_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "CH2_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "CH2_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x230++0x03
|
|
line.long 0x00 "CH2_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "CH2_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x250++0x03
|
|
line.long 0x00 "CH3_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "CH3_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x270++0x03
|
|
line.long 0x00 "CH3_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "CH3_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "CH3_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x2A0++0x03
|
|
line.long 0x00 "CH3_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x2B0++0x03
|
|
line.long 0x00 "CH3_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x2C0++0x03
|
|
line.long 0x00 "CH4_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "CH4_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x2E0++0x03
|
|
line.long 0x00 "CH4_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x2F0++0x03
|
|
line.long 0x00 "CH4_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "CH4_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "CH4_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x320++0x03
|
|
line.long 0x00 "CH4_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x330++0x03
|
|
line.long 0x00 "CH5_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "CH5_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "CH5_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "CH5_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "CH5_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x380++0x03
|
|
line.long 0x00 "CH5_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x390++0x03
|
|
line.long 0x00 "CH5_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x3A0++0x03
|
|
line.long 0x00 "CH6_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "CH6_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x3C0++0x03
|
|
line.long 0x00 "CH6_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x3D0++0x03
|
|
line.long 0x00 "CH6_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "CH6_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x3F0++0x03
|
|
line.long 0x00 "CH6_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "CH6_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "CH7_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "CH7_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "CH7_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "CH7_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "CH7_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x460++0x03
|
|
line.long 0x00 "CH7_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x470++0x03
|
|
line.long 0x00 "CH7_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x480++0x03
|
|
line.long 0x00 "CH8_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "CH8_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x4A0++0x03
|
|
line.long 0x00 "CH8_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x4B0++0x03
|
|
line.long 0x00 "CH8_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "CH8_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x4D0++0x03
|
|
line.long 0x00 "CH8_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x4E0++0x03
|
|
line.long 0x00 "CH8_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x4F0++0x03
|
|
line.long 0x00 "CH9_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "CH9_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x510++0x03
|
|
line.long 0x00 "CH9_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x520++0x03
|
|
line.long 0x00 "CH9_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "CH9_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x540++0x03
|
|
line.long 0x00 "CH9_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x550++0x03
|
|
line.long 0x00 "CH9_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x560++0x03
|
|
line.long 0x00 "CH10_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "CH10_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x580++0x03
|
|
line.long 0x00 "CH10_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x590++0x03
|
|
line.long 0x00 "CH10_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "CH10_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x5B0++0x03
|
|
line.long 0x00 "CH10_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x5C0++0x03
|
|
line.long 0x00 "CH10_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x5D0++0x03
|
|
line.long 0x00 "CH11_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "CH11_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x5F0++0x03
|
|
line.long 0x00 "CH11_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x600++0x03
|
|
line.long 0x00 "CH11_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "CH11_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x620++0x03
|
|
line.long 0x00 "CH11_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x630++0x03
|
|
line.long 0x00 "CH11_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "CH12_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "CH12_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x660++0x03
|
|
line.long 0x00 "CH12_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x670++0x03
|
|
line.long 0x00 "CH12_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "CH12_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x690++0x03
|
|
line.long 0x00 "CH12_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x6A0++0x03
|
|
line.long 0x00 "CH12_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x6B0++0x03
|
|
line.long 0x00 "CH13_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "CH13_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x6D0++0x03
|
|
line.long 0x00 "CH13_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x6E0++0x03
|
|
line.long 0x00 "CH13_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "CH13_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x700++0x03
|
|
line.long 0x00 "CH13_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x710++0x03
|
|
line.long 0x00 "CH13_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x720++0x03
|
|
line.long 0x00 "CH14_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x730++0x03
|
|
line.long 0x00 "CH14_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x740++0x03
|
|
line.long 0x00 "CH14_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x750++0x03
|
|
line.long 0x00 "CH14_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x760++0x03
|
|
line.long 0x00 "CH14_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x770++0x03
|
|
line.long 0x00 "CH14_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x780++0x03
|
|
line.long 0x00 "CH14_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x790++0x03
|
|
line.long 0x00 "CH15_CURCMDAR,APBH DMA Channel n Current Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
group.long 0x7A0++0x03
|
|
line.long 0x00 "CH15_NXTCMDAR,APBH DMA Channel n Next Command Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMD_ADDR,CMD_ADDR"
|
|
rgroup.long 0x7B0++0x03
|
|
line.long 0x00 "CH15_CMD,APBH DMA Channel n Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "XFER_COUNT,XFER_COUNT"
|
|
bitfld.long 0x00 12.--15. "CMDWORDS,CMDWORDS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "HALTONTERMINATE,HALTONTERMINATE" "0,1"
|
|
bitfld.long 0x00 7. "WAIT4ENDCMD,WAIT4ENDCMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "SEMAPHORE,SEMAPHORE" "0,1"
|
|
bitfld.long 0x00 5. "NANDWAIT4READY,NANDWAIT4READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "NANDLOCK,NANDLOCK" "0,1"
|
|
bitfld.long 0x00 3. "IRQONCMPLT,IRQONCMPLT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CHAIN,CHAIN" "0,1"
|
|
bitfld.long 0x00 0.--1. "COMMAND,COMMAND" "0: Perform any requested PIO word transfers but..,1: Perform any requested PIO word transfers and..,2: Perform any requested PIO word transfers and..,3: Perform any requested PIO word transfers and.."
|
|
rgroup.long 0x7C0++0x03
|
|
line.long 0x00 "CH15_BAR,APBH DMA Channel n Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x7D0++0x03
|
|
line.long 0x00 "CH15_SEMA,APBH DMA Channel n Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PHORE,PHORE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "INCREMENT_SEMA,INCREMENT_SEMA"
|
|
rgroup.long 0x7E0++0x03
|
|
line.long 0x00 "CH15_DEBUG1,AHB to APBH DMA Channel n Debug Information"
|
|
bitfld.long 0x00 31. "REQ,REQ" "0,1"
|
|
bitfld.long 0x00 30. "BURST,BURST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "KICK,KICK" "0,1"
|
|
bitfld.long 0x00 28. "END,END" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "READY,READY" "0,1"
|
|
bitfld.long 0x00 24. "NEXTCMDADDRVALID,NEXTCMDADDRVALID" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RD_FIFO_EMPTY,RD_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 22. "RD_FIFO_FULL,RD_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WR_FIFO_EMPTY,WR_FIFO_EMPTY" "0,1"
|
|
bitfld.long 0x00 20. "WR_FIFO_FULL,WR_FIFO_FULL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "STATEMACHINE,STATEMACHINE" "0: This is the idle state of the DMA state machine,1: State in which the DMA is waiting to receive..,2: State in which the DMA is waiting to receive..,3: State in which the DMA is waiting to receive..,4: The state machine processes the descriptor..,5: The state machine waits in this state for the..,6: State in which the DMA is waiting to receive..,7: This state determines whether another PIO..,8: During a read transfers the state machine..,9: When an AHB read request occurs the state..,?,?,12: During DMA Write transfers the state machine..,13: During DMA Read transfers the state machine..,14: Upon completion of the DMA transfers this..,15: The state machine goes to this state after..,?,?,?,?,20: When a terminate signal is set the state..,21: When the Wait for Command End bit is set the..,?,?,?,?,?,?,28: During DMA Write transfers the state machine..,29: If HALTONTERMINATE is set and a terminate..,30: If the Chain bit is a 0 the state machine..,31: When the NAND Wait for Ready bit is set the.."
|
|
rgroup.long 0x7F0++0x03
|
|
line.long 0x00 "CH15_DEBUG2,AHB to APBH DMA Channel n Debug Information"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_BYTES,APB_BYTES"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHB_BYTES,AHB_BYTES"
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "VERSION,APBH Bridge Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,MAJOR"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,MINOR"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "STEP,STEP"
|
|
tree.end
|
|
tree "ASRC"
|
|
base ad:0x59000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ASRCTR,ASRC Control Register"
|
|
bitfld.long 0x00 22. "ATSC,ATSC" "0,1"
|
|
bitfld.long 0x00 21. "ATSB,ATSB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "ATSA,ATSA" "0,1"
|
|
bitfld.long 0x00 18. "USRC,USRC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "IDRC,IDRC" "0,1"
|
|
bitfld.long 0x00 16. "USRB,USRB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IDRB,IDRB" "0,1"
|
|
bitfld.long 0x00 14. "USRA,USRA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "IDRA,IDRA" "0,1"
|
|
bitfld.long 0x00 4. "SRST,SRST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ASREC,ASREC" "0,1"
|
|
bitfld.long 0x00 2. "ASREB,ASREB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ASREA,ASREA" "0,1"
|
|
bitfld.long 0x00 0. "ASRCEN,ASRCEN" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ASRIER,ASRC Interrupt Enable Register"
|
|
bitfld.long 0x00 7. "AFPWE,AFPWE" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x00 6. "AOLIE,AOLIE" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "ADOEC,ADOEC" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x00 4. "ADOEB,ADOEB" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "ADOEA,ADOEA" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x00 2. "ADIEC,ADIEC" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "ADIEB,ADIEB" "0: interrupt disabled,1: interrupt enabled"
|
|
bitfld.long 0x00 0. "ADIEA,ADIEA" "0: interrupt disabled,1: interrupt enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ASRCNCR,ASRC Channel Number Configuration Register"
|
|
bitfld.long 0x00 8.--11. "ANCC,ANCC" "0: 0 channels in C (Pair C is disabled),1: 1 channel in C,2: 2 channels in C,3: 3 channels in C,4: 4 channels in C,5: 5 channels in C,6: 6 channels in C,7: 7 channels in C,8: 8 channels in C,9: 9 channels in C,10: 10 channels in C,11: Should not be used,12: Should not be used,13: Should not be used,14: Should not be used,15: Should not be used"
|
|
bitfld.long 0x00 4.--7. "ANCB,ANCB" "0: 0 channels in B (Pair B is disabled),1: 1 channel in B,2: 2 channels in B,3: 3 channels in B,4: 4 channels in B,5: 5 channels in B,6: 6 channels in B,7: 7 channels in B,8: 8 channels in B,9: 9 channels in B,10: 10 channels in B,11: Should not be used,12: Should not be used,13: Should not be used,14: Should not be used,15: Should not be used"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "ANCA,ANCA" "0: 0 channels in A (Pair A is disabled),1: 1 channel in A,2: 2 channels in A,3: 3 channels in A,4: 4 channels in A,5: 5 channels in A,6: 6 channels in A,7: 7 channels in A,8: 8 channels in A,9: 9 channels in A,10: 10 channels in A,11: Should not be used,12: Should not be used,13: Should not be used,14: Should not be used,15: Should not be used"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ASRCFG,ASRC Filter Configuration Status Register"
|
|
rbitfld.long 0x00 23. "INIRQC,INIRQC" "0,1"
|
|
rbitfld.long 0x00 22. "INIRQB,INIRQB" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 21. "INIRQA,INIRQA" "0,1"
|
|
bitfld.long 0x00 20. "NDPRC,NDPRC" "0: Use default parameters for RAM-stored..,1: Don't use default parameters for RAM-stored.."
|
|
newline
|
|
bitfld.long 0x00 19. "NDPRB,NDPRB" "0: Use default parameters for RAM-stored..,1: Don't use default parameters for RAM-stored.."
|
|
bitfld.long 0x00 18. "NDPRA,NDPRA" "0: Use default parameters for RAM-stored..,1: Don't use default parameters for RAM-stored.."
|
|
newline
|
|
bitfld.long 0x00 16.--17. "POSTMODC,POSTMODC" "0: Select Upsampling-by-2 as defined in Signal..,1: Select Direct-Connection as defined in Signal..,2: Select Downsampling-by-2 as defined in Signal..,?..."
|
|
bitfld.long 0x00 14.--15. "PREMODC,PREMODC" "0: Select Upsampling-by-2 as defined in,1: Select Direct-Connection as defined in,2: Select Downsampling-by-2 as defined in,3: Select passthrough mode"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "POSTMODB,POSTMODB" "0: Select Upsampling-by-2 as defined in,1: Select Direct-Connection as defined in,2: Select Downsampling-by-2 as defined in,?..."
|
|
bitfld.long 0x00 10.--11. "PREMODB,PREMODB" "0: Select Upsampling-by-2 as defined in,1: Select Direct-Connection as defined in,2: Select Downsampling-by-2 as defined in,3: Select passthrough mode"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "POSTMODA,POSTMODA" "0: Select Upsampling-by-2 as defined in,1: Select Direct-Connection as defined in,2: Select Downsampling-by-2 as defined in,?..."
|
|
bitfld.long 0x00 6.--7. "PREMODA,PREMODA" "0: Select Upsampling-by-2 as defined in,1: Select Direct-Connection as defined in,2: Select Downsampling-by-2 as defined in,3: Select passthrough mode"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ASRCSR,ASRC Clock Source Register"
|
|
bitfld.long 0x00 20.--23. "AOCSC,AOCSC" "0: bit clock 0,1: bit clock 1,2: bit clock 2,3: bit clock 3,4: bit clock 4,5: bit clock 5,6: bit clock 6,7: bit clock 7,8: bit clock 8,9: bit clock 9,10: bit clock A,11: bit clock B,12: bit clock C,13: bit clock D,14: bit clock E,15: clock disabled connected to zero"
|
|
bitfld.long 0x00 16.--19. "AOCSB,AOCSB" "0: bit clock 0,1: bit clock 1,2: bit clock 2,3: bit clock 3,4: bit clock 4,5: bit clock 5,6: bit clock 6,7: bit clock 7,8: bit clock 8,9: bit clock 9,10: bit clock A,11: bit clock B,12: bit clock C,13: bit clock D,14: bit clock E,15: clock disabled connected to zero"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "AOCSA,AOCSA" "0: bit clock 0,1: bit clock 1,2: bit clock 2,3: bit clock 3,4: bit clock 4,5: bit clock 5,6: bit clock 6,7: bit clock 7,8: bit clock 8,9: bit clock 9,10: bit clock A,11: bit clock B,12: bit clock C,13: bit clock D,14: bit clock E,15: clock disabled connected to zero"
|
|
bitfld.long 0x00 8.--11. "AICSC,AICSC" "0: bit clock 0,1: bit clock 1,2: bit clock 2,3: bit clock 3,4: bit clock 4,5: bit clock 5,6: bit clock 6,7: bit clock 7,8: bit clock 8,9: bit clock 9,10: bit clock A,11: bit clock B,12: bit clock C,13: bit clock D,14: bit clock E,15: clock disabled connected to zero"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "AICSB,AICSB" "0: bit clock 0,1: bit clock 1,2: bit clock 2,3: bit clock 3,4: bit clock 4,5: bit clock 5,6: bit clock 6,7: bit clock 7,8: bit clock 8,9: bit clock 9,10: bit clock A,11: bit clock B,12: bit clock C,13: bit clock D,14: bit clock E,15: clock disabled connected to zero"
|
|
bitfld.long 0x00 0.--3. "AICSA,AICSA" "0: bit clock 0,1: bit clock 1,2: bit clock 2,3: bit clock 3,4: bit clock 4,5: bit clock 5,6: bit clock 6,7: bit clock 7,8: bit clock 8,9: bit clock 9,10: bit clock A,11: bit clock B,12: bit clock C,13: bit clock D,14: bit clock E,15: clock disabled connected to zero"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ASRCDR1,ASRC Clock Divider Register 1"
|
|
bitfld.long 0x00 21.--23. "AOCDB,AOCDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. "AOCPB,AOCPB" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--17. "AOCDA,AOCDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. "AOCPA,AOCPA" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "AICDB,AICDB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. "AICPB,AICPB" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "AICDA,AICDA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "AICPA,AICPA" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ASRCDR2,ASRC Clock Divider Register 2"
|
|
bitfld.long 0x00 9.--11. "AOCDC,AOCDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. "AOCPC,AOCPC" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "AICDC,AICDC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "AICPC,AICPC" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ASRSTR,ASRC Status Register"
|
|
bitfld.long 0x00 21. "DSLCNT,DSLCNT" "0,1"
|
|
bitfld.long 0x00 20. "ATQOL,ATQOL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "AOOLC,AOOLC" "0,1"
|
|
bitfld.long 0x00 18. "AOOLB,AOOLB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "AOOLA,AOOLA" "0,1"
|
|
bitfld.long 0x00 16. "AIOLC,AIOLC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "AIOLB,AIOLB" "0,1"
|
|
bitfld.long 0x00 14. "AIOLA,AIOLA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "AODOC,AODOC" "0,1"
|
|
bitfld.long 0x00 12. "AODOB,AODOB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "AODOA,AODOA" "0,1"
|
|
bitfld.long 0x00 10. "AIDUC,AIDUC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "AIDUB,AIDUB" "0,1"
|
|
bitfld.long 0x00 8. "AIDUA,AIDUA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "FPWT,FPWT" "0,1"
|
|
bitfld.long 0x00 6. "AOLE,AOLE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "AODFC,AODFC" "0,1"
|
|
bitfld.long 0x00 4. "AODFB,AODFB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AODFA,AODFA" "0,1"
|
|
bitfld.long 0x00 2. "AIDEC,AIDEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "AIDEB,AIDEB" "0,1"
|
|
bitfld.long 0x00 0. "AIDEA,AIDEA" "0,1"
|
|
repeat 5. (strings "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "ASRPM$1,ASRC Parameter Register n"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "PARAMETER_VALUE,PARAMETER_VALUE"
|
|
repeat.end
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ASRTFR1,ASRC ASRC Task Queue FIFO Register 1"
|
|
hexmask.long.byte 0x00 13.--19. 1. "TF_FILL,TF_FILL"
|
|
hexmask.long.byte 0x00 6.--12. 1. "TF_BASE,TF_BASE"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "ASRCCR,ASRC Channel Counter Register"
|
|
bitfld.long 0x00 20.--23. "ACOC,ACOC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "ACOB,ACOB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "ACOA,ACOA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "ACIC,ACIC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "ACIB,ACIB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "ACIA,ACIA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x60++0x03
|
|
line.long 0x00 "ASRDIA,ASRC Data Input Register for Pair x"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,DATA"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "ASRDOA,ASRC Data Output Register for Pair x"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,DATA"
|
|
wgroup.long 0x68++0x03
|
|
line.long 0x00 "ASRDIB,ASRC Data Input Register for Pair x"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,DATA"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "ASRDOB,ASRC Data Output Register for Pair x"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,DATA"
|
|
wgroup.long 0x70++0x03
|
|
line.long 0x00 "ASRDIC,ASRC Data Input Register for Pair x"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,DATA"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "ASRDOC,ASRC Data Output Register for Pair x"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "DATA,DATA"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ASRIDRHA,ASRC Ideal Ratio for Pair A-High Part"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IDRATIOA_H,IDRATIOA_H"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ASRIDRLA,ASRC Ideal Ratio for Pair A -Low Part"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "IDRATIOA_L,IDRATIOA_L"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ASRIDRHB,ASRC Ideal Ratio for Pair B-High Part"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IDRATIOB_H,IDRATIOB_H"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "ASRIDRLB,ASRC Ideal Ratio for Pair B-Low Part"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "IDRATIOB_L,IDRATIOB_L"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "ASRIDRHC,ASRC Ideal Ratio for Pair C-High Part"
|
|
hexmask.long.byte 0x00 0.--7. 1. "IDRATIOC_H,IDRATIOC_H"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ASRIDRLC,ASRC Ideal Ratio for Pair C-Low Part"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "IDRATIOC_L,IDRATIOC_L"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "ASR76K,ASRC 76 kHz Period in terms of ASRC processing clock"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. "ASR76K,ASR76K"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "ASR56K,ASRC 56 kHz Period in terms of ASRC processing clock"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. "ASR56K,ASR56K"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ASRMCRA,ASRC Misc Control Register for Pair A"
|
|
bitfld.long 0x00 23. "ZEROBUFA,ZEROBUFA" "0: Zeroize the buffer,1: Don't zeroize the buffer"
|
|
bitfld.long 0x00 22. "EXTTHRSHA,EXTTHRSHA" "0: Use default thresholds,1: Use external defined thresholds"
|
|
newline
|
|
bitfld.long 0x00 21. "BUFSTALLA,BUFSTALLA" "0: Don't stall Pair A conversion even in case of..,1: Stall Pair A conversion in case of near.."
|
|
bitfld.long 0x00 20. "BYPASSPOLYA,BYPASSPOLYA" "0: Don't bypass polyphase filtering,1: Bypass polyphase filtering"
|
|
newline
|
|
bitfld.long 0x00 12.--17. "OUTFIFO_THRESHOLDA,OUTFIFO_THRESHOLDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 11. "RSYNIFA,RSYNIFA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "RSYNOFA,RSYNOFA" "0,1"
|
|
bitfld.long 0x00 0.--5. "INFIFO_THRESHOLDA,INFIFO_THRESHOLDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "ASRFSTA,ASRC FIFO Status Register for Pair A"
|
|
bitfld.long 0x00 23. "OAFA,OAFA" "0,1"
|
|
hexmask.long.byte 0x00 12.--18. 1. "OUTFIFO_FILLA,OUTFIFO_FILLA"
|
|
newline
|
|
bitfld.long 0x00 11. "IAEA,IAEA" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "INFIFO_FILLA,INFIFO_FILLA"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "ASRMCRB,ASRC Misc Control Register for Pair B"
|
|
bitfld.long 0x00 23. "ZEROBUFB,ZEROBUFB" "0: Zeroize the buffer,1: Don't zeroize the buffer"
|
|
bitfld.long 0x00 22. "EXTTHRSHB,EXTTHRSHB" "0: Use default thresholds,1: Use external defined thresholds"
|
|
newline
|
|
bitfld.long 0x00 21. "BUFSTALLB,BUFSTALLB" "0: Don't stall Pair B conversion even in case of..,1: Stall Pair B conversion in case of near.."
|
|
bitfld.long 0x00 20. "BYPASSPOLYB,BYPASSPOLYB" "0: Don't bypass polyphase filtering,1: Bypass polyphase filtering"
|
|
newline
|
|
bitfld.long 0x00 12.--17. "OUTFIFO_THRESHOLDB,OUTFIFO_THRESHOLDB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 11. "RSYNIFB,RSYNIFB" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "RSYNOFB,RSYNOFB" "0,1"
|
|
bitfld.long 0x00 0.--5. "INFIFO_THRESHOLDB,INFIFO_THRESHOLDB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "ASRFSTB,ASRC FIFO Status Register for Pair B"
|
|
bitfld.long 0x00 23. "OAFB,OAFB" "0,1"
|
|
hexmask.long.byte 0x00 12.--18. 1. "OUTFIFO_FILLB,OUTFIFO_FILLB"
|
|
newline
|
|
bitfld.long 0x00 11. "IAEB,IAEB" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "INFIFO_FILLB,INFIFO_FILLB"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "ASRMCRC,ASRC Misc Control Register for Pair C"
|
|
bitfld.long 0x00 23. "ZEROBUFC,ZEROBUFC" "0: Zeroize the buffer,1: Don't zeroize the buffer"
|
|
bitfld.long 0x00 22. "EXTTHRSHC,EXTTHRSHC" "0: Use default thresholds,1: Use external defined thresholds"
|
|
newline
|
|
bitfld.long 0x00 21. "BUFSTALLC,BUFSTALLC" "0: Don't stall Pair C conversion even in case of..,1: Stall Pair C conversion in case of near.."
|
|
bitfld.long 0x00 20. "BYPASSPOLYC,BYPASSPOLYC" "0: Don't bypass polyphase filtering,1: Bypass polyphase filtering"
|
|
newline
|
|
bitfld.long 0x00 12.--17. "OUTFIFO_THRESHOLDC,OUTFIFO_THRESHOLDC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 11. "RSYNIFC,RSYNIFC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "RSYNOFC,RSYNOFC" "0,1"
|
|
bitfld.long 0x00 0.--5. "INFIFO_THRESHOLDC,INFIFO_THRESHOLDC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "ASRFSTC,ASRC FIFO Status Register for Pair C"
|
|
bitfld.long 0x00 23. "OAFC,OAFC" "0,1"
|
|
hexmask.long.byte 0x00 12.--18. 1. "OUTFIFO_FILLC,OUTFIFO_FILLC"
|
|
newline
|
|
bitfld.long 0x00 11. "IAEC,IAEC" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "INFIFO_FILLC,INFIFO_FILLC"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "ASRMCR1A,ASRC Misc Control Register 1 for Pair X"
|
|
bitfld.long 0x00 9.--11. "IWD,IWD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. "IMSB,IMSB" "0: LSB aligned,1: MSB aligned"
|
|
newline
|
|
bitfld.long 0x00 2. "OMSB,OMSB" "0: LSB aligned,1: MSB aligned"
|
|
bitfld.long 0x00 1. "OSGN,OSGN" "0: No sign extension,1: Sign extension"
|
|
newline
|
|
bitfld.long 0x00 0. "OW16,OW16" "0: 24-bit output data,1: 16-bit output data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "ASRMCR1B,ASRC Misc Control Register 1 for Pair X"
|
|
bitfld.long 0x00 9.--11. "IWD,IWD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. "IMSB,IMSB" "0: LSB aligned,1: MSB aligned"
|
|
newline
|
|
bitfld.long 0x00 2. "OMSB,OMSB" "0: LSB aligned,1: MSB aligned"
|
|
bitfld.long 0x00 1. "OSGN,OSGN" "0: No sign extension,1: Sign extension"
|
|
newline
|
|
bitfld.long 0x00 0. "OW16,OW16" "0: 24-bit output data,1: 16-bit output data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ASRMCR1C,ASRC Misc Control Register 1 for Pair X"
|
|
bitfld.long 0x00 9.--11. "IWD,IWD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. "IMSB,IMSB" "0: LSB aligned,1: MSB aligned"
|
|
newline
|
|
bitfld.long 0x00 2. "OMSB,OMSB" "0: LSB aligned,1: MSB aligned"
|
|
bitfld.long 0x00 1. "OSGN,OSGN" "0: No sign extension,1: Sign extension"
|
|
newline
|
|
bitfld.long 0x00 0. "OW16,OW16" "0: 24-bit output data,1: 16-bit output data"
|
|
tree.end
|
|
tree "BBS_SIM (ASMC)"
|
|
tree "CM4__ASMC"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x41410000
|
|
else
|
|
base ad:0x37410000
|
|
endif
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SRS,System Reset Status Register"
|
|
bitfld.long 0x00 12. "SACKERR,Stop Mode Acknowledge Error Reset" "0: Reset not caused by peripheral failure to..,1: Reset caused by peripheral failure to.."
|
|
bitfld.long 0x00 10. "SW,Software" "0: Reset not caused by software setting of..,1: Reset caused by software setting of.."
|
|
newline
|
|
bitfld.long 0x00 9. "LOCKUP,Core 1 Lockup" "0: Reset not caused by core LOCKUP event,1: Reset caused by core LOCKUP event"
|
|
bitfld.long 0x00 7. "POR,Power-On Reset" "0: Reset not caused by POR,1: Reset caused by POR"
|
|
newline
|
|
bitfld.long 0x00 6. "RES,Chip Reset not POR" "0: Chip Reset did not occur,1: Chip Reset caused by a source other than POR.."
|
|
bitfld.long 0x00 5. "WDOG1,Watchdog" "0: Reset not caused by watchdog timeout,1: Reset caused by watchdog timeout"
|
|
newline
|
|
bitfld.long 0x00 0. "WAKEUP,Low Leakage Wakeup Reset" "0: Reset not caused by LLWU module wakeup source,1: Reset caused by LLWU module wakeup source"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PMPROT,Power Mode Protection register"
|
|
bitfld.long 0x00 7. "AHSRUN,Allow High Speed Run mode" "0: HSRUN is not allowed,1: HSRUN is allowed"
|
|
bitfld.long 0x00 5. "AVLP,Allow Very-Low-Power Modes" "0: VLPR VLPW and VLPS are not allowed,1: VLPR VLPW and VLPS are allowed"
|
|
newline
|
|
bitfld.long 0x00 3. "ALLS,Allow Low-Leakage Stop Mode" "0: NOT_ALLOWED,1: ALLOWED"
|
|
bitfld.long 0x00 1. "AVLLS,Allow Very-Low-Leakage Stop Mode" "0: NOT_ALLOWED,1: ALLOWED"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PMCTRL,Power Mode Control register"
|
|
bitfld.long 0x00 5.--6. "RUNM,Run Mode Control" "0: Normal Run mode (RUN),?,2: Very-Low-Power Run mode (VLPR),3: High Speed Run mode (HSRUN)"
|
|
bitfld.long 0x00 0.--2. "STOPM,Stop Mode Control" "0: Normal Stop (STOP),?,2: Very-Low-Power Stop (VLPS),3: Low-leakage stop,4: Very-low-leakage stop,?..."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "STOPCTRL,Stop Control Register"
|
|
bitfld.long 0x00 6.--7. "PSTOPO,Partial Stop Option" "0: STOP - Normal Stop mode,1: PSTOP1 - Partial Stop with both system and..,2: PSTOP2 - Partial Stop with system clock..,?..."
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PMSTAT,Power Mode Status register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PMSTAT,Power Mode Status"
|
|
tree.end
|
|
tree "SCU__ASMC"
|
|
base ad:0x33410000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SRS,System Reset Status Register"
|
|
bitfld.long 0x00 12. "SACKERR,Stop Mode Acknowledge Error Reset" "0: Reset not caused by peripheral failure to..,1: Reset caused by peripheral failure to.."
|
|
bitfld.long 0x00 10. "SW,Software" "0: Reset not caused by software setting of..,1: Reset caused by software setting of.."
|
|
newline
|
|
bitfld.long 0x00 9. "LOCKUP,Core 1 Lockup" "0: Reset not caused by core LOCKUP event,1: Reset caused by core LOCKUP event"
|
|
bitfld.long 0x00 7. "POR,Power-On Reset" "0: Reset not caused by POR,1: Reset caused by POR"
|
|
newline
|
|
bitfld.long 0x00 6. "RES,Chip Reset not POR" "0: Chip Reset did not occur,1: Chip Reset caused by a source other than POR.."
|
|
bitfld.long 0x00 5. "WDOG1,Watchdog" "0: Reset not caused by watchdog timeout,1: Reset caused by watchdog timeout"
|
|
newline
|
|
bitfld.long 0x00 0. "WAKEUP,Low Leakage Wakeup Reset" "0: Reset not caused by LLWU module wakeup source,1: Reset caused by LLWU module wakeup source"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PMPROT,Power Mode Protection register"
|
|
bitfld.long 0x00 7. "AHSRUN,Allow High Speed Run mode" "0: HSRUN is not allowed,1: HSRUN is allowed"
|
|
bitfld.long 0x00 5. "AVLP,Allow Very-Low-Power Modes" "0: VLPR VLPW and VLPS are not allowed,1: VLPR VLPW and VLPS are allowed"
|
|
newline
|
|
bitfld.long 0x00 3. "ALLS,Allow Low-Leakage Stop Mode" "0: NOT_ALLOWED,1: ALLOWED"
|
|
bitfld.long 0x00 1. "AVLLS,Allow Very-Low-Leakage Stop Mode" "0: NOT_ALLOWED,1: ALLOWED"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PMCTRL,Power Mode Control register"
|
|
bitfld.long 0x00 5.--6. "RUNM,Run Mode Control" "0: Normal Run mode (RUN),?,2: Very-Low-Power Run mode (VLPR),3: High Speed Run mode (HSRUN)"
|
|
bitfld.long 0x00 0.--2. "STOPM,Stop Mode Control" "0: Normal Stop (STOP),?,2: Very-Low-Power Stop (VLPS),3: Low-leakage stop,4: Very-low-leakage stop,?..."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "STOPCTRL,Stop Control Register"
|
|
bitfld.long 0x00 6.--7. "PSTOPO,Partial Stop Option" "0: STOP - Normal Stop mode,1: PSTOP1 - Partial Stop with both system and..,2: PSTOP2 - Partial Stop with system clock..,?..."
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PMSTAT,Power Mode Status register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PMSTAT,Power Mode Status"
|
|
tree.end
|
|
tree.end
|
|
tree "BCH32 (BCH)"
|
|
base ad:0x5B814000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Hardware BCH ECC Accelerator Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,SFTRST" "0: Allow BCH to operate normally,1: Hold BCH in reset"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,CLKGATE" "0: Allow BCH to operate normally,1: Do not clock BCH gates in order to minimize.."
|
|
newline
|
|
bitfld.long 0x00 22. "DEBUGSYNDROME,DEBUGSYNDROME" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "M2M_LAYOUT,M2M_LAYOUT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "M2M_ENCODE,M2M_ENCODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "M2M_ENABLE,M2M_ENABLE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "DEBUG_STALL_IRQ_EN,DEBUG_STALL_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "COMPLETE_IRQ_EN,COMPLETE_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BM_ERROR_IRQ,BM_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DEBUG_STALL_IRQ,DEBUG_STALL_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "COMPLETE_IRQ,COMPLETE_IRQ" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL_SET,Hardware BCH ECC Accelerator Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,SFTRST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,CLKGATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DEBUGSYNDROME,DEBUGSYNDROME" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "M2M_LAYOUT,M2M_LAYOUT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "M2M_ENCODE,M2M_ENCODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "M2M_ENABLE,M2M_ENABLE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "DEBUG_STALL_IRQ_EN,DEBUG_STALL_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "COMPLETE_IRQ_EN,COMPLETE_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BM_ERROR_IRQ,BM_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DEBUG_STALL_IRQ,DEBUG_STALL_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "COMPLETE_IRQ,COMPLETE_IRQ" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL_CLR,Hardware BCH ECC Accelerator Control Register"
|
|
eventfld.long 0x00 31. "SFTRST,SFTRST" "0,1"
|
|
newline
|
|
eventfld.long 0x00 30. "CLKGATE,CLKGATE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 22. "DEBUGSYNDROME,DEBUGSYNDROME" "0,1"
|
|
newline
|
|
eventfld.long 0x00 18.--19. "M2M_LAYOUT,M2M_LAYOUT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 17. "M2M_ENCODE,M2M_ENCODE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 16. "M2M_ENABLE,M2M_ENABLE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 10. "DEBUG_STALL_IRQ_EN,DEBUG_STALL_IRQ_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 8. "COMPLETE_IRQ_EN,COMPLETE_IRQ_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 3. "BM_ERROR_IRQ,BM_ERROR_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 2. "DEBUG_STALL_IRQ,DEBUG_STALL_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 0. "COMPLETE_IRQ,COMPLETE_IRQ" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTRL_TOG,Hardware BCH ECC Accelerator Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,SFTRST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,CLKGATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DEBUGSYNDROME,DEBUGSYNDROME" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "M2M_LAYOUT,M2M_LAYOUT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "M2M_ENCODE,M2M_ENCODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "M2M_ENABLE,M2M_ENABLE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "DEBUG_STALL_IRQ_EN,DEBUG_STALL_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "COMPLETE_IRQ_EN,COMPLETE_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BM_ERROR_IRQ,BM_ERROR_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DEBUG_STALL_IRQ,DEBUG_STALL_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "COMPLETE_IRQ,COMPLETE_IRQ" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "STATUS0,Hardware ECC Accelerator Status Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. "HANDLE,HANDLE"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "COMPLETED_CE,COMPLETED_CE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "STATUS_BLK0,STATUS_BLK0"
|
|
newline
|
|
bitfld.long 0x00 4. "ALLONES,ALLONES" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CORRECTED,CORRECTED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UNCORRECTABLE,UNCORRECTABLE" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "STATUS0_SET,Hardware ECC Accelerator Status Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. "HANDLE,HANDLE"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "COMPLETED_CE,COMPLETED_CE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "STATUS_BLK0,STATUS_BLK0"
|
|
newline
|
|
bitfld.long 0x00 4. "ALLONES,ALLONES" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CORRECTED,CORRECTED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UNCORRECTABLE,UNCORRECTABLE" "0,1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "STATUS0_CLR,Hardware ECC Accelerator Status Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. "HANDLE,HANDLE"
|
|
newline
|
|
eventfld.long 0x00 16.--19. "COMPLETED_CE,COMPLETED_CE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "STATUS_BLK0,STATUS_BLK0"
|
|
newline
|
|
eventfld.long 0x00 4. "ALLONES,ALLONES" "0,1"
|
|
newline
|
|
eventfld.long 0x00 3. "CORRECTED,CORRECTED" "0,1"
|
|
newline
|
|
eventfld.long 0x00 2. "UNCORRECTABLE,UNCORRECTABLE" "0,1"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "STATUS0_TOG,Hardware ECC Accelerator Status Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. "HANDLE,HANDLE"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "COMPLETED_CE,COMPLETED_CE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "STATUS_BLK0,STATUS_BLK0"
|
|
newline
|
|
bitfld.long 0x00 4. "ALLONES,ALLONES" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CORRECTED,CORRECTED" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UNCORRECTABLE,UNCORRECTABLE" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MODE,Hardware ECC Accelerator Mode Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERASE_THRESHOLD,ERASE_THRESHOLD"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODE_SET,Hardware ECC Accelerator Mode Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERASE_THRESHOLD,ERASE_THRESHOLD"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MODE_CLR,Hardware ECC Accelerator Mode Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERASE_THRESHOLD,ERASE_THRESHOLD"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MODE_TOG,Hardware ECC Accelerator Mode Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERASE_THRESHOLD,ERASE_THRESHOLD"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ENCODEPTR,Hardware BCH ECC Loopback Encode Buffer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,ADDR"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ENCODEPTR_SET,Hardware BCH ECC Loopback Encode Buffer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,ADDR"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ENCODEPTR_CLR,Hardware BCH ECC Loopback Encode Buffer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,ADDR"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ENCODEPTR_TOG,Hardware BCH ECC Loopback Encode Buffer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,ADDR"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DATAPTR,Hardware BCH ECC Loopback Data Buffer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,ADDR"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DATAPTR_SET,Hardware BCH ECC Loopback Data Buffer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,ADDR"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DATAPTR_CLR,Hardware BCH ECC Loopback Data Buffer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,ADDR"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DATAPTR_TOG,Hardware BCH ECC Loopback Data Buffer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,ADDR"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "METAPTR,Hardware BCH ECC Loopback Metadata Buffer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,ADDR"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "METAPTR_SET,Hardware BCH ECC Loopback Metadata Buffer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,ADDR"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "METAPTR_CLR,Hardware BCH ECC Loopback Metadata Buffer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,ADDR"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "METAPTR_TOG,Hardware BCH ECC Loopback Metadata Buffer Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,ADDR"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "LAYOUTSELECT,Hardware ECC Accelerator Layout Select Register"
|
|
bitfld.long 0x00 30.--31. "CS15_SELECT,CS15_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "CS14_SELECT,CS14_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "CS13_SELECT,CS13_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "CS12_SELECT,CS12_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CS11_SELECT,CS11_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "CS10_SELECT,CS10_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "CS9_SELECT,CS9_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "CS8_SELECT,CS8_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "CS7_SELECT,CS7_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "CS6_SELECT,CS6_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "CS5_SELECT,CS5_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CS4_SELECT,CS4_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CS3_SELECT,CS3_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "CS2_SELECT,CS2_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "CS1_SELECT,CS1_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CS0_SELECT,CS0_SELECT" "0,1,2,3"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "LAYOUTSELECT_SET,Hardware ECC Accelerator Layout Select Register"
|
|
bitfld.long 0x00 30.--31. "CS15_SELECT,CS15_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "CS14_SELECT,CS14_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "CS13_SELECT,CS13_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "CS12_SELECT,CS12_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CS11_SELECT,CS11_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "CS10_SELECT,CS10_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "CS9_SELECT,CS9_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "CS8_SELECT,CS8_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "CS7_SELECT,CS7_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "CS6_SELECT,CS6_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "CS5_SELECT,CS5_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CS4_SELECT,CS4_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CS3_SELECT,CS3_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "CS2_SELECT,CS2_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "CS1_SELECT,CS1_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CS0_SELECT,CS0_SELECT" "0,1,2,3"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "LAYOUTSELECT_CLR,Hardware ECC Accelerator Layout Select Register"
|
|
eventfld.long 0x00 30.--31. "CS15_SELECT,CS15_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 28.--29. "CS14_SELECT,CS14_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 26.--27. "CS13_SELECT,CS13_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 24.--25. "CS12_SELECT,CS12_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 22.--23. "CS11_SELECT,CS11_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 20.--21. "CS10_SELECT,CS10_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 18.--19. "CS9_SELECT,CS9_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 16.--17. "CS8_SELECT,CS8_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 14.--15. "CS7_SELECT,CS7_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 12.--13. "CS6_SELECT,CS6_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 10.--11. "CS5_SELECT,CS5_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 8.--9. "CS4_SELECT,CS4_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 6.--7. "CS3_SELECT,CS3_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 4.--5. "CS2_SELECT,CS2_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 2.--3. "CS1_SELECT,CS1_SELECT" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 0.--1. "CS0_SELECT,CS0_SELECT" "0,1,2,3"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "LAYOUTSELECT_TOG,Hardware ECC Accelerator Layout Select Register"
|
|
bitfld.long 0x00 30.--31. "CS15_SELECT,CS15_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "CS14_SELECT,CS14_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "CS13_SELECT,CS13_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "CS12_SELECT,CS12_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CS11_SELECT,CS11_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "CS10_SELECT,CS10_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "CS9_SELECT,CS9_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "CS8_SELECT,CS8_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "CS7_SELECT,CS7_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "CS6_SELECT,CS6_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "CS5_SELECT,CS5_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CS4_SELECT,CS4_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "CS3_SELECT,CS3_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "CS2_SELECT,CS2_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "CS1_SELECT,CS1_SELECT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CS0_SELECT,CS0_SELECT" "0,1,2,3"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FLASH0LAYOUT0,Hardware BCH ECC Flash 0 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECC0,ECC0" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FLASH0LAYOUT0_SET,Hardware BCH ECC Flash 0 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECC0,ECC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FLASH0LAYOUT0_CLR,Hardware BCH ECC Flash 0 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
eventfld.long 0x00 11.--15. "ECC0,ECC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
eventfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FLASH0LAYOUT0_TOG,Hardware BCH ECC Flash 0 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECC0,ECC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "FLASH0LAYOUT1,Hardware BCH ECC Flash 0 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECCN,ECCN" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FLASH0LAYOUT1_SET,Hardware BCH ECC Flash 0 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECCN,ECCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "FLASH0LAYOUT1_CLR,Hardware BCH ECC Flash 0 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
eventfld.long 0x00 11.--15. "ECCN,ECCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
eventfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "FLASH0LAYOUT1_TOG,Hardware BCH ECC Flash 0 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECCN,ECCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "FLASH1LAYOUT0,Hardware BCH ECC Flash 1 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECC0,ECC0" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "FLASH1LAYOUT0_SET,Hardware BCH ECC Flash 1 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECC0,ECC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "FLASH1LAYOUT0_CLR,Hardware BCH ECC Flash 1 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
eventfld.long 0x00 11.--15. "ECC0,ECC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
eventfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "FLASH1LAYOUT0_TOG,Hardware BCH ECC Flash 1 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECC0,ECC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "FLASH1LAYOUT1,Hardware BCH ECC Flash 1 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECCN,ECCN" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "FLASH1LAYOUT1_SET,Hardware BCH ECC Flash 1 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECCN,ECCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "FLASH1LAYOUT1_CLR,Hardware BCH ECC Flash 1 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
eventfld.long 0x00 11.--15. "ECCN,ECCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
eventfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "FLASH1LAYOUT1_TOG,Hardware BCH ECC Flash 1 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECCN,ECCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FLASH2LAYOUT0,Hardware BCH ECC Flash 2 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECC0,ECC0" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "FLASH2LAYOUT0_SET,Hardware BCH ECC Flash 2 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECC0,ECC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "FLASH2LAYOUT0_CLR,Hardware BCH ECC Flash 2 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
eventfld.long 0x00 11.--15. "ECC0,ECC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
eventfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "FLASH2LAYOUT0_TOG,Hardware BCH ECC Flash 2 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECC0,ECC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "FLASH2LAYOUT1,Hardware BCH ECC Flash 2 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECCN,ECCN" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FLASH2LAYOUT1_SET,Hardware BCH ECC Flash 2 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECCN,ECCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FLASH2LAYOUT1_CLR,Hardware BCH ECC Flash 2 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
eventfld.long 0x00 11.--15. "ECCN,ECCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
eventfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "FLASH2LAYOUT1_TOG,Hardware BCH ECC Flash 2 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECCN,ECCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "FLASH3LAYOUT0,Hardware BCH ECC Flash 3 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECC0,ECC0" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "FLASH3LAYOUT0_SET,Hardware BCH ECC Flash 3 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECC0,ECC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "FLASH3LAYOUT0_CLR,Hardware BCH ECC Flash 3 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
eventfld.long 0x00 11.--15. "ECC0,ECC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
eventfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "FLASH3LAYOUT0_TOG,Hardware BCH ECC Flash 3 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "NBLOCKS,NBLOCKS"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "META_SIZE,META_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECC0,ECC0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATA0_SIZE,DATA0_SIZE"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "FLASH3LAYOUT1,Hardware BCH ECC Flash 3 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECCN,ECCN" "0: No ECC to be performed,1: ECC 2 to be performed,2: ECC 4 to be performed,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ECC 60 to be performed,31: ECC 62 to be performed"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "FLASH3LAYOUT1_SET,Hardware BCH ECC Flash 3 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECCN,ECCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "FLASH3LAYOUT1_CLR,Hardware BCH ECC Flash 3 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
eventfld.long 0x00 11.--15. "ECCN,ECCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
eventfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "FLASH3LAYOUT1_TOG,Hardware BCH ECC Flash 3 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PAGE_SIZE,PAGE_SIZE"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "ECCN,ECCN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "GF13_0_GF14_1,GF13_0_GF14_1" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "DATAN_SIZE,DATAN_SIZE"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DEBUG0,Hardware BCH ECC Debug Register0"
|
|
hexmask.long.word 0x00 16.--24. 1. "KES_DEBUG_SYNDROME_SYMBOL,KES_DEBUG_SYNDROME_SYMBOL"
|
|
newline
|
|
bitfld.long 0x00 15. "KES_DEBUG_SHIFT_SYND,KES_DEBUG_SHIFT_SYND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "KES_DEBUG_PAYLOAD_FLAG,KES_DEBUG_PAYLOAD_FLAG" "?,1: Payload is set for 512 bytes data block"
|
|
newline
|
|
bitfld.long 0x00 13. "KES_DEBUG_MODE4K,KES_DEBUG_MODE4K" "?,1: Mode is set for 4K NAND pages"
|
|
newline
|
|
bitfld.long 0x00 12. "KES_DEBUG_KICK,KES_DEBUG_KICK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "KES_STANDALONE,KES_STANDALONE" "0: Bus master address generator for SYND_GEN..,1: Bus master address generator always addresses.."
|
|
newline
|
|
bitfld.long 0x00 10. "KES_DEBUG_STEP,KES_DEBUG_STEP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "KES_DEBUG_STALL,KES_DEBUG_STALL" "0: KES FSM proceeds to next block supplied by..,1: KES FSM waits after current equations are.."
|
|
newline
|
|
bitfld.long 0x00 8. "BM_KES_TEST_BYPASS,BM_KES_TEST_BYPASS" "0: Bus master address generator for SYND_GEN..,1: Bus master address generator always addresses.."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DEBUG_REG_SELECT,DEBUG_REG_SELECT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DEBUG0_SET,Hardware BCH ECC Debug Register0"
|
|
hexmask.long.word 0x00 16.--24. 1. "KES_DEBUG_SYNDROME_SYMBOL,KES_DEBUG_SYNDROME_SYMBOL"
|
|
newline
|
|
bitfld.long 0x00 15. "KES_DEBUG_SHIFT_SYND,KES_DEBUG_SHIFT_SYND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "KES_DEBUG_PAYLOAD_FLAG,KES_DEBUG_PAYLOAD_FLAG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "KES_DEBUG_MODE4K,KES_DEBUG_MODE4K" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "KES_DEBUG_KICK,KES_DEBUG_KICK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "KES_STANDALONE,KES_STANDALONE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "KES_DEBUG_STEP,KES_DEBUG_STEP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "KES_DEBUG_STALL,KES_DEBUG_STALL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "BM_KES_TEST_BYPASS,BM_KES_TEST_BYPASS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DEBUG_REG_SELECT,DEBUG_REG_SELECT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DEBUG0_CLR,Hardware BCH ECC Debug Register0"
|
|
hexmask.long.word 0x00 16.--24. 1. "KES_DEBUG_SYNDROME_SYMBOL,KES_DEBUG_SYNDROME_SYMBOL"
|
|
newline
|
|
eventfld.long 0x00 15. "KES_DEBUG_SHIFT_SYND,KES_DEBUG_SHIFT_SYND" "0,1"
|
|
newline
|
|
eventfld.long 0x00 14. "KES_DEBUG_PAYLOAD_FLAG,KES_DEBUG_PAYLOAD_FLAG" "0,1"
|
|
newline
|
|
eventfld.long 0x00 13. "KES_DEBUG_MODE4K,KES_DEBUG_MODE4K" "0,1"
|
|
newline
|
|
eventfld.long 0x00 12. "KES_DEBUG_KICK,KES_DEBUG_KICK" "0,1"
|
|
newline
|
|
eventfld.long 0x00 11. "KES_STANDALONE,KES_STANDALONE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 10. "KES_DEBUG_STEP,KES_DEBUG_STEP" "0,1"
|
|
newline
|
|
eventfld.long 0x00 9. "KES_DEBUG_STALL,KES_DEBUG_STALL" "0,1"
|
|
newline
|
|
eventfld.long 0x00 8. "BM_KES_TEST_BYPASS,BM_KES_TEST_BYPASS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 0.--5. "DEBUG_REG_SELECT,DEBUG_REG_SELECT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DEBUG0_TOG,Hardware BCH ECC Debug Register0"
|
|
hexmask.long.word 0x00 16.--24. 1. "KES_DEBUG_SYNDROME_SYMBOL,KES_DEBUG_SYNDROME_SYMBOL"
|
|
newline
|
|
bitfld.long 0x00 15. "KES_DEBUG_SHIFT_SYND,KES_DEBUG_SHIFT_SYND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "KES_DEBUG_PAYLOAD_FLAG,KES_DEBUG_PAYLOAD_FLAG" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "KES_DEBUG_MODE4K,KES_DEBUG_MODE4K" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "KES_DEBUG_KICK,KES_DEBUG_KICK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "KES_STANDALONE,KES_STANDALONE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "KES_DEBUG_STEP,KES_DEBUG_STEP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "KES_DEBUG_STALL,KES_DEBUG_STALL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "BM_KES_TEST_BYPASS,BM_KES_TEST_BYPASS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DEBUG_REG_SELECT,DEBUG_REG_SELECT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "DBGKESREAD,KES Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "DBGKESREAD_SET,KES Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "DBGKESREAD_CLR,KES Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "DBGKESREAD_TOG,KES Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "DBGCSFEREAD,Chien Search Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "DBGCSFEREAD_SET,Chien Search Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "DBGCSFEREAD_CLR,Chien Search Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "DBGCSFEREAD_TOG,Chien Search Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "DBGSYNDGENREAD,Syndrome Generator Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "DBGSYNDGENREAD_SET,Syndrome Generator Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "DBGSYNDGENREAD_CLR,Syndrome Generator Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "DBGSYNDGENREAD_TOG,Syndrome Generator Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "DBGAHBMREAD,Bus Master and ECC Controller Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "DBGAHBMREAD_SET,Bus Master and ECC Controller Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "DBGAHBMREAD_CLR,Bus Master and ECC Controller Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x14C++0x03
|
|
line.long 0x00 "DBGAHBMREAD_TOG,Bus Master and ECC Controller Debug Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "VALUES,VALUES"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "BLOCKNAME,Block Name Register"
|
|
hexmask.long 0x00 0.--31. 1. "NAME,NAME"
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "BLOCKNAME_SET,Block Name Register"
|
|
hexmask.long 0x00 0.--31. 1. "NAME,NAME"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "BLOCKNAME_CLR,Block Name Register"
|
|
hexmask.long 0x00 0.--31. 1. "NAME,NAME"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "BLOCKNAME_TOG,Block Name Register"
|
|
hexmask.long 0x00 0.--31. 1. "NAME,NAME"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "VERSION,BCH Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,MAJOR"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,MINOR"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "STEP,STEP"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "VERSION_SET,BCH Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,MAJOR"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,MINOR"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "STEP,STEP"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "VERSION_CLR,BCH Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,MAJOR"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,MINOR"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "STEP,STEP"
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "VERSION_TOG,BCH Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,MAJOR"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,MINOR"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "STEP,STEP"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "DEBUG1,Hardware BCH ECC Debug Register 1"
|
|
bitfld.long 0x00 31. "DEBUG1_PREERASECHK,DEBUG1_PREERASECHK" "0: Turn off pre-erase check,1: Turn on pre-erase check"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "ERASED_ZERO_COUNT,ERASED_ZERO_COUNT"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "DEBUG1_SET,Hardware BCH ECC Debug Register 1"
|
|
bitfld.long 0x00 31. "DEBUG1_PREERASECHK,DEBUG1_PREERASECHK" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "ERASED_ZERO_COUNT,ERASED_ZERO_COUNT"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "DEBUG1_CLR,Hardware BCH ECC Debug Register 1"
|
|
eventfld.long 0x00 31. "DEBUG1_PREERASECHK,DEBUG1_PREERASECHK" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "ERASED_ZERO_COUNT,ERASED_ZERO_COUNT"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "DEBUG1_TOG,Hardware BCH ECC Debug Register 1"
|
|
bitfld.long 0x00 31. "DEBUG1_PREERASECHK,DEBUG1_PREERASECHK" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "ERASED_ZERO_COUNT,ERASED_ZERO_COUNT"
|
|
tree.end
|
|
tree "CM4_LPCG_LPI2C"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x41630000
|
|
else
|
|
base ad:0x37630000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_LPI2C_0,na"
|
|
rbitfld.long 0x00 7. "lpi2c1_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "lpi2c1_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "lpi2c1_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "lpi2c1_lpi2c_clk_HWEN_AND_lpi2c1_lpi2c_div_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CM4_LPCG_LPIT"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x41610000
|
|
else
|
|
base ad:0x37610000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_LPIT_0,na"
|
|
rbitfld.long 0x00 7. "lpit1_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "lpit1_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "lpit1_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "lpit1_ipg_per_clk_HWEN_AND_lpit1_ipg_ungated_per_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CM4_LPCG_LPUART"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x41620000
|
|
else
|
|
base ad:0x37620000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_LPUART_0,na"
|
|
rbitfld.long 0x00 7. "lpuart1_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "lpuart1_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "lpuart1_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "lpuart1_lpuart_baud_clk_HWEN_AND_lpuart1_lpuart_baud_gated_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CM4_LPCG_MMCAU_HCLK"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x415F0000
|
|
else
|
|
base ad:0x375F0000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MMCAU_HCLK_0,na"
|
|
rbitfld.long 0x00 3. "cm4_mmcau_hclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 1. "cm4_mmcau_hclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "cm4_mmcau_hclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CM4_LPCG_TCMC_HCLK"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x415E0000
|
|
else
|
|
base ad:0x375E0000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_TCMC_HCLK_0,na"
|
|
rbitfld.long 0x00 3. "cm4_tcmc_hclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 1. "cm4_tcmc_hclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "cm4_tcmc_hclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CM4_LPCG_TPM"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x41600000
|
|
else
|
|
base ad:0x37600000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_TPM_0,na"
|
|
rbitfld.long 0x00 7. "tpm1_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 5. "tpm1_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "tpm1_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "tpm1_lptpm_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "tpm1_lptpm_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "tpm1_lptpm_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CONNECTIVITY_LPCG_ENET_QOS"
|
|
base ad:0x5B240000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_enet_qos_0,na"
|
|
rbitfld.long 0x00 27. "enet_qos_clk_csr_i_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "enet_qos_clk_csr_i_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 24. "enet_qos_clk_csr_i_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ccm_enet_qos_clock_generate_enet_qos_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ccm_enet_qos_clock_generate_enet_qos_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ccm_enet_qos_clock_generate_enet_qos_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "enet_qos_aclk_i_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "enet_qos_aclk_i_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "enet_qos_aclk_i_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "enet_qos_mem_clk_ptp_ref_i_STOP_AND_enet_qos_mem_mem_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "enet_qos_mem_clk_ptp_ref_i_SWEN_AND_enet_qos_mem_mem_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "enet_qos_mem_clk_ptp_ref_i_HWEN_AND_enet_qos_mem_mem_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "enet_qos_clk_ptp_ref_i_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "enet_qos_clk_ptp_ref_i_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "enet_qos_clk_ptp_ref_i_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CONNECTIVITY_LPCG_ENET0"
|
|
base ad:0x5B230000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_enet1_0,na"
|
|
rbitfld.long 0x00 23. "enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 20. "enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "enet1_ipg_clk_HWEN_AND_enet1_ipg_clk_mac0_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 15. "enet1_clkdiv_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "enet1_clkdiv_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 12. "enet1_clkdiv_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "enet_mem1_mac0_txmem_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "enet_mem1_mac0_txmem_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "enet_mem1_mac0_txmem_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "enet1_2x_txclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "enet1_2x_txclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "enet1_2x_txclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "enet1_ipg_clk_time_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "enet1_ipg_clk_time_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "enet1_ipg_clk_time_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "LPCG_lpcg_enet1_4,na"
|
|
rbitfld.long 0x00 3. "enet1_mac0_rxclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "enet1_mac0_rxclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "enet1_mac0_rxclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CONNECTIVITY_LPCG_RAWNAND"
|
|
base ad:0x5B290000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_rawnand_0,na"
|
|
rbitfld.long 0x00 23. "rawnand_u_bch_input_apb_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "rawnand_u_bch_input_apb_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "rawnand_u_bch_input_apb_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "rawnand_u_gpmi_input_apb_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "rawnand_u_gpmi_input_apb_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "rawnand_u_gpmi_input_apb_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "rawnand_u_gpmi_bch_input_gpmi_io_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "rawnand_u_gpmi_bch_input_bch_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "rawnand_u_gpmi_bch_input_bch_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "rawnand_u_gpmi_bch_input_bch_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "LPCG_lpcg_rawnand_4,na"
|
|
rbitfld.long 0x00 19. "apbhdma_hclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "apbhdma_hclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "apbhdma_hclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CONNECTIVITY_LPCG_USBO2"
|
|
base ad:0x5B260000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_usbo2_0,na"
|
|
rbitfld.long 0x00 27. "usbo2_ipg_ahb_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "usbo2_ipg_ahb_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 24. "usbo2_ipg_ahb_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "usbo2_ipg_clk_s_pl301_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "usbo2_ipg_clk_s_pl301_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "usbo2_ipg_clk_s_pl301_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "usbo2_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "usbo2_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "usbo2_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CONNECTIVITY_LPCG_USBPHY_"
|
|
tree "CONNECTIVITY__LPCG_USBPHY_1"
|
|
base ad:0x5B270000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_usbphy_1_0,na"
|
|
rbitfld.long 0x00 31. "da_ip_hs_usb2phy_28fdsoi_1_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "da_ip_hs_usb2phy_28fdsoi_1_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 28. "da_ip_hs_usb2phy_28fdsoi_1_ipg_clk_HWEN_AND_da_ip_hs_usb2phy_28fdsoi_1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CONNECTIVITY__LPCG_USBPHY_2"
|
|
base ad:0x5B280000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_usbphy_2_0,na"
|
|
rbitfld.long 0x00 31. "da_ip_hs_usb2phy_28fdsoi_2_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_2_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "da_ip_hs_usb2phy_28fdsoi_2_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_2_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 28. "da_ip_hs_usb2phy_28fdsoi_2_ipg_clk_HWEN_AND_da_ip_hs_usb2phy_28fdsoi_2_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "CONNECTIVITY_LPCG_USDHC"
|
|
tree "CONNECTIVITY__LPCG_USDHC0"
|
|
base ad:0x5B200000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_usdhc1_0,na"
|
|
rbitfld.long 0x00 23. "usdhc1_hclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "usdhc1_hclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "usdhc1_hclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "usdhc1_ipg_clk_s_HWEN_AND_usdhc1_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "usdhc1_ipg_clk_perclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "usdhc1_ipg_clk_perclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "usdhc1_ipg_clk_perclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CONNECTIVITY__LPCG_USDHC1"
|
|
base ad:0x5B210000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_usdhc2_0,na"
|
|
rbitfld.long 0x00 23. "usdhc2_hclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "usdhc2_hclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "usdhc2_hclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "usdhc2_ipg_clk_s_HWEN_AND_usdhc2_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "usdhc2_ipg_clk_perclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "usdhc2_ipg_clk_perclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "usdhc2_ipg_clk_perclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "CONNECTIVITY__LPCG_USDHC2"
|
|
base ad:0x5B220000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_usdhc3_0,na"
|
|
rbitfld.long 0x00 23. "usdhc3_hclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "usdhc3_hclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "usdhc3_hclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "usdhc3_ipg_clk_s_STOP_AND_usdhc3_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "usdhc3_ipg_clk_s_SWEN_AND_usdhc3_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "usdhc3_ipg_clk_s_HWEN_AND_usdhc3_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "usdhc3_ipg_clk_perclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "usdhc3_ipg_clk_perclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "usdhc3_ipg_clk_perclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "D_IP_FLEXCAN3_SYN (CAN)"
|
|
repeat 3. (list 0. 1. 2.) (list ad:0x5A8D0000 ad:0x5A8E0000 ad:0x5A8F0000)
|
|
tree "ADMA__CAN$1"
|
|
base $2
|
|
sif cpuis("IMX8D?L-CM4")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration register"
|
|
bitfld.long 0x00 31. "MDIS,Module Disable" "0: Enable the FlexCAN module,1: Disable the FlexCAN module"
|
|
bitfld.long 0x00 30. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode,1: Enabled to enter Freeze mode"
|
|
newline
|
|
bitfld.long 0x00 29. "RFEN,Rx FIFO Enable" "0: Rx FIFO not enabled,1: Rx FIFO enabled"
|
|
bitfld.long 0x00 28. "HALT,Halt FlexCAN" "0: No Freeze mode request,1: Enters Freeze mode if the FRZ bit is asserted"
|
|
newline
|
|
rbitfld.long 0x00 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN module is either in Normal mode..,1: FlexCAN module is either in Disable mode Doze.."
|
|
bitfld.long 0x00 26. "WAKMSK,Wake Up Interrupt Mask" "0: Wake Up interrupt is disabled,1: Wake Up interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "SOFTRST,Soft Reset" "0: SOFTRST_no_reset_request,1: Resets the registers affected by soft reset"
|
|
rbitfld.long 0x00 24. "FRZACK,Freeze Mode Acknowledge" "0: FlexCAN not in Freeze mode prescaler running,1: FlexCAN in Freeze mode prescaler stopped"
|
|
newline
|
|
bitfld.long 0x00 22. "SLFWAK,Self Wake Up" "0: FlexCAN Self Wake Up feature is disabled,1: FlexCAN Self Wake Up feature is enabled"
|
|
bitfld.long 0x00 21. "WRNEN,Warning Interrupt Enable" "0: TWRNINT and RWRNINT bits are zero independent..,1: TWRNINT and RWRNINT bits are set when the.."
|
|
newline
|
|
rbitfld.long 0x00 20. "LPMACK,Low-Power Mode Acknowledge" "0: FlexCAN is not in a low-power mode,1: FlexCAN is in a low-power mode"
|
|
bitfld.long 0x00 19. "WAKSRC,Wake Up Source" "0: FlexCAN uses the unfiltered Rx input to..,1: FlexCAN uses the filtered Rx input to detect.."
|
|
newline
|
|
bitfld.long 0x00 18. "DOZE,Doze Mode Enable" "0: FlexCAN is not enabled to enter low-power..,1: FlexCAN is enabled to enter low-power mode.."
|
|
bitfld.long 0x00 17. "SRXDIS,Self Reception Disable" "0: Self-reception enabled,1: Self-reception disabled"
|
|
newline
|
|
bitfld.long 0x00 16. "IRMQ,Individual Rx Masking And Queue Enable" "0: Individual Rx masking and queue feature are..,1: Individual Rx masking and queue feature are.."
|
|
bitfld.long 0x00 15. "DMA,DMA Enable" "0: DMA feature for RX FIFO disabled,1: DMA feature for RX FIFO enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "LPRIOEN,Local Priority Enable" "0: Local Priority disabled,1: Local Priority enabled"
|
|
bitfld.long 0x00 12. "AEN,Abort Enable" "0: Abort disabled,1: Abort enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FDEN,CAN FD operation enable" "0: CAN FD is disabled,1: CAN FD is enabled"
|
|
bitfld.long 0x00 8.--9. "IDAM,ID Acceptance Mode" "0: Format A,1: Format B,2: Format C,3: Format D"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB,Number Of The Last Message Buffer"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRESDIV,Prescaler Division Factor"
|
|
bitfld.long 0x00 22.--23. "RJW,Resync Jump Width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Bus Off interrupt disabled,1: Bus Off interrupt enabled"
|
|
bitfld.long 0x00 14. "ERRMSK,Error Interrupt Mask" "0: Error interrupt disabled,1: Error interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "CLKSRC,CAN Engine Clock Source" "0: The CAN engine clock source is the oscillator..,1: The CAN engine clock source is the peripheral.."
|
|
bitfld.long 0x00 12. "LPB,Loop Back Mode" "0: Loop Back disabled,1: Loop Back enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TWRNMSK,Tx Warning Interrupt Mask" "0: Tx Warning interrupt disabled,1: Tx Warning interrupt enabled"
|
|
bitfld.long 0x00 10. "RWRNMSK,Rx Warning Interrupt Mask" "0: Rx Warning interrupt disabled,1: Rx Warning interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SMP,CAN Bit Sampling" "0: Just one sample is used to determine the bit..,1: Three samples are used to determine the value.."
|
|
bitfld.long 0x00 6. "BOFFREC,Bus Off Recovery" "0: Automatic recovering from Bus Off state enabled,1: Automatic recovering from Bus Off state.."
|
|
newline
|
|
bitfld.long 0x00 5. "TSYN,Timer Sync" "0: Timer sync feature disabled,1: Timer sync feature enabled"
|
|
bitfld.long 0x00 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted..,1: Lowest number buffer is transmitted first"
|
|
newline
|
|
bitfld.long 0x00 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated,1: FlexCAN module operates in Listen-Only mode"
|
|
bitfld.long 0x00 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMER,Free Running Timer"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMER,Timer Value"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "MG,Rx Mailboxes Global Mask Bits"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RX14MASK,Rx 14 Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "RX14M,Rx Buffer 14 Mask Bits"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RX15MASK,Rx 15 Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "RX15M,Rx Buffer 15 Mask Bits"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ECR,Error Counter"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for fast bits"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for fast bits"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXERRCNT,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXERRCNT,Transmit Error Counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ESR1,Error and Status 1 register"
|
|
rbitfld.long 0x00 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as recessive is.."
|
|
rbitfld.long 0x00 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as dominant is received.."
|
|
newline
|
|
rbitfld.long 0x00 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A CRC error occurred since last read of this.."
|
|
rbitfld.long 0x00 27. "FRMERR_FAST,Form Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A form error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A stuffing error occurred since last read of.."
|
|
eventfld.long 0x00 21. "ERROVR,Error Overrun" "0: Overrun has not occurred,1: Overrun has occurred"
|
|
newline
|
|
eventfld.long 0x00 20. "ERRINT_FAST,Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set" "0: errors_data_phase_no,1: Indicates setting of any error bit detected.."
|
|
eventfld.long 0x00 19. "BOFFDONEINT,Bus Off Done Interrupt" "0: No such occurrence,1: FlexCAN module has completed Bus Off process"
|
|
newline
|
|
rbitfld.long 0x00 18. "SYNCH,CAN Synchronization Status" "0: FlexCAN is not synchronized to the CAN bus,1: FlexCAN is synchronized to the CAN bus"
|
|
eventfld.long 0x00 17. "TWRNINT,Tx Warning Interrupt Flag" "0: No such occurrence,1: The Tx error counter transitioned from less.."
|
|
newline
|
|
eventfld.long 0x00 16. "RWRNINT,Rx Warning Interrupt Flag" "0: No such occurrence,1: The Rx error counter transitioned from less.."
|
|
rbitfld.long 0x00 15. "BIT1ERR,Bit1 Error" "0: No such occurrence,1: At least one bit sent as recessive is.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIT0ERR,Bit0 Error" "0: No such occurrence,1: At least one bit sent as dominant is received.."
|
|
rbitfld.long 0x00 13. "ACKERR,Acknowledge Error" "0: No such occurrence,1: An ACK error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 12. "CRCERR,Cyclic Redundancy Check Error" "0: No such occurrence,1: A CRC error occurred since last read of this.."
|
|
rbitfld.long 0x00 11. "FRMERR,Form Error" "0: No such occurrence,1: A Form Error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 10. "STFERR,Stuffing Error" "0: No such occurrence,1: A stuffing error occurred since last read of.."
|
|
rbitfld.long 0x00 9. "TXWRN,TX Error Warning" "0: No such occurrence,1: TXERRCNT is greater than or equal to 96"
|
|
newline
|
|
rbitfld.long 0x00 8. "RXWRN,Rx Error Warning" "0: No such occurrence,1: RXERRCNT is greater than or equal to 96"
|
|
rbitfld.long 0x00 7. "IDLE,IDLE" "0: No such occurrence,1: CAN bus is now IDLE"
|
|
newline
|
|
rbitfld.long 0x00 6. "TX,FlexCAN In Transmission" "0: FlexCAN is not transmitting a message,1: FlexCAN is transmitting a message"
|
|
rbitfld.long 0x00 4.--5. "FLTCONF,Fault Confinement State" "0: error_active,1: error_passive,2: bus_off,3: bus_off"
|
|
newline
|
|
rbitfld.long 0x00 3. "RX,FlexCAN In Reception" "0: FlexCAN is not receiving a message,1: FlexCAN is receiving a message"
|
|
eventfld.long 0x00 2. "BOFFINT,Bus Off Interrupt" "0: No such occurrence,1: FlexCAN module entered Bus Off state"
|
|
newline
|
|
eventfld.long 0x00 1. "ERRINT,Error Interrupt" "0: No such occurrence,1: Indicates setting of any error bit in the.."
|
|
eventfld.long 0x00 0. "WAKINT,Wake-Up Interrupt" "0: No such occurrence,1: Indicates a recessive to dominant transition.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IMASK2,Interrupt Masks 2 register"
|
|
hexmask.long 0x00 0.--31. 1. "BUF63TO32M,Buffer MBi Mask"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMASK1,Interrupt Masks 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "BUF31TO0M,Buffer MBi Mask"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IFLAG2,Interrupt Flags 2 register"
|
|
hexmask.long 0x00 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IFLAG1,Interrupt Flags 1 register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt"
|
|
eventfld.long 0x00 7. "BUF7I,Buffer MB7 Interrupt Or Rx FIFO Overflow" "0: No occurrence of MB7 completing..,1: MB7 completed transmission/reception when.."
|
|
newline
|
|
eventfld.long 0x00 6. "BUF6I,Buffer MB6 Interrupt Or Rx FIFO Warning" "0: No occurrence of MB6 completing..,1: MB6 completed transmission/reception when.."
|
|
eventfld.long 0x00 5. "BUF5I,Buffer MB5 Interrupt Or Frames available in Rx FIFO" "0: No occurrence of MB5 completing..,1: MB5 completed transmission/reception when.."
|
|
newline
|
|
eventfld.long 0x00 1.--4. "BUF4TO1I,Buffer MBi Interrupt Or Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
eventfld.long 0x00 0. "BUF0I,Buffer MB0 Interrupt Or Clear FIFO bit" "0: The corresponding buffer has no occurrence of..,1: The corresponding buffer has successfully.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL2,Control 2 register"
|
|
bitfld.long 0x00 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames" "0: ERRINT_FAST error interrupt disabled,1: ERRINT_FAST error interrupt enabled"
|
|
bitfld.long 0x00 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Bus off done interrupt disabled,1: Bus off done interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "RFFN,Number Of Rx FIFO Filters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. "TASD,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 18. "MRP,Mailboxes Reception Priority" "0: Matching starts from Rx FIFO and continues on..,1: Matching starts from mailboxes and continues.."
|
|
bitfld.long 0x00 17. "RRS,Remote Request Storing" "0: remote_response_frame_not_generated,1: remote_response_frame_generated"
|
|
newline
|
|
bitfld.long 0x00 16. "EACEN,Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes" "0: Rx mailbox filter's IDE bit is always..,1: Enables the comparison of both Rx mailbox.."
|
|
bitfld.long 0x00 14. "PREXCEN,Protocol Exception Enable" "0: Protocol exception is disabled,1: Protocol exception is enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "ISOCANFDEN,ISO CAN FD Enable" "0: FlexCAN operates using the non-ISO CAN FD..,1: FlexCAN operates using the ISO CAN FD.."
|
|
bitfld.long 0x00 11. "EDFLTDIS,Edge Filter Disable" "0: Edge filter is enabled,1: Edge filter is disabled"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "ESR2,Error and Status 2 register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "LPTM,Lowest Priority Tx Mailbox"
|
|
bitfld.long 0x00 14. "VPS,Valid Priority Status" "0: Contents of IMB and LPTM are invalid,1: Contents of IMB and LPTM are valid"
|
|
newline
|
|
bitfld.long 0x00 13. "IMB,Inactive Mailbox" "0: If ESR2[VPS] is asserted the ESR2[LPTM] is..,1: If ESR2[VPS] is asserted there is at least.."
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CRCR,CRC register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "MBCRC,CRC Mailbox"
|
|
hexmask.long.word 0x00 0.--14. 1. "TXCRC,Transmitted CRC value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "FGM,Rx FIFO Global Mask Bits"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "RXFIR,Rx FIFO Information register"
|
|
hexmask.long.word 0x00 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CBT,CAN Bit Timing register"
|
|
bitfld.long 0x00 31. "BTF,Bit Timing Format Enable" "0: Extended bit time definitions disabled,1: Extended bit time definitions enabled"
|
|
hexmask.long.word 0x00 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "ERJW,Extended Resync Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--15. "EPROPSEG,Extended Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "EPSEG1,Extended Phase Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "EPSEG2,Extended Phase Segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 64. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x880)++0x03
|
|
line.long 0x00 "RXIMR[$1],Rx Individual Mask registers $1"
|
|
hexmask.long 0x00 0.--31. 1. "MI,Individual Mask Bits"
|
|
repeat.end
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "FDCTRL,CAN FD Control register"
|
|
bitfld.long 0x00 31. "FDRATE,Bit Rate Switch Enable" "0: Transmit a frame in nominal rate,1: Transmit a frame with bit rate switching if.."
|
|
bitfld.long 0x00 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: Selects 8 bytes per message buffer,1: Selects 16 bytes per message buffer,2: Selects 32 bytes per message buffer,3: Selects 64 bytes per message buffer"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: Selects 8 bytes per message buffer,1: Selects 16 bytes per message buffer,2: Selects 32 bytes per message buffer,3: Selects 64 bytes per message buffer"
|
|
bitfld.long 0x00 15. "TDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled"
|
|
newline
|
|
eventfld.long 0x00 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: Measured loop delay is in range,1: Measured loop delay is out of range"
|
|
bitfld.long 0x00 8.--12. "TDCOFF,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 0.--5. "TDCVAL,Transceiver Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "FDCBT,CAN FD Bit Timing register"
|
|
hexmask.long.word 0x00 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor"
|
|
bitfld.long 0x00 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 10.--14. "FPROPSEG,Fast Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "FDCRC,CAN FD CRC register"
|
|
hexmask.long.byte 0x00 24.--30. 1. "FD_MBCRC,CRC Mailbox Number for FD_TXCRC"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value"
|
|
endif
|
|
repeat 64. (increment 0 1)(increment 0 0x10)
|
|
tree "MB[$1]"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "CS,Message Buffer index CS Register"
|
|
bitfld.long 0x00 31. "EDL,Extended Data Length" "0,1"
|
|
bitfld.long 0x00 30. "BRS,Bit Rate Switch" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "ESI,Error State Indicator" "0,1"
|
|
bitfld.long 0x00 24.--27. "CODE,Message Buffer Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request" "0,1"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "TIME_STAMP,Free-Running Counter Time stamp"
|
|
group.long ($2+0x84)++0x03
|
|
line.long 0x00 "ID,Message Buffer index ID Register"
|
|
bitfld.long 0x00 29.--31. "PRIO,Local priority" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 18.--28. 1. "STD,Contains standard/extended (HIGH word) identifier of message buffer"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "EXT,Contains extended (LOW word) identifier of message buffer"
|
|
group.long ($2+0x88)++0x03
|
|
line.long 0x00 "WORD0,Message Buffer index WORD0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 3 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 2 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 1 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 0 of Rx/Tx frame"
|
|
group.long ($2+0x8C)++0x03
|
|
line.long 0x00 "WORD1,Message Buffer index WORD1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_4,Data byte 3 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_5,Data byte 2 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_6,Data byte 1 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_7,Data byte 0 of Rx/Tx frame"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "D_IP_FLEXTIMER32_SYN (FTM)"
|
|
repeat 2. (list 0. 1.) (list ad:0x5A8A0000 ad:0x5A8B0000)
|
|
tree "ADMA__FTM$1"
|
|
base $2
|
|
sif cpuis("IMX8D?L-CM4")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC,Status And Control"
|
|
bitfld.long 0x00 24.--27. "FLTPS,Filter Prescaler" "0: FLTPS_divideby1,1: FLTPS_divideby2,2: FLTPS_divideby3,3: FLTPS_divideby4,4: FLTPS_divideby5,5: FLTPS_divideby6,6: FLTPS_divideby7,7: FLTPS_divideby8,8: FLTPS_divideby9,9: FLTPS_divideby10,10: FLTPS_divideby11,11: FLTPS_divideby12,12: FLTPS_divideby13,13: FLTPS_divideby14,14: FLTPS_divideby15,15: FLTPS_divideby16"
|
|
bitfld.long 0x00 23. "PWMEN7,Channel 7 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 22. "PWMEN6,Channel 6 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 21. "PWMEN5,Channel 5 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "PWMEN4,Channel 4 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 19. "PWMEN3,Channel 3 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "PWMEN2,Channel 2 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 17. "PWMEN1,Channel 1 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "PWMEN0,Channel 0 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 9. "TOF,Timer Overflow Flag" "0: FTM counter has not overflowed,1: FTM counter has overflowed"
|
|
newline
|
|
bitfld.long 0x00 8. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
|
|
bitfld.long 0x00 7. "RF,Reload Flag" "0: A selected reload point did not happen,1: A selected reload point happened"
|
|
newline
|
|
bitfld.long 0x00 6. "RIE,Reload Point Interrupt Enable" "0: Reload point interrupt is disabled,1: Reload point interrupt is enabled"
|
|
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: FTM counter operates in Up Counting mode,1: FTM counter operates in Up-Down Counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CLKS,Clock Source Selection" "0: No clock selected,1: CLKS_ftminputclock,2: Fixed frequency clock,3: External clock"
|
|
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: PS_divideby1,1: PS_divideby2,2: PS_divideby4,3: PS_divideby8,4: PS_divideby16,5: PS_divideby32,6: PS_divideby64,7: PS_divideby128"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Counter Value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MOD,Modulo"
|
|
hexmask.long.word 0x00 0.--15. 1. "MOD,MOD"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CNTIN,Counter Initial Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "INIT,INIT"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "STATUS,Capture And Compare Status"
|
|
bitfld.long 0x00 7. "CH7F,Channel 7 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 6. "CH6F,Channel 6 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. "FAULTIE,Fault Interrupt Enable" "0: Fault control interrupt is disabled,1: Fault control interrupt is enabled"
|
|
bitfld.long 0x00 5.--6. "FAULTM,Fault Control Mode" "0: Fault control is disabled for all channels,1: Fault control is enabled for even channels..,2: Fault control is enabled for all channels and..,3: Fault control is enabled for all channels and.."
|
|
newline
|
|
bitfld.long 0x00 4. "CAPTEST,Capture Test Mode Enable" "0: Capture test mode is disabled,1: Capture test mode is enabled"
|
|
bitfld.long 0x00 3. "PWMSYNC,PWM Synchronization Mode" "0: No restrictions,1: Software trigger can only be used by MOD and.."
|
|
newline
|
|
bitfld.long 0x00 2. "WPDIS,Write Protection Disable" "0: Write protection is enabled,1: Write protection is disabled"
|
|
bitfld.long 0x00 1. "INIT,Initialize The Channels Output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "FTMEN,FTM Enable" "0: TPM compatibility,1: Free running counter and synchronization are.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SYNC,Synchronization"
|
|
bitfld.long 0x00 7. "SWSYNC,PWM Synchronization Software Trigger" "0: Software trigger is not selected,1: Software trigger is selected"
|
|
bitfld.long 0x00 6. "TRIG2,PWM Synchronization Hardware Trigger 2" "0: Trigger is disabled,1: Trigger is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "TRIG1,PWM Synchronization Hardware Trigger 1" "0: Trigger is disabled,1: Trigger is enabled"
|
|
bitfld.long 0x00 4. "TRIG0,PWM Synchronization Hardware Trigger 0" "0: Trigger is disabled,1: Trigger is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "SYNCHOM,Output Mask Synchronization" "0: OUTMASK register is updated with the value of..,1: OUTMASK register is updated with the value of.."
|
|
bitfld.long 0x00 2. "REINIT,FTM Counter Reinitialization by Synchronization" "0: FTM counter continues to count normally,1: FTM counter is updated with its initial value.."
|
|
newline
|
|
bitfld.long 0x00 1. "CNTMAX,Maximum Loading Point Enable" "0: The maximum loading point is disabled,1: The maximum loading point is enabled"
|
|
bitfld.long 0x00 0. "CNTMIN,Minimum Loading Point Enable" "0: The minimum loading point is disabled,1: The minimum loading point is enabled"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "OUTINIT,Initial State For Channels Output"
|
|
bitfld.long 0x00 7. "CH7OI,Channel 7 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
bitfld.long 0x00 6. "CH6OI,Channel 6 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5OI,Channel 5 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
bitfld.long 0x00 4. "CH4OI,Channel 4 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3OI,Channel 3 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
bitfld.long 0x00 2. "CH2OI,Channel 2 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1OI,Channel 1 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
bitfld.long 0x00 0. "CH0OI,Channel 0 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OUTMASK,Output Mask"
|
|
bitfld.long 0x00 7. "CH7OM,Channel 7 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
bitfld.long 0x00 6. "CH6OM,Channel 6 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5OM,Channel 5 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
bitfld.long 0x00 4. "CH4OM,Channel 4 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3OM,Channel 3 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
bitfld.long 0x00 2. "CH2OM,Channel 2 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1OM,Channel 1 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
bitfld.long 0x00 0. "CH0OM,Channel 0 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "COMBINE,Function For Linked Channels"
|
|
bitfld.long 0x00 31. "MCOMBINE3,Modified Combine Mode For n = 6" "0,1"
|
|
bitfld.long 0x00 30. "FAULTEN3,Fault Control Enable For n = 6" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
|
|
newline
|
|
bitfld.long 0x00 29. "SYNCEN3,Synchronization Enable For n = 6" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
|
|
bitfld.long 0x00 28. "DTEN3,Deadtime Enable For n = 6" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
|
|
newline
|
|
bitfld.long 0x00 27. "DECAP3,Dual Edge Capture Mode Captures For n = 6" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 26. "DECAPEN3,Dual Edge Capture Mode Enable For n = 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "COMP3,Complement Of Channel (n) for n = 6" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
|
|
bitfld.long 0x00 24. "COMBINE3,Combine Channels For n = 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "MCOMBINE2,Modified Combine Mode For n = 4" "0,1"
|
|
bitfld.long 0x00 22. "FAULTEN2,Fault Control Enable For n = 4" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
|
|
newline
|
|
bitfld.long 0x00 21. "SYNCEN2,Synchronization Enable For n = 4" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
|
|
bitfld.long 0x00 20. "DTEN2,Deadtime Enable For n = 4" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
|
|
newline
|
|
bitfld.long 0x00 19. "DECAP2,Dual Edge Capture Mode Captures For n = 4" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 18. "DECAPEN2,Dual Edge Capture Mode Enable For n = 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "COMP2,Complement Of Channel (n) For n = 4" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
|
|
bitfld.long 0x00 16. "COMBINE2,Combine Channels For n = 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "MCOMBINE1,Modified Combine Mode For n = 2" "0,1"
|
|
bitfld.long 0x00 14. "FAULTEN1,Fault Control Enable For n = 2" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
|
|
newline
|
|
bitfld.long 0x00 13. "SYNCEN1,Synchronization Enable For n = 2" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
|
|
bitfld.long 0x00 12. "DTEN1,Deadtime Enable For n = 2" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
|
|
newline
|
|
bitfld.long 0x00 11. "DECAP1,Dual Edge Capture Mode Captures For n = 2" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 10. "DECAPEN1,Dual Edge Capture Mode Enable For n = 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "COMP1,Complement Of Channel (n) For n = 2" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
|
|
bitfld.long 0x00 8. "COMBINE1,Combine Channels For n = 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "MCOMBINE0,Modified Combine Mode For n = 0" "0,1"
|
|
bitfld.long 0x00 6. "FAULTEN0,Fault Control Enable For n = 0" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
|
|
newline
|
|
bitfld.long 0x00 5. "SYNCEN0,Synchronization Enable For n = 0" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
|
|
bitfld.long 0x00 4. "DTEN0,Deadtime Enable For n = 0" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
|
|
newline
|
|
bitfld.long 0x00 3. "DECAP0,Dual Edge Capture Mode Captures For n = 0" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 2. "DECAPEN0,Dual Edge Capture Mode Enable For n = 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "COMP0,Complement Of Channel (n) For n = 0" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
|
|
bitfld.long 0x00 0. "COMBINE0,Combine Channels For n = 0" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "DEADTIME,Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "EXTTRIG,FTM External Trigger"
|
|
bitfld.long 0x00 9. "CH7TRIG,Channel 7 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
bitfld.long 0x00 8. "CH6TRIG,Channel 6 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
newline
|
|
bitfld.long 0x00 7. "TRIGF,Channel Trigger Flag" "0: No channel trigger was generated,1: A channel trigger was generated"
|
|
bitfld.long 0x00 6. "INITTRIGEN,Initialization Trigger Enable" "0: The generation of initialization trigger is..,1: The generation of initialization trigger is.."
|
|
newline
|
|
bitfld.long 0x00 5. "CH1TRIG,Channel 1 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
bitfld.long 0x00 4. "CH0TRIG,Channel 0 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
newline
|
|
bitfld.long 0x00 3. "CH5TRIG,Channel 5 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
bitfld.long 0x00 2. "CH4TRIG,Channel 4 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
newline
|
|
bitfld.long 0x00 1. "CH3TRIG,Channel 3 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
bitfld.long 0x00 0. "CH2TRIG,Channel 2 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "POL,Channels Polarity"
|
|
bitfld.long 0x00 7. "POL7,Channel 7 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 6. "POL6,Channel 6 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "FMS,Fault Mode Status"
|
|
bitfld.long 0x00 7. "FAULTF,Fault Detection Flag" "0: No fault condition was detected,1: A fault condition was detected"
|
|
bitfld.long 0x00 6. "WPEN,Write Protection Enable" "0: Write protection is disabled,1: Write protection is enabled"
|
|
newline
|
|
rbitfld.long 0x00 5. "FAULTIN,Fault Inputs" "0: The logic OR of the enabled fault inputs is 0,1: The logic OR of the enabled fault inputs is 1"
|
|
bitfld.long 0x00 3. "FAULTF3,Fault Detection Flag 3" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
|
|
newline
|
|
bitfld.long 0x00 2. "FAULTF2,Fault Detection Flag 2" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
|
|
bitfld.long 0x00 1. "FAULTF1,Fault Detection Flag 1" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
|
|
newline
|
|
bitfld.long 0x00 0. "FAULTF0,Fault Detection Flag 0" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,Input Capture Filter Control"
|
|
bitfld.long 0x00 12.--15. "CH3FVAL,Channel 3 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "CH2FVAL,Channel 2 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CH1FVAL,Channel 1 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CH0FVAL,Channel 0 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "FLTCTRL,Fault Control"
|
|
bitfld.long 0x00 15. "FSTATE,Fault output state" "0: FTM outputs will be placed into safe values..,1: FTM outputs will be tri-stated when fault.."
|
|
bitfld.long 0x00 8.--11. "FFVAL,Fault Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "FFLTR3EN,Fault Input 3 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
|
|
bitfld.long 0x00 6. "FFLTR2EN,Fault Input 2 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "FFLTR1EN,Fault Input 1 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
|
|
bitfld.long 0x00 4. "FFLTR0EN,Fault Input 0 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "FAULT3EN,Fault Input 3 Enable" "0: Fault input is disabled,1: Fault input is enabled"
|
|
bitfld.long 0x00 2. "FAULT2EN,Fault Input 2 Enable" "0: Fault input is disabled,1: Fault input is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "FAULT1EN,Fault Input 1 Enable" "0: Fault input is disabled,1: Fault input is enabled"
|
|
bitfld.long 0x00 0. "FAULT0EN,Fault Input 0 Enable" "0: Fault input is disabled,1: Fault input is enabled"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status"
|
|
bitfld.long 0x00 7. "PHAFLTREN,Phase A Input Filter Enable" "0: Phase A input filter is disabled,1: Phase A input filter is enabled"
|
|
bitfld.long 0x00 6. "PHBFLTREN,Phase B Input Filter Enable" "0: Phase B input filter is disabled,1: Phase B input filter is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "PHAPOL,Phase A Input Polarity" "0: Normal polarity,1: Inverted polarity"
|
|
bitfld.long 0x00 4. "PHBPOL,Phase B Input Polarity" "0: Normal polarity,1: Inverted polarity"
|
|
newline
|
|
bitfld.long 0x00 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase A and phase B encoding mode,1: Count and direction encoding mode"
|
|
rbitfld.long 0x00 2. "QUADIR,FTM Counter Direction In Quadrature Decoder Mode" "0: Counting direction is decreasing (FTM counter..,1: Counting direction is increasing (FTM counter.."
|
|
newline
|
|
rbitfld.long 0x00 1. "TOFDIR,Timer Overflow Direction In Quadrature Decoder Mode" "0: TOF bit was set on the bottom of counting,1: TOF bit was set on the top of counting"
|
|
bitfld.long 0x00 0. "QUADEN,Quadrature Decoder Mode Enable" "0: Quadrature Decoder mode is disabled,1: Quadrature Decoder mode is enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CONF,Configuration"
|
|
bitfld.long 0x00 11. "ITRIGR,Initialization trigger on Reload Point" "0: Initialization trigger is generated on..,1: Initialization trigger is generated when a.."
|
|
bitfld.long 0x00 10. "GTBEOUT,Global Time Base Output" "0: A global time base signal generation is..,1: A global time base signal generation is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "GTBEEN,Global Time Base Enable" "0: Use of an external global time base is disabled,1: Use of an external global time base is enabled"
|
|
bitfld.long 0x00 6.--7. "BDMMODE,BDM Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "LDFQ,Frequency of the Reload Opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FLTPOL,FTM Fault Input Polarity"
|
|
bitfld.long 0x00 3. "FLT3POL,Fault Input 3 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
|
|
bitfld.long 0x00 2. "FLT2POL,Fault Input 2 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 1. "FLT1POL,Fault Input 1 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
|
|
bitfld.long 0x00 0. "FLT0POL,Fault Input 0 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SYNCONF,Synchronization Configuration"
|
|
bitfld.long 0x00 20. "HWSOC,Software output control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the SWOCTRL.."
|
|
bitfld.long 0x00 19. "HWINVC,Inverting control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the INVCTRL.."
|
|
newline
|
|
bitfld.long 0x00 18. "HWOM,Output mask synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the OUTMASK.."
|
|
bitfld.long 0x00 17. "HWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate MOD HCR..,1: A hardware trigger activates MOD HCR CNTIN.."
|
|
newline
|
|
bitfld.long 0x00 16. "HWRSTCNT,FTM counter synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the FTM..,1: A hardware trigger activates the FTM counter.."
|
|
bitfld.long 0x00 12. "SWSOC,Software output control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the SWOCTRL.."
|
|
newline
|
|
bitfld.long 0x00 11. "SWINVC,Inverting control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the INVCTRL.."
|
|
bitfld.long 0x00 10. "SWOM,Output mask synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the OUTMASK.."
|
|
newline
|
|
bitfld.long 0x00 9. "SWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by the software trigger" "0: The software trigger does not activate MOD..,1: The software trigger activates MOD HCR CNTIN.."
|
|
bitfld.long 0x00 8. "SWRSTCNT,FTM counter synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the FTM.."
|
|
newline
|
|
bitfld.long 0x00 7. "SYNCMODE,Synchronization Mode" "0: Legacy PWM synchronization is selected,1: Enhanced PWM synchronization is selected"
|
|
bitfld.long 0x00 5. "SWOC,SWOCTRL Register Synchronization" "0: SWOCTRL register is updated with its buffer..,1: SWOCTRL register is updated with its buffer.."
|
|
newline
|
|
bitfld.long 0x00 4. "INVC,INVCTRL Register Synchronization" "0: INVCTRL register is updated with its buffer..,1: INVCTRL register is updated with its buffer.."
|
|
bitfld.long 0x00 2. "CNTINC,CNTIN Register Synchronization" "0: CNTIN register is updated with its buffer..,1: CNTIN register is updated with its buffer.."
|
|
newline
|
|
bitfld.long 0x00 0. "HWTRIGMODE,Hardware Trigger Mode" "0: FTM clears the TRIGj bit when the hardware..,1: FTM does not clear the TRIGj bit when the.."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "INVCTRL,FTM Inverting Control"
|
|
bitfld.long 0x00 3. "INV3EN,Pair Channels 3 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
bitfld.long 0x00 2. "INV2EN,Pair Channels 2 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "INV1EN,Pair Channels 1 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
bitfld.long 0x00 0. "INV0EN,Pair Channels 0 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "SWOCTRL,FTM Software Output Control"
|
|
bitfld.long 0x00 15. "CH7OCV,Channel 7 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
bitfld.long 0x00 14. "CH6OCV,Channel 6 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
newline
|
|
bitfld.long 0x00 13. "CH5OCV,Channel 5 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
bitfld.long 0x00 12. "CH4OCV,Channel 4 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
newline
|
|
bitfld.long 0x00 11. "CH3OCV,Channel 3 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
bitfld.long 0x00 10. "CH2OCV,Channel 2 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
newline
|
|
bitfld.long 0x00 9. "CH1OCV,Channel 1 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
bitfld.long 0x00 8. "CH0OCV,Channel 0 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
newline
|
|
bitfld.long 0x00 7. "CH7OC,Channel 7 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 6. "CH6OC,Channel 6 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
newline
|
|
bitfld.long 0x00 5. "CH5OC,Channel 5 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 4. "CH4OC,Channel 4 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
newline
|
|
bitfld.long 0x00 3. "CH3OC,Channel 3 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 2. "CH2OC,Channel 2 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
newline
|
|
bitfld.long 0x00 1. "CH1OC,Channel 1 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 0. "CH0OC,Channel 0 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PWMLOAD,FTM PWM Load"
|
|
bitfld.long 0x00 11. "GLDOK,Global Load OK" "0: No action,1: LDOK bit is set"
|
|
bitfld.long 0x00 10. "GLEN,Global Load Enable" "0: Global Load Ok disabled,1: Global Load OK enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "LDOK,Load Enable" "0: Loading updated values is disabled,1: Loading updated values is enabled"
|
|
bitfld.long 0x00 8. "HCSEL,Half Cycle Select" "0: Half cycle reload is disabled and it is not..,1: Half cycle reload is enabled and it is.."
|
|
newline
|
|
bitfld.long 0x00 7. "CH7SEL,Channel 7 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 6. "CH6SEL,Channel 6 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
newline
|
|
bitfld.long 0x00 5. "CH5SEL,Channel 5 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 4. "CH4SEL,Channel 4 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
newline
|
|
bitfld.long 0x00 3. "CH3SEL,Channel 3 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 2. "CH2SEL,Channel 2 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
newline
|
|
bitfld.long 0x00 1. "CH1SEL,Channel 1 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 0. "CH0SEL,Channel 0 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "HCR,Half Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "HCVAL,Half Cycle Value"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MOD_MIRROR,Mirror of Modulo Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "MOD,Mirror of the Modulo Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACMOD,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 8. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x204)++0x03
|
|
line.long 0x00 "CV_MIRROR[$1],Mirror of Channel (n) Match Value $1"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
endif
|
|
repeat 8. (increment 0 1)(increment 0 0x8)
|
|
tree "CONTROLS[$1]"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
group.long ($2+0x0C)++0x03
|
|
line.long 0x00 "CSC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
bitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "CV,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "D_IP_IRQ_STEER_SYN (IRQSTEER)"
|
|
base ad:0x51070000
|
|
repeat 12. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "CHn_MASK[$1],Channel n Interrupt Mask Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "MASKFLD,Mask bits"
|
|
repeat.end
|
|
repeat 12. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x34)++0x03
|
|
line.long 0x00 "CHn_SET[$1],Channel n Interrupt Set Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "FORCEFLD,Force interrupt"
|
|
repeat.end
|
|
repeat 12. (increment 0 1) (increment 0 0x4)
|
|
rgroup.long ($2+0x64)++0x03
|
|
line.long 0x00 "CHn_STATUS[$1],Channel n Interrupt Status Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "STATUS,Status of an interrupt"
|
|
repeat.end
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CHn_MINTDIS,Channel n Master Interrupt Disable Register"
|
|
bitfld.long 0x00 0.--5. "DISABLE,Each bit of this field disables the corresponding interrupts in table above" "0: Enable interrupts,1: Disable interrupts,?..."
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "CHn_MSTRSTAT,Channel n Master Status Register"
|
|
bitfld.long 0x00 0. "STATUS,Status of all interrupts" "0: No interrupts are asserted,1: At least one interrupt is asserted"
|
|
tree.end
|
|
tree "D_IP_LPIT_SYN (LPIT)"
|
|
tree "CM4__LPIT"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x41210000
|
|
else
|
|
base ad:0x37210000
|
|
endif
|
|
sif cpuis("IMX8D?L-CM4")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXT_TRIG,Number of External Trigger Inputs"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHANNEL,Number of Timer Channels"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MCR,Module Control Register"
|
|
bitfld.long 0x00 3. "DBG_EN,Debug Enable Bit" "0: Stop timer channels in Debug mode,1: Allow timer channels to continue to run in.."
|
|
bitfld.long 0x00 2. "DOZE_EN,DOZE Mode Enable Bit" "0: Stop timer channels in DOZE mode,1: Allow timer channels to continue to run in.."
|
|
newline
|
|
bitfld.long 0x00 1. "SW_RST,Software Reset Bit" "0: Timer channels and registers are not reset,1: Reset timer channels and registers"
|
|
bitfld.long 0x00 0. "M_CEN,Module Clock Enable" "0: Disable peripheral clock to timers,1: Enable peripheral clock to timers"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MSR,Module Status Register"
|
|
eventfld.long 0x00 3. "TIF3,Channel 3 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
eventfld.long 0x00 2. "TIF2,Channel 2 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
newline
|
|
eventfld.long 0x00 1. "TIF1,Channel 1 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
eventfld.long 0x00 0. "TIF0,Channel 0 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MIER,Module Interrupt Enable Register"
|
|
bitfld.long 0x00 3. "TIE3,Channel 3 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "TIE2,Channel 2 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "TIE1,Channel 1 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "TIE0,Channel 0 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SETTEN,Set Timer Enable Register"
|
|
bitfld.long 0x00 3. "SET_T_EN_3,Set Timer 3 Enable" "0: SET_T_EN_3_0,1: Enables Timer Channel 3"
|
|
bitfld.long 0x00 2. "SET_T_EN_2,Set Timer 2 Enable" "0: SET_T_EN_2_0,1: Enables Timer Channel 2"
|
|
newline
|
|
bitfld.long 0x00 1. "SET_T_EN_1,Set Timer 1 Enable" "0: SET_T_EN_1_0,1: Enables Timer Channel 1"
|
|
bitfld.long 0x00 0. "SET_T_EN_0,Set Timer 0 Enable" "0: SET_T_EN_0_0,1: Enables Timer Channel 0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CLRTEN,Clear Timer Enable Register"
|
|
bitfld.long 0x00 3. "CLR_T_EN_3,Clear Timer 3 Enable" "0: CLR_T_EN_3_0,1: Clear the Timer Enable bit (TCTRL3[T_EN]) for.."
|
|
bitfld.long 0x00 2. "CLR_T_EN_2,Clear Timer 2 Enable" "0: CLR_T_EN_2_0,1: Clear the Timer Enable bit (TCTRL2[T_EN]) for.."
|
|
newline
|
|
bitfld.long 0x00 1. "CLR_T_EN_1,Clear Timer 1 Enable" "0: CLR_T_EN_1_0,1: Clear the Timer Enable bit (TCTRL1[T_EN]) for.."
|
|
bitfld.long 0x00 0. "CLR_T_EN_0,Clear Timer 0 Enable" "0: CLR_T_EN_0_0,1: Clear the Timer Enable bit (TCTRL0[T_EN]) for.."
|
|
endif
|
|
repeat 4. (increment 0 1)(increment 0 0x10)
|
|
tree "CHANNEL[$1]"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "TVAL,Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_VAL,Timer Value"
|
|
rgroup.long ($2+0x24)++0x03
|
|
line.long 0x00 "CVAL,Current Timer Value"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_CUR_VAL,Current Timer Value"
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "TCTRL,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. "TRG_SEL,Trigger Select" "0: Timer channel 0 - 3 trigger source is selected,1: Timer channel 0 - 3 trigger source is selected,2: Timer channel 0 - 3 trigger source is selected,3: Timer channel 0 - 3 trigger source is selected,?..."
|
|
bitfld.long 0x00 23. "TRG_SRC,Trigger Source" "0: Selects external triggers,1: Selects internal triggers"
|
|
newline
|
|
bitfld.long 0x00 18. "TROT,Timer Reload On Trigger" "0: Timer will not reload on the selected trigger,1: Timer will reload on the selected trigger"
|
|
bitfld.long 0x00 17. "TSOI,Timer Stop On Interrupt" "0: The channel timer does not stop after timeout,1: The channel timer will stop after a timeout.."
|
|
newline
|
|
bitfld.long 0x00 16. "TSOT,Timer Start On Trigger" "0: Timer starts to decrement immediately based..,1: Timer starts to decrement when a rising edge.."
|
|
bitfld.long 0x00 2.--3. "MODE,Timer Operation Mode" "0: 32-bit Periodic Counter,1: Dual 16-bit Periodic Counter,2: 32-bit Trigger Accumulator,3: 32-bit Trigger Input Capture"
|
|
newline
|
|
bitfld.long 0x00 1. "CHAIN,Chain Channel" "0: Channel Chaining is disabled,1: Channel Chaining is enabled"
|
|
bitfld.long 0x00 0. "T_EN,Timer Enable" "0: Timer Channel is disabled,1: Timer Channel is enabled"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SCU__LPIT"
|
|
base ad:0x33210000
|
|
sif cpuis("IMX8D?L-CM4")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXT_TRIG,Number of External Trigger Inputs"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHANNEL,Number of Timer Channels"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MCR,Module Control Register"
|
|
bitfld.long 0x00 3. "DBG_EN,Debug Enable Bit" "0: Stop timer channels in Debug mode,1: Allow timer channels to continue to run in.."
|
|
bitfld.long 0x00 2. "DOZE_EN,DOZE Mode Enable Bit" "0: Stop timer channels in DOZE mode,1: Allow timer channels to continue to run in.."
|
|
newline
|
|
bitfld.long 0x00 1. "SW_RST,Software Reset Bit" "0: Timer channels and registers are not reset,1: Reset timer channels and registers"
|
|
bitfld.long 0x00 0. "M_CEN,Module Clock Enable" "0: Disable peripheral clock to timers,1: Enable peripheral clock to timers"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MSR,Module Status Register"
|
|
eventfld.long 0x00 3. "TIF3,Channel 3 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
eventfld.long 0x00 2. "TIF2,Channel 2 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
newline
|
|
eventfld.long 0x00 1. "TIF1,Channel 1 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
eventfld.long 0x00 0. "TIF0,Channel 0 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred (timer has timed out)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MIER,Module Interrupt Enable Register"
|
|
bitfld.long 0x00 3. "TIE3,Channel 3 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "TIE2,Channel 2 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "TIE1,Channel 1 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "TIE0,Channel 0 Timer Interrupt Enable" "0: Disabled,1: Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SETTEN,Set Timer Enable Register"
|
|
bitfld.long 0x00 3. "SET_T_EN_3,Set Timer 3 Enable" "0: SET_T_EN_3_0,1: Enables Timer Channel 3"
|
|
bitfld.long 0x00 2. "SET_T_EN_2,Set Timer 2 Enable" "0: SET_T_EN_2_0,1: Enables Timer Channel 2"
|
|
newline
|
|
bitfld.long 0x00 1. "SET_T_EN_1,Set Timer 1 Enable" "0: SET_T_EN_1_0,1: Enables Timer Channel 1"
|
|
bitfld.long 0x00 0. "SET_T_EN_0,Set Timer 0 Enable" "0: SET_T_EN_0_0,1: Enables Timer Channel 0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CLRTEN,Clear Timer Enable Register"
|
|
bitfld.long 0x00 3. "CLR_T_EN_3,Clear Timer 3 Enable" "0: CLR_T_EN_3_0,1: Clear the Timer Enable bit (TCTRL3[T_EN]) for.."
|
|
bitfld.long 0x00 2. "CLR_T_EN_2,Clear Timer 2 Enable" "0: CLR_T_EN_2_0,1: Clear the Timer Enable bit (TCTRL2[T_EN]) for.."
|
|
newline
|
|
bitfld.long 0x00 1. "CLR_T_EN_1,Clear Timer 1 Enable" "0: CLR_T_EN_1_0,1: Clear the Timer Enable bit (TCTRL1[T_EN]) for.."
|
|
bitfld.long 0x00 0. "CLR_T_EN_0,Clear Timer 0 Enable" "0: CLR_T_EN_0_0,1: Clear the Timer Enable bit (TCTRL0[T_EN]) for.."
|
|
endif
|
|
repeat 4. (increment 0 1)(increment 0 0x10)
|
|
tree "CHANNEL[$1]"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "TVAL,Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_VAL,Timer Value"
|
|
rgroup.long ($2+0x24)++0x03
|
|
line.long 0x00 "CVAL,Current Timer Value"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_CUR_VAL,Current Timer Value"
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "TCTRL,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. "TRG_SEL,Trigger Select" "0: Timer channel 0 - 3 trigger source is selected,1: Timer channel 0 - 3 trigger source is selected,2: Timer channel 0 - 3 trigger source is selected,3: Timer channel 0 - 3 trigger source is selected,?..."
|
|
bitfld.long 0x00 23. "TRG_SRC,Trigger Source" "0: Selects external triggers,1: Selects internal triggers"
|
|
newline
|
|
bitfld.long 0x00 18. "TROT,Timer Reload On Trigger" "0: Timer will not reload on the selected trigger,1: Timer will reload on the selected trigger"
|
|
bitfld.long 0x00 17. "TSOI,Timer Stop On Interrupt" "0: The channel timer does not stop after timeout,1: The channel timer will stop after a timeout.."
|
|
newline
|
|
bitfld.long 0x00 16. "TSOT,Timer Start On Trigger" "0: Timer starts to decrement immediately based..,1: Timer starts to decrement when a rising edge.."
|
|
bitfld.long 0x00 2.--3. "MODE,Timer Operation Mode" "0: 32-bit Periodic Counter,1: Dual 16-bit Periodic Counter,2: 32-bit Trigger Accumulator,3: 32-bit Trigger Input Capture"
|
|
newline
|
|
bitfld.long 0x00 1. "CHAIN,Chain Channel" "0: Channel Chaining is disabled,1: Channel Chaining is enabled"
|
|
bitfld.long 0x00 0. "T_EN,Timer Enable" "0: Timer Channel is disabled,1: Timer Channel is enabled"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "D_IP_USB_DCD_SYN (USBDCD)"
|
|
repeat 2. (list 1. 2.) (list ad:0x5B100800 ad:0x5B110800)
|
|
tree "CONNECTIVITY__USBDCD$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONTROL,Control register"
|
|
bitfld.long 0x00 25. "SR,Software Reset" "0: Do not perform a software reset,1: Perform a software reset"
|
|
bitfld.long 0x00 24. "START,Start Change Detection Sequence" "0: Do not start the sequence,1: Initiate the charger detection sequence"
|
|
newline
|
|
bitfld.long 0x00 17. "BC12,BC12" "0: Compatible with BC1.1 (default),1: Compatible with BC1.2"
|
|
bitfld.long 0x00 16. "IE,Interrupt Enable" "0: Disable interrupts to the system,1: Enable interrupts to the system"
|
|
newline
|
|
rbitfld.long 0x00 8. "IF,Interrupt Flag" "0: No interrupt is pending,1: An interrupt is pending"
|
|
bitfld.long 0x00 0. "IACK,Interrupt Acknowledge" "0: Do not clear the interrupt,1: Clear the IF bit (interrupt flag)"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CLOCK,Clock register"
|
|
hexmask.long.word 0x00 2.--11. 1. "CLOCK_SPEED,Numerical Value of Clock Speed in Binary"
|
|
bitfld.long 0x00 0. "CLOCK_UNIT,Unit of Measurement Encoding for Clock Speed" "0: kHz Speed (between 1 kHz and 1023 kHz),1: MHz Speed (between 1 MHz and 1023 MHz)"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STATUS,Status register"
|
|
bitfld.long 0x00 22. "ACTIVE,Active Status Indicator" "0: The sequence is not running,1: The sequence is running"
|
|
bitfld.long 0x00 21. "TO,Timeout Flag" "0: The detection sequence has not been running..,1: It has been over 1 s since the data pin.."
|
|
newline
|
|
bitfld.long 0x00 20. "ERR,Error Flag" "0: No sequence errors,1: Error in the detection sequence"
|
|
bitfld.long 0x00 18.--19. "SEQ_STAT,Charger Detection Sequence Status" "0: The module is either not enabled or the..,1: Data pin contact detection is complete,2: Charging port detection is complete,3: Charger type detection is complete"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "SEQ_RES,Charger Detection Sequence Results" "0: No results to report,1: Attached to an SDP,2: Attached to a charging port,3: Attached to a DCP"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SIGNAL_OVERRIDE,Signal Override Register"
|
|
bitfld.long 0x00 0.--1. "PS,Phase Selection" "0: No overrides,?,2: Enables VDP_SRC voltage source for the USB_DP..,?..."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMER0,TIMER0 register"
|
|
hexmask.long.word 0x00 16.--25. 1. "TSEQ_INIT,Sequence Initiation Time"
|
|
hexmask.long.word 0x00 0.--11. 1. "TUNITCON,Unit Connection Timer Elapse (in ms)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIMER1,TIMER1 register"
|
|
hexmask.long.word 0x00 16.--25. 1. "TDCD_DBNC,Time Period to Debounce D+ Signal"
|
|
hexmask.long.word 0x00 0.--9. 1. "TVDPSRC_ON,Time Period Comparator Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIMER2_BC11,TIMER2_BC11 register"
|
|
hexmask.long.word 0x00 16.--25. 1. "TVDPSRC_CON,Time Period Before Enabling D+ Pullup"
|
|
bitfld.long 0x00 0.--3. "CHECK_DM,Time Before Check of D- Line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIMER2_BC12,TIMER2_BC12 register"
|
|
hexmask.long.word 0x00 16.--25. 1. "TWAIT_AFTER_PRD,TWAIT_AFTER_PRD"
|
|
hexmask.long.word 0x00 0.--9. 1. "TVDMSRC_ON,TVDMSRC_ON"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "D_SSL_SCU_LPC_SYN (SCU_LPC)"
|
|
base ad:0x32070000
|
|
repeat 7. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "LPC_PC[$1],LPC Power Control Register N $1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "PC,Power Control bus"
|
|
repeat.end
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LPC_CR,LPC Configuration Register"
|
|
bitfld.long 0x00 7. "CLKG,LPC Clock Gate" "0: LPC Clock gate not requested,1: LPC Clock gate requested"
|
|
rbitfld.long 0x00 6. "CLKS,LPC Clock Status" "0: LPC Clock is not gated,1: LPC Clock is gated"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "CLKSEL,LPC Clock Select" "0: 25MHz clock selected,1: 1MHz clock selected,2: 32kHz clock selected,?..."
|
|
bitfld.long 0x00 2. "PCSEL,LPC/DSC Power Control Select" "0: Power controls driven by DSC,1: Power controls driven by LPC"
|
|
newline
|
|
bitfld.long 0x00 1. "PMICSTDBY,PMIC Standby" "0: PMIC standby request deasserted during low..,1: PMIC standby request asserted during low.."
|
|
bitfld.long 0x00 0. "ROSCDIS,ROSC Disable" "0: ROSC enabled during low power mode,1: ROSC disabled during low power mode"
|
|
repeat 7. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "LPC_ED[$1],LPC Entry Delay Stage N $1"
|
|
bitfld.long 0x00 0.--4. "ED,Entry Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 6. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "LPC_XD[$1],LPC Exit Delay Stage N $1"
|
|
bitfld.long 0x00 0.--4. "XD,Exit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LPC_XD6,LPC Exit Delay Stage 6"
|
|
hexmask.long.word 0x00 0.--15. 1. "XD,Exit Delay"
|
|
tree.end
|
|
tree "DDRC (DDR Controller)"
|
|
base ad:0x5C000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MSTR,Master Register0"
|
|
bitfld.long 0x00 30.--31. "device_config,Indicates the configuration of the device used in the system" "0: device_config_0,1: device_config_1,2: device_config_2,3: device_config_3"
|
|
newline
|
|
bitfld.long 0x00 29. "frequency_mode,Choose which registers are used" "0: Original Registers,1: frequency_mode_1"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "active_ranks,Only present for multi-rank configurations" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22. "frequency_ratio,Selects the Frequency Ratio" "0: frequency_ratio_0,1: frequency_ratio_1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "burst_rdwr,SDRAM burst length used" "?,1: Burst length of 2 (only supported for mDDR),2: Burst length of 4,?,4: Burst length of 8,?,?,?,8: Burst length of 16 (only supported for mDDR..,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "dll_off_mode,Set to 1 when the DDRC and DRAM has to be put in DLL-off mode for low frequency operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "data_bus_width,Selects proportion of DQ bus width that is used by the SDRAM" "0: Full DQ bus width to SDRAM,1: Half DQ bus width to SDRAM,2: Quarter DQ bus width to SDRAM,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 11. "geardown_mode,1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "en_2t_timing_mode,If 1 then DDRC uses 2T timing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "burstchop,When set enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "lpddr4,Select LPDDR4 SDRAM" "0: non-LPDDR4 device in use Present only in..,1: LPDDR4 SDRAM device in use"
|
|
newline
|
|
bitfld.long 0x00 3. "lpddr3,Select LPDDR3 SDRAM" "0: non-LPDDR3 device in use Present only in..,1: LPDDR3 SDRAM device in use"
|
|
newline
|
|
bitfld.long 0x00 2. "lpddr2,Select LPDDR2 SDRAM" "0: non-LPDDR2 device in use Present only in..,1: LPDDR2 SDRAM device in use"
|
|
newline
|
|
bitfld.long 0x00 0. "ddr3,Select DDR3 SDRAM" "0: non-DDR3 SDRAM device in use Only present in,1: DDR3 SDRAM device in use"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STAT,Operating Mode Status Register"
|
|
bitfld.long 0x00 8.--9. "selfref_state,Self refresh state" "0: SDRAM is not in Self Refresh,1: selfref_state_1,2: Self refresh power down,3: selfref_state_3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "selfref_type,Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not" "0: SDRAM is not in Self Refresh (except LPDDR4)..,?,2: SDRAM is in Self Refresh (except LPDDR4) or..,3: SDRAM is in Self Refresh (except LPDDR4) or.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "operating_mode,Operating mode" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MSTR1,Operating Mode Status Register"
|
|
bitfld.long 0x00 16. "alt_addrmap_en,Enable Alternative Address Map" "0: Disable Alternative Address Map,1: Enable Alternative Address Map"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "rank_tmgreg_sel,rank_tmgreg_sel" "0: USE DRAMTMGx registers for the rank,1: USE MRAMTMGx registers for the rank,?..."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MRCTRL3,Operating Mode Status Register"
|
|
bitfld.long 0x00 0.--1. "mr_rank_sel,mr_rank_sel" "0,1,2,3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MRCTRL0,Mode Register Read/Write Control Register 0"
|
|
bitfld.long 0x00 31. "mr_wr,Setting this register bit to 1 triggers a mode register read or write operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "pba_mode,Indicates whether PBA access is executed" "0: Per DRAM Addressability mode,1: Per Buffer Addressability mode The completion.."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "mr_addr,Address of the mode register that is to be written to" "0: mr_addr_0,1: mr_addr_1,2: mr_addr_2,3: mr_addr_3,4: mr_addr_4,5: mr_addr_5,6: mr_addr_6,7: mr_addr_7,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "mr_rank,Controls which rank is accessed by MRCTRL0.mr_wr" "?,1: select rank 0 only,2: select rank 1 only,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "sw_init_int,Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not" "0: Software intervention is not allowed,1: Software intervention is allowed"
|
|
newline
|
|
bitfld.long 0x00 2. "pda_en,Indicates whether the mode register operation is MRS in PDA mode or not" "0: pda_en_0,1: MRS in Per DRAM Addressability"
|
|
newline
|
|
bitfld.long 0x00 1. "mpr_en,Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4)" "0: mpr_en_0,1: WR/RD for MPR"
|
|
newline
|
|
bitfld.long 0x00 0. "mr_type,Indicates whether the mode register operation is read or write" "0: mr_type_0,1: mr_type_1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MRCTRL1,Mode Register Read/Write Control Register 1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "mr_data,Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "MRSTAT,Mode Register Read/Write Status Register"
|
|
bitfld.long 0x00 8. "pda_done,The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is low" "0: Indicates that mode register write operation..,1: Indicates that mode register write operation.."
|
|
newline
|
|
bitfld.long 0x00 0. "mr_wr_busy,The SoC core may initiate a MR write operation only if this signal is low" "0: Indicates that the SoC core can initiate a..,1: Indicates that mode register write operation.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MRCTRL2,Mode Register Read/Write Control Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "mr_device_sel,Indicates the device(s) to be selected during the MRS that happens in PDA mode"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DERATEEN,Temperature Derate Enable Register"
|
|
bitfld.long 0x00 8.--9. "rc_derate_value,Derate value of tRC for LPDDR4" "0: rc_derate_value_0,1: rc_derate_value_1,2: rc_derate_value_2,3: rc_derate_value_3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "derate_byte,Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used for derating" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. "derate_value,Derate value" "0: Derating uses +1,1: Derating uses +2"
|
|
newline
|
|
bitfld.long 0x00 0. "derate_enable,Enables derating" "0: Timing parameter derating is disabled,1: Timing parameter derating is enabled using.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DERATEINT,Temperature Derate Interval Register"
|
|
hexmask.long 0x00 0.--31. 1. "mr4_read_interval,Interval between two MR4 reads used to derate the timing parameters"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PWRCTL,Low Power Control Register"
|
|
bitfld.long 0x00 6. "stay_in_selfref,Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state for LPDDR4" "0: no description available,1: no description available"
|
|
newline
|
|
bitfld.long 0x00 5. "selfref_sw,A value of 1 to this register causes system to move to Self Refresh state immediately as long as it is not in INIT or DPD/MPSM operating_mode" "0: Software Exit from Self Refresh,1: Software Entry to Self Refresh"
|
|
newline
|
|
bitfld.long 0x00 4. "mpsm_en,When this is 1 the DDRC puts the SDRAM into maximum power saving mode when the transaction store is empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "en_dfi_dram_clk_disable,Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "deeppowerdown_en,When this is 1 DDRC puts the SDRAM into deep power-down mode when the transaction store is empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "powerdown_en,If true then the DDRC goes into power-down after a programmable number of cycles maximum idle clocks before power down (PWRTMG.powerdown_to_x32)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "selfref_en,If true then the DDRC puts the SDRAM into Self Refresh after a programmable number of cycles maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PWRTMG,Low Power Timing Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "selfref_to_x32,After this many clocks of the DDRC command channel being idle the DDRC automatically puts the SDRAM into Self Refresh"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "t_dpd_x4096,Minimum deep power-down time"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "powerdown_to_x32,After this many clocks of the DDRC command channel being idle the DDRC automatically puts the SDRAM into power-down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "HWLPCTL,Hardware Low Power Control Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "hw_lp_idle_x32,Hardware idle period"
|
|
newline
|
|
bitfld.long 0x00 1. "hw_lp_exit_idle_en,When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop automatic power down or automatic self-refresh modes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "hw_lp_en,Enable for Hardware Low Power Interface" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "RFSHCTL0,Refresh Control Register 0"
|
|
bitfld.long 0x00 20.--23. "refresh_margin,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--16. "refresh_to_x32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once but it has not expired (RFSHCTL0.refresh_burst+1) times yet then a speculative refresh may be performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 4.--8. "refresh_burst,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0: single refresh,1: burst-of-2 refresh,?,?,?,?,?,7: burst-of-8 refresh For information on burst,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "per_bank_refresh,Per bank refresh allows traffic to flow to other banks" "0: per_bank_refresh_0,1: per_bank_refresh_1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "RFSHCTL1,Refresh Control Register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. "refresh_timer1_start_value_x32,Refresh timer start for rank 1 (only present in multi-rank configurations)"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "refresh_timer0_start_value_x32,Refresh timer start for rank 0 (only present in multi-rank configurations)"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "RFSHCTL3,Refresh Control Register 3"
|
|
bitfld.long 0x00 4.--6. "refresh_mode,Fine Granularity Refresh Mode" "0: Fixed 1x (Normal mode),1: Fixed 2x,2: Fixed 4x,?,?,5: Enable on the fly 2x (not supported),6: Enable on the fly 4x (not supported),?..."
|
|
newline
|
|
bitfld.long 0x00 1. "refresh_update_level,Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dis_auto_refresh,When '1' disable auto-refresh generated by the DDRC" "0,1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "RFSHTMG,Refresh Timing Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "t_rfc_nom_x32,tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4)"
|
|
newline
|
|
bitfld.long 0x00 15. "lpddr3_trefbw_en,Used only when LPDDR3 memory type is connected" "0: tREFBW parameter not used,1: tREFBW parameter used"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "t_rfc_min,tRFC (min): Minimum time from refresh to refresh or activate"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "INIT0,SDRAM Initialization Register 0"
|
|
bitfld.long 0x00 30.--31. "skip_dram_init,If lower bit is enabled the SDRAM initialization routine is skipped" "0: SDRAM Initialization routine is run after..,1: SDRAM Initialization routine is skipped after..,2: SDRAM Initialization routine is run after..,3: SDRAM Initialization routine is skipped after.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--25. 1. "post_cke_x1024,Cycles to wait after driving CKE high to start the SDRAM initialization sequence"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "pre_cke_x1024,Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "INIT1,SDRAM Initialization Register 1"
|
|
hexmask.long.word 0x00 16.--24. 1. "dram_rstn_x1024,Number of cycles to assert SDRAM reset signal during init sequence"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "pre_ocd_x32,Wait period before driving the OCD complete command to SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "INIT2,SDRAM Initialization Register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "idle_after_reset_x32,Idle time after the reset command tINIT4"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "min_stable_clock_x1,Time to wait after the first CKE high tINIT2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "INIT3,SDRAM Initialization Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "mr,DDR2: Value to write to MR register"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "emr,DDR2: Value to write to EMR register"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "INIT4,SDRAM Initialization Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "emr2,DDR2: Value to write to EMR2 register"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "emr3,DDR2: Value to write to EMR3 register"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "INIT5,SDRAM Initialization Register 5"
|
|
hexmask.long.byte 0x00 16.--23. 1. "dev_zqinit_x32,ZQ initial calibration tZQINIT"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "max_auto_init_x1024,Maximum duration of the auto initialization tINIT5"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "INIT6,SDRAM Initialization Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. "mr4,DDR4- Value to be loaded into SDRAM MR4 registers"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "mr5,DDR4- Value to be loaded into SDRAM MR5 registers"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "INIT7,SDRAM Initialization Register 7"
|
|
hexmask.long.word 0x00 16.--31. 1. "mr6,DDR4- Value to be loaded into SDRAM MR6 registers"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DIMMCTL,DIMM Control Register"
|
|
bitfld.long 0x00 6. "lrdimm_bcom_cmd_prot,Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM commands defined in the Data Buffer specification" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "dimm_dis_bg_mirroring,Disabling Address Mirroring for BG bits" "0: BG0 and BG1 are swapped if address mirroring..,1: BG0 and BG1 are NOT swapped"
|
|
newline
|
|
bitfld.long 0x00 4. "mrs_bg1_en,Enable for BG1 bit of MRS command" "0: mrs_bg1_en_0,1: mrs_bg1_en_1"
|
|
newline
|
|
bitfld.long 0x00 3. "mrs_a17_en,Enable for A17 bit of MRS command" "0: mrs_a17_en_0,1: mrs_a17_en_1"
|
|
newline
|
|
bitfld.long 0x00 2. "dimm_output_inv_en,Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only)" "0: Do not implement output inversion for B-side..,1: Implement output inversion for B-side DRAMs"
|
|
newline
|
|
bitfld.long 0x00 1. "dimm_addr_mirr_en,Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations)" "0: Do not implement address mirroring,1: For odd ranks implement address mirroring for.."
|
|
newline
|
|
bitfld.long 0x00 0. "dimm_stagger_cs_en,Staggering enable for multi-rank accesses (for multi-rank UDIMM RDIMM and LRDIMM implementations only)" "0: Do not stagger accesses,1: (non-DDR4) Send all commands to even and odd.."
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "RANKCTL,Rank Control Register"
|
|
bitfld.long 0x00 8.--11. "diff_rank_wr_gap,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "diff_rank_rd_gap,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "max_rank_rd,Only present for multi-rank configurations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DRAMTMG0,SDRAM Timing Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. "wr2pre,Minimum time between write and precharge to same bank"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "t_faw,tFAW Valid only when 8 or more banks(or banks x bank groups) are present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "t_ras_max,tRAS(max): Maximum time between activate and precharge to same bank"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "t_ras_min,tRAS(min): Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DRAMTMG1,SDRAM Timing Register 1"
|
|
bitfld.long 0x00 16.--20. "t_xp,tXP: Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "rd2pre,tRTP: Minimum time from read to precharge of same bank" "?,?,2: DDR3,?,4: LPDDR4,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "t_rc,tRC: Minimum time between activates to same bank"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DRAMTMG2,SDRAM Timing Register 2"
|
|
bitfld.long 0x00 24.--29. "write_latency,Set to WL Time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "read_latency,Set to RL Time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "rd2wr,DDR2/3/mDDR: RL + BL/2 +" "?,1: WL LPDDR4(DQ ODT is Disabled),2: WL DDR4,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "wr2rd,DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DRAMTMG3,SDRAM Timing Register 3"
|
|
hexmask.long.word 0x00 20.--29. 1. "t_mrw,Time to wait after a mode register write or read (MRW or MRR)"
|
|
newline
|
|
bitfld.long 0x00 12.--17. "t_mrd,tMRD: Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "t_mod,tMOD: Parameter used only in DDR3 and DDR4"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DRAMTMG4,SDRAM Timing Register 4"
|
|
bitfld.long 0x00 24.--28. "t_rcd,tRCD - tAL: Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "t_ccd,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "t_rrd,DDR4: tRRD_L: Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "t_rp,tRP: Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DRAMTMG5,SDRAM Timing Register 5"
|
|
bitfld.long 0x00 24.--27. "t_cksrx,This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX" "?,1: DDR3,2: LPDDR4,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "t_cksre,This is the time after Self Refresh Down Entry that CK is maintained as a valid clock" "0: LPDDR2,1: DDR3,2: LPDDR4,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--13. "t_ckesr,Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "t_cke,Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRAMTMG6,SDRAM Timing Register 6"
|
|
bitfld.long 0x00 24.--27. "t_ckdpde,This is the time after Deep Power Down Entry that CK is maintained as a valid clock" "0: LPDDR2,?,2: LPDDR3,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "t_ckdpdx,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "?,1: LPDDR2,2: LPDDR3,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "t_ckcsx,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit" "?,1: LPDDR2,2: LPDDR4,?..."
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DRAMTMG7,SDRAM Timing Register 7"
|
|
bitfld.long 0x00 8.--11. "t_ckpde,This is the time after Power Down Entry that CK is maintained as a valid clock" "0: LPDDR2,?,2: LPDDR4,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "t_ckpdx,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX" "0: LPDDR2,?,2: LPDDR4,?..."
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DRAMTMG8,SDRAM Timing Register 8"
|
|
hexmask.long.byte 0x00 24.--30. 1. "t_xs_fast_x32,tXS_FAST: Exit Self Refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode)"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "t_xs_abort_x32,tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "t_xs_dll_x32,tXSDLL: Exit Self Refresh to commands requiring a locked DLL"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "t_xs_x32,tXS: Exit Self Refresh to commands not requiring a locked DLL"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DRAMTMG9,SDRAM Timing Register 9"
|
|
bitfld.long 0x00 30. "ddr4_wr_preamble,DDR4 Write preamble mode" "0: 1tCK preamble,1: 2tCK preamble Present only with"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "t_ccd_s,tCCD_S: This is the minimum time between two reads or two writes for different bank group" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "t_rrd_s,tRRD_S: Minimum time between activates from bank a to bank b for different bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "wr2rd_s,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DRAMTMG10,SDRAM Timing Register 10"
|
|
bitfld.long 0x00 16.--20. "t_sync_gear,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "t_cmd_gear,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "t_gear_setup,Geardown setup time" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "t_gear_hold,Geardown hold time" "0,1,2,3"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DRAMTMG11,SDRAM Timing Register 11"
|
|
hexmask.long.byte 0x00 24.--30. 1. "post_mpsm_gap_x32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "t_mpx_lh,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "t_mpx_s,tMPX_S: Minimum time CS setup time to CKE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "t_ckmpe,tCKMPE: Minimum valid clock requirement after MPSM entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "DRAMTMG12,SDRAM Timing Register 12"
|
|
bitfld.long 0x00 16.--17. "t_cmdcke,tCMDCKE: Delay from valid command to CKE input LOW" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "t_ckehcmd,tCKEHCMD: Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "t_mrd_pda,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DRAMTMG13,SDRAM Timing Register 13"
|
|
hexmask.long.byte 0x00 24.--30. 1. "odtloff,LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "t_ccd_mw,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "t_ppd,LPDDR4: tPPD: This is the minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DRAMTMG14,SDRAM Timing Register 14"
|
|
hexmask.long.word 0x00 0.--11. 1. "t_xsr,tXSR: Exit Self Refresh to any command"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DRAMTMG15,SDRAM Timing Register 15"
|
|
bitfld.long 0x00 31. "en_dfi_lp_t_stab,Enable DFI tSTAB" "0: Disable using tSTAB when exiting DFI LP,1: Enable using tSTAB when exiting DFI LP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "t_stab_x32,tSTAB: Stabilization time"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "ZQCTL0,ZQ Control Register 0"
|
|
bitfld.long 0x00 31. "dis_auto_zq,Disable Auto ZQCS/MPC" "0: Internally generate ZQCS/MPC(ZQ calibration)..,1: Disable DDRC generation of ZQCS/MPC(ZQ.."
|
|
newline
|
|
bitfld.long 0x00 30. "dis_srx_zqcl,Disable ZQCL/MPC" "0: Enable issuing of ZQCL/MPC(ZQ calibration)..,1: Disable issuing of ZQCL/MPC(ZQ calibration).."
|
|
newline
|
|
bitfld.long 0x00 29. "zq_resistor_shared,ZQ resistor sharing" "0: ZQ resistor is not shared,1: Denotes that ZQ resistor is shared between.."
|
|
newline
|
|
bitfld.long 0x00 28. "dis_mpsmx_zqcl,Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC configuration parameter is set" "0: Enable issuing of ZQCL command at Maximum..,1: Disable issuing of ZQCL command at Maximum.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--26. 1. "t_zq_long_nop,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "t_zq_short_nop,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "ZQCTL1,ZQ Control Register 1"
|
|
hexmask.long.word 0x00 20.--29. 1. "t_zq_reset_nop,tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "t_zq_short_interval_x1024,Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "ZQCTL2,ZQ Control Register 2"
|
|
bitfld.long 0x00 0. "zq_reset,Setting this register bit to 1 triggers a ZQ Reset operation" "0,1"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "ZQSTAT,ZQ Status Register"
|
|
bitfld.long 0x00 0. "zq_reset_busy,SoC core may initiate a ZQ Reset operation only if this signal is low" "0: Indicates that the SoC core can initiate a ZQ..,1: Indicates that ZQ Reset operation is in.."
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "DFITMG0,DFI Timing Register 0"
|
|
bitfld.long 0x00 24.--28. "dfi_t_ctrl_delay,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 23. "dfi_rddata_use_sdr,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "dfi_t_rddata_en,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal"
|
|
newline
|
|
bitfld.long 0x00 15. "dfi_wrdata_use_sdr,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "dfi_tphy_wrdata,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "dfi_tphy_wrlat,Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "DFITMG1,DFI Timing Register 1"
|
|
bitfld.long 0x00 28.--31. "dfi_t_cmd_lat,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "dfi_t_parin_lat,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "dfi_t_wrdata_delay,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "dfi_t_dram_clk_disable,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "dfi_t_dram_clk_enable,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "DFILPCFG0,DFI Low Power Configuration Register 0"
|
|
bitfld.long 0x00 24.--28. "dfi_tlp_resp,Setting in DFI clock cycles for DFI's tlp_resp time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "dfi_lp_wakeup_dpd,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered" "0: dfi_lp_wakeup_dpd_0,1: dfi_lp_wakeup_dpd_1,2: dfi_lp_wakeup_dpd_2,3: dfi_lp_wakeup_dpd_3,4: dfi_lp_wakeup_dpd_4,5: dfi_lp_wakeup_dpd_5,6: dfi_lp_wakeup_dpd_6,7: dfi_lp_wakeup_dpd_7,8: dfi_lp_wakeup_dpd_8,9: dfi_lp_wakeup_dpd_9,10: dfi_lp_wakeup_dpd_10,11: dfi_lp_wakeup_dpd_11,12: dfi_lp_wakeup_dpd_12,13: dfi_lp_wakeup_dpd_13,14: dfi_lp_wakeup_dpd_14,15: dfi_lp_wakeup_dpd_15"
|
|
newline
|
|
bitfld.long 0x00 16. "dfi_lp_en_dpd,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit" "0: Disabled,1: Enabled This is only present"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "dfi_lp_wakeup_sr,Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered" "0: dfi_lp_wakeup_sr_0,1: dfi_lp_wakeup_sr_1,2: dfi_lp_wakeup_sr_2,3: dfi_lp_wakeup_sr_3,4: dfi_lp_wakeup_sr_4,5: dfi_lp_wakeup_sr_5,6: dfi_lp_wakeup_sr_6,7: dfi_lp_wakeup_sr_7,8: dfi_lp_wakeup_sr_8,9: dfi_lp_wakeup_sr_9,10: dfi_lp_wakeup_sr_10,11: dfi_lp_wakeup_sr_11,12: dfi_lp_wakeup_sr_12,13: dfi_lp_wakeup_sr_13,14: dfi_lp_wakeup_sr_14,15: dfi_lp_wakeup_sr_15"
|
|
newline
|
|
bitfld.long 0x00 8. "dfi_lp_en_sr,Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit" "0: dfi_lp_en_sr_0,1: dfi_lp_en_sr_1"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "dfi_lp_wakeup_pd,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered" "0: dfi_lp_wakeup_pd_0,1: dfi_lp_wakeup_pd_1,2: dfi_lp_wakeup_pd_2,3: dfi_lp_wakeup_pd_3,4: dfi_lp_wakeup_pd_4,5: dfi_lp_wakeup_pd_5,6: dfi_lp_wakeup_pd_6,7: dfi_lp_wakeup_pd_7,8: dfi_lp_wakeup_pd_8,9: dfi_lp_wakeup_pd_9,10: dfi_lp_wakeup_pd_10,11: dfi_lp_wakeup_pd_11,12: dfi_lp_wakeup_pd_12,13: dfi_lp_wakeup_pd_13,14: dfi_lp_wakeup_pd_14,15: dfi_lp_wakeup_pd_15"
|
|
newline
|
|
bitfld.long 0x00 0. "dfi_lp_en_pd,Enables DFI Low Power interface handshaking during Power Down Entry/Exit" "0: Disabled,1: Enabled"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "DFILPCFG1,DFI Low Power Configuration Register 1"
|
|
bitfld.long 0x00 4.--7. "dfi_lp_wakeup_mpsm,Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered" "0: dfi_lp_wakeup_mpsm_0,1: dfi_lp_wakeup_mpsm_1,2: dfi_lp_wakeup_mpsm_2,3: dfi_lp_wakeup_mpsm_3,4: dfi_lp_wakeup_mpsm_4,5: dfi_lp_wakeup_mpsm_5,6: dfi_lp_wakeup_mpsm_6,7: dfi_lp_wakeup_mpsm_7,8: dfi_lp_wakeup_mpsm_8,9: dfi_lp_wakeup_mpsm_9,10: dfi_lp_wakeup_mpsm_10,11: dfi_lp_wakeup_mpsm_11,12: dfi_lp_wakeup_mpsm_12,13: dfi_lp_wakeup_mpsm_13,14: dfi_lp_wakeup_mpsm_14,15: dfi_lp_wakeup_mpsm_15"
|
|
newline
|
|
bitfld.long 0x00 0. "dfi_lp_en_mpsm,Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit" "0: Disabled,1: Enabled This is only present"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "DFIUPD0,DFI Update Register 0"
|
|
bitfld.long 0x00 31. "dis_auto_ctrlupd,automatic dfi_ctrlupd_req generation by the DDRC" "0: DDRC issues dfi_ctrlupd_req periodically,1: disable the automatic dfi_ctrlupd_req.."
|
|
newline
|
|
bitfld.long 0x00 30. "dis_auto_ctrlupd_srx,Auto ctrlupd request generation" "0: DDRC issues a dfi_ctrlupd_req before or after..,1: disable the automatic dfi_ctrlupd_req.."
|
|
newline
|
|
bitfld.long 0x00 29. "ctrlupd_pre_srx,Selects dfi_ctrlupd_req requirements at SRX" "0: send ctrlupd after SRX,1: send ctrlupd before SRX"
|
|
newline
|
|
hexmask.long.word 0x00 16.--25. 1. "dfi_t_ctrlup_max,Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "dfi_t_ctrlup_min,Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "DFIUPD1,DFI Update Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "dfi_t_ctrlupd_interval_min_x1024,This is the minimum amount of time between DDRC initiated DFI update requests (which is executed whenever the DDRC is idle)"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "dfi_t_ctrlupd_interval_max_x1024,This is the maximum amount of time between DDRC initiated DFI update requests"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "DFIUPD2,DFI Update Register 2"
|
|
bitfld.long 0x00 31. "dfi_phyupd_en,Enables the support for acknowledging PHY-initiated updates" "0: dfi_phyupd_en_0,1: dfi_phyupd_en_1"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "DFIMISC,DFI Miscellaneous Control Register"
|
|
bitfld.long 0x00 8.--12. "dfi_frequency,Indicates the operating frequency of the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5. "dfi_init_start,PHY init start request signal.When asserted it triggers the PHY init start request" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ctl_idle_en,Enables support of ctl_idle signal which is non-DFI related pin specific to certain PHYs" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "dfi_data_cs_polarity,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals" "0: dfi_data_cs_polarity_0,1: Signals are active high"
|
|
newline
|
|
bitfld.long 0x00 1. "phy_dbi_mode,DBI implemented in DDRC or PHY" "0: DDRC implements DBI functionality,1: PHY implements DBI functionality"
|
|
newline
|
|
bitfld.long 0x00 0. "dfi_init_complete_en,PHY initialization complete enable signal" "0,1"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "DFITMG2,DFI Timing Register 2"
|
|
hexmask.long.byte 0x00 8.--14. 1. "dfi_tphy_rdcslat,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "dfi_tphy_wrcslat,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "DFITMG3,DFI Timing Register 3"
|
|
bitfld.long 0x00 0.--4. "dfi_t_geardown_delay,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "DFISTAT,DFI Status Register"
|
|
bitfld.long 0x00 1. "dfi_lp_ack,Stores the value of the dfi_lp_ack input to the controller" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dfi_init_complete,The status flag register which announces when the DFI initialization has been completed" "0,1"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "DBICTL,DM/DBI Control Register"
|
|
bitfld.long 0x00 2. "rd_dbi_en,Read DBI enable signal in DDRC" "0: Read DBI is disabled,1: Read DBI is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "wr_dbi_en,This signal must be set the same value as DRAM's mode register" "0: Write DBI is disabled,1: Write DBI is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "dm_en,DM enable signal in DDRC" "0: DM is disabled,1: DM is enabled"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "ADDRMAP0,Address Map Register 0"
|
|
bitfld.long 0x00 0.--4. "addrmap_cs_bit0,Selects the HIF address bit used as rank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "ADDRMAP1,Address Map Register 1"
|
|
bitfld.long 0x00 16.--20. "addrmap_bank_b2,Selects the HIF address bit used as bank address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "addrmap_bank_b1,Selects the HIF address bits used as bank address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "addrmap_bank_b0,Selects the HIF address bits used as bank address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "ADDRMAP2,Address Map Register 2"
|
|
bitfld.long 0x00 24.--27. "addrmap_col_b5,- Full bus width mode: Selects the HIF address bit used as column address bit 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "addrmap_col_b4,- Full bus width mode: Selects the HIF address bit used as column address bit 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "addrmap_col_b3,- Full bus width mode: Selects the HIF address bit used as column address bit 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "addrmap_col_b2,- Full bus width mode: Selects the HIF address bit used as column address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "ADDRMAP3,Address Map Register 3"
|
|
bitfld.long 0x00 24.--27. "addrmap_col_b9,- Full bus width mode: Selects the HIF address bit used as column address bit 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "addrmap_col_b8,- Full bus width mode: Selects the HIF address bit used as column address bit 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "addrmap_col_b7,- Full bus width mode: Selects the HIF address bit used as column address bit 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "addrmap_col_b6,- Full bus width mode: Selects the HIF address bit used as column address bit 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "ADDRMAP4,Address Map Register 4"
|
|
bitfld.long 0x00 8.--11. "addrmap_col_b11,- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "addrmap_col_b10,- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "ADDRMAP5,Address Map Register 5"
|
|
bitfld.long 0x00 24.--27. "addrmap_row_b11,Selects the HIF address bit used as row address bit 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "addrmap_row_b2_10,Selects the HIF address bits used as row address bits 2 to 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "addrmap_row_b1,Selects the HIF address bits used as row address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "addrmap_row_b0,Selects the HIF address bits used as row address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "ADDRMAP6,Address Map Register 6"
|
|
bitfld.long 0x00 31. "lpddr3_6gb_12gb,Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use" "0: non-LPDDR3 6Gb/12Gb device in use,1: LPDDR3 SDRAM 6Gb/12Gb device in use"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "addrmap_row_b15,Selects the HIF address bit used as row address bit 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "addrmap_row_b14,Selects the HIF address bit used as row address bit 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "addrmap_row_b13,Selects the HIF address bit used as row address bit 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "addrmap_row_b12,Selects the HIF address bit used as row address bit 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "ADDRMAP7,Address Map Register 7"
|
|
bitfld.long 0x00 8.--11. "addrmap_row_b17,Selects the HIF address bit used as row address bit 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "addrmap_row_b16,Selects the HIF address bit used as row address bit 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "ADDRMAP8,Address Map Register 8"
|
|
bitfld.long 0x00 8.--13. "addrmap_bg_b1,Selects the HIF address bits used as bank group address bit 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "addrmap_bg_b0,Selects the HIF address bits used as bank group address bit 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "ADDRMAP9,Address Map Register 9"
|
|
bitfld.long 0x00 24.--27. "addrmap_row_b5,Selects the HIF address bits used as row address bit 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "addrmap_row_b4,Selects the HIF address bits used as row address bit 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "addrmap_row_b3,Selects the HIF address bits used as row address bit 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "addrmap_row_b2,Selects the HIF address bits used as row address bit 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "ADDRMAP10,Address Map Register 10"
|
|
bitfld.long 0x00 24.--27. "addrmap_row_b9,Selects the HIF address bits used as row address bit 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "addrmap_row_b8,Selects the HIF address bits used as row address bit 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "addrmap_row_b7,Selects the HIF address bits used as row address bit 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "addrmap_row_b6,Selects the HIF address bits used as row address bit 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "ADDRMAP11,Address Map Register 11"
|
|
bitfld.long 0x00 0.--3. "addrmap_row_b10,Selects the HIF address bits used as row address bit 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "ODTCFG,ODT Configuration Register"
|
|
bitfld.long 0x00 24.--27. "wr_odt_hold,DFI PHY clock cycles to hold ODT for a write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "wr_odt_delay,The delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "rd_odt_hold,DFI PHY clock cycles to hold ODT for a read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--6. "rd_odt_delay,The delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "ODTMAP,ODT/Rank Map Register"
|
|
bitfld.long 0x00 12.--13. "rank1_rd_odt,Indicates which remote ODTs must be turned on during a read from rank 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "rank1_wr_odt,Indicates which remote ODTs must be turned on during a write to rank 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "rank0_rd_odt,Indicates which remote ODTs must be turned on during a read from rank 0" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "rank0_wr_odt,Indicates which remote ODTs must be turned on during a write to rank 0" "0,1,2,3"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "SCHED,Scheduler Control Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. "rdwr_idle_gap,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "go2critical_hysteresis,UNUSED"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "lpr_num_entries,Number of entries in the low priority transaction store is this value + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2. "pageclose,If true bank is kept open only while there are page hit transactions available in the CAM to that bank" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "prefer_write,If set then the bank selector prefers writes over reads" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "force_low_pri_n,Active low signal" "0,1"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "SCHED1,Scheduler Control Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "pageclose_timer,This field works in conjunction with SCHED.pageclose"
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "PERFHPR1,High Priority Read CAM Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "hpr_xact_run_length,Number of transactions that are serviced once the HPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "hpr_max_starve,Number of DFI clocks that the HPR queue can be starved before it goes critical"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "PERFLPR1,Low Priority Read CAM Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "lpr_xact_run_length,Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "lpr_max_starve,Number of DFI clocks that the LPR queue can be starved before it goes critical"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "PERFWR1,Write CAM Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "w_xact_run_length,Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "w_max_starve,Number of DFI clocks that the WR queue can be starved before it goes critical"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DBG0,Debug Register 0"
|
|
bitfld.long 0x00 4. "dis_collision_page_opt,When this is set to '0' auto-precharge is disabled for the flushed command in a collision case" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "dis_act_bypass,Only present in designs supporting activate bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "dis_rd_bypass,Only present in designs supporting read bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dis_wc,When 1 disable write combine" "0,1"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DBG1,Debug Register 1"
|
|
bitfld.long 0x00 1. "dis_hif,When 1 DDRC asserts the HIF command signal hif_cmd_stall" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "dis_dq,When 1 DDRC will not de-queue any transactions from the CAM" "0,1"
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "DBGCAM,CAM Debug Register"
|
|
bitfld.long 0x00 31. "dbg_stall_rd,Stall for Read channel FOR DEBUG ONLY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "dbg_stall_wr,Stall for Write channel FOR DEBUG ONLY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "wr_data_pipeline_empty,This bit indicates that the write data pipeline on the DFI interface is empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "rd_data_pipeline_empty,This bit indicates that the read data pipeline on the DFI interface is empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "dbg_wr_q_empty,When 1 all the Write command queues and Write data buffers inside DDRC are empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "dbg_rd_q_empty,When 1 all the Read command queues and Read data buffers inside DDRC are empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "dbg_stall,Stall FOR DEBUG ONLY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "dbg_w_q_depth,Write queue depth The last entry of WR queue is reserved for ECC SCRUB operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "dbg_lpr_q_depth,Low priority read queue depth The last entry of Lpr queue is reserved for ECC SCRUB operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "dbg_hpr_q_depth,High priority read queue depth FOR DEBUG ONLY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "DBGCMD,Command Debug Register"
|
|
bitfld.long 0x00 5. "ctrlupd,Setting this register bit to 1 indicates to the DDRC to issue a dfi_ctrlupd_req to the PHY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "zq_calib_short,Setting this register bit to 1 indicates to the DDRC to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "rank1_refresh,Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "rank0_refresh,Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank 0" "0,1"
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "DBGSTAT,Status Debug Register"
|
|
bitfld.long 0x00 5. "ctrlupd_busy,SoC core may initiate a ctrlupd operation only if this signal is low" "0: Indicates that the SoC core can initiate a,1: Indicates that ctrlupd operation has not been"
|
|
newline
|
|
bitfld.long 0x00 4. "zq_calib_short_busy,SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low" "0: Indicates that the SoC core can initiate a ZQCS,1: Indicates that ZQCS operation has not been"
|
|
newline
|
|
bitfld.long 0x00 1. "rank1_refresh_busy,SoC core may initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low" "0: Indicates that the SoC core can initiate a,1: Indicates that rank1_refresh operation has not"
|
|
newline
|
|
bitfld.long 0x00 0. "rank0_refresh_busy,SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low" "0: Indicates that the SoC core can initiate a,1: Indicates that rank0_refresh operation has not"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "SWCTL,Software Register Programming Control Enable"
|
|
bitfld.long 0x00 0. "sw_done,Enable quasi-dynamic register programming outside reset" "0,1"
|
|
rgroup.long 0x324++0x03
|
|
line.long 0x00 "SWSTAT,Software Register Programming Control Status"
|
|
bitfld.long 0x00 0. "sw_done_ack,Register programming done" "0,1"
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "POISONCFG,AXI Poison Configuration Register"
|
|
bitfld.long 0x00 24. "rd_poison_intr_clr,Interrupt clear for read transaction poisoning" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "rd_poison_intr_en,If set to 1 enables interrupts for read transaction poisoning" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "rd_poison_slverr_en,If set to 1 enables SLVERR response for read transaction poisoning" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "wr_poison_intr_clr,Interrupt clear for write transaction poisoning" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "wr_poison_intr_en,If set to 1 enables interrupts for write transaction poisoning" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wr_poison_slverr_en,If set to 1 enables SLVERR response for write transaction poisoning" "0,1"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "POISONSTAT,AXI Poison Status Register"
|
|
bitfld.long 0x00 16. "rd_poison_intr_0,Read transaction poisoning error interrupt for port 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "wr_poison_intr_0,Write transaction poisoning error interrupt for port 0" "0,1"
|
|
rgroup.long 0x3FC++0x03
|
|
line.long 0x00 "PSTAT,Port Status Register"
|
|
bitfld.long 0x00 16. "wr_port_busy_0,Indicates if there are outstanding writes for AXI port 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "rd_port_busy_0,Indicates if there are outstanding reads for AXI port 0" "0,1"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PCCFG,Port Common Configuration Register"
|
|
bitfld.long 0x00 8. "bl_exp_mode,Burst length expansion mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "pagematch_limit,Page match four limit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "go2critical_en,If set to 1 (enabled) sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent arurgent) coming from AXI master" "0,1"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "PCFGR_0,Port n Configuration Read Register"
|
|
bitfld.long 0x00 16. "rdwr_ordered_en,Enable ordered read/writes" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "rd_port_pagematch_en,If set to 1 enables the Page Match feature" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "rd_port_urgent_en,If set to 1 enables the AXI urgent sideband signal (arurgent)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "rd_port_aging_en,If set to 1 enables aging function for the read channel of the port" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "rd_port_priority,Determines the initial load value of read aging counters"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "PCFGW_0,Port n Configuration Write Register"
|
|
bitfld.long 0x00 14. "wr_port_pagematch_en,If set to 1 enables the Page Match feature" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "wr_port_urgent_en,If set to 1 enables the AXI urgent sideband signal (awurgent)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "wr_port_aging_en,If set to 1 enables aging function for the write channel of the port" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "wr_port_priority,Determines the initial load value of write aging counters"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "PCTRL_0,Port n Control Register"
|
|
bitfld.long 0x00 0. "port_en,Enables AXI port n" "0,1"
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "PCFGQOS0_0,Port n Read QoS Configuration Register 0"
|
|
bitfld.long 0x00 20.--21. "rqos_map_region1,This bitfield indicates the traffic class of region 1" "0: LPR and,1: VPR only,2: HPR,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--17. "rqos_map_region0,This bitfield indicates the traffic class of region 0" "0: LPR and,1: VPR only,2: HPR,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "rqos_map_level1,Separation level1 indicating the end of region0 mapping start of region0 is 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "PCFGQOS1_0,Port n Read QoS Configuration Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. "rqos_map_timeoutr,Specifies the timeout value for transactions mapped to the red address queue"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "rqos_map_timeoutb,Specifies the timeout value for transactions mapped to the blue address queue"
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "PCFGWQOS0_0,Port n Write QoS Configuration Register 0"
|
|
bitfld.long 0x00 20.--21. "wqos_map_region1,This bitfield indicates the traffic class of region 1" "0: NPW,1: VPW,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--17. "wqos_map_region0,This bitfield indicates the traffic class of region 0" "0: NPW,1: VPW,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "wqos_map_level,Separation level indicating the end of region0 mapping start of region0 is 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1"
|
|
hexmask.long.word 0x00 0.--10. 1. "wqos_map_timeout,Specifies the timeout value for write transactions"
|
|
group.long 0x2020++0x03
|
|
line.long 0x00 "DERATEEN_SHADOW,[SHADOW] Temperature Derate Enable Register"
|
|
bitfld.long 0x00 8.--9. "rc_derate_value,Derate value of tRC for LPDDR4" "0: Derating uses +1,1: Derating uses +2,2: Derating uses +3,3: Derating uses +4"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "derate_byte,Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used for derating" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. "derate_value,Derate value" "0: Derating uses +1,1: Derating uses +2"
|
|
newline
|
|
bitfld.long 0x00 0. "derate_enable,Enables derating" "0: Timing parameter derating is disabled,1: Timing parameter derating is enabled using MR4"
|
|
group.long 0x2024++0x03
|
|
line.long 0x00 "DERATEINT_SHADOW,[SHADOW] Temperature Derate Interval Register"
|
|
hexmask.long 0x00 0.--31. 1. "mr4_read_interval,Interval between two MR4 reads used to derate the timing parameters"
|
|
group.long 0x2050++0x03
|
|
line.long 0x00 "RFSHCTL0_SHADOW,[SHADOW] Refresh Control Register 0"
|
|
bitfld.long 0x00 20.--23. "refresh_margin,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--16. "refresh_to_x32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once but it has not expired (RFSHCTL0.refresh_burst+1) times yet then a speculative refresh may be performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 4.--8. "refresh_burst,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute" "0: single refresh,1: burst-of-2 refresh,?,?,?,?,?,7: burst-of-8 refresh For information on burst,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "per_bank_refresh," "0: All bank refresh,1: Per bank refresh"
|
|
group.long 0x2064++0x03
|
|
line.long 0x00 "RFSHTMG_SHADOW,[SHADOW] Refresh Timing Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "t_rfc_nom_x32,tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4)"
|
|
newline
|
|
bitfld.long 0x00 15. "lpddr3_trefbw_en,Used only when LPDDR3 memory type is connected" "0: tREFBW parameter not used,1: tREFBW parameter used"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "t_rfc_min,tRFC (min): Minimum time from refresh to refresh or activate"
|
|
group.long 0x20DC++0x03
|
|
line.long 0x00 "INIT3_SHADOW,[SHADOW] SDRAM Initialization Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "mr,DDR2: Value to write to MR register"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "emr,DDR2: Value to write to EMR register"
|
|
group.long 0x20E0++0x03
|
|
line.long 0x00 "INIT4_SHADOW,[SHADOW] SDRAM Initialization Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "emr2,DDR2: Value to write to EMR2 register"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "emr3,DDR2: Value to write to EMR3 register"
|
|
group.long 0x20E8++0x03
|
|
line.long 0x00 "INIT6_SHADOW,[SHADOW] SDRAM Initialization Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. "mr4,DDR4- Value to be loaded into SDRAM MR4 registers"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "mr5,DDR4- Value to be loaded into SDRAM MR5 registers"
|
|
group.long 0x20EC++0x03
|
|
line.long 0x00 "INIT7_SHADOW,[SHADOW] SDRAM Initialization Register 7"
|
|
hexmask.long.word 0x00 16.--31. 1. "mr6,DDR4- Value to be loaded into SDRAM MR6 registers"
|
|
group.long 0x2100++0x03
|
|
line.long 0x00 "DRAMTMG0_SHADOW,[SHADOW] SDRAM Timing Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. "wr2pre,Minimum time between write and precharge to same bank"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "t_faw,tFAW Valid only when 8 or more banks(or banks x bank groups) are present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "t_ras_max,tRAS(max): Maximum time between activate and precharge to same bank"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "t_ras_min,tRAS(min): Minimum time between activate and precharge to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2104++0x03
|
|
line.long 0x00 "DRAMTMG1_SHADOW,[SHADOW] SDRAM Timing Register 1"
|
|
bitfld.long 0x00 16.--20. "t_xp,tXP: Minimum time after power-down exit to any operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "rd2pre,tRTP: Minimum time from read to precharge of same bank" "?,?,2: DDR3,?,4: LPDDR4,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "t_rc,tRC: Minimum time between activates to same bank"
|
|
group.long 0x2108++0x03
|
|
line.long 0x00 "DRAMTMG2_SHADOW,[SHADOW] SDRAM Timing Register 2"
|
|
bitfld.long 0x00 24.--29. "write_latency,Set to WL Time from write command to write data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "read_latency,Set to RL Time from read command to read data on SDRAM interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "rd2wr,DDR2/3/mDDR: RL + BL/2 +" "?,1: WL LPDDR4(DQ ODT is Disabled),2: WL DDR4,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--5. "wr2rd,DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x210C++0x03
|
|
line.long 0x00 "DRAMTMG3_SHADOW,[SHADOW] SDRAM Timing Register 3"
|
|
hexmask.long.word 0x00 20.--29. 1. "t_mrw,Time to wait after a mode register write or read (MRW or MRR)"
|
|
newline
|
|
bitfld.long 0x00 12.--17. "t_mrd,tMRD: Cycles to wait after a mode register write or read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "t_mod,tMOD: Parameter used only in DDR3 and DDR4"
|
|
group.long 0x2110++0x03
|
|
line.long 0x00 "DRAMTMG4_SHADOW,[SHADOW] SDRAM Timing Register 4"
|
|
bitfld.long 0x00 24.--28. "t_rcd,tRCD - tAL: Minimum time from activate to read or write command to same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "t_ccd,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "t_rrd,DDR4: tRRD_L: Minimum time between activates from bank a to bank b for same bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "t_rp,tRP: Minimum time from precharge to activate of same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2114++0x03
|
|
line.long 0x00 "DRAMTMG5_SHADOW,[SHADOW] SDRAM Timing Register 5"
|
|
bitfld.long 0x00 24.--27. "t_cksrx,This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX" "?,1: DDR3,2: LPDDR4,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "t_cksre,This is the time after Self Refresh Down Entry that CK is maintained as a valid clock" "0: LPDDR2,1: DDR3,2: LPDDR4,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--13. "t_ckesr,Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "t_cke,Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2118++0x03
|
|
line.long 0x00 "DRAMTMG6_SHADOW,[SHADOW] SDRAM Timing Register 6"
|
|
bitfld.long 0x00 24.--27. "t_ckdpde,This is the time after Deep Power Down Entry that CK is maintained as a valid clock" "0: LPDDR2,?,2: LPDDR3,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "t_ckdpdx,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX" "?,1: LPDDR2,2: LPDDR3,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "t_ckcsx,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit" "?,1: LPDDR2,2: LPDDR4,?..."
|
|
group.long 0x211C++0x03
|
|
line.long 0x00 "DRAMTMG7_SHADOW,[SHADOW] SDRAM Timing Register 7"
|
|
bitfld.long 0x00 8.--11. "t_ckpde,This is the time after Power Down Entry that CK is maintained as a valid clock" "0: LPDDR2,?,2: LPDDR4,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "t_ckpdx,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX" "0: LPDDR2,?,2: LPDDR4,?..."
|
|
group.long 0x2120++0x03
|
|
line.long 0x00 "DRAMTMG8_SHADOW,[SHADOW] SDRAM Timing Register 8"
|
|
hexmask.long.byte 0x00 24.--30. 1. "t_xs_fast_x32,tXS_FAST: Exit Self Refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode)"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "t_xs_abort_x32,tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "t_xs_dll_x32,tXSDLL: Exit Self Refresh to commands requiring a locked DLL"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "t_xs_x32,tXS: Exit Self Refresh to commands not requiring a locked DLL"
|
|
group.long 0x2124++0x03
|
|
line.long 0x00 "DRAMTMG9_SHADOW,[SHADOW] SDRAM Timing Register 9"
|
|
bitfld.long 0x00 30. "ddr4_wr_preamble,DDR4 Write preamble mode" "0: 1tCK preamble,1: 2tCK preamble Present only with"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "t_ccd_s,tCCD_S: This is the minimum time between two reads or two writes for different bank group" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "t_rrd_s,tRRD_S: Minimum time between activates from bank a to bank b for different bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "wr2rd_s,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2128++0x03
|
|
line.long 0x00 "DRAMTMG10_SHADOW,[SHADOW] SDRAM Timing Register 10"
|
|
bitfld.long 0x00 16.--20. "t_sync_gear,Indicates the time between MRS command and the sync pulse time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "t_cmd_gear,Sync pulse to first valid command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "t_gear_setup,Geardown setup time" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "t_gear_hold,Geardown hold time" "0,1,2,3"
|
|
group.long 0x212C++0x03
|
|
line.long 0x00 "DRAMTMG11_SHADOW,[SHADOW] SDRAM Timing Register 11"
|
|
hexmask.long.byte 0x00 24.--30. 1. "post_mpsm_gap_x32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "t_mpx_lh,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "t_mpx_s,tMPX_S: Minimum time CS setup time to CKE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "t_ckmpe,tCKMPE: Minimum valid clock requirement after MPSM entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2130++0x03
|
|
line.long 0x00 "DRAMTMG12_SHADOW,[SHADOW] SDRAM Timing Register 12"
|
|
bitfld.long 0x00 16.--17. "t_cmdcke,tCMDCKE: Delay from valid command to CKE input LOW" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "t_ckehcmd,tCKEHCMD: Valid command requirement after CKE input HIGH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "t_mrd_pda,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2134++0x03
|
|
line.long 0x00 "DRAMTMG13_SHADOW,[SHADOW] SDRAM Timing Register 13"
|
|
hexmask.long.byte 0x00 24.--30. 1. "odtloff,LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "t_ccd_mw,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "t_ppd,LPDDR4: tPPD: This is the minimum time from precharge to precharge command" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2138++0x03
|
|
line.long 0x00 "DRAMTMG14_SHADOW,[SHADOW] SDRAM Timing Register 14"
|
|
hexmask.long.word 0x00 0.--11. 1. "t_xsr,tXSR: Exit Self Refresh to any command"
|
|
group.long 0x213C++0x03
|
|
line.long 0x00 "DRAMTMG15_SHADOW,[SHADOW] SDRAM Timing Register 15"
|
|
bitfld.long 0x00 31. "en_dfi_lp_t_stab," "0: Disable using tSTAB when exiting DFI LP,1: Enable using tSTAB when exiting DFI LP"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "t_stab_x32,tSTAB: Stabilization time"
|
|
group.long 0x2180++0x03
|
|
line.long 0x00 "ZQCTL0_SHADOW,[SHADOW] ZQ Control Register 0"
|
|
bitfld.long 0x00 31. "dis_auto_zq," "0: Internally generate ZQCS/MPC(ZQ calibration),1: Disable DDRC generation of ZQCS/MPC(ZQ"
|
|
newline
|
|
bitfld.long 0x00 30. "dis_srx_zqcl," "0: Enable issuing of ZQCL/MPC(ZQ calibration),1: Disable issuing of ZQCL/MPC(ZQ calibration)"
|
|
newline
|
|
bitfld.long 0x00 29. "zq_resistor_shared," "0: ZQ resistor is not shared,1: Denotes that ZQ resistor is shared between.."
|
|
newline
|
|
bitfld.long 0x00 28. "dis_mpsmx_zqcl," "0: Enable issuing of ZQCL command at Maximum Power,1: Disable issuing of ZQCL command at Maximum.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--26. 1. "t_zq_long_nop,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "t_zq_short_nop,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM"
|
|
group.long 0x2190++0x03
|
|
line.long 0x00 "DFITMG0_SHADOW,[SHADOW] DFI Timing Register 0"
|
|
bitfld.long 0x00 24.--28. "dfi_t_ctrl_delay,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 23. "dfi_rddata_use_sdr,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "dfi_t_rddata_en,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal"
|
|
newline
|
|
bitfld.long 0x00 15. "dfi_wrdata_use_sdr,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "dfi_tphy_wrdata,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "dfi_tphy_wrlat,Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2194++0x03
|
|
line.long 0x00 "DFITMG1_SHADOW,[SHADOW] DFI Timing Register 1"
|
|
bitfld.long 0x00 28.--31. "dfi_t_cmd_lat,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "dfi_t_parin_lat,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "dfi_t_wrdata_delay,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "dfi_t_dram_clk_disable,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "dfi_t_dram_clk_enable,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x21B4++0x03
|
|
line.long 0x00 "DFITMG2_SHADOW,[SHADOW] DFI Timing Register 2"
|
|
hexmask.long.byte 0x00 8.--14. 1. "dfi_tphy_rdcslat,Number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "dfi_tphy_wrcslat,Number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x21B8++0x03
|
|
line.long 0x00 "DFITMG3_SHADOW,[SHADOW] DFI Timing Register 3"
|
|
bitfld.long 0x00 0.--4. "dfi_t_geardown_delay,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2240++0x03
|
|
line.long 0x00 "ODTCFG_SHADOW,[SHADOW] ODT Configuration Register"
|
|
bitfld.long 0x00 24.--27. "wr_odt_hold,DFI PHY clock cycles to hold ODT for a write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "wr_odt_delay,The delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "rd_odt_hold,DFI PHY clock cycles to hold ODT for a read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--6. "rd_odt_delay,The delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "DWC_DDRPHY_TOP"
|
|
base ad:0x5C010000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RIDR,Revision Identification Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "UDRID,User-Defined Revision ID"
|
|
bitfld.long 0x00 20.--23. "PHYMJR,PHY Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "PHYMDR,PHY Moderate Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "PHYMNR,PHY Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PUBMJR,PUB Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "PUBMDR,PUB Moderate Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "PUBMNR,PUB Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PIR,PHY Initialization Register"
|
|
rbitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "ZCALBYP,Impedance Calibration Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "DCALPSE,Digital Delay Line (DDL) Calibration Pause" "0,1"
|
|
hexmask.long.byte 0x00 21.--28. 1. "RESERVED_28_21,Reserved"
|
|
newline
|
|
bitfld.long 0x00 20. "DQS2DQ,Write DQS2DQ Training" "0,1"
|
|
bitfld.long 0x00 19. "RDIMMINIT,RDIMM Initialization" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CTLDINIT,Controller DRAM Initialization" "0,1"
|
|
bitfld.long 0x00 17. "VREF,VREF Training" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "SRD,Static Read Training" "0,1"
|
|
bitfld.long 0x00 15. "WREYE,Write Data Eye Training" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "RDEYE,Read Data Eye Training" "0,1"
|
|
bitfld.long 0x00 13. "WRDSKW,Write Data Bit Deskew" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "RDDSKW,Read Data Bit Deskew" "0,1"
|
|
bitfld.long 0x00 11. "WLADJ,Write Leveling Adjust" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "QSGATE,Read DQS Gate Training" "0,1"
|
|
bitfld.long 0x00 9. "WL,Write Leveling" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DRAMINIT,DRAM Initialization" "0,1"
|
|
bitfld.long 0x00 7. "DRAMRST,DRAM Reset (DDR3/DDR4/LPDDR4 Only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PHYRST,PHY Reset" "0,1"
|
|
bitfld.long 0x00 5. "DCAL,Digital Delay Line (DDL) Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PLLINIT,PLL Initialiazation" "0,1"
|
|
rbitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CA,CA Training" "0,1"
|
|
bitfld.long 0x00 1. "ZCAL,Impedance Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INIT,Initialization Trigger" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PGCR0,PHY General Configuration Register 0"
|
|
bitfld.long 0x00 31. "ADCP,Address Copy" "0,1"
|
|
rbitfld.long 0x00 27.--30. "RESERVED_30_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 26. "PHYFRST,PHY FIFO Reset" "0,1"
|
|
bitfld.long 0x00 24.--25. "OSCACDL,Oscillator Mode Address/Command Delay Line Select" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 19.--23. "RESERVED_23_19,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14.--18. "DTOSEL,Digital Test Output Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 13. "RESERVED_13,Reserved" "0,1"
|
|
bitfld.long 0x00 9.--12. "OSCDIV,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "OSCEN,Oscillator Enable" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED_7_0,Reserved"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PGCR1,PHY General Configuration Register 1"
|
|
bitfld.long 0x00 31. "LBMODE,Loopback Mode" "0,1"
|
|
rbitfld.long 0x00 29.--30. "RESERVED_30_29,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 28. "LBGSDQS,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value (equivalent to one CK period)" "0,1"
|
|
bitfld.long 0x00 27. "DLTST,Delay Line Test Start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "DLTMODE,Delay Line Test Mode" "0,1"
|
|
bitfld.long 0x00 25. "PHYHRST,PHY High-Speed Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "ACVLDTRN,AC Loopback Valid Train" "0,1"
|
|
bitfld.long 0x00 21.--23. "ACVLDDLY,AC Loopback Valid Delay" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20. "LRDIMMST,LRDIMM Software Training" "0,1"
|
|
rbitfld.long 0x00 19. "RESERVED_19,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "UPDMSTRC0,DFI Update Master Channel 0" "0,1"
|
|
bitfld.long 0x00 17. "DISDIC,Enable/Disable control for dfi_init_complete" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ACPDDC,AC Power-Down with Dual Channels" "0,1"
|
|
bitfld.long 0x00 15. "DUALCHN,Dual Channel Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "FDEPTH,Filter Depth" "0,1,2,3"
|
|
bitfld.long 0x00 11.--12. "LPFDEPTH,Low-Pass Filter Depth" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10. "LPFEN,Low-Pass Filter Enable" "0,1"
|
|
bitfld.long 0x00 9. "MDLEN,Master Delay Line Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7.--8. "RESERVED_8_7,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 6. "PUBMODE,Enables if set the PUB to control the interface to the PHY and SDRAM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "CAST,CA Software Training" "0,1"
|
|
bitfld.long 0x00 4. "DX_DQSOUT_DIFF,Selects PDIFF cell for DQS generation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "AC_CKOUT_DIFF,Selects PDIFF cell for CK generation" "0,1"
|
|
bitfld.long 0x00 2. "WLSTEP,Write Leveling Step" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "WLMODE,Write Leveling (Software) Mode" "0,1"
|
|
bitfld.long 0x00 0. "DTOMODE,Digital Test Output Mode" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PGCR2,PHY General Configuration Register 2"
|
|
bitfld.long 0x00 31. "CLRTSTAT,Clear Training Status Registers" "0,1"
|
|
bitfld.long 0x00 30. "CLRZCAL,Clear Impedance Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "CLRPERR,Clear Parity Error" "0,1"
|
|
bitfld.long 0x00 28. "ICPC,Initialization Complete Pin Configuration" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 20.--27. 1. "DTPMXTMR,Data Training PUB Mode Exit Timer"
|
|
bitfld.long 0x00 19. "INITFSMBYP,Initialization Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "PLLFSMBYP,PLL FSM Bypass" "0,1"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "tREFPRD,Refresh Period"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PGCR3,PHY General Configuration Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CKNEN,CKN Enable"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CKEN,CK Enable"
|
|
newline
|
|
rbitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
bitfld.long 0x00 13.--14. "GATEACRDCLK,Enable Clock Gating for AC [0] ctl_rd_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 11.--12. "GATEACDDRCLK,Enable Clock Gating for AC [0] ddr_clk" "0,1,2,3"
|
|
bitfld.long 0x00 9.--10. "GATEACCTLCLK,Enable Clock Gating for AC [0] ctl_clk" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 8. "RESERVED_8,Reserved" "0,1"
|
|
bitfld.long 0x00 6.--7. "DDLBYPMODE,Controls DDL Bypass Modes" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "IOLB,IO Loop-Back Select" "0,1"
|
|
bitfld.long 0x00 3.--4. "RDMODE,AC Receive FIFO Read Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2. "DISRST,Read FIFO Reset Disable" "0,1"
|
|
bitfld.long 0x00 0.--1. "CLKLEVEL,Clock Level when Clock Gating" "0,1,2,3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PGCR4,PHY General Configuration Register 4"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 29. "ACDDLLD,AC DDL Delay Select Dymainc Load" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--28. "ACDDLBYP,AC DDL Bypass" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. "OEDDLBYP,AC OE DDL Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "TEDDLBYP,AC ODT DDL Bypass" "0,1"
|
|
bitfld.long 0x00 21. "PDRDDLBYP,AC PDR DDL Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "RRRMODE,AC Macro Read Path Rise-to-Rise Mode" "0,1"
|
|
bitfld.long 0x00 19. "WRRMODE,AC Macro Write Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 18. "RESERVED_18,Reserved" "0,1"
|
|
bitfld.long 0x00 17. "DCALTYPE,DDL Calibration Type" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 8.--16. 1. "DCALSVAL,DDL Calibration Starting Value"
|
|
bitfld.long 0x00 4.--7. "LPWAKEUP_THRSH,AC Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 1. "LPPLLPD,AC Low Power PLL Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "LPIOPD,AC Low Power IO Power Down" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PGCR5,PHY General Configuration Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. "FRQBT,Frequency B Ratio Term"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FRQAT,Frequency A Ratio Term"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DISCNPERIOD,DFI Disconnect Time Period"
|
|
bitfld.long 0x00 4.--7. "VREF_RBCTRL,Receiver bias core side control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
bitfld.long 0x00 2. "DXREFISELRANGE,Internal VREF generator REFSEL ragne select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DDLPGACT,DDL Page Read Write select" "0,1"
|
|
bitfld.long 0x00 0. "DDLPGRW,DDL Page Read Write select" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PGCR6,PHY General Configuration Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DLDLMT,Delay Line VT Drift Limit"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 13. "ACDLVT,AC Address/Command Delay LCDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "ACBVT,Address/Command Bit Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 11. "ODTBVT,ODT Bit Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "CKEBVT,CKE Bit Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 9. "CSNBVT,CSN Bit Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "CKBVT,CK Bit Delay VT Compensation" "0,1"
|
|
rbitfld.long 0x00 2.--7. "RESERVED_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 1. "FVT,Forced VT Compensation Trigger" "0,1"
|
|
bitfld.long 0x00 0. "INHVT,VT Calculation Inhibit" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PGCR7,PHY General Configuration Register 7"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
bitfld.long 0x00 6.--7. "ACRSVD_7_6,These bits are reserved for future AC special PHY modes but the registers are already connected to existing (unused) AC phy_mode bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "ACCALCLK,AC Calibration Clock Select" "0,1"
|
|
bitfld.long 0x00 4. "ACRCLKMD,AC Read Clock Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ACDLDT,AC DDL Load Type" "0,1"
|
|
bitfld.long 0x00 2. "ACRSVD_2,This bit is reserved for future AC special PHY modes but the register is already connected to existing (unused) AC phy_mode bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ACDTOSEL,AC Digital Test Output Select" "0,1"
|
|
bitfld.long 0x00 0. "ACTMODE,AC Test Mode" "0,1"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "PGSR0,PHY General Status Register 0"
|
|
bitfld.long 0x00 31. "APLOCK,AC PLL Lock" "0,1"
|
|
bitfld.long 0x00 30. "SRDERR,Static Read Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "CAWRN,CA Training Warning" "0,1"
|
|
bitfld.long 0x00 28. "CAERR,CA Training Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "WEERR,Write Eye Training Error" "0,1"
|
|
bitfld.long 0x00 26. "REERR,Read Eye Training Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "WDERR,Write Bit Deskew Error" "0,1"
|
|
bitfld.long 0x00 24. "RDERR,Read Bit Deskew Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "WLAERR,Write Leveling Adjustment Error" "0,1"
|
|
bitfld.long 0x00 22. "QSGERR,DQS Gate Training Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WLERR,Write Leveling Error" "0,1"
|
|
bitfld.long 0x00 20. "ZCERR,Impedance Calibration Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "VERR,VREF Training Error" "0,1"
|
|
bitfld.long 0x00 18. "DQS2DQERR,Write DQS2DQ Training Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "RESERVED_17_16,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 15. "DQS2DQDONE,Write DQS2DQ Training Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "VDONE,VREF Training Done" "0,1"
|
|
bitfld.long 0x00 13. "SRDDONE,Static Read Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "CADONE,CA Training Done" "0,1"
|
|
bitfld.long 0x00 11. "WEDONE,Write Eye Training Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "REDONE,Read Eye Training Done" "0,1"
|
|
bitfld.long 0x00 9. "WDDONE,Write Bit Deskew Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "RDDONE,Read Bit Deskew Done" "0,1"
|
|
bitfld.long 0x00 7. "WLADONE,Write Leveling Adjustment Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "QSGDONE,DQS Gate Training Done" "0,1"
|
|
bitfld.long 0x00 5. "WLDONE,Write Leveling Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DIDONE,DRAM Initialization Done" "0,1"
|
|
bitfld.long 0x00 3. "ZCDONE,Impedance Calibration Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DCDONE,Digital Delay Line (DDL) Calibration Done" "0,1"
|
|
bitfld.long 0x00 1. "PLDONE,PLL Lock Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IDONE,Initialization Done" "0,1"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "PGSR1,PHY General Status Register 1"
|
|
bitfld.long 0x00 31. "PARERR,RDIMM Parity Error" "0,1"
|
|
bitfld.long 0x00 30. "VTSTOP,VT Stop" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--29. "RESERVED_29_25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.tbyte 0x00 1.--24. 1. "DLTCODE,Delay Line Test Code for AC macro 0"
|
|
newline
|
|
bitfld.long 0x00 0. "DLTDONE,Delay Line Test Done for AC macro 0" "0,1"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "PGSR2,PHY General Status Register 2"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.tbyte 0x00 1.--24. 1. "DLTCODE,Delay Line Test Code for AC macro 1"
|
|
newline
|
|
bitfld.long 0x00 0. "DLTDONE,Delay Line Test Done for AC macro 1" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PTR0,PHY Timing Register 0"
|
|
hexmask.long.word 0x00 21.--31. 1. "tPLLPD,PLL Power-Down Time"
|
|
hexmask.long.word 0x00 6.--20. 1. "tPLLGS,PLL Gear Shift Time"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "tPHYRST,PHY Reset Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PTR1,PHY Timing Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "tPLLLOCK,PLL Lock Time"
|
|
rbitfld.long 0x00 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "tPLLRST,PLL Reset Time"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PTR2,PHY Timing Register 2"
|
|
hexmask.long.word 0x00 20.--31. 1. "RESERVED_31_20,Reserved"
|
|
bitfld.long 0x00 15.--19. "tWLDLYS,Write Leveling Delay Settling Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10.--14. "tCALH,Calibration Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--9. "tCALS,Calibration Setup Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "tCALON,Calibration On Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PTR3,PHY Timing Register 3"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED_31_23,Reserved"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. "tDINIT0,DRAM Initialization Time 0"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PTR4,PHY Timing Register 4"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED_31_13,Reserved"
|
|
hexmask.long.word 0x00 0.--12. 1. "tDINIT1,DRAM Initialization Time 1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PTR5,PHY Timing Register 5"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED_31_19,Reserved"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. "tDINIT2,DRAM Initialization Time 1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PTR6,PHY Timing Register 6"
|
|
rbitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 20.--26. 1. "tDINIT4,DRAM Initialization Time 4"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "RESERVED_19_12,Reserved"
|
|
hexmask.long.word 0x00 0.--11. 1. "tDINIT3,DRAM Initialization Time 3"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PLLCR0,PLL Control Register 0 (Type B PLL Only)"
|
|
bitfld.long 0x00 31. "PLLBYP,PLL Bypass" "0,1"
|
|
bitfld.long 0x00 30. "PLLRST,PLL Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PLLPD,PLL Power Down" "0,1"
|
|
bitfld.long 0x00 28. "RSTOPM,Reference Stop Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FRQSEL,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RLOCKM,Relock Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--22. "CPPC,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 13.--16. "CPIC,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "GSHIFT,Gear Shift" "0,1"
|
|
rbitfld.long 0x00 9.--11. "RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "ATOEN,Analog Test Enable" "0,1"
|
|
bitfld.long 0x00 4.--7. "ATC,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTC,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PLLCR1,PLL Control Register 1 (Type B PLL Only)"
|
|
hexmask.long.word 0x00 16.--31. 1. "PLLPROG,Connects to the PLL PLL_PROG bus"
|
|
hexmask.long.word 0x00 6.--15. 1. "RESERVED_15_6,Reserved"
|
|
newline
|
|
bitfld.long 0x00 5. "BYPVREGCP,Bypass PLL vreg_cp" "0,1"
|
|
bitfld.long 0x00 4. "BYPVREGDIG,Bypass PLL vreg_dig" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BYPVDD,PLL VDD voltage level control" "0,1"
|
|
bitfld.long 0x00 2. "LOCKPS,Lock Detector Phase Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKCS,Lock Detector Counter Select" "0,1"
|
|
bitfld.long 0x00 0. "LOCKDS,Lock Detector Select" "0,1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PLLCR2,PLL Control Register 2 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_31_0,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PLLCR3,PLL Control Register 3 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_63_32,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PLLCR4,PLL Control Register 4 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_95_64,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PLLCR5,PLL Control Register 5 (Type B PLL Only)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PLLCTRL_103_96,Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "DXCCR,DATX8 Common Configuration Register"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 29. "RKLOOP,Rank looping (per-rank eye centering) enable" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 7.--28. 1. "RESERVED_28_7,Reserved"
|
|
bitfld.long 0x00 3.--6. "DQS2DQMPER,Write DQS2DQ Training Measurement Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RESERVED_2_0,Reserved" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DSGCR,DDR System General Configuration Register"
|
|
rbitfld.long 0x00 28.--31. "RESERVED_31_28,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. "RDBICLSEL,When RDBI enabled this bit is used to select RDBI CL calculation if it is 1b1 calculation will use RDBICL otherwise use default calculation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "RDBICL,When RDBI enabled if RDBICLSEL is asserted RDBI CL adjust using this value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. "PHYZUEN,PHY Impedance Update Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
bitfld.long 0x00 21. "RSTOE,SDRAM Reset Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "SDRMODE,Single Data Rate Mode" "0,1,2,3"
|
|
rbitfld.long 0x00 18. "RESERVED_18,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "ATOAE,ATO Analog Test Enable" "0,1"
|
|
bitfld.long 0x00 16. "DTOOE,DTO Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "DTOIOM,DTO I/O Mode" "0,1"
|
|
bitfld.long 0x00 14. "DTOPDR,DTO Power Down Receiver" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 13. "RESERVED_13,Reserved" "0,1"
|
|
bitfld.long 0x00 12. "DTOODT,DTO On-Die Termination" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--11. "PUAD,PHY Update Acknowledge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 5. "CUAEN,Controller Update Acknowledge Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
bitfld.long 0x00 3. "MSTRVER,Master Version" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "CTLZUEN,Controller Impedance Update Enable" "0,1"
|
|
bitfld.long 0x00 1. "MREN,Master Request Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PUREN,PHY Update Request Enable" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "ODTCR,ODT Configuration Register"
|
|
rbitfld.long 0x00 28.--31. "RESERVED_31_28,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 17.--27. 1. "WRODT_RSVD,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "WRODT,Write ODT" "0,1"
|
|
rbitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 1.--11. 1. "RDODT_RSVD,Reserved"
|
|
bitfld.long 0x00 0. "RDODT,Read ODT" "0,1"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "AACR,Anti-Aging Control Register"
|
|
bitfld.long 0x00 31. "AAOENC,Anti-Aging PAD Output Enable Control" "0,1"
|
|
bitfld.long 0x00 30. "AAENC,Anti-Aging Enable Control" "0,1"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "AATR,Anti-Aging Toggle Rate"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "GPR0,General Purpose Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "GPR0,General Purpose Register 0"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "GPR1,General Purpose Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "GPR1,General Purpose Register 1"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DCR,DRAM Configuration Register"
|
|
bitfld.long 0x00 31. "GEARDN,DDR4 Gear Down Timing" "0,1"
|
|
bitfld.long 0x00 30. "UBG,Un-used Bank Group" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "UDIMM,Un-buffered DIMM Address Mirroring" "0,1"
|
|
bitfld.long 0x00 28. "DDR2T,DDR 2T Timing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "NOSRA,No Simultaneous Rank Access" "0,1"
|
|
hexmask.long.word 0x00 18.--26. 1. "RESERVED_26_18,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--17. 1. "BYTEMASK,Byte Mask"
|
|
bitfld.long 0x00 8.--9. "DDRTYPE,DDR Type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7. "MPRDQ,Multi-Purpose Register (MPR) DQ (DDR3 Only)" "0,1"
|
|
bitfld.long 0x00 4.--6. "PDQ,Primary DQ (DDR3 Only)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "DDR8BNK,DDR 8-Bank" "0,1"
|
|
bitfld.long 0x00 0.--2. "DDRMD,DDR Mode" "0,1,2,3,4,5,6,7"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DTPR0,DRAM Timing Parameters Register 0"
|
|
rbitfld.long 0x00 29.--31. "RESERVED_31_29,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. "tRRD,Activate to activate command delay (different banks)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "tRAS,Activate to precharge command delay"
|
|
newline
|
|
rbitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "tRP,Precharge command period"
|
|
newline
|
|
rbitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "tRTP,Internal read to precharge command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DTPR1,DRAM Timing Parameters Register 1"
|
|
rbitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "tWLMRD,Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge"
|
|
newline
|
|
rbitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "tFAW,4-bank activate period"
|
|
newline
|
|
rbitfld.long 0x00 11.--15. "RESERVED_15_11,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. "tMOD,Load mode update delay (DDR4 and DDR3 only)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "tMRD,Load mode cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DTPR2,DRAM Timing Parameters Register 2"
|
|
rbitfld.long 0x00 29.--31. "RESERVED_31_29,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "tRTW,Read to Write command delay" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 25.--27. "RESERVED_27_25,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24. "tRTODT,Read to ODT delay (DDR3 only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "tCMDCKE,Delay from Valid command to CKE Input low (LPDDR4 mode only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "tCKE,CKE minimum pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "tXS,Self refresh exit delay"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DTPR3,DRAM Timing Parameters Register 3"
|
|
bitfld.long 0x00 29.--31. "tOFDx,ODT turn-off delay extension" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 26.--28. "tCCD,Read to read and write to write command delay" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 16.--25. 1. "tDLLK,DLL locking time"
|
|
rbitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "tDQSCKmax,Maximum DQS output access time from CK/CK# (LPDDR2/3 only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 3.--7. "RESERVED_7_3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "TDQSCK,DQS output access time from CK/CK# (LPDDR2/3 only)" "0,1,2,3,4,5,6,7"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DTPR4,DRAM Timing Parameters Register 4"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "tAOND_tAOFD,ODT turn-on/turn-off delays (DDR2 only)" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 26.--27. "RESERVED_27_26,Reserved" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--25. 1. "tRFC,Refresh-to-Refresh"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "tWLO,Write leveling output delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "tXP,Power down exit delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DTPR5,DRAM Timing Parameters Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
hexmask.long.byte 0x00 16.--23. 1. "tRC,Activate to activate command delay (same bank)"
|
|
newline
|
|
rbitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "tRCD,Activate to read or write delay"
|
|
newline
|
|
rbitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "tWTR,Internal write to read command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DTPR6,DRAM Timing Parameters Register 6"
|
|
bitfld.long 0x00 31. "PUBWLEN,PUB Write Latency Enable" "0,1"
|
|
bitfld.long 0x00 30. "PUBRLEN,PUB Read Latency Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 14.--29. 1. "RESERVED_29_14,Reserved"
|
|
bitfld.long 0x00 8.--13. "PUBWL,Write Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "PUBRL,Read Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RDIMMGCR0,RDIMM General Configuration Register 0"
|
|
rbitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "QCSEN,RDMIMM Quad CS Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 28.--29. "RESERVED_29_28,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 27. "RDIMMIOM,RDIMM Outputs I/O Mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 24.--26. "RESERVED_26_24,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. "ERROUTOE,ERROUT# Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "ERROUTIOM,ERROUT# I/O Mode" "0,1"
|
|
bitfld.long 0x00 21. "ERROUTPDR,ERROUT# Power Down Receiver" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "RESERVED_20,Reserved" "0,1"
|
|
bitfld.long 0x00 19. "ERROUTODT,ERROUT# On-Die Termination" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "LRDIMM,Load Reduced DIMM" "0,1"
|
|
bitfld.long 0x00 17. "PARINIOM,PAR_IN I/O Mode" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 8.--16. 1. "RESERVED_16_8,Reserved"
|
|
rbitfld.long 0x00 5.--7. "RNKMRREN_RSVD,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4. "RNKMRREN,Rank Mirror Enable" "0,1"
|
|
rbitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SOPERR,Stop on Parity Error" "0,1"
|
|
bitfld.long 0x00 1. "ERRNOREG,Parity Error No Registering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RDIMM,Registered DIMM" "0,1"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "RDIMMGCR1,RDIMM General Configuration Register 1"
|
|
rbitfld.long 0x00 29.--31. "RESERVED_31_29,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "A17BID,Address [17] B-side Inversion Disable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 27. "RESERVED_27,Reserved" "0,1"
|
|
bitfld.long 0x00 24.--26. "tBCMRD_L2,Command word to command word programming delay" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
bitfld.long 0x00 20.--22. "tBCMRD_L,Command word to command word programming delay" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 19. "RESERVED_19,Reserved" "0,1"
|
|
bitfld.long 0x00 16.--18. "tBCMRD,Command word to command word programming delay" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. "tBCSTAB,Stabilization time"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "RDIMMGCR2,RDIMM General Configuration Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "CRINIT,Control Registers Initialization Enable"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "RDIMMCR0,RDIMM Control Register 0"
|
|
bitfld.long 0x00 28.--31. "RC7,DDR4/DDR3 Control Word 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "RC6,DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RC5,DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "RC4,DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Control Word)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "RC3,DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristrics Control Word)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "RC2,DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "RC1,DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "RC0,DDR4/DDR3 Control Word 0 (Global Features Control Word)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "RDIMMCR1,RDIMM Control Register 1"
|
|
bitfld.long 0x00 28.--31. "RC15,Control Word 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "RC14,DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RC13,DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "RC12,DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "RC11,DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Control Word)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "RC10,DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "RC9,DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "RC8,DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting Control Word)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "RDIMMCR2,RDIMM Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RC4X,Control Word RC4X"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RC3X,Control Word RC3X"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RC2X,Control Word RC2X"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RC1X,Control Word RC1X"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "RDIMMCR3,RDIMM Control Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RC8X,Control Word RC8X"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RC7X,Control Word RC7X"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RC6X,Control Word RC6X"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RC5X,Control Word RC5X"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "RDIMMCR4,RDIMM Control Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RCXX,Reserved for future use"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RCBX,Control Word RC11X"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RCAX,Control Word RC10X"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RC9X,Control Word RC9X"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "SCHCR0,Scheduler Command Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "SCHDQV,Scheduler Command DQ Value"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "SP_CMD,Special Command codes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CMD,Specifies the Command to be issued" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "SCHTRIG,Mode Register Command Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "SCHCR1,Scheduler Command Register 1"
|
|
bitfld.long 0x00 28.--31. "SCRNK,Scheduler Rank Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 8.--27. 1. "SCADDR,Scheduler Command Address Specifies the value to be driven on the address bus"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "SCBG,Scheduler Command Bank Group" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "SCBK,Scheduler Command Bank Address" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
bitfld.long 0x00 2. "ALLRANK,All Ranks enabled" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "MR0,LPDDR4 Mode Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RSVD_15_8,Reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "CATR,CA Terminating Rank" "0,1"
|
|
bitfld.long 0x00 5.--6. "RSVD_6_5,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "RZQI,Built-in Self-Test for RZQ" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. "RSVD_2_0,Reserved" "0,1,2,3,4,5,6,7"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "MR1,LPDDR4 Mode Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RSVD,Reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "RDPST,Read Postamble Length" "0,1"
|
|
bitfld.long 0x00 4.--6. "nWR,Write-recovery for auto-precharge command" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "RDPRE,Read Preamble Length" "0,1"
|
|
bitfld.long 0x00 2. "WRPRE,Write Preamble Length" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "BL,Burst Length" "0,1,2,3"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "MR2,LPDDR4 Mode Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RSVD,Reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "WRL,Write Leveling" "0,1"
|
|
bitfld.long 0x00 6. "WLS,Write Latency Set" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "WL,Write Latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "RL,Read Latency" "0,1,2,3,4,5,6,7"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "MR3,LPDDR4 Mode Register 3"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
bitfld.long 0x00 7. "DBIWR,DBI-Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "DBIRD,DBI-Read Enable" "0,1"
|
|
bitfld.long 0x00 3.--5. "PDDS,Pull-down Drive Strength" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2. "RSVD,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0" "0,1"
|
|
bitfld.long 0x00 1. "WRPST,Write Postamble Length" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PUCAL,Pull-up Calibration Point" "0,1"
|
|
repeat 4. (strings "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x190)++0x03
|
|
line.long 0x00 "MR$1,LPDDR4 Mode Register $1"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RSVD,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0"
|
|
repeat.end
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "MR11,LPDDR4 Mode Register 11"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RSVD_15_8,Reserved"
|
|
newline
|
|
bitfld.long 0x00 7. "RSVD_7,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0" "0,1"
|
|
bitfld.long 0x00 4.--6. "CAODT,CA Bus Receiver On-Die-Termination" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "RSVD_3,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0" "0,1"
|
|
bitfld.long 0x00 0.--2. "DQODT,DQ Bus Receiver On-Die-Termination" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "MR12,LPDDR4 Mode Register 12"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
bitfld.long 0x00 7. "RSVD,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "VR_CA,VREF_CA Range Select" "0,1"
|
|
bitfld.long 0x00 0.--5. "VREF_CA,Controls the VREF(ca) levels for Frequency-Set-Point[1:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "MR13,LPDDR4 Mode Register 13"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
bitfld.long 0x00 7. "FSPOP,Frequency Set Point Operation Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "FSPWR,Frequency Set Point Write Enable" "0,1"
|
|
bitfld.long 0x00 5. "DMD,Data Mask Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RRO,Refresh Rate Option" "0,1"
|
|
bitfld.long 0x00 3. "VRCG,VREF Current Generator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "VRO,VREF Output" "0,1"
|
|
bitfld.long 0x00 1. "RPT,Read Preamble Training Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "CBT,Command Bus Training" "0,1"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "MR14,LPDDR4 Mode Register 14"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
bitfld.long 0x00 7. "RSVD,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "VR_DQ,VREFDQ Range Selects" "0,1"
|
|
bitfld.long 0x00 0.--5. "VREF_DQ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "MR22,LPDDR4 Mode Register 22"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
bitfld.long 0x00 6.--7. "RSVD,These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5. "ODTD_CA,CA ODT termination disable" "0,1"
|
|
bitfld.long 0x00 4. "ODTE_CS,ODT CS override" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ODTE_CK,ODT CK override" "0,1"
|
|
bitfld.long 0x00 0.--2. "CODT,Controller ODT value for VOH calibration" "0,1,2,3,4,5,6,7"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DTCR0,Data Training Configuration Register 0"
|
|
bitfld.long 0x00 28.--31. "RFSHDT,Refresh During Training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 26.--27. "RESERVED_27_26,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "DTDRS,Data Training Debug Rank Select" "0,1,2,3"
|
|
bitfld.long 0x00 23. "DTEXG,Data Training with Early/Extended Gate" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "DTEXD,Data Training Extended Write DQS" "0,1"
|
|
bitfld.long 0x00 21. "DTDSTP,Data Training Debug Step" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "DTDEN,Data Training Debug Enable" "0,1"
|
|
bitfld.long 0x00 16.--19. "DTDBS,Data Training Debug Byte Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "DTRDBITR,Data Training read DBI deskewing configuration" "0,1,2,3"
|
|
bitfld.long 0x00 13. "DTBDC,Data Training Bit Deskew Centering" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "DTWBDDM,Data Training Write Bit Deskew Data Mask" "0,1"
|
|
bitfld.long 0x00 8.--11. "RFSHEN,Refreshes Issued During Entry to Training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "DTCMPD,Data Training Compare Data" "0,1"
|
|
bitfld.long 0x00 6. "DTMPR,Data Training Using MPR" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
bitfld.long 0x00 4. "MPCWEYE,WEYE Training using MPC FIFO Commands" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTRPTN,Data Training Repeat Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "DTCR1,Data Training Configuration Register 1"
|
|
hexmask.long.word 0x00 17.--31. 1. "RANKEN_RSVD,Rank Enable"
|
|
bitfld.long 0x00 16. "RANKEN,Rank Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. "DTRANK,Data Training Rank" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 11. "RESERVED_11,Reserved" "0,1"
|
|
bitfld.long 0x00 8.--10. "RDLVLGDIFF,Read Leveling Gate Sampling Difference" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
bitfld.long 0x00 4.--6. "RDLVLGS,Read Leveling Gate Shift" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
bitfld.long 0x00 2. "RDPRMVL_TRN,Read Preamble Training enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RDLVLEN,Read Leveling Enable" "0,1"
|
|
bitfld.long 0x00 0. "BSTEN,Basic Gate Training Enable" "0,1"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "DTAR0,Data Training Address Register 0"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "MPRLOC,Multi-Purpose Register (MPR) Location" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "DTBGBK1,Data Training Bank Group and Bank Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "DTBGBK0,Data Training Bank Group and Bank Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 18.--19. "RESERVED_19_18,Reserved" "0,1,2,3"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "DTROW,Data Training Row Address"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "DTAR1,Data Training Address Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "DTCOL1,Data Training Column Address"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DTCOL0,Data Training Column Address"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "DTAR2,Data Training Address Register 2"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "DTCOL3,Data Training Column Address"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DTCOL2,Data Training Column Address"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "DTDR0,Data Training Data Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DTBYTE3,Data Training Data"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DTBYTE2,Data Training Data"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DTBYTE1,Data Training Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTBYTE0,Data Training Data"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "DTDR1,Data Training Data Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DTBYTE7,Data Training Data"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DTBYTE6,Data Training Data"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DTBYTE5,Data Training Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTBYTE4,Data Training Data"
|
|
rgroup.long 0x230++0x03
|
|
line.long 0x00 "DTEDR0,Data Training Eye Data Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WDQBMX,Data Training Write BDL Shift Maximum"
|
|
bitfld.long 0x00 18.--23. "WDQBMN,Data Training Write BDL Shift Minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.word 0x00 9.--17. 1. "WDQLMX,Data Training WDQ LCDL Maximum"
|
|
hexmask.long.word 0x00 0.--8. 1. "WDQLMN,Data Training WDQ LCDL Minimum"
|
|
rgroup.long 0x234++0x03
|
|
line.long 0x00 "DTEDR1,Data Training Eye Data Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RDQSBMX,Data Training Read BDL Shift Maximum"
|
|
bitfld.long 0x00 18.--23. "RDQSBMN,Data Training Read BDL Shift Minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.word 0x00 9.--17. 1. "RDQSLMX,Data Training RDQS LCDL Maximum"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSLMN,Data Training RDQS LCDL Minimum"
|
|
rgroup.long 0x238++0x03
|
|
line.long 0x00 "DTEDR2,Data Training Eye Data Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RDQSNBMX,Data Training Read BDL Shift Maximum"
|
|
bitfld.long 0x00 18.--23. "RDQSNBMN,Data Training Read BDL Shift Minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.word 0x00 9.--17. 1. "RDQSNLMX,Data Training RDQSN LCDL Maximum"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSNLMN,Data Training RDQSN LCDL Minimum"
|
|
rgroup.long 0x23C++0x03
|
|
line.long 0x00 "VTDR,VREF Training Data Register"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "HVREFMX,DRAM DQ VREF Maximum"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "HVREFMN,DRAM DQ VREF Minimum"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DVREFMX,DRAM DQ VREF Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DVREFMN,DRAM DQ VREF Minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "CATR0,CA Training Register 0"
|
|
hexmask.long.word 0x00 21.--31. 1. "RESERVED_31_21,Reserved"
|
|
bitfld.long 0x00 16.--20. "CACD,Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "CAADR,Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command has been sent to the memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CA1BYTE1,CA_1 Response Byte Lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CA1BYTE0,CA_1 Response Byte Lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "CATR1,CA Training Register 1"
|
|
rbitfld.long 0x00 28.--31. "RESERVED_31_28,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "CA0BYTE1,CA_0 Response Byte Lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "CA0BYTE0,CA_0 Response Byte Lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "CAMRZ,Minimum time (in terms of number of dram clocks) for DRAM DQ going tristate after MRW CA exit calibration command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "CACKEH,Minimum time (in terms of number of dram clocks) for CKE high after last CA calibration response is driven by memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "CACKEL,Minimum time (in terms of number of dram clocks) for CKE going low after CA calibration mode is programmed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CAEXT,Minimum time (in terms of number of dram clocks) for CA calibration exit command after CKE is high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CAENT,Minimum time (in terms of number of dram clocks) for first CA calibration command after CKE is low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "PGCR8,PHY General Configuration Register 8"
|
|
bitfld.long 0x00 28.--31. "INC_DQS2DQ_CF,Counter Cycles Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 20.--27. 1. "INC_DQS2DQ_CM,Counter Cycle Multiplier"
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "INC_DQS2DQ_RANKEN_RSVD,Rank Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. "INC_DQS2DQ_RANKEN,Rank Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "INC_DQS2DQ_MODE,Self Incremental DQS2DQ Training" "0,1"
|
|
bitfld.long 0x00 14. "INC_DQS2DQ_EN,Incremental DQS2DQ Training" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9.--13. "RESERVED_13_9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--8. 1. "BSWAPMSB,When a bit is set it indicates that the corresponding PHY byte lane is connected to MSByte of the LPDDR4 DRAM 16 bit instance it is connected to"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "DQSDR0,DQS Drift Register 0"
|
|
bitfld.long 0x00 28.--31. "DFTDLY,Number of delay taps by which the DQS gate LCDL will be updated when DQS drift is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. "DFTZQUP,Drift Impedance Update" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "DFTDDLUP,Drift DDL Update" "0,1"
|
|
rbitfld.long 0x00 22.--25. "RESERVED_25_22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DFTRDSPC,Drift Read Spacing" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "DFTB2BRD,Drift Back-to-Back Reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DFTIDLRD,Drift Idle Reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DFTGPULSE,Gate Pulse Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--3. "DFTUPMODE,DQS Drift Update Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "DFTDTMODE,DQS Drift Detection Mode" "0,1"
|
|
bitfld.long 0x00 0. "DFTDTEN,DQS Drift Detection Enable" "0,1"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "DQSDR1,DQS Drift Register 1"
|
|
bitfld.long 0x00 29.--31. "DFTUPDACKF,Drift DFI Update Request ACK to DQS Drift FSM issing IDLE REad Cycles Factor" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. "DFTUPDACKC,Drift DFI Update ACK to DQS Drift FSM issuing IDLE Read Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DFTRDB2BF,Drift Back-to-Back Read Cycles Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "DFTRDIDLF,Drift Idle Read Cycles Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DFTRDB2BC,Drift Back-to-Back Read Cycles"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DFTRDIDLC,Drift Idle Read Cycles"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "DQSDR2,DQS Drift Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DFTTHRSH,Drift Threshold"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DFTMNTPRD,Drift Monitor Period"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DCUAR,DCU Address Register"
|
|
hexmask.long.word 0x00 20.--31. 1. "RESERVED_31_20,Reserved"
|
|
bitfld.long 0x00 16.--19. "CSADDR_R,Cache Slice Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "CWADDR_R,Cache Word Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. "ATYPE,Access Type" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "INCA,Increment Address" "0,1"
|
|
bitfld.long 0x00 8.--9. "CSEL,Cache Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CSADDR_W,Cache Slice Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CWADDR_W,Cache Word Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DCUDR,DCU Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "CDATA,Cache Data"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "DCURR,DCU Run Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 23. "XCEN,Expected Compare Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "RCEN,Read Capture Enable" "0,1"
|
|
bitfld.long 0x00 21. "SCOF,Stop Capture On Full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "SONF,Stop On Nth Fail" "0,1"
|
|
hexmask.long.byte 0x00 12.--19. 1. "NFAIL,Number of Failures"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "EADDR,End Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "SADDR,Start Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DINST,DCU Instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "DCULR,DCU Loop Register"
|
|
bitfld.long 0x00 28.--31. "XLEADDR,Expected Data Loop End Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 18.--27. 1. "RESERVED_27_18,Reserved"
|
|
newline
|
|
bitfld.long 0x00 17. "IDA,Increment DRAM Address" "0,1"
|
|
bitfld.long 0x00 16. "LINF,Loop Infinite" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "LCNT,Loop Count"
|
|
bitfld.long 0x00 4.--7. "LEADDR,Loop End Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "LSADDR,Loop Start Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "DCUGCR,DCU General Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "RCSW,Read Capture Start Word"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DCUTPR,DCU Timing Parameters Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "tDCUT2,DCU Generic Timing Parameter 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "tDCUT1,DCU Generic Timing Parameter 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "tDCUT0,DCU Generic Timing Parameter 0"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "DCUSR0,DCU Status Register 0"
|
|
hexmask.long 0x00 3.--31. 1. "RESERVED_31_3,Reserved"
|
|
bitfld.long 0x00 2. "CFULL,Capture Full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CFAIL,Capture Fail" "0,1"
|
|
bitfld.long 0x00 0. "RDONE,Run Done" "0,1"
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "DCUSR1,DCU Status Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "LPCNT,Loop Count"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FLCNT,Fail Count"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RDCNT,Read Count"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "BISTRR,BIST Run Register"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 29. "BPRBST,BIST PRBS Type" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "BSOMA,BIST Stop on Maximum Address" "0,1"
|
|
bitfld.long 0x00 26.--27. "BACDPAT,BIST AC Data Pattern" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 25. "BCCSEL,BIST Clock Cycle Select" "0,1"
|
|
bitfld.long 0x00 23.--24. "BCKSEL,BIST CK Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 19.--22. "BDXSEL,BIST DATX8 Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 17.--18. "BDXDPAT,BIST Data Pattern" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16. "BDMEN,BIST Data Mask Enable" "0,1"
|
|
bitfld.long 0x00 15. "BACEN,BIST AC Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "BDXEN,BIST DATX8 Enable" "0,1"
|
|
bitfld.long 0x00 13. "BSONF,BIST Stop On Nth Fail" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 5.--12. 1. "NFAIL,Number of Failures"
|
|
bitfld.long 0x00 4. "BINF,BIST Infinite Run" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BMODE,BIST Mode" "0,1"
|
|
bitfld.long 0x00 0.--2. "BINST,BIST Instruction" "0,1,2,3,4,5,6,7"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "BISTWCR,BIST Word Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "BACWCNT,BIST AC Word Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "BDXWCNT,BIST DX Word Count"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "BISTMSKR0,BIST Mask Register 0"
|
|
hexmask.long.word 0x00 21.--31. 1. "CSMSK_RSVD,Reserved"
|
|
bitfld.long 0x00 20. "CSMSK,Mask bit for each of the up to 12 CS_N bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "ACTMSK,Mask bit for the RAS" "0,1"
|
|
rbitfld.long 0x00 18. "RESERVED_18,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "AMSK,Mask bit for each of the up to 16 address bits"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "BISTMSKR1,BIST Mask Register 1"
|
|
bitfld.long 0x00 28.--31. "DMMSK,Mask bit for the data mask (DM) bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. "PARINMSK,Mask bit for the PAR_IN" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 25.--26. "CIDMSK_RSVD,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24. "CIDMSK,Mask bits for each of the up to 3 Chip IP bits" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 17.--23. 1. "ODTMSK_RSVD,Reserved"
|
|
bitfld.long 0x00 16. "ODTMSK,Mask bit for each of the up to 8 ODT bits" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "CKEMSK_RSVD,Reserved"
|
|
bitfld.long 0x00 8. "CKEMSK,Mask bit for each of the up to 8 CKE bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "BAMSK,Mask bit for each of the up to 4 bank address bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 0.--3. "RESERVED_3_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "BISTMSKR2,BIST Mask Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "DQMSK,Mask bit for each of the 8 data (DQ) bits"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "BISTLSR,BIST LFSR Seed Register"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,LFSR seed for pseudo-random BIST patterns"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "BISTAR0,BIST Address Register 0"
|
|
bitfld.long 0x00 28.--31. "BBANK,BIST Bank Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 12.--27. 1. "RESERVED_27_12,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BCOL,BIST Column Address"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "BISTAR1,BIST Address Register 1"
|
|
hexmask.long.word 0x00 20.--31. 1. "RESERVED_31_20,Reserved"
|
|
bitfld.long 0x00 16.--19. "BMRANK,BIST Maximum Rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 4.--15. 1. "BAINC,BIST Address Increment"
|
|
bitfld.long 0x00 0.--3. "BRANK,BIST Rank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "BISTAR2,BIST Address Register 2"
|
|
bitfld.long 0x00 28.--31. "BMBANK,BIST Maximum Bank Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 12.--27. 1. "RESERVED_27_12,Reserved"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BMCOL,BIST Maximum Column Address"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "BISTAR3,BIST Address Register 3"
|
|
hexmask.long.word 0x00 18.--31. 1. "RESERVED_31_18,Reserved"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "BROW,BIST Row Address"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "BISTAR4,BIST Address Register 4"
|
|
hexmask.long.word 0x00 18.--31. 1. "RESERVED_31_18,Reserved"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "BMROW,BIST Maximum Row Address"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "BISTUDPR,BIST User Data Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "BUDP1,BIST User Data Pattern 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "BUDP0,BIST User Data Pattern 0"
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "BISTGSR,BIST General Status Register"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "RASBER,RAS_n/ACT_n Bit Error" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 20.--27. 1. "DMBER,DM Bit Error"
|
|
hexmask.long.byte 0x00 12.--19. 1. "RESERVED_19_12,Reserved"
|
|
newline
|
|
bitfld.long 0x00 11. "RESERVED_11,Reserved" "0,1"
|
|
hexmask.long.word 0x00 2.--10. 1. "BDXERR,BIST Data Error"
|
|
newline
|
|
bitfld.long 0x00 1. "BACERR,BIST Address/Command Error" "0,1"
|
|
bitfld.long 0x00 0. "BDONE,BIST Done" "0,1"
|
|
rgroup.long 0x434++0x03
|
|
line.long 0x00 "BISTWER0,BIST Word Error Register 0"
|
|
hexmask.long.word 0x00 18.--31. 1. "RESERVED_31_18,Reserved"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "ACWER,Address/Command Word Error"
|
|
rgroup.long 0x438++0x03
|
|
line.long 0x00 "BISTWER1,BIST Word Error Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "DXWER,Byte Word Error"
|
|
rgroup.long 0x43C++0x03
|
|
line.long 0x00 "BISTBER0,BIST Bit Error Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ABER,Address Bit Error"
|
|
rgroup.long 0x440++0x03
|
|
line.long 0x00 "BISTBER1,BIST Bit Error Register 1"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "CSBER_RSVD,Reserved"
|
|
bitfld.long 0x00 8.--9. "CSBER,CS_N Bit Error" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "BABER,Bank Address Bit Error"
|
|
rgroup.long 0x444++0x03
|
|
line.long 0x00 "BISTBER2,BIST Bit Error Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "DQBER0,Data Bit Error"
|
|
rgroup.long 0x448++0x03
|
|
line.long 0x00 "BISTBER3,BIST Bit Error Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "DQBER1,Data Bit Error"
|
|
rgroup.long 0x44C++0x03
|
|
line.long 0x00 "BISTBER4,BIST Bit Error Register 4"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED_31_14,Reserved"
|
|
bitfld.long 0x00 10.--13. "CIDBER_RSVD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CIDBER,Chip ID Bit Error" "0,1,2,3"
|
|
bitfld.long 0x00 4.--7. "RESERVED_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "ABER,Address Bit Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x450++0x03
|
|
line.long 0x00 "BISTWCSR,BIST Word Count Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXWCNT,Byte Word Count"
|
|
hexmask.long.word 0x00 0.--15. 1. "ACWCNT,Address/Command Word Count"
|
|
rgroup.long 0x454++0x03
|
|
line.long 0x00 "BISTFWR0,BIST Fail Word Register 0"
|
|
hexmask.long.word 0x00 21.--31. 1. "CSWEBS_RSVD,Reserved"
|
|
bitfld.long 0x00 20. "CSWEBS,Bit status during a word error for each of the up to 12 CS# bits" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "RESERVED_19,Reserved" "0,1"
|
|
bitfld.long 0x00 18. "ACTWEBS,Bit status during a word error for the RAS" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "AWEBS,Bit status during a word error for each of the up to 16 address bits"
|
|
rgroup.long 0x458++0x03
|
|
line.long 0x00 "BISTFWR1,BIST Fail Word Register 1"
|
|
bitfld.long 0x00 28.--31. "DMWEBS,Bit status during a word error for the data mask (DM) bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "RESERVED_27_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED_23_22,Reserved" "0,1"
|
|
bitfld.long 0x00 21.--22. "CIDWEBS_RSVD,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20. "CIDWEBS,Bit status during a word error for each of the up to 3 chip ID bits" "0,1"
|
|
bitfld.long 0x00 16.--19. "BAWEBS,Bit status during a word error for each of the bank address bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "ODTWEBS_RSVD,Reserved"
|
|
bitfld.long 0x00 8. "ODTWEBS,Bit status during a word error for each of the up to 8 ODT bits" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--7. 1. "CKEWEBS_RSVD,Reserved"
|
|
bitfld.long 0x00 0. "CKEWEBS,Bit status during a word error for each of the up to 8 CKE bits" "0,1"
|
|
rgroup.long 0x45C++0x03
|
|
line.long 0x00 "BISTFWR2,BIST Fail Word Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "DQWEBS,Bit status during a word error for each of the 8 data (DQ) bits"
|
|
rgroup.long 0x460++0x03
|
|
line.long 0x00 "BISTBER5,BIST Bit Error Register 5"
|
|
hexmask.long.word 0x00 18.--31. 1. "ODTBER_RSVD,Reserved"
|
|
bitfld.long 0x00 16.--17. "ODTBER,ODT Bit Error" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "CKEBER_RSVD,Reserved"
|
|
bitfld.long 0x00 0.--1. "CKEBER,CKE Bit Error" "0,1,2,3"
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "RANKIDR,Rank ID Register"
|
|
hexmask.long.word 0x00 20.--31. 1. "RESERVED_31_20,Reserved"
|
|
bitfld.long 0x00 16.--19. "RANKRID,Rank Read ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 4.--15. 1. "RESERVED_15_4,Reserved"
|
|
bitfld.long 0x00 0.--3. "RANKWID,Rank Write ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x4E0)++0x03
|
|
line.long 0x00 "RIOCR$1,Rank I/O Configuration Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
repeat.end
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "RIOCR2,Rank I/O Configuration Register 2"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 26.--29. "COEMODE_RSVD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "COEMODE,SDRAM C Output Enable (OE) Mode Selection" "0,1,2,3"
|
|
hexmask.long.tbyte 0x00 2.--23. 1. "CSOEMODE_RSVD,Reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CSOEMODE,SDRAM CS_n Output Enable (OE) Mode Selection" "0,1,2,3"
|
|
rgroup.long 0x4EC++0x03
|
|
line.long 0x00 "RIOCR3,Rank I/O Configuration Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "RIOCR4,Rank I/O Configuration Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 2.--15. 1. "CKEOEMODE_RSVD,Reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CKEOEMODE,SDRAM CKE Output Enable (OE) Mode Selection" "0,1,2,3"
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "RIOCR5,Rank I/O Configuration Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 2.--15. 1. "ODTOEMODE_RSVD,Reserved"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "ODTOEMODE,SDRAM On-die Termination Output Enable (OE) Mode Selection" "0,1,2,3"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "ACIOCR0,AC I/O Configuration Register 0"
|
|
bitfld.long 0x00 30.--31. "ACSR,Address/Command Slew Rate (D3F I/O Only)" "0,1,2,3"
|
|
bitfld.long 0x00 29. "RSTIOM,SDRAM Reset I/O Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "RSTPDR,SDRAM Reset Power Down Receiver" "0,1"
|
|
rbitfld.long 0x00 27. "RESERVED_27,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "RSTODT,SDRAM Reset On-Die Termination" "0,1"
|
|
rbitfld.long 0x00 24.--25. "RESERVED_25_24,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "ESR,Decoupling Capacitance ESR Control in D5M I/O ring"
|
|
rbitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "ACPNUMSEL,Address/Command custom pin mapping configuration" "0,1,2,3"
|
|
bitfld.long 0x00 6.--9. "CKDCC,CK Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "ACPDRMODE,AC Power Down Receiver Mode" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "ACODTMODE,AC On-die Termination Mode" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
bitfld.long 0x00 0. "ACRANKCLKSEL,Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices" "0,1"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "ACIOCR1,AC I/O Configuration Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "AOEMODE,SDRAM Address Output Enable (OE) Mode Selection"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "ACIOCR2,AC I/O Configuration Register 2"
|
|
bitfld.long 0x00 31. "CLKGENCLKGATE,Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice" "0,1"
|
|
bitfld.long 0x00 30. "ACOECLKGATE0,Clock gating for Output Enable D slices [0]" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "ACPDRCLKGATE0,Clock gating for Power Down Receiver D slices [0]" "0,1"
|
|
bitfld.long 0x00 28. "ACTECLKGATE0,Clock gating for Termination Enable D slices [0]" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "CKNCLKGATE0,Clock gating for CK# D slices [1:0]" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "CKCLKGATE0,Clock gating for CK D slices [1:0]" "0,1,2,3"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "ACCLKGATE0,Clock gating for AC D slices [23:0]"
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "ACIOCR3,AC I/O Configuration Register 3"
|
|
bitfld.long 0x00 30.--31. "PAROEMODE,SDRAM Parity Output Enable (OE) Mode Selection" "0,1,2,3"
|
|
bitfld.long 0x00 26.--29. "BGOEMODE,SDRAM Bank Group Output Enable (OE) Mode Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 22.--25. "BAOEMODE,SDRAM Bank Address Output Enable (OE) Mode Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--21. "A17OEMODE,SDRAM A[17] Output Enable (OE) Mode Selection" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "A16OEMODE,SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "ACTOEMODE,SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RESERVED_15_8,Reserved"
|
|
rbitfld.long 0x00 4.--7. "CKOEMODE_RSVD,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "CKOEMODE,SDRAM CK Output Enable (OE) Mode Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "ACIOCR4,AC I/O Configuration Register 4"
|
|
bitfld.long 0x00 31. "LBCLKGATE,Clock gating for AC LB slices and loopback read valid slices" "0,1"
|
|
bitfld.long 0x00 30. "ACOECLKGATE1,Clock gating for Output Enable D slices [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "ACPDRCLKGATE1,Clock gating for Power Down Receiver D slices [1]" "0,1"
|
|
bitfld.long 0x00 28. "ACTECLKGATE1,Clock gating for Termination Enable D slices [1]" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "CKNCLKGATE1,Clock gating for CK# D slices [3:2]" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "CKCLKGATE1,Clock gating for CK D slices [3:2]" "0,1,2,3"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "ACCLKGATE1,Clock gating for AC D slices [47:24]"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "ACIOCR5,AC I/O Configuration Register 5"
|
|
rbitfld.long 0x00 28.--31. "RESERVED_31_28,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 25.--27. "ACVREFIOM,IOM bits for PVREF and PVREFE cells in AC IO ring" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "ACXIOM,AC IO Mode" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 11.--21. 1. "ACTXM,AC IO Transmitter Mode"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "ACRXM,AC IO Receiver Mode"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "IOVCR0,IO VREF Control Register 0"
|
|
rbitfld.long 0x00 29.--31. "RESERVED_31_29,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "ACREFPEN,Address/command lane VREF Pad Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "ACREFEEN,Address/command lane Internal VREF Enable" "0,1,2,3"
|
|
bitfld.long 0x00 25. "ACREFSEN,Address/command lane Single-End VREF Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "ACREFIEN,Address/command lane Internal VREF Enable" "0,1"
|
|
bitfld.long 0x00 23. "ACREFESELRANGE,External VREF generato REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "ACREFESEL,Address/command lane External VREF Select"
|
|
bitfld.long 0x00 15. "ACREFSSELRANGE,Single ended VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "ACREFSSEL,Address/command lane Single-End VREF Select"
|
|
bitfld.long 0x00 7. "ACVREFISELRANGE,Internal VREF generator REFSEL ragne select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "ACVREFISEL,REFSEL Control for internal AC IOs"
|
|
rgroup.long 0x524++0x03
|
|
line.long 0x00 "IOVCR1,IO VREF Control Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "VTCR0,VREF Training Control Register 0"
|
|
bitfld.long 0x00 29.--31. "tVREF,Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "DVEN,DRM DQ VREF training Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "PDAEN,Per Device Addressability Enable" "0,1"
|
|
rbitfld.long 0x00 26. "RESERVED_26,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--25. "VWCR,VREF Word Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--21. "DVSS,DRAM DQ VREF step size used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--17. "DVMAX,Maximum VREF limit value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 6.--11. "DVMIN,Minimum VREF limit value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DVINIT,Initial DRAM DQ VREF value used during DRAM VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "VTCR1,VREF Training Control Register 1"
|
|
bitfld.long 0x00 28.--31. "HVSS,Host VREF step size used during VREF training" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. "RESERVED_27,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 20.--26. 1. "HVMAX,Maximum VREF limit value used during DRAM VREF training"
|
|
rbitfld.long 0x00 19. "RESERVED_19,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--18. 1. "HVMIN,Minimum VREF limit value used during DRAM VREF training"
|
|
rbitfld.long 0x00 11. "RESERVED_11,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "SHRNK,Static Host Vref Rank Value" "0,1,2,3"
|
|
bitfld.long 0x00 8. "SHREN,Static Host Vref Rank Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "tVREFIO,Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--4. "EOFF,Eye LCDL Offset value for VREF training" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2. "ENUM,Number of LCDL Eye points for which VREF training is repeated" "0,1"
|
|
bitfld.long 0x00 1. "HVEN,HOST (IO) internal VREF training Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "HVIO,Host IO Type Control" "0,1"
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "ACBDLR0,AC Bit Delay Line Register 0"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "CK3BD,CK3 Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "CK2BD,CK2 Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "CK1BD,CK1 Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "CK0BD,CK0 Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "ACBDLR1,AC Bit Delay Line Register 1"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "PARBD,Delay select for the BDL on Parity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "A16BD,Delay select for the BDL on Address A[16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "A17BD,Delay select for the BDL on Address A[17]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "ACTBD,Delay select for the BDL on ACTN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "ACBDLR2,AC Bit Delay Line Register 2"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "BG1BD,Delay select for the BDL on BG[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "BG0BD,Delay select for the BDL on BG[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reser.ved Return zeroes on reads" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "BA1BD,Delay select for the BDL on BA[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "BA0BD,Delay select for the BDL on BA[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "ACBDLR3,AC Bit Delay Line Register 3"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 24.--29. "CS3BD,Delay select for the BDL on CS[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 16.--21. "CS2BD,Delay select for the BDL on CS[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 8.--13. "CS1BD,Delay select for the BDL on CS[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "CS0BD,Delay select for the BDL on CS[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "ACBDLR4,AC Bit Delay Line Register 4"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 24.--29. "ODT3BD,Delay select for the BDL on ODT[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 16.--21. "ODT2BD,Delay select for the BDL on ODT[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 8.--13. "ODT1BD,Delay select for the BDL on ODT[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "ODT0BD,Delay select for the BDL on ODT[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "ACBDLR5,AC Bit Delay Line Register 5"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 24.--29. "CKE3BD,Delay select for the BDL on CKE[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 16.--21. "CKE2BD,Delay select for the BDL on CKE[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 8.--13. "CKE1BD,Delay select for the BDL on CKE[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "CKE0BD,Delay select for the BDL on CKE[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "ACBDLR6,AC Bit Delay Line Register 6"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "A03BD,Delay select for the BDL on Address A[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "A02BD,Delay select for the BDL on Address A[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "A01BD,Delay select for the BDL on Address A[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "A00BD,Delay select for the BDL on Address A[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "ACBDLR7,AC Bit Delay Line Register 7"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "A07BD,Delay select for the BDL on Address A[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "A06BD,Delay select for the BDL on Address A[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "A05BD,Delay select for the BDL on Address A[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "A04BD,Delay select for the BDL on Address A[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "ACBDLR8,AC Bit Delay Line Register 8"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "A11BD,Delay select for the BDL on Address A[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "A10BD,Delay select for the BDL on Address A[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "A09BD,Delay select for the BDL on Address A[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "A08BD,Delay select for the BDL on Address A[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "ACBDLR9,AC Bit Delay Line Register 9"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "A15BD,Delay select for the BDL on Address A[15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "A14BD,Delay select for the BDL on Address A[14]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "A13BD,Delay select for the BDL on Address A[13]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "A12BD,Delay select for the BDL on Address A[12]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "ACBDLR10,AC Bit Delay Line Register 10"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 24.--29. "CID2BD,Delay select for the BDL on Chip ID CID[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x00 16.--21. "CID1BD,Delay select for the BDL on Chip ID CID[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "CID0BD,Delay select for the BDL on Chip ID CID[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED_7_0,Reserved"
|
|
rgroup.long 0x56C++0x03
|
|
line.long 0x00 "ACBDLR11,AC Bit Delay Line Register 11"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "CS7BD,Delay select for the BDL on CS[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "CS6BD,Delay select for the BDL on CS[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "CS5BD,Delay select for the BDL on CS[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "CS4BD,Delay select for the BDL on CS[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x570++0x03
|
|
line.long 0x00 "ACBDLR12,AC Bit Delay Line Register 12"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "CS11BD,Delay select for the BDL on CS[11]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "CS10BD,Delay select for the BDL on CS[10]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "CS9BD,Delay select for the BDL on CS[9]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "CS8BD,Delay select for the BDL on CS[8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x574++0x03
|
|
line.long 0x00 "ACBDLR13,AC Bit Delay Line Register 13"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "ODT7BD,Delay select for the BDL on ODT[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "ODT6BD,Delay select for the BDL on ODT[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "ODT5BD,Delay select for the BDL on ODT[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "ODT4BD,Delay select for the BDL on ODT[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x578++0x03
|
|
line.long 0x00 "ACBDLR14,AC Bit Delay Line Register 14"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "CKE7BD,Delay select for the BDL on CKE[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "CKE6BD,Delay select for the BDL on CKE[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "CKE5BD,Delay select for the BDL on CKE[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "CKE4BD,Delay select for the BDL on CKE[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "ACBDLR15,AC Bit Delay Line Register 15"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "OEBD,Delay select for the BDL on OE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "TEBD,Delay select for the BDL on TE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "PDRBD,Delay select for the BDL on PDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "ACBDLR16,AC Bit Delay Line Register 16"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "CKN3BD,Delay select for the BDL on CKN[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "CKN2BD,Delay select for the BDL on CKN[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "CKN1BD,Delay select for the BDL on CKN[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "CKN0BD,Delay select for the BDL on CKN[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "ACLCDLR,AC Local Calibrated Delay Line Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "ACD1,Address/Command Delay for AC Macro 1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "ACD,Address/Command Delay for AC Macro 0"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "ACMDLR0,AC Master Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "TPRD,Target Period"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "IPRD,Initial Period"
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "ACMDLR1,AC Master Delay Line Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "MDLD1,MDL Delay for AC Macro 1"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "MDLD,MDL Delay for AC Macro 0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "ZQCR,ZQ Impedance Control Register"
|
|
rbitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 25. "ZQREFISELRANGE,ZQ VREF Range" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--24. "PGWAIT_FRQB,Programmable Wait for Frequency B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 13.--18. "PGWAIT_FRQA,Programmable Wait for Frequency A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 12. "ZQREFPEN,ZQ VREF Pad Enable" "0,1"
|
|
bitfld.long 0x00 11. "ZQREFIEN,ZQ Internal VREF Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "ODT_MODE,Choice of termination mode" "0,1,2,3"
|
|
bitfld.long 0x00 8. "FORCE_ZCAL_VT_UPDATE,Force ZCAL VT update" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "IODLMT,IO VT Drift Limit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. "AVGEN,Averaging algorithm enable if set enables averaging algorithm" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "AVGMAX,Maximum number of averaging rounds to be used by averaging algorithm" "0,1,2,3"
|
|
bitfld.long 0x00 1. "ZCALT,ZQ Calibration Type" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ZQPD,ZQ Power Down" "0,1"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "ZQ0PR0,ZQ n Impedance Control Program Register 0"
|
|
bitfld.long 0x00 31. "PD_DRV_ZDEN,Pull-down drive strength ZCTRL over-ride enable" "0,1"
|
|
bitfld.long 0x00 30. "PU_DRV_ZDEN,Pull-up drive strength ZCTRL over-ride enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PD_ODT_ZDEN,Pull-down termination ZCTRL over-ride enable" "0,1"
|
|
bitfld.long 0x00 28. "PU_ODT_ZDEN,Pull-up termination ZCTRL over-ride enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "ZSEGBYP,Calibration segment bypass" "0,1"
|
|
bitfld.long 0x00 25.--26. "ZLE_MODE,VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "ODT_ADJUST,Termination adjustment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19.--21. "PD_DRV_ADJUST,Pulldown drive strength adjustment" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PU_DRV_ADJUST,Pullup drive strength adjustment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--15. "ZPROG_DRAM_ODT,DRAM Impedance Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "ZPROG_HOST_ODT,HOST Impedance Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "ZPROG_ASYM_DRV_PD,Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "ZPROG_ASYM_DRV_PU,Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "ZQ0PR1,ZQ n Impedance Control Program Register 1"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED_31_15,Reserved"
|
|
hexmask.long.byte 0x00 8.--14. 1. "PU_REFSEL,Pull-up REFSEL for PZCTRL cell"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "PD_REFSEL,Pull-down REFSEL for PZCTRL cell"
|
|
rgroup.long 0x68C++0x03
|
|
line.long 0x00 "ZQ0DR0,ZQ n Impedance Control Data Register 0"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_DRV_RESULT,Pull-up drive strength calibration code result"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_DRV_RESULT,Pull-down drive strength calibration code result"
|
|
rgroup.long 0x690++0x03
|
|
line.long 0x00 "ZQ0DR1,ZQ n Impedance Control Data Register 1"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_ODT_RESULT,Pull-up termination calibration code result"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_ODT_RESULT,Pull-down termination calibration code result"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "ZQ0OR0,ZQ n Impedance Control Override Data Register 0"
|
|
rbitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_DRV_OVRD,Override value for the pull-up output impedance"
|
|
newline
|
|
rbitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_DRV_OVRD,Override value for the pull-down output impedance"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "ZQ0OR1,ZQ n Impedance Control Override Data Register 1"
|
|
rbitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_ODT_OVRD,Override value for the pull-up termination"
|
|
newline
|
|
rbitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_ODT_OVRD,Override value for the pull-down termination"
|
|
rgroup.long 0x69C++0x03
|
|
line.long 0x00 "ZQ0SR,ZQ n Impedance Control Status Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED_31_14,Reserved"
|
|
bitfld.long 0x00 13. "PD_ODT_SAT,Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "PU_ODT_SAT,Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register" "0,1"
|
|
bitfld.long 0x00 11. "PD_DRV_SAT,Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "PU_DRV_SAT,Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register" "0,1"
|
|
bitfld.long 0x00 9. "ZDONE,Impedance Calibration Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ZERR,Impedance Calibration Error" "0,1"
|
|
bitfld.long 0x00 6.--7. "OPU,On-die termination (ODT) pull-up calibration status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "OPD,On-die termination (ODT) pull-down calibration status" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "ZPU,Output impedance pull-up calibration status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "ZPD,Output impedance pull-down calibration status" "0,1,2,3"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "ZQ1PR0,ZQ n Impedance Control Program Register 0"
|
|
bitfld.long 0x00 31. "PD_DRV_ZDEN,Pull-down drive strength ZCTRL over-ride enable" "0,1"
|
|
bitfld.long 0x00 30. "PU_DRV_ZDEN,Pull-up drive strength ZCTRL over-ride enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PD_ODT_ZDEN,Pull-down termination ZCTRL over-ride enable" "0,1"
|
|
bitfld.long 0x00 28. "PU_ODT_ZDEN,Pull-up termination ZCTRL over-ride enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "ZSEGBYP,Calibration segment bypass" "0,1"
|
|
bitfld.long 0x00 25.--26. "ZLE_MODE,VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "ODT_ADJUST,Termination adjustment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19.--21. "PD_DRV_ADJUST,Pulldown drive strength adjustment" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PU_DRV_ADJUST,Pullup drive strength adjustment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--15. "ZPROG_DRAM_ODT,DRAM Impedance Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "ZPROG_HOST_ODT,HOST Impedance Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "ZPROG_ASYM_DRV_PD,Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "ZPROG_ASYM_DRV_PU,Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "ZQ1PR1,ZQ n Impedance Control Program Register 1"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED_31_15,Reserved"
|
|
hexmask.long.byte 0x00 8.--14. 1. "PU_REFSEL,Pull-up REFSEL for PZCTRL cell"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "PD_REFSEL,Pull-down REFSEL for PZCTRL cell"
|
|
rgroup.long 0x6AC++0x03
|
|
line.long 0x00 "ZQ1DR0,ZQ n Impedance Control Data Register 0"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_DRV_RESULT,Pull-up drive strength calibration code result"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_DRV_RESULT,Pull-down drive strength calibration code result"
|
|
rgroup.long 0x6B0++0x03
|
|
line.long 0x00 "ZQ1DR1,ZQ n Impedance Control Data Register 1"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_ODT_RESULT,Pull-up termination calibration code result"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_ODT_RESULT,Pull-down termination calibration code result"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "ZQ1OR0,ZQ n Impedance Control Override Data Register 0"
|
|
rbitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_DRV_OVRD,Override value for the pull-up output impedance"
|
|
newline
|
|
rbitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_DRV_OVRD,Override value for the pull-down output impedance"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "ZQ1OR1,ZQ n Impedance Control Override Data Register 1"
|
|
rbitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_ODT_OVRD,Override value for the pull-up termination"
|
|
newline
|
|
rbitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_ODT_OVRD,Override value for the pull-down termination"
|
|
rgroup.long 0x6BC++0x03
|
|
line.long 0x00 "ZQ1SR,ZQ n Impedance Control Status Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED_31_14,Reserved"
|
|
bitfld.long 0x00 13. "PD_ODT_SAT,Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "PU_ODT_SAT,Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register" "0,1"
|
|
bitfld.long 0x00 11. "PD_DRV_SAT,Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "PU_DRV_SAT,Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register" "0,1"
|
|
bitfld.long 0x00 9. "ZDONE,Impedance Calibration Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ZERR,Impedance Calibration Error" "0,1"
|
|
bitfld.long 0x00 6.--7. "OPU,On-die termination (ODT) pull-up calibration status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "OPD,On-die termination (ODT) pull-down calibration status" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "ZPU,Output impedance pull-up calibration status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "ZPD,Output impedance pull-down calibration status" "0,1,2,3"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "ZQ2PR0,ZQ n Impedance Control Program Register 0"
|
|
bitfld.long 0x00 31. "PD_DRV_ZDEN,Pull-down drive strength ZCTRL over-ride enable" "0,1"
|
|
bitfld.long 0x00 30. "PU_DRV_ZDEN,Pull-up drive strength ZCTRL over-ride enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PD_ODT_ZDEN,Pull-down termination ZCTRL over-ride enable" "0,1"
|
|
bitfld.long 0x00 28. "PU_ODT_ZDEN,Pull-up termination ZCTRL over-ride enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "ZSEGBYP,Calibration segment bypass" "0,1"
|
|
bitfld.long 0x00 25.--26. "ZLE_MODE,VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "ODT_ADJUST,Termination adjustment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19.--21. "PD_DRV_ADJUST,Pulldown drive strength adjustment" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PU_DRV_ADJUST,Pullup drive strength adjustment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--15. "ZPROG_DRAM_ODT,DRAM Impedance Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "ZPROG_HOST_ODT,HOST Impedance Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "ZPROG_ASYM_DRV_PD,Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "ZPROG_ASYM_DRV_PU,Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "ZQ2PR1,ZQ n Impedance Control Program Register 1"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED_31_15,Reserved"
|
|
hexmask.long.byte 0x00 8.--14. 1. "PU_REFSEL,Pull-up REFSEL for PZCTRL cell"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "PD_REFSEL,Pull-down REFSEL for PZCTRL cell"
|
|
rgroup.long 0x6CC++0x03
|
|
line.long 0x00 "ZQ2DR0,ZQ n Impedance Control Data Register 0"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_DRV_RESULT,Pull-up drive strength calibration code result"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_DRV_RESULT,Pull-down drive strength calibration code result"
|
|
rgroup.long 0x6D0++0x03
|
|
line.long 0x00 "ZQ2DR1,ZQ n Impedance Control Data Register 1"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_ODT_RESULT,Pull-up termination calibration code result"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_ODT_RESULT,Pull-down termination calibration code result"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "ZQ2OR0,ZQ n Impedance Control Override Data Register 0"
|
|
rbitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_DRV_OVRD,Override value for the pull-up output impedance"
|
|
newline
|
|
rbitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_DRV_OVRD,Override value for the pull-down output impedance"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "ZQ2OR1,ZQ n Impedance Control Override Data Register 1"
|
|
rbitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_ODT_OVRD,Override value for the pull-up termination"
|
|
newline
|
|
rbitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_ODT_OVRD,Override value for the pull-down termination"
|
|
rgroup.long 0x6DC++0x03
|
|
line.long 0x00 "ZQ2SR,ZQ n Impedance Control Status Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED_31_14,Reserved"
|
|
bitfld.long 0x00 13. "PD_ODT_SAT,Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "PU_ODT_SAT,Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register" "0,1"
|
|
bitfld.long 0x00 11. "PD_DRV_SAT,Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "PU_DRV_SAT,Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register" "0,1"
|
|
bitfld.long 0x00 9. "ZDONE,Impedance Calibration Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ZERR,Impedance Calibration Error" "0,1"
|
|
bitfld.long 0x00 6.--7. "OPU,On-die termination (ODT) pull-up calibration status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "OPD,On-die termination (ODT) pull-down calibration status" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "ZPU,Output impedance pull-up calibration status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "ZPD,Output impedance pull-down calibration status" "0,1,2,3"
|
|
rgroup.long 0x6E4++0x03
|
|
line.long 0x00 "ZQ3PR0,ZQ n Impedance Control Program Register 0"
|
|
bitfld.long 0x00 31. "PD_DRV_ZDEN,Pull-down drive strength ZCTRL over-ride enable" "0,1"
|
|
bitfld.long 0x00 30. "PU_DRV_ZDEN,Pull-up drive strength ZCTRL over-ride enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PD_ODT_ZDEN,Pull-down termination ZCTRL over-ride enable" "0,1"
|
|
bitfld.long 0x00 28. "PU_ODT_ZDEN,Pull-up termination ZCTRL over-ride enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "ZSEGBYP,Calibration segment bypass" "0,1"
|
|
bitfld.long 0x00 25.--26. "ZLE_MODE,VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "ODT_ADJUST,Termination adjustment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19.--21. "PD_DRV_ADJUST,Pulldown drive strength adjustment" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PU_DRV_ADJUST,Pullup drive strength adjustment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--15. "ZPROG_DRAM_ODT,DRAM Impedance Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "ZPROG_HOST_ODT,HOST Impedance Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "ZPROG_ASYM_DRV_PD,Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "ZPROG_ASYM_DRV_PU,Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x6E8++0x03
|
|
line.long 0x00 "ZQ3PR1,ZQ n Impedance Control Program Register 1"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "RESERVED_31_15,Reserved"
|
|
hexmask.long.byte 0x00 8.--14. 1. "PU_REFSEL,Pull-up REFSEL for PZCTRL cell"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "PD_REFSEL,Pull-down REFSEL for PZCTRL cell"
|
|
rgroup.long 0x6EC++0x03
|
|
line.long 0x00 "ZQ3DR0,ZQ n Impedance Control Data Register 0"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_DRV_RESULT,Pull-up drive strength calibration code result"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_DRV_RESULT,Pull-down drive strength calibration code result"
|
|
rgroup.long 0x6F0++0x03
|
|
line.long 0x00 "ZQ3DR1,ZQ n Impedance Control Data Register 1"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_ODT_RESULT,Pull-up termination calibration code result"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_ODT_RESULT,Pull-down termination calibration code result"
|
|
rgroup.long 0x6F4++0x03
|
|
line.long 0x00 "ZQ3OR0,ZQ n Impedance Control Override Data Register 0"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_DRV_OVRD,Override value for the pull-up output impedance"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_DRV_OVRD,Override value for the pull-down output impedance"
|
|
rgroup.long 0x6F8++0x03
|
|
line.long 0x00 "ZQ3OR1,ZQ n Impedance Control Override Data Register 1"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 16.--25. 1. "ZDATA_PU_ODT_OVRD,Override value for the pull-up termination"
|
|
newline
|
|
bitfld.long 0x00 10.--15. "RESERVED_15_10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 0.--9. 1. "ZDATA_PD_ODT_OVRD,Override value for the pull-down termination"
|
|
rgroup.long 0x6FC++0x03
|
|
line.long 0x00 "ZQ3SR,ZQ n Impedance Control Status Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED_31_14,Reserved"
|
|
bitfld.long 0x00 13. "PD_ODT_SAT,Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "PU_ODT_SAT,Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register" "0,1"
|
|
bitfld.long 0x00 11. "PD_DRV_SAT,Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "PU_DRV_SAT,Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register" "0,1"
|
|
bitfld.long 0x00 9. "ZDONE,Impedance Calibration Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ZERR,Impedance Calibration Error" "0,1"
|
|
bitfld.long 0x00 6.--7. "OPU,On-die termination (ODT) pull-up calibration status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "OPD,On-die termination (ODT) pull-down calibration status" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. "ZPU,Output impedance pull-up calibration status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "ZPD,Output impedance pull-down calibration status" "0,1,2,3"
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "DX0GCR0,DATX8 n General Configuration Register 0"
|
|
bitfld.long 0x00 31. "CALBYP,Calibration Bypass" "0,1"
|
|
bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "CODTSHFT,Configurable ODT(TE) Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DQSDCC,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RDDLY,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 14.--19. "RESERVED_19_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 13. "DQSNSEPDR,DQSNSE Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 12. "DQSSEPDR,DQSSE Power Down Receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RTTOAL,RTT On Additive Latency" "0,1"
|
|
bitfld.long 0x00 9.--10. "RTTOH,RTT Output Hold" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "CPDRSHFT,Configurable PDR Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 6. "DQSRPD,DQSR Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DQSGPDR,DQSG Power Down Receiver" "0,1"
|
|
rbitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DQSGODT,DQSG On-Die Termination" "0,1"
|
|
bitfld.long 0x00 2. "DQSGOE,DQSG Output Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
group.long 0x704++0x03
|
|
line.long 0x00 "DX0GCR1,DATX8 n General Configuration Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXPDRMODE,Enables the PDR mode for DQ[7:0]"
|
|
rbitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "QSNSEL,Select the delayed or non-delayed read data strobe #" "0,1"
|
|
bitfld.long 0x00 13. "QSSEL,Select the delayed or non-delayed read data strobe" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "OEEN,Enables Read Data Strobe in a byte lane" "0,1"
|
|
bitfld.long 0x00 11. "PDREN,Enables PDR in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TEEN,Enables ODT/TE in a byte lane" "0,1"
|
|
bitfld.long 0x00 9. "DSEN,Enables Write Data strobe in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DMEN,Enables DM pin in a byte lane" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DQEN,Enables DQ corresponding to each bit in a byte"
|
|
group.long 0x708++0x03
|
|
line.long 0x00 "DX0GCR2,DATX8 n General Configuration Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXOEMODE,Enables the OE mode values for DQ[7:0]"
|
|
hexmask.long.word 0x00 0.--15. 1. "DXTEMODE,Enables the TE (ODT) mode values for DQ[7:0]"
|
|
group.long 0x70C++0x03
|
|
line.long 0x00 "DX0GCR3,DATX8 n General Configuration Register 3"
|
|
bitfld.long 0x00 31. "OEBVT,Output Enable BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 30. "TEBVT,Termination Enable BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RDBVT,Read Data BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 28. "WDBVT,Write Data BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "RGLVT,Read DQS Gating LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 26. "RDLVT,Read DQS LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "WDLVT,Write DQ LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 24. "WLLVT,Write Leveling LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RGSLVT,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 22. "PDRBVT,Power Down Receiver BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DSNOEMODE,Enables the OE mode for DQs" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "DSNTEMODE,Enables the TE mode for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "DSNPDRMODE,Enables the PDR mode for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "DMOEMODE,Enables the OE mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "DMTEMODE,Enables the TE mode values for DM" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "DMPDRMODE,Enables the PDR mode values for DM" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 9. "RESERVED_9,Reserved" "0,1"
|
|
bitfld.long 0x00 8. "WDSBVT,Write Data Strobe BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "DSOEMODE,Enables the OE mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "DSTEMODE,Enables the TE mode values for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "DSPDRMODE,Enables the PDR mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 1. "RDMBVT,Read Data Mask BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDMBVT,Write Data Mask BDL VT Compensation" "0,1"
|
|
group.long 0x710++0x03
|
|
line.long 0x00 "DX0GCR4,DATX8 n General Configuration Register 4"
|
|
rbitfld.long 0x00 29.--31. "RESERVED_31_29,Byte lane VREF IOM (Used only by D4MU IOs)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "DXREFPEN,Byte Lane VREF Pad Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "DXREFEEN,Byte Lane Internal VREF Enable" "0,1,2,3"
|
|
bitfld.long 0x00 25. "DXREFSEN,Byte Lane Single-End VREF Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 24. "RESERVED_24,Reserved" "0,1"
|
|
bitfld.long 0x00 23. "DXREFESELRANGE,External VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFESEL,Byte Lane External VREF Select"
|
|
bitfld.long 0x00 15. "DXREFSSELRANGE,Single ended VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFSSEL,Byte Lane Single-End VREF Select"
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--5. "DXREFIEN,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "DXREFIMON,VRMON control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3"
|
|
group.long 0x714++0x03
|
|
line.long 0x00 "DX0GCR5,DATX8 n General Configuration Register 5"
|
|
rbitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "DXREFISELR3,Byte Lane internal VREF Select for Rank 3"
|
|
newline
|
|
rbitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFISELR2,Byte Lane internal VREF Select for Rank 2"
|
|
newline
|
|
rbitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFISELR1,Byte Lane internal VREF Select for Rank 1"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DXREFISELR0,Byte Lane internal VREF Select for Rank 0"
|
|
group.long 0x718++0x03
|
|
line.long 0x00 "DX0GCR6,DATX8 n General Configuration Register 6"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DXDQVREFR3,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DXDQVREFR2,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DXDQVREFR1,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DXDQVREFR0,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x71C++0x03
|
|
line.long 0x00 "DX0GCR7,DATX8 n General Configuration Register 7"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED_31_19,Reserved"
|
|
rbitfld.long 0x00 18. "RESERVED_18,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--17. 1. "RESERVED_17_10,Reserved"
|
|
bitfld.long 0x00 9. "DCALTYPE,DDL Calibration Type" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "DCALSVAL,DDL Calibration Starting Value"
|
|
repeat 2. (strings "8" "9" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x720)++0x03
|
|
line.long 0x00 "DX0GCR$1,DATX8 n General Configuration Register $1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "RESERVED_29_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x728++0x03
|
|
line.long 0x00 "DX0DQMAP0,DATX8 n DQ/DM Mapping Register 0"
|
|
rbitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED_30_20,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DQ4MAP,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "DQ3MAP,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DQ2MAP,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "DQ1MAP,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DQ0MAP,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x72C++0x03
|
|
line.long 0x00 "DX0DQMAP1,DATX8 n DQ/DM Mapping Register 1"
|
|
rbitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "RESERVED_30_16,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DMMAP,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "DQ7MAP,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQ6MAP,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQ5MAP,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x740++0x03
|
|
line.long 0x00 "DX0BDLR0,DATX8 n Bit Delay Line Register 0"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3WBD,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2WBD,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1WBD,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0WBD,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x744++0x03
|
|
line.long 0x00 "DX0BDLR1,DATX8 n Bit Delay Line Register 1"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7WBD,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6WBD,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5WBD,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4WBD,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x748++0x03
|
|
line.long 0x00 "DX0BDLR2,DATX8 n Bit Delay Line Register 2"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DSNWBD,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DSOEBD,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DSWBD,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DMWBD,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x750++0x03
|
|
line.long 0x00 "DX0BDLR3,DATX8 n Bit Delay Line Register 3"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3RBD,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2RBD,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1RBD,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0RBD,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x754++0x03
|
|
line.long 0x00 "DX0BDLR4,DATX8 n Bit Delay Line Register 4"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7RBD,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6RBD,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5RBD,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4RBD,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x758++0x03
|
|
line.long 0x00 "DX0BDLR5,DATX8 n Bit Delay Line Register 5"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED_31_6,Reserved"
|
|
bitfld.long 0x00 0.--5. "DMRBD,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x760++0x03
|
|
line.long 0x00 "DX0BDLR6,DATX8 n Bit Delay Line Register 6"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "TERBD,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "PDRBD,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED_7_0,Reserved"
|
|
repeat 3. (strings "7" "8" "9" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x764)++0x03
|
|
line.long 0x00 "DX0BDLR$1,DATX8 n Bit Delay Line Register $1"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x780++0x03
|
|
line.long 0x00 "DX0LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WLD,Write Leveling Delay"
|
|
group.long 0x784++0x03
|
|
line.long 0x00 "DX0LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WDQD,Write Data Delay"
|
|
group.long 0x788++0x03
|
|
line.long 0x00 "DX0LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGD,Read DQS Gating Delay"
|
|
group.long 0x78C++0x03
|
|
line.long 0x00 "DX0LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSD,Read DQS Delay"
|
|
group.long 0x790++0x03
|
|
line.long 0x00 "DX0LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSND,Read DQSN Delay"
|
|
group.long 0x794++0x03
|
|
line.long 0x00 "DX0LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGSD,DQS Gating Status Delay"
|
|
group.long 0x7A0++0x03
|
|
line.long 0x00 "DX0MDLR0,DATX8 n Master Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "TPRD,Target Period"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "IPRD,Initial Period"
|
|
group.long 0x7A4++0x03
|
|
line.long 0x00 "DX0MDLR1,DATX8 n Master Delay Line Register 1"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED_31_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "MDLD,MDL Delay"
|
|
group.long 0x7C0++0x03
|
|
line.long 0x00 "DX0GTR0,DATX8 n General Timing Register 0"
|
|
rbitfld.long 0x00 27.--31. "RESERVED_31_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "WDQSL,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WLSL,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 8.--12. "RESERVED_12_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "DGSL,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x7D0++0x03
|
|
line.long 0x00 "DX0RSR0,DATX8 n Rank Status Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "QSGERR,DQS Gate Training Error"
|
|
rgroup.long 0x7D4++0x03
|
|
line.long 0x00 "DX0RSR1,DATX8 n Rank Status Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVLERR,Read Leveling Error"
|
|
rgroup.long 0x7D8++0x03
|
|
line.long 0x00 "DX0RSR2,DATX8 n Rank Status Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAWN,Write Latency Adjustment (DQS off on some DQ lines) Warning"
|
|
rgroup.long 0x7DC++0x03
|
|
line.long 0x00 "DX0RSR3,DATX8 n Rank Status Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAERR,Write Leveling Adjustment Error"
|
|
rgroup.long 0x7E0++0x03
|
|
line.long 0x00 "DX0GSR0,DATX8 n General Status Register 0"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "WLDQ,Write Leveling DQ Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--29. "RESERVED_29_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 17.--25. 1. "GDQSPRD,Read DQS gating Period"
|
|
newline
|
|
bitfld.long 0x00 16. "DPLOCK,DATX8 PLL Lock" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "WLPRD,Write Leveling Period"
|
|
newline
|
|
bitfld.long 0x00 6. "WLERR,Write Leveling Error" "0,1"
|
|
bitfld.long 0x00 5. "WLDONE,Write Leveling Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "WLCAL,Write Leveling Calibration" "0,1"
|
|
bitfld.long 0x00 3. "GDQSCAL,Read DQS gating Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RDQSNCAL,Read DQS# Calibration" "0,1"
|
|
bitfld.long 0x00 1. "RDQSCAL,Read DQS Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDQCAL,Write DQ Calibration" "0,1"
|
|
rgroup.long 0x7E4++0x03
|
|
line.long 0x00 "DX0GSR1,DATX8 n General Status Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.tbyte 0x00 1.--24. 1. "DLTCODE,Delay Line Test Code"
|
|
newline
|
|
bitfld.long 0x00 0. "DLTDONE,Delay Line Test Done" "0,1"
|
|
rgroup.long 0x7E8++0x03
|
|
line.long 0x00 "DX0GSR2,DATX8 n General Status Register 2"
|
|
hexmask.long.word 0x00 23.--31. 1. "GSDQSPRD,Read DQS gating Status Period"
|
|
bitfld.long 0x00 22. "GSDQSCAL,Read DQS Gating Status Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "SRDERR,Static Read Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "DQS2DQERR,Write DQS2DQ Training Error"
|
|
bitfld.long 0x00 8.--11. "ESTAT,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "WEWN,Write Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 6. "WEERR,Write Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "REWN,Read Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 4. "REERR,Read Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "WDWN,Write Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 2. "WDERR,Write Bit Deskew Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RDWN,Read Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 0. "RDERR,Read Bit Deskew Error" "0,1"
|
|
rgroup.long 0x7EC++0x03
|
|
line.long 0x00 "DX0GSR3,DATX8 n General Status Register 3"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "ESTAT,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DVWRN,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "DVERR,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HVWRN,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HVERR,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "RESERVED_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. "SRDPC,Static Read Delay Pass Count" "0,1,2,3"
|
|
rgroup.long 0x7F0++0x03
|
|
line.long 0x00 "DX0GSR4,DATX8 n General Status Register 4"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 17.--25. 1. "RESERVED_25_17,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "RESERVED_16,Reserved" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "RESERVED_15_7,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0x7F4++0x03
|
|
line.long 0x00 "DX0GSR5,DATX8 n General Status Register 5"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED_31_23,Reserved"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "RESERVED_20,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "RESERVED_19_12,Reserved"
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0x7F8++0x03
|
|
line.long 0x00 "DX0GSR6,DATX8 n General Status Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "RESERVED_19_15,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "RESERVED_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "DX1GCR0,DATX8 n General Configuration Register 0"
|
|
bitfld.long 0x00 31. "CALBYP,Calibration Bypass" "0,1"
|
|
bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "CODTSHFT,Configurable ODT(TE) Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DQSDCC,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RDDLY,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 14.--19. "RESERVED_19_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 13. "DQSNSEPDR,DQSNSE Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 12. "DQSSEPDR,DQSSE Power Down Receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RTTOAL,RTT On Additive Latency" "0,1"
|
|
bitfld.long 0x00 9.--10. "RTTOH,RTT Output Hold" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "CPDRSHFT,Configurable PDR Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 6. "DQSRPD,DQSR Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DQSGPDR,DQSG Power Down Receiver" "0,1"
|
|
rbitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DQSGODT,DQSG On-Die Termination" "0,1"
|
|
bitfld.long 0x00 2. "DQSGOE,DQSG Output Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "DX1GCR1,DATX8 n General Configuration Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXPDRMODE,Enables the PDR mode for DQ[7:0]"
|
|
rbitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "QSNSEL,Select the delayed or non-delayed read data strobe #" "0,1"
|
|
bitfld.long 0x00 13. "QSSEL,Select the delayed or non-delayed read data strobe" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "OEEN,Enables Read Data Strobe in a byte lane" "0,1"
|
|
bitfld.long 0x00 11. "PDREN,Enables PDR in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TEEN,Enables ODT/TE in a byte lane" "0,1"
|
|
bitfld.long 0x00 9. "DSEN,Enables Write Data strobe in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DMEN,Enables DM pin in a byte lane" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DQEN,Enables DQ corresponding to each bit in a byte"
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "DX1GCR2,DATX8 n General Configuration Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXOEMODE,Enables the OE mode values for DQ[7:0]"
|
|
hexmask.long.word 0x00 0.--15. 1. "DXTEMODE,Enables the TE (ODT) mode values for DQ[7:0]"
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "DX1GCR3,DATX8 n General Configuration Register 3"
|
|
bitfld.long 0x00 31. "OEBVT,Output Enable BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 30. "TEBVT,Termination Enable BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RDBVT,Read Data BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 28. "WDBVT,Write Data BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "RGLVT,Read DQS Gating LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 26. "RDLVT,Read DQS LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "WDLVT,Write DQ LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 24. "WLLVT,Write Leveling LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RGSLVT,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 22. "PDRBVT,Power Down Receiver BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DSNOEMODE,Enables the OE mode for DQs" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "DSNTEMODE,Enables the TE mode for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "DSNPDRMODE,Enables the PDR mode for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "DMOEMODE,Enables the OE mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "DMTEMODE,Enables the TE mode values for DM" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "DMPDRMODE,Enables the PDR mode values for DM" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 9. "RESERVED_9,Reserved" "0,1"
|
|
bitfld.long 0x00 8. "WDSBVT,Write Data Strobe BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "DSOEMODE,Enables the OE mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "DSTEMODE,Enables the TE mode values for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "DSPDRMODE,Enables the PDR mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 1. "RDMBVT,Read Data Mask BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDMBVT,Write Data Mask BDL VT Compensation" "0,1"
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "DX1GCR4,DATX8 n General Configuration Register 4"
|
|
rbitfld.long 0x00 29.--31. "RESERVED_31_29,Byte lane VREF IOM (Used only by D4MU IOs)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "DXREFPEN,Byte Lane VREF Pad Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "DXREFEEN,Byte Lane Internal VREF Enable" "0,1,2,3"
|
|
bitfld.long 0x00 25. "DXREFSEN,Byte Lane Single-End VREF Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 24. "RESERVED_24,Reserved" "0,1"
|
|
bitfld.long 0x00 23. "DXREFESELRANGE,External VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFESEL,Byte Lane External VREF Select"
|
|
bitfld.long 0x00 15. "DXREFSSELRANGE,Single ended VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFSSEL,Byte Lane Single-End VREF Select"
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--5. "DXREFIEN,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "DXREFIMON,VRMON control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3"
|
|
group.long 0x814++0x03
|
|
line.long 0x00 "DX1GCR5,DATX8 n General Configuration Register 5"
|
|
rbitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "DXREFISELR3,Byte Lane internal VREF Select for Rank 3"
|
|
newline
|
|
rbitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFISELR2,Byte Lane internal VREF Select for Rank 2"
|
|
newline
|
|
rbitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFISELR1,Byte Lane internal VREF Select for Rank 1"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DXREFISELR0,Byte Lane internal VREF Select for Rank 0"
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "DX1GCR6,DATX8 n General Configuration Register 6"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DXDQVREFR3,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DXDQVREFR2,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DXDQVREFR1,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DXDQVREFR0,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x81C++0x03
|
|
line.long 0x00 "DX1GCR7,DATX8 n General Configuration Register 7"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED_31_19,Reserved"
|
|
rbitfld.long 0x00 18. "RESERVED_18,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--17. 1. "RESERVED_17_10,Reserved"
|
|
bitfld.long 0x00 9. "DCALTYPE,DDL Calibration Type" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "DCALSVAL,DDL Calibration Starting Value"
|
|
repeat 2. (strings "8" "9" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x820)++0x03
|
|
line.long 0x00 "DX1GCR$1,DATX8 n General Configuration Register $1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "RESERVED_29_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "DX1DQMAP0,DATX8 n DQ/DM Mapping Register 0"
|
|
rbitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED_30_20,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DQ4MAP,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "DQ3MAP,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DQ2MAP,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "DQ1MAP,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DQ0MAP,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "DX1DQMAP1,DATX8 n DQ/DM Mapping Register 1"
|
|
rbitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "RESERVED_30_16,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DMMAP,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "DQ7MAP,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQ6MAP,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQ5MAP,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "DX1BDLR0,DATX8 n Bit Delay Line Register 0"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3WBD,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2WBD,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1WBD,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0WBD,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "DX1BDLR1,DATX8 n Bit Delay Line Register 1"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7WBD,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6WBD,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5WBD,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4WBD,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "DX1BDLR2,DATX8 n Bit Delay Line Register 2"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DSNWBD,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DSOEBD,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DSWBD,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DMWBD,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "DX1BDLR3,DATX8 n Bit Delay Line Register 3"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3RBD,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2RBD,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1RBD,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0RBD,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x854++0x03
|
|
line.long 0x00 "DX1BDLR4,DATX8 n Bit Delay Line Register 4"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7RBD,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6RBD,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5RBD,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4RBD,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "DX1BDLR5,DATX8 n Bit Delay Line Register 5"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED_31_6,Reserved"
|
|
bitfld.long 0x00 0.--5. "DMRBD,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "DX1BDLR6,DATX8 n Bit Delay Line Register 6"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "TERBD,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "PDRBD,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED_7_0,Reserved"
|
|
repeat 3. (strings "7" "8" "9" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x864)++0x03
|
|
line.long 0x00 "DX1BDLR$1,DATX8 n Bit Delay Line Register $1"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "DX1LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WLD,Write Leveling Delay"
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "DX1LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WDQD,Write Data Delay"
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "DX1LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGD,Read DQS Gating Delay"
|
|
group.long 0x88C++0x03
|
|
line.long 0x00 "DX1LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSD,Read DQS Delay"
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "DX1LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSND,Read DQSN Delay"
|
|
group.long 0x894++0x03
|
|
line.long 0x00 "DX1LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGSD,DQS Gating Status Delay"
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "DX1MDLR0,DATX8 n Master Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "TPRD,Target Period"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "IPRD,Initial Period"
|
|
group.long 0x8A4++0x03
|
|
line.long 0x00 "DX1MDLR1,DATX8 n Master Delay Line Register 1"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED_31_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "MDLD,MDL Delay"
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "DX1GTR0,DATX8 n General Timing Register 0"
|
|
rbitfld.long 0x00 27.--31. "RESERVED_31_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "WDQSL,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WLSL,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 8.--12. "RESERVED_12_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "DGSL,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x8D0++0x03
|
|
line.long 0x00 "DX1RSR0,DATX8 n Rank Status Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "QSGERR,DQS Gate Training Error"
|
|
rgroup.long 0x8D4++0x03
|
|
line.long 0x00 "DX1RSR1,DATX8 n Rank Status Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVLERR,Read Leveling Error"
|
|
rgroup.long 0x8D8++0x03
|
|
line.long 0x00 "DX1RSR2,DATX8 n Rank Status Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAWN,Write Latency Adjustment (DQS off on some DQ lines) Warning"
|
|
rgroup.long 0x8DC++0x03
|
|
line.long 0x00 "DX1RSR3,DATX8 n Rank Status Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAERR,Write Leveling Adjustment Error"
|
|
rgroup.long 0x8E0++0x03
|
|
line.long 0x00 "DX1GSR0,DATX8 n General Status Register 0"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "WLDQ,Write Leveling DQ Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--29. "RESERVED_29_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 17.--25. 1. "GDQSPRD,Read DQS gating Period"
|
|
newline
|
|
bitfld.long 0x00 16. "DPLOCK,DATX8 PLL Lock" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "WLPRD,Write Leveling Period"
|
|
newline
|
|
bitfld.long 0x00 6. "WLERR,Write Leveling Error" "0,1"
|
|
bitfld.long 0x00 5. "WLDONE,Write Leveling Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "WLCAL,Write Leveling Calibration" "0,1"
|
|
bitfld.long 0x00 3. "GDQSCAL,Read DQS gating Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RDQSNCAL,Read DQS# Calibration" "0,1"
|
|
bitfld.long 0x00 1. "RDQSCAL,Read DQS Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDQCAL,Write DQ Calibration" "0,1"
|
|
rgroup.long 0x8E4++0x03
|
|
line.long 0x00 "DX1GSR1,DATX8 n General Status Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.tbyte 0x00 1.--24. 1. "DLTCODE,Delay Line Test Code"
|
|
newline
|
|
bitfld.long 0x00 0. "DLTDONE,Delay Line Test Done" "0,1"
|
|
rgroup.long 0x8E8++0x03
|
|
line.long 0x00 "DX1GSR2,DATX8 n General Status Register 2"
|
|
hexmask.long.word 0x00 23.--31. 1. "GSDQSPRD,Read DQS gating Status Period"
|
|
bitfld.long 0x00 22. "GSDQSCAL,Read DQS Gating Status Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "SRDERR,Static Read Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "DQS2DQERR,Write DQS2DQ Training Error"
|
|
bitfld.long 0x00 8.--11. "ESTAT,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "WEWN,Write Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 6. "WEERR,Write Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "REWN,Read Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 4. "REERR,Read Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "WDWN,Write Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 2. "WDERR,Write Bit Deskew Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RDWN,Read Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 0. "RDERR,Read Bit Deskew Error" "0,1"
|
|
rgroup.long 0x8EC++0x03
|
|
line.long 0x00 "DX1GSR3,DATX8 n General Status Register 3"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "ESTAT,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DVWRN,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "DVERR,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HVWRN,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HVERR,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "RESERVED_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. "SRDPC,Static Read Delay Pass Count" "0,1,2,3"
|
|
rgroup.long 0x8F0++0x03
|
|
line.long 0x00 "DX1GSR4,DATX8 n General Status Register 4"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 17.--25. 1. "RESERVED_25_17,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "RESERVED_16,Reserved" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "RESERVED_15_7,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0x8F4++0x03
|
|
line.long 0x00 "DX1GSR5,DATX8 n General Status Register 5"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED_31_23,Reserved"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "RESERVED_20,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "RESERVED_19_12,Reserved"
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0x8F8++0x03
|
|
line.long 0x00 "DX1GSR6,DATX8 n General Status Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "RESERVED_19_15,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "RESERVED_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "DX2GCR0,DATX8 n General Configuration Register 0"
|
|
bitfld.long 0x00 31. "CALBYP,Calibration Bypass" "0,1"
|
|
bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "CODTSHFT,Configurable ODT(TE) Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DQSDCC,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RDDLY,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 14.--19. "RESERVED_19_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 13. "DQSNSEPDR,DQSNSE Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 12. "DQSSEPDR,DQSSE Power Down Receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RTTOAL,RTT On Additive Latency" "0,1"
|
|
bitfld.long 0x00 9.--10. "RTTOH,RTT Output Hold" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "CPDRSHFT,Configurable PDR Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 6. "DQSRPD,DQSR Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DQSGPDR,DQSG Power Down Receiver" "0,1"
|
|
rbitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DQSGODT,DQSG On-Die Termination" "0,1"
|
|
bitfld.long 0x00 2. "DQSGOE,DQSG Output Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
group.long 0x904++0x03
|
|
line.long 0x00 "DX2GCR1,DATX8 n General Configuration Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXPDRMODE,Enables the PDR mode for DQ[7:0]"
|
|
rbitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "QSNSEL,Select the delayed or non-delayed read data strobe #" "0,1"
|
|
bitfld.long 0x00 13. "QSSEL,Select the delayed or non-delayed read data strobe" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "OEEN,Enables Read Data Strobe in a byte lane" "0,1"
|
|
bitfld.long 0x00 11. "PDREN,Enables PDR in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TEEN,Enables ODT/TE in a byte lane" "0,1"
|
|
bitfld.long 0x00 9. "DSEN,Enables Write Data strobe in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DMEN,Enables DM pin in a byte lane" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DQEN,Enables DQ corresponding to each bit in a byte"
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "DX2GCR2,DATX8 n General Configuration Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXOEMODE,Enables the OE mode values for DQ[7:0]"
|
|
hexmask.long.word 0x00 0.--15. 1. "DXTEMODE,Enables the TE (ODT) mode values for DQ[7:0]"
|
|
group.long 0x90C++0x03
|
|
line.long 0x00 "DX2GCR3,DATX8 n General Configuration Register 3"
|
|
bitfld.long 0x00 31. "OEBVT,Output Enable BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 30. "TEBVT,Termination Enable BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RDBVT,Read Data BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 28. "WDBVT,Write Data BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "RGLVT,Read DQS Gating LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 26. "RDLVT,Read DQS LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "WDLVT,Write DQ LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 24. "WLLVT,Write Leveling LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RGSLVT,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 22. "PDRBVT,Power Down Receiver BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DSNOEMODE,Enables the OE mode for DQs" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "DSNTEMODE,Enables the TE mode for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "DSNPDRMODE,Enables the PDR mode for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "DMOEMODE,Enables the OE mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "DMTEMODE,Enables the TE mode values for DM" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "DMPDRMODE,Enables the PDR mode values for DM" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 9. "RESERVED_9,Reserved" "0,1"
|
|
bitfld.long 0x00 8. "WDSBVT,Write Data Strobe BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "DSOEMODE,Enables the OE mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "DSTEMODE,Enables the TE mode values for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "DSPDRMODE,Enables the PDR mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 1. "RDMBVT,Read Data Mask BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDMBVT,Write Data Mask BDL VT Compensation" "0,1"
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "DX2GCR4,DATX8 n General Configuration Register 4"
|
|
rbitfld.long 0x00 29.--31. "RESERVED_31_29,Byte lane VREF IOM (Used only by D4MU IOs)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "DXREFPEN,Byte Lane VREF Pad Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "DXREFEEN,Byte Lane Internal VREF Enable" "0,1,2,3"
|
|
bitfld.long 0x00 25. "DXREFSEN,Byte Lane Single-End VREF Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 24. "RESERVED_24,Reserved" "0,1"
|
|
bitfld.long 0x00 23. "DXREFESELRANGE,External VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFESEL,Byte Lane External VREF Select"
|
|
bitfld.long 0x00 15. "DXREFSSELRANGE,Single ended VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFSSEL,Byte Lane Single-End VREF Select"
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--5. "DXREFIEN,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "DXREFIMON,VRMON control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3"
|
|
group.long 0x914++0x03
|
|
line.long 0x00 "DX2GCR5,DATX8 n General Configuration Register 5"
|
|
rbitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "DXREFISELR3,Byte Lane internal VREF Select for Rank 3"
|
|
newline
|
|
rbitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFISELR2,Byte Lane internal VREF Select for Rank 2"
|
|
newline
|
|
rbitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFISELR1,Byte Lane internal VREF Select for Rank 1"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DXREFISELR0,Byte Lane internal VREF Select for Rank 0"
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "DX2GCR6,DATX8 n General Configuration Register 6"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DXDQVREFR3,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DXDQVREFR2,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DXDQVREFR1,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DXDQVREFR0,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x91C++0x03
|
|
line.long 0x00 "DX2GCR7,DATX8 n General Configuration Register 7"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED_31_19,Reserved"
|
|
rbitfld.long 0x00 18. "RESERVED_18,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--17. 1. "RESERVED_17_10,Reserved"
|
|
bitfld.long 0x00 9. "DCALTYPE,DDL Calibration Type" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "DCALSVAL,DDL Calibration Starting Value"
|
|
repeat 2. (strings "8" "9" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0x920)++0x03
|
|
line.long 0x00 "DX2GCR$1,DATX8 n General Configuration Register $1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "RESERVED_29_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "DX2DQMAP0,DATX8 n DQ/DM Mapping Register 0"
|
|
rbitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED_30_20,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DQ4MAP,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "DQ3MAP,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DQ2MAP,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "DQ1MAP,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DQ0MAP,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x92C++0x03
|
|
line.long 0x00 "DX2DQMAP1,DATX8 n DQ/DM Mapping Register 1"
|
|
rbitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "RESERVED_30_16,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DMMAP,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "DQ7MAP,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQ6MAP,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQ5MAP,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "DX2BDLR0,DATX8 n Bit Delay Line Register 0"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3WBD,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2WBD,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1WBD,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0WBD,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x944++0x03
|
|
line.long 0x00 "DX2BDLR1,DATX8 n Bit Delay Line Register 1"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7WBD,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6WBD,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5WBD,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4WBD,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "DX2BDLR2,DATX8 n Bit Delay Line Register 2"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DSNWBD,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DSOEBD,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DSWBD,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DMWBD,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "DX2BDLR3,DATX8 n Bit Delay Line Register 3"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3RBD,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2RBD,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1RBD,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0RBD,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x954++0x03
|
|
line.long 0x00 "DX2BDLR4,DATX8 n Bit Delay Line Register 4"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7RBD,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6RBD,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5RBD,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4RBD,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "DX2BDLR5,DATX8 n Bit Delay Line Register 5"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED_31_6,Reserved"
|
|
bitfld.long 0x00 0.--5. "DMRBD,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "DX2BDLR6,DATX8 n Bit Delay Line Register 6"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "TERBD,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "PDRBD,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED_7_0,Reserved"
|
|
repeat 3. (strings "7" "8" "9" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0x964)++0x03
|
|
line.long 0x00 "DX2BDLR$1,DATX8 n Bit Delay Line Register $1"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "DX2LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WLD,Write Leveling Delay"
|
|
group.long 0x984++0x03
|
|
line.long 0x00 "DX2LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WDQD,Write Data Delay"
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "DX2LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGD,Read DQS Gating Delay"
|
|
group.long 0x98C++0x03
|
|
line.long 0x00 "DX2LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSD,Read DQS Delay"
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "DX2LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSND,Read DQSN Delay"
|
|
group.long 0x994++0x03
|
|
line.long 0x00 "DX2LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGSD,DQS Gating Status Delay"
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "DX2MDLR0,DATX8 n Master Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "TPRD,Target Period"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "IPRD,Initial Period"
|
|
group.long 0x9A4++0x03
|
|
line.long 0x00 "DX2MDLR1,DATX8 n Master Delay Line Register 1"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED_31_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "MDLD,MDL Delay"
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "DX2GTR0,DATX8 n General Timing Register 0"
|
|
rbitfld.long 0x00 27.--31. "RESERVED_31_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "WDQSL,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WLSL,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 8.--12. "RESERVED_12_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "DGSL,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x9D0++0x03
|
|
line.long 0x00 "DX2RSR0,DATX8 n Rank Status Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "QSGERR,DQS Gate Training Error"
|
|
rgroup.long 0x9D4++0x03
|
|
line.long 0x00 "DX2RSR1,DATX8 n Rank Status Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVLERR,Read Leveling Error"
|
|
rgroup.long 0x9D8++0x03
|
|
line.long 0x00 "DX2RSR2,DATX8 n Rank Status Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAWN,Write Latency Adjustment (DQS off on some DQ lines) Warning"
|
|
rgroup.long 0x9DC++0x03
|
|
line.long 0x00 "DX2RSR3,DATX8 n Rank Status Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAERR,Write Leveling Adjustment Error"
|
|
rgroup.long 0x9E0++0x03
|
|
line.long 0x00 "DX2GSR0,DATX8 n General Status Register 0"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "WLDQ,Write Leveling DQ Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--29. "RESERVED_29_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 17.--25. 1. "GDQSPRD,Read DQS gating Period"
|
|
newline
|
|
bitfld.long 0x00 16. "DPLOCK,DATX8 PLL Lock" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "WLPRD,Write Leveling Period"
|
|
newline
|
|
bitfld.long 0x00 6. "WLERR,Write Leveling Error" "0,1"
|
|
bitfld.long 0x00 5. "WLDONE,Write Leveling Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "WLCAL,Write Leveling Calibration" "0,1"
|
|
bitfld.long 0x00 3. "GDQSCAL,Read DQS gating Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RDQSNCAL,Read DQS# Calibration" "0,1"
|
|
bitfld.long 0x00 1. "RDQSCAL,Read DQS Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDQCAL,Write DQ Calibration" "0,1"
|
|
rgroup.long 0x9E4++0x03
|
|
line.long 0x00 "DX2GSR1,DATX8 n General Status Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.tbyte 0x00 1.--24. 1. "DLTCODE,Delay Line Test Code"
|
|
newline
|
|
bitfld.long 0x00 0. "DLTDONE,Delay Line Test Done" "0,1"
|
|
rgroup.long 0x9E8++0x03
|
|
line.long 0x00 "DX2GSR2,DATX8 n General Status Register 2"
|
|
hexmask.long.word 0x00 23.--31. 1. "GSDQSPRD,Read DQS gating Status Period"
|
|
bitfld.long 0x00 22. "GSDQSCAL,Read DQS Gating Status Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "SRDERR,Static Read Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "DQS2DQERR,Write DQS2DQ Training Error"
|
|
bitfld.long 0x00 8.--11. "ESTAT,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "WEWN,Write Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 6. "WEERR,Write Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "REWN,Read Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 4. "REERR,Read Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "WDWN,Write Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 2. "WDERR,Write Bit Deskew Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RDWN,Read Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 0. "RDERR,Read Bit Deskew Error" "0,1"
|
|
rgroup.long 0x9EC++0x03
|
|
line.long 0x00 "DX2GSR3,DATX8 n General Status Register 3"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "ESTAT,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DVWRN,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "DVERR,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HVWRN,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HVERR,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "RESERVED_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. "SRDPC,Static Read Delay Pass Count" "0,1,2,3"
|
|
rgroup.long 0x9F0++0x03
|
|
line.long 0x00 "DX2GSR4,DATX8 n General Status Register 4"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 17.--25. 1. "RESERVED_25_17,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "RESERVED_16,Reserved" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "RESERVED_15_7,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0x9F4++0x03
|
|
line.long 0x00 "DX2GSR5,DATX8 n General Status Register 5"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED_31_23,Reserved"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "RESERVED_20,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "RESERVED_19_12,Reserved"
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0x9F8++0x03
|
|
line.long 0x00 "DX2GSR6,DATX8 n General Status Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "RESERVED_19_15,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "RESERVED_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "DX3GCR0,DATX8 n General Configuration Register 0"
|
|
bitfld.long 0x00 31. "CALBYP,Calibration Bypass" "0,1"
|
|
bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "CODTSHFT,Configurable ODT(TE) Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DQSDCC,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RDDLY,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 14.--19. "RESERVED_19_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 13. "DQSNSEPDR,DQSNSE Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 12. "DQSSEPDR,DQSSE Power Down Receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RTTOAL,RTT On Additive Latency" "0,1"
|
|
bitfld.long 0x00 9.--10. "RTTOH,RTT Output Hold" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "CPDRSHFT,Configurable PDR Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 6. "DQSRPD,DQSR Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DQSGPDR,DQSG Power Down Receiver" "0,1"
|
|
rbitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DQSGODT,DQSG On-Die Termination" "0,1"
|
|
bitfld.long 0x00 2. "DQSGOE,DQSG Output Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "DX3GCR1,DATX8 n General Configuration Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXPDRMODE,Enables the PDR mode for DQ[7:0]"
|
|
rbitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "QSNSEL,Select the delayed or non-delayed read data strobe #" "0,1"
|
|
bitfld.long 0x00 13. "QSSEL,Select the delayed or non-delayed read data strobe" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "OEEN,Enables Read Data Strobe in a byte lane" "0,1"
|
|
bitfld.long 0x00 11. "PDREN,Enables PDR in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TEEN,Enables ODT/TE in a byte lane" "0,1"
|
|
bitfld.long 0x00 9. "DSEN,Enables Write Data strobe in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DMEN,Enables DM pin in a byte lane" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DQEN,Enables DQ corresponding to each bit in a byte"
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "DX3GCR2,DATX8 n General Configuration Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXOEMODE,Enables the OE mode values for DQ[7:0]"
|
|
hexmask.long.word 0x00 0.--15. 1. "DXTEMODE,Enables the TE (ODT) mode values for DQ[7:0]"
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "DX3GCR3,DATX8 n General Configuration Register 3"
|
|
bitfld.long 0x00 31. "OEBVT,Output Enable BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 30. "TEBVT,Termination Enable BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RDBVT,Read Data BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 28. "WDBVT,Write Data BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "RGLVT,Read DQS Gating LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 26. "RDLVT,Read DQS LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "WDLVT,Write DQ LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 24. "WLLVT,Write Leveling LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RGSLVT,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 22. "PDRBVT,Power Down Receiver BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DSNOEMODE,Enables the OE mode for DQs" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "DSNTEMODE,Enables the TE mode for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "DSNPDRMODE,Enables the PDR mode for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "DMOEMODE,Enables the OE mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "DMTEMODE,Enables the TE mode values for DM" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "DMPDRMODE,Enables the PDR mode values for DM" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 9. "RESERVED_9,Reserved" "0,1"
|
|
bitfld.long 0x00 8. "WDSBVT,Write Data Strobe BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "DSOEMODE,Enables the OE mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "DSTEMODE,Enables the TE mode values for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "DSPDRMODE,Enables the PDR mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 1. "RDMBVT,Read Data Mask BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDMBVT,Write Data Mask BDL VT Compensation" "0,1"
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "DX3GCR4,DATX8 n General Configuration Register 4"
|
|
rbitfld.long 0x00 29.--31. "RESERVED_31_29,Byte lane VREF IOM (Used only by D4MU IOs)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "DXREFPEN,Byte Lane VREF Pad Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "DXREFEEN,Byte Lane Internal VREF Enable" "0,1,2,3"
|
|
bitfld.long 0x00 25. "DXREFSEN,Byte Lane Single-End VREF Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 24. "RESERVED_24,Reserved" "0,1"
|
|
bitfld.long 0x00 23. "DXREFESELRANGE,External VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFESEL,Byte Lane External VREF Select"
|
|
bitfld.long 0x00 15. "DXREFSSELRANGE,Single ended VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFSSEL,Byte Lane Single-End VREF Select"
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--5. "DXREFIEN,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "DXREFIMON,VRMON control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3"
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "DX3GCR5,DATX8 n General Configuration Register 5"
|
|
rbitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "DXREFISELR3,Byte Lane internal VREF Select for Rank 3"
|
|
newline
|
|
rbitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFISELR2,Byte Lane internal VREF Select for Rank 2"
|
|
newline
|
|
rbitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFISELR1,Byte Lane internal VREF Select for Rank 1"
|
|
newline
|
|
rbitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DXREFISELR0,Byte Lane internal VREF Select for Rank 0"
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "DX3GCR6,DATX8 n General Configuration Register 6"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DXDQVREFR3,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DXDQVREFR2,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DXDQVREFR1,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DXDQVREFR0,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "DX3GCR7,DATX8 n General Configuration Register 7"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED_31_19,Reserved"
|
|
rbitfld.long 0x00 18. "RESERVED_18,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--17. 1. "RESERVED_17_10,Reserved"
|
|
bitfld.long 0x00 9. "DCALTYPE,DDL Calibration Type" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "DCALSVAL,DDL Calibration Starting Value"
|
|
repeat 2. (strings "8" "9" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xA20)++0x03
|
|
line.long 0x00 "DX3GCR$1,DATX8 n General Configuration Register $1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "RESERVED_29_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "DX3DQMAP0,DATX8 n DQ/DM Mapping Register 0"
|
|
rbitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED_30_20,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DQ4MAP,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "DQ3MAP,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DQ2MAP,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "DQ1MAP,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DQ0MAP,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xA2C++0x03
|
|
line.long 0x00 "DX3DQMAP1,DATX8 n DQ/DM Mapping Register 1"
|
|
rbitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "RESERVED_30_16,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DMMAP,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "DQ7MAP,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQ6MAP,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQ5MAP,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "DX3BDLR0,DATX8 n Bit Delay Line Register 0"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3WBD,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2WBD,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1WBD,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0WBD,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA44++0x03
|
|
line.long 0x00 "DX3BDLR1,DATX8 n Bit Delay Line Register 1"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7WBD,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6WBD,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5WBD,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4WBD,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "DX3BDLR2,DATX8 n Bit Delay Line Register 2"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DSNWBD,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DSOEBD,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DSWBD,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DMWBD,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "DX3BDLR3,DATX8 n Bit Delay Line Register 3"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3RBD,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2RBD,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1RBD,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0RBD,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA54++0x03
|
|
line.long 0x00 "DX3BDLR4,DATX8 n Bit Delay Line Register 4"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7RBD,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6RBD,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5RBD,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4RBD,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "DX3BDLR5,DATX8 n Bit Delay Line Register 5"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED_31_6,Reserved"
|
|
bitfld.long 0x00 0.--5. "DMRBD,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "DX3BDLR6,DATX8 n Bit Delay Line Register 6"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "TERBD,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "PDRBD,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED_7_0,Reserved"
|
|
repeat 3. (strings "7" "8" "9" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xA64)++0x03
|
|
line.long 0x00 "DX3BDLR$1,DATX8 n Bit Delay Line Register $1"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "DX3LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WLD,Write Leveling Delay"
|
|
group.long 0xA84++0x03
|
|
line.long 0x00 "DX3LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WDQD,Write Data Delay"
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "DX3LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGD,Read DQS Gating Delay"
|
|
group.long 0xA8C++0x03
|
|
line.long 0x00 "DX3LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSD,Read DQS Delay"
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "DX3LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSND,Read DQSN Delay"
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "DX3LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGSD,DQS Gating Status Delay"
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "DX3MDLR0,DATX8 n Master Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "TPRD,Target Period"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "IPRD,Initial Period"
|
|
group.long 0xAA4++0x03
|
|
line.long 0x00 "DX3MDLR1,DATX8 n Master Delay Line Register 1"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED_31_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "MDLD,MDL Delay"
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "DX3GTR0,DATX8 n General Timing Register 0"
|
|
rbitfld.long 0x00 27.--31. "RESERVED_31_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "WDQSL,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WLSL,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 8.--12. "RESERVED_12_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "DGSL,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xAD0++0x03
|
|
line.long 0x00 "DX3RSR0,DATX8 n Rank Status Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "QSGERR,DQS Gate Training Error"
|
|
rgroup.long 0xAD4++0x03
|
|
line.long 0x00 "DX3RSR1,DATX8 n Rank Status Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVLERR,Read Leveling Error"
|
|
rgroup.long 0xAD8++0x03
|
|
line.long 0x00 "DX3RSR2,DATX8 n Rank Status Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAWN,Write Latency Adjustment (DQS off on some DQ lines) Warning"
|
|
rgroup.long 0xADC++0x03
|
|
line.long 0x00 "DX3RSR3,DATX8 n Rank Status Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAERR,Write Leveling Adjustment Error"
|
|
rgroup.long 0xAE0++0x03
|
|
line.long 0x00 "DX3GSR0,DATX8 n General Status Register 0"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "WLDQ,Write Leveling DQ Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--29. "RESERVED_29_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 17.--25. 1. "GDQSPRD,Read DQS gating Period"
|
|
newline
|
|
bitfld.long 0x00 16. "DPLOCK,DATX8 PLL Lock" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "WLPRD,Write Leveling Period"
|
|
newline
|
|
bitfld.long 0x00 6. "WLERR,Write Leveling Error" "0,1"
|
|
bitfld.long 0x00 5. "WLDONE,Write Leveling Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "WLCAL,Write Leveling Calibration" "0,1"
|
|
bitfld.long 0x00 3. "GDQSCAL,Read DQS gating Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RDQSNCAL,Read DQS# Calibration" "0,1"
|
|
bitfld.long 0x00 1. "RDQSCAL,Read DQS Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDQCAL,Write DQ Calibration" "0,1"
|
|
rgroup.long 0xAE4++0x03
|
|
line.long 0x00 "DX3GSR1,DATX8 n General Status Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.tbyte 0x00 1.--24. 1. "DLTCODE,Delay Line Test Code"
|
|
newline
|
|
bitfld.long 0x00 0. "DLTDONE,Delay Line Test Done" "0,1"
|
|
rgroup.long 0xAE8++0x03
|
|
line.long 0x00 "DX3GSR2,DATX8 n General Status Register 2"
|
|
hexmask.long.word 0x00 23.--31. 1. "GSDQSPRD,Read DQS gating Status Period"
|
|
bitfld.long 0x00 22. "GSDQSCAL,Read DQS Gating Status Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "SRDERR,Static Read Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "DQS2DQERR,Write DQS2DQ Training Error"
|
|
bitfld.long 0x00 8.--11. "ESTAT,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "WEWN,Write Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 6. "WEERR,Write Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "REWN,Read Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 4. "REERR,Read Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "WDWN,Write Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 2. "WDERR,Write Bit Deskew Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RDWN,Read Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 0. "RDERR,Read Bit Deskew Error" "0,1"
|
|
rgroup.long 0xAEC++0x03
|
|
line.long 0x00 "DX3GSR3,DATX8 n General Status Register 3"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "ESTAT,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DVWRN,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "DVERR,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HVWRN,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HVERR,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "RESERVED_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. "SRDPC,Static Read Delay Pass Count" "0,1,2,3"
|
|
rgroup.long 0xAF0++0x03
|
|
line.long 0x00 "DX3GSR4,DATX8 n General Status Register 4"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 17.--25. 1. "RESERVED_25_17,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "RESERVED_16,Reserved" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "RESERVED_15_7,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0xAF4++0x03
|
|
line.long 0x00 "DX3GSR5,DATX8 n General Status Register 5"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED_31_23,Reserved"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "RESERVED_20,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "RESERVED_19_12,Reserved"
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0xAF8++0x03
|
|
line.long 0x00 "DX3GSR6,DATX8 n General Status Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "RESERVED_19_15,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "RESERVED_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
rgroup.long 0xB00++0x03
|
|
line.long 0x00 "DX4GCR0,DATX8 n General Configuration Register 0"
|
|
bitfld.long 0x00 31. "CALBYP,Calibration Bypass" "0,1"
|
|
bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "CODTSHFT,Configurable ODT(TE) Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DQSDCC,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RDDLY,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--19. "RESERVED_19_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 13. "DQSNSEPDR,DQSNSE Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 12. "DQSSEPDR,DQSSE Power Down Receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RTTOAL,RTT On Additive Latency" "0,1"
|
|
bitfld.long 0x00 9.--10. "RTTOH,RTT Output Hold" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "CPDRSHFT,Configurable PDR Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 6. "DQSRPD,DQSR Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DQSGPDR,DQSG Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DQSGODT,DQSG On-Die Termination" "0,1"
|
|
bitfld.long 0x00 2. "DQSGOE,DQSG Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
rgroup.long 0xB04++0x03
|
|
line.long 0x00 "DX4GCR1,DATX8 n General Configuration Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXPDRMODE,Enables the PDR mode for DQ[7:0]"
|
|
bitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "QSNSEL,Select the delayed or non-delayed read data strobe #" "0,1"
|
|
bitfld.long 0x00 13. "QSSEL,Select the delayed or non-delayed read data strobe" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "OEEN,Enables Read Data Strobe in a byte lane" "0,1"
|
|
bitfld.long 0x00 11. "PDREN,Enables PDR in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TEEN,Enables ODT/TE in a byte lane" "0,1"
|
|
bitfld.long 0x00 9. "DSEN,Enables Write Data strobe in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DMEN,Enables DM pin in a byte lane" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DQEN,Enables DQ corresponding to each bit in a byte"
|
|
rgroup.long 0xB08++0x03
|
|
line.long 0x00 "DX4GCR2,DATX8 n General Configuration Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXOEMODE,Enables the OE mode values for DQ[7:0]"
|
|
hexmask.long.word 0x00 0.--15. 1. "DXTEMODE,Enables the TE (ODT) mode values for DQ[7:0]"
|
|
rgroup.long 0xB0C++0x03
|
|
line.long 0x00 "DX4GCR3,DATX8 n General Configuration Register 3"
|
|
bitfld.long 0x00 31. "OEBVT,Output Enable BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 30. "TEBVT,Termination Enable BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RDBVT,Read Data BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 28. "WDBVT,Write Data BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "RGLVT,Read DQS Gating LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 26. "RDLVT,Read DQS LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "WDLVT,Write DQ LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 24. "WLLVT,Write Leveling LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RGSLVT,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 22. "PDRBVT,Power Down Receiver BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DSNOEMODE,Enables the OE mode for DQs" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "DSNTEMODE,Enables the TE mode for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "DSNPDRMODE,Enables the PDR mode for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "DMOEMODE,Enables the OE mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "DMTEMODE,Enables the TE mode values for DM" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "DMPDRMODE,Enables the PDR mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "RESERVED_9,Reserved" "0,1"
|
|
bitfld.long 0x00 8. "WDSBVT,Write Data Strobe BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "DSOEMODE,Enables the OE mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "DSTEMODE,Enables the TE mode values for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "DSPDRMODE,Enables the PDR mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 1. "RDMBVT,Read Data Mask BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDMBVT,Write Data Mask BDL VT Compensation" "0,1"
|
|
rgroup.long 0xB10++0x03
|
|
line.long 0x00 "DX4GCR4,DATX8 n General Configuration Register 4"
|
|
bitfld.long 0x00 29.--31. "RESERVED_31_29,Byte lane VREF IOM (Used only by D4MU IOs)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "DXREFPEN,Byte Lane VREF Pad Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "DXREFEEN,Byte Lane Internal VREF Enable" "0,1,2,3"
|
|
bitfld.long 0x00 25. "DXREFSEN,Byte Lane Single-End VREF Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RESERVED_24,Reserved" "0,1"
|
|
bitfld.long 0x00 23. "DXREFESELRANGE,External VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFESEL,Byte Lane External VREF Select"
|
|
bitfld.long 0x00 15. "DXREFSSELRANGE,Single ended VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFSSEL,Byte Lane Single-End VREF Select"
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--5. "DXREFIEN,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "DXREFIMON,VRMON control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3"
|
|
rgroup.long 0xB14++0x03
|
|
line.long 0x00 "DX4GCR5,DATX8 n General Configuration Register 5"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "DXREFISELR3,Byte Lane internal VREF Select for Rank 3"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFISELR2,Byte Lane internal VREF Select for Rank 2"
|
|
newline
|
|
bitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFISELR1,Byte Lane internal VREF Select for Rank 1"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DXREFISELR0,Byte Lane internal VREF Select for Rank 0"
|
|
rgroup.long 0xB18++0x03
|
|
line.long 0x00 "DX4GCR6,DATX8 n General Configuration Register 6"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DXDQVREFR3,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DXDQVREFR2,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DXDQVREFR1,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DXDQVREFR0,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xB1C++0x03
|
|
line.long 0x00 "DX4GCR7,DATX8 n General Configuration Register 7"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED_31_19,Reserved"
|
|
bitfld.long 0x00 18. "RESERVED_18,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--17. 1. "RESERVED_17_10,Reserved"
|
|
bitfld.long 0x00 9. "DCALTYPE,DDL Calibration Type" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "DCALSVAL,DDL Calibration Starting Value"
|
|
repeat 2. (strings "8" "9" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xB20)++0x03
|
|
line.long 0x00 "DX4GCR$1,DATX8 n General Configuration Register $1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "RESERVED_29_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
rgroup.long 0xB28++0x03
|
|
line.long 0x00 "DX4DQMAP0,DATX8 n DQ/DM Mapping Register 0"
|
|
bitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED_30_20,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DQ4MAP,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "DQ3MAP,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DQ2MAP,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "DQ1MAP,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DQ0MAP,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB2C++0x03
|
|
line.long 0x00 "DX4DQMAP1,DATX8 n DQ/DM Mapping Register 1"
|
|
bitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "RESERVED_30_16,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DMMAP,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "DQ7MAP,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQ6MAP,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQ5MAP,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "DX4BDLR0,DATX8 n Bit Delay Line Register 0"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3WBD,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2WBD,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1WBD,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0WBD,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xB44++0x03
|
|
line.long 0x00 "DX4BDLR1,DATX8 n Bit Delay Line Register 1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7WBD,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6WBD,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5WBD,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4WBD,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "DX4BDLR2,DATX8 n Bit Delay Line Register 2"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DSNWBD,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DSOEBD,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DSWBD,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DMWBD,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "DX4BDLR3,DATX8 n Bit Delay Line Register 3"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3RBD,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2RBD,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1RBD,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0RBD,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xB54++0x03
|
|
line.long 0x00 "DX4BDLR4,DATX8 n Bit Delay Line Register 4"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7RBD,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6RBD,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5RBD,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4RBD,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "DX4BDLR5,DATX8 n Bit Delay Line Register 5"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED_31_6,Reserved"
|
|
bitfld.long 0x00 0.--5. "DMRBD,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "DX4BDLR6,DATX8 n Bit Delay Line Register 6"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "TERBD,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "PDRBD,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED_7_0,Reserved"
|
|
repeat 3. (strings "7" "8" "9" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xB64)++0x03
|
|
line.long 0x00 "DX4BDLR$1,DATX8 n Bit Delay Line Register $1"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
rgroup.long 0xB80++0x03
|
|
line.long 0x00 "DX4LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WLD,Write Leveling Delay"
|
|
rgroup.long 0xB84++0x03
|
|
line.long 0x00 "DX4LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WDQD,Write Data Delay"
|
|
rgroup.long 0xB88++0x03
|
|
line.long 0x00 "DX4LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGD,Read DQS Gating Delay"
|
|
rgroup.long 0xB8C++0x03
|
|
line.long 0x00 "DX4LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSD,Read DQS Delay"
|
|
rgroup.long 0xB90++0x03
|
|
line.long 0x00 "DX4LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSND,Read DQSN Delay"
|
|
rgroup.long 0xB94++0x03
|
|
line.long 0x00 "DX4LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGSD,DQS Gating Status Delay"
|
|
rgroup.long 0xBA0++0x03
|
|
line.long 0x00 "DX4MDLR0,DATX8 n Master Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "TPRD,Target Period"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "IPRD,Initial Period"
|
|
rgroup.long 0xBA4++0x03
|
|
line.long 0x00 "DX4MDLR1,DATX8 n Master Delay Line Register 1"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED_31_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "MDLD,MDL Delay"
|
|
rgroup.long 0xBC0++0x03
|
|
line.long 0x00 "DX4GTR0,DATX8 n General Timing Register 0"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "WDQSL,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WLSL,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "RESERVED_12_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "DGSL,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xBD0++0x03
|
|
line.long 0x00 "DX4RSR0,DATX8 n Rank Status Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "QSGERR,DQS Gate Training Error"
|
|
rgroup.long 0xBD4++0x03
|
|
line.long 0x00 "DX4RSR1,DATX8 n Rank Status Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVLERR,Read Leveling Error"
|
|
rgroup.long 0xBD8++0x03
|
|
line.long 0x00 "DX4RSR2,DATX8 n Rank Status Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAWN,Write Latency Adjustment (DQS off on some DQ lines) Warning"
|
|
rgroup.long 0xBDC++0x03
|
|
line.long 0x00 "DX4RSR3,DATX8 n Rank Status Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAERR,Write Leveling Adjustment Error"
|
|
rgroup.long 0xBE0++0x03
|
|
line.long 0x00 "DX4GSR0,DATX8 n General Status Register 0"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "WLDQ,Write Leveling DQ Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--29. "RESERVED_29_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 17.--25. 1. "GDQSPRD,Read DQS gating Period"
|
|
newline
|
|
bitfld.long 0x00 16. "DPLOCK,DATX8 PLL Lock" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "WLPRD,Write Leveling Period"
|
|
newline
|
|
bitfld.long 0x00 6. "WLERR,Write Leveling Error" "0,1"
|
|
bitfld.long 0x00 5. "WLDONE,Write Leveling Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "WLCAL,Write Leveling Calibration" "0,1"
|
|
bitfld.long 0x00 3. "GDQSCAL,Read DQS gating Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RDQSNCAL,Read DQS# Calibration" "0,1"
|
|
bitfld.long 0x00 1. "RDQSCAL,Read DQS Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDQCAL,Write DQ Calibration" "0,1"
|
|
rgroup.long 0xBE4++0x03
|
|
line.long 0x00 "DX4GSR1,DATX8 n General Status Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.tbyte 0x00 1.--24. 1. "DLTCODE,Delay Line Test Code"
|
|
newline
|
|
bitfld.long 0x00 0. "DLTDONE,Delay Line Test Done" "0,1"
|
|
rgroup.long 0xBE8++0x03
|
|
line.long 0x00 "DX4GSR2,DATX8 n General Status Register 2"
|
|
hexmask.long.word 0x00 23.--31. 1. "GSDQSPRD,Read DQS gating Status Period"
|
|
bitfld.long 0x00 22. "GSDQSCAL,Read DQS Gating Status Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "SRDERR,Static Read Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "DQS2DQERR,Write DQS2DQ Training Error"
|
|
bitfld.long 0x00 8.--11. "ESTAT,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "WEWN,Write Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 6. "WEERR,Write Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "REWN,Read Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 4. "REERR,Read Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "WDWN,Write Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 2. "WDERR,Write Bit Deskew Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RDWN,Read Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 0. "RDERR,Read Bit Deskew Error" "0,1"
|
|
rgroup.long 0xBEC++0x03
|
|
line.long 0x00 "DX4GSR3,DATX8 n General Status Register 3"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "ESTAT,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DVWRN,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "DVERR,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HVWRN,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HVERR,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "RESERVED_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. "SRDPC,Static Read Delay Pass Count" "0,1,2,3"
|
|
rgroup.long 0xBF0++0x03
|
|
line.long 0x00 "DX4GSR4,DATX8 n General Status Register 4"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 17.--25. 1. "RESERVED_25_17,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "RESERVED_16,Reserved" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "RESERVED_15_7,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0xBF4++0x03
|
|
line.long 0x00 "DX4GSR5,DATX8 n General Status Register 5"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED_31_23,Reserved"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "RESERVED_20,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "RESERVED_19_12,Reserved"
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0xBF8++0x03
|
|
line.long 0x00 "DX4GSR6,DATX8 n General Status Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "RESERVED_19_15,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "RESERVED_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
rgroup.long 0xC00++0x03
|
|
line.long 0x00 "DX5GCR0,DATX8 n General Configuration Register 0"
|
|
bitfld.long 0x00 31. "CALBYP,Calibration Bypass" "0,1"
|
|
bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "CODTSHFT,Configurable ODT(TE) Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DQSDCC,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RDDLY,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--19. "RESERVED_19_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 13. "DQSNSEPDR,DQSNSE Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 12. "DQSSEPDR,DQSSE Power Down Receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RTTOAL,RTT On Additive Latency" "0,1"
|
|
bitfld.long 0x00 9.--10. "RTTOH,RTT Output Hold" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "CPDRSHFT,Configurable PDR Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 6. "DQSRPD,DQSR Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DQSGPDR,DQSG Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DQSGODT,DQSG On-Die Termination" "0,1"
|
|
bitfld.long 0x00 2. "DQSGOE,DQSG Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
rgroup.long 0xC04++0x03
|
|
line.long 0x00 "DX5GCR1,DATX8 n General Configuration Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXPDRMODE,Enables the PDR mode for DQ[7:0]"
|
|
bitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "QSNSEL,Select the delayed or non-delayed read data strobe #" "0,1"
|
|
bitfld.long 0x00 13. "QSSEL,Select the delayed or non-delayed read data strobe" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "OEEN,Enables Read Data Strobe in a byte lane" "0,1"
|
|
bitfld.long 0x00 11. "PDREN,Enables PDR in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TEEN,Enables ODT/TE in a byte lane" "0,1"
|
|
bitfld.long 0x00 9. "DSEN,Enables Write Data strobe in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DMEN,Enables DM pin in a byte lane" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DQEN,Enables DQ corresponding to each bit in a byte"
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "DX5GCR2,DATX8 n General Configuration Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXOEMODE,Enables the OE mode values for DQ[7:0]"
|
|
hexmask.long.word 0x00 0.--15. 1. "DXTEMODE,Enables the TE (ODT) mode values for DQ[7:0]"
|
|
rgroup.long 0xC0C++0x03
|
|
line.long 0x00 "DX5GCR3,DATX8 n General Configuration Register 3"
|
|
bitfld.long 0x00 31. "OEBVT,Output Enable BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 30. "TEBVT,Termination Enable BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RDBVT,Read Data BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 28. "WDBVT,Write Data BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "RGLVT,Read DQS Gating LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 26. "RDLVT,Read DQS LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "WDLVT,Write DQ LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 24. "WLLVT,Write Leveling LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RGSLVT,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 22. "PDRBVT,Power Down Receiver BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DSNOEMODE,Enables the OE mode for DQs" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "DSNTEMODE,Enables the TE mode for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "DSNPDRMODE,Enables the PDR mode for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "DMOEMODE,Enables the OE mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "DMTEMODE,Enables the TE mode values for DM" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "DMPDRMODE,Enables the PDR mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "RESERVED_9,Reserved" "0,1"
|
|
bitfld.long 0x00 8. "WDSBVT,Write Data Strobe BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "DSOEMODE,Enables the OE mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "DSTEMODE,Enables the TE mode values for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "DSPDRMODE,Enables the PDR mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 1. "RDMBVT,Read Data Mask BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDMBVT,Write Data Mask BDL VT Compensation" "0,1"
|
|
rgroup.long 0xC10++0x03
|
|
line.long 0x00 "DX5GCR4,DATX8 n General Configuration Register 4"
|
|
bitfld.long 0x00 29.--31. "RESERVED_31_29,Byte lane VREF IOM (Used only by D4MU IOs)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "DXREFPEN,Byte Lane VREF Pad Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "DXREFEEN,Byte Lane Internal VREF Enable" "0,1,2,3"
|
|
bitfld.long 0x00 25. "DXREFSEN,Byte Lane Single-End VREF Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RESERVED_24,Reserved" "0,1"
|
|
bitfld.long 0x00 23. "DXREFESELRANGE,External VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFESEL,Byte Lane External VREF Select"
|
|
bitfld.long 0x00 15. "DXREFSSELRANGE,Single ended VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFSSEL,Byte Lane Single-End VREF Select"
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--5. "DXREFIEN,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "DXREFIMON,VRMON control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3"
|
|
rgroup.long 0xC14++0x03
|
|
line.long 0x00 "DX5GCR5,DATX8 n General Configuration Register 5"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "DXREFISELR3,Byte Lane internal VREF Select for Rank 3"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFISELR2,Byte Lane internal VREF Select for Rank 2"
|
|
newline
|
|
bitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFISELR1,Byte Lane internal VREF Select for Rank 1"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DXREFISELR0,Byte Lane internal VREF Select for Rank 0"
|
|
rgroup.long 0xC18++0x03
|
|
line.long 0x00 "DX5GCR6,DATX8 n General Configuration Register 6"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DXDQVREFR3,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DXDQVREFR2,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DXDQVREFR1,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DXDQVREFR0,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xC1C++0x03
|
|
line.long 0x00 "DX5GCR7,DATX8 n General Configuration Register 7"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED_31_19,Reserved"
|
|
bitfld.long 0x00 18. "RESERVED_18,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--17. 1. "RESERVED_17_10,Reserved"
|
|
bitfld.long 0x00 9. "DCALTYPE,DDL Calibration Type" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "DCALSVAL,DDL Calibration Starting Value"
|
|
repeat 2. (strings "8" "9" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xC20)++0x03
|
|
line.long 0x00 "DX5GCR$1,DATX8 n General Configuration Register $1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "RESERVED_29_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
rgroup.long 0xC28++0x03
|
|
line.long 0x00 "DX5DQMAP0,DATX8 n DQ/DM Mapping Register 0"
|
|
bitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED_30_20,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DQ4MAP,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "DQ3MAP,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DQ2MAP,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "DQ1MAP,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DQ0MAP,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xC2C++0x03
|
|
line.long 0x00 "DX5DQMAP1,DATX8 n DQ/DM Mapping Register 1"
|
|
bitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "RESERVED_30_16,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DMMAP,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "DQ7MAP,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQ6MAP,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQ5MAP,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xC40++0x03
|
|
line.long 0x00 "DX5BDLR0,DATX8 n Bit Delay Line Register 0"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3WBD,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2WBD,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1WBD,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0WBD,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xC44++0x03
|
|
line.long 0x00 "DX5BDLR1,DATX8 n Bit Delay Line Register 1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7WBD,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6WBD,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5WBD,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4WBD,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xC48++0x03
|
|
line.long 0x00 "DX5BDLR2,DATX8 n Bit Delay Line Register 2"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DSNWBD,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DSOEBD,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DSWBD,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DMWBD,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xC50++0x03
|
|
line.long 0x00 "DX5BDLR3,DATX8 n Bit Delay Line Register 3"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3RBD,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2RBD,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1RBD,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0RBD,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xC54++0x03
|
|
line.long 0x00 "DX5BDLR4,DATX8 n Bit Delay Line Register 4"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7RBD,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6RBD,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5RBD,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4RBD,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xC58++0x03
|
|
line.long 0x00 "DX5BDLR5,DATX8 n Bit Delay Line Register 5"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED_31_6,Reserved"
|
|
bitfld.long 0x00 0.--5. "DMRBD,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xC60++0x03
|
|
line.long 0x00 "DX5BDLR6,DATX8 n Bit Delay Line Register 6"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "TERBD,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "PDRBD,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED_7_0,Reserved"
|
|
repeat 3. (strings "7" "8" "9" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xC64)++0x03
|
|
line.long 0x00 "DX5BDLR$1,DATX8 n Bit Delay Line Register $1"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
rgroup.long 0xC80++0x03
|
|
line.long 0x00 "DX5LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WLD,Write Leveling Delay"
|
|
rgroup.long 0xC84++0x03
|
|
line.long 0x00 "DX5LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WDQD,Write Data Delay"
|
|
rgroup.long 0xC88++0x03
|
|
line.long 0x00 "DX5LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGD,Read DQS Gating Delay"
|
|
rgroup.long 0xC8C++0x03
|
|
line.long 0x00 "DX5LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSD,Read DQS Delay"
|
|
rgroup.long 0xC90++0x03
|
|
line.long 0x00 "DX5LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSND,Read DQSN Delay"
|
|
rgroup.long 0xC94++0x03
|
|
line.long 0x00 "DX5LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGSD,DQS Gating Status Delay"
|
|
rgroup.long 0xCA0++0x03
|
|
line.long 0x00 "DX5MDLR0,DATX8 n Master Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "TPRD,Target Period"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "IPRD,Initial Period"
|
|
rgroup.long 0xCA4++0x03
|
|
line.long 0x00 "DX5MDLR1,DATX8 n Master Delay Line Register 1"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED_31_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "MDLD,MDL Delay"
|
|
rgroup.long 0xCC0++0x03
|
|
line.long 0x00 "DX5GTR0,DATX8 n General Timing Register 0"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "WDQSL,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WLSL,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "RESERVED_12_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "DGSL,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xCD0++0x03
|
|
line.long 0x00 "DX5RSR0,DATX8 n Rank Status Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "QSGERR,DQS Gate Training Error"
|
|
rgroup.long 0xCD4++0x03
|
|
line.long 0x00 "DX5RSR1,DATX8 n Rank Status Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVLERR,Read Leveling Error"
|
|
rgroup.long 0xCD8++0x03
|
|
line.long 0x00 "DX5RSR2,DATX8 n Rank Status Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAWN,Write Latency Adjustment (DQS off on some DQ lines) Warning"
|
|
rgroup.long 0xCDC++0x03
|
|
line.long 0x00 "DX5RSR3,DATX8 n Rank Status Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAERR,Write Leveling Adjustment Error"
|
|
rgroup.long 0xCE0++0x03
|
|
line.long 0x00 "DX5GSR0,DATX8 n General Status Register 0"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "WLDQ,Write Leveling DQ Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--29. "RESERVED_29_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 17.--25. 1. "GDQSPRD,Read DQS gating Period"
|
|
newline
|
|
bitfld.long 0x00 16. "DPLOCK,DATX8 PLL Lock" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "WLPRD,Write Leveling Period"
|
|
newline
|
|
bitfld.long 0x00 6. "WLERR,Write Leveling Error" "0,1"
|
|
bitfld.long 0x00 5. "WLDONE,Write Leveling Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "WLCAL,Write Leveling Calibration" "0,1"
|
|
bitfld.long 0x00 3. "GDQSCAL,Read DQS gating Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RDQSNCAL,Read DQS# Calibration" "0,1"
|
|
bitfld.long 0x00 1. "RDQSCAL,Read DQS Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDQCAL,Write DQ Calibration" "0,1"
|
|
rgroup.long 0xCE4++0x03
|
|
line.long 0x00 "DX5GSR1,DATX8 n General Status Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.tbyte 0x00 1.--24. 1. "DLTCODE,Delay Line Test Code"
|
|
newline
|
|
bitfld.long 0x00 0. "DLTDONE,Delay Line Test Done" "0,1"
|
|
rgroup.long 0xCE8++0x03
|
|
line.long 0x00 "DX5GSR2,DATX8 n General Status Register 2"
|
|
hexmask.long.word 0x00 23.--31. 1. "GSDQSPRD,Read DQS gating Status Period"
|
|
bitfld.long 0x00 22. "GSDQSCAL,Read DQS Gating Status Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "SRDERR,Static Read Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "DQS2DQERR,Write DQS2DQ Training Error"
|
|
bitfld.long 0x00 8.--11. "ESTAT,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "WEWN,Write Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 6. "WEERR,Write Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "REWN,Read Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 4. "REERR,Read Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "WDWN,Write Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 2. "WDERR,Write Bit Deskew Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RDWN,Read Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 0. "RDERR,Read Bit Deskew Error" "0,1"
|
|
rgroup.long 0xCEC++0x03
|
|
line.long 0x00 "DX5GSR3,DATX8 n General Status Register 3"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "ESTAT,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DVWRN,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "DVERR,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HVWRN,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HVERR,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "RESERVED_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. "SRDPC,Static Read Delay Pass Count" "0,1,2,3"
|
|
rgroup.long 0xCF0++0x03
|
|
line.long 0x00 "DX5GSR4,DATX8 n General Status Register 4"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 17.--25. 1. "RESERVED_25_17,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "RESERVED_16,Reserved" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "RESERVED_15_7,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0xCF4++0x03
|
|
line.long 0x00 "DX5GSR5,DATX8 n General Status Register 5"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED_31_23,Reserved"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "RESERVED_20,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "RESERVED_19_12,Reserved"
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0xCF8++0x03
|
|
line.long 0x00 "DX5GSR6,DATX8 n General Status Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "RESERVED_19_15,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "RESERVED_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "DX6GCR0,DATX8 n General Configuration Register 0"
|
|
bitfld.long 0x00 31. "CALBYP,Calibration Bypass" "0,1"
|
|
bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "CODTSHFT,Configurable ODT(TE) Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DQSDCC,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RDDLY,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--19. "RESERVED_19_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 13. "DQSNSEPDR,DQSNSE Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 12. "DQSSEPDR,DQSSE Power Down Receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RTTOAL,RTT On Additive Latency" "0,1"
|
|
bitfld.long 0x00 9.--10. "RTTOH,RTT Output Hold" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "CPDRSHFT,Configurable PDR Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 6. "DQSRPD,DQSR Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DQSGPDR,DQSG Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DQSGODT,DQSG On-Die Termination" "0,1"
|
|
bitfld.long 0x00 2. "DQSGOE,DQSG Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
rgroup.long 0xD04++0x03
|
|
line.long 0x00 "DX6GCR1,DATX8 n General Configuration Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXPDRMODE,Enables the PDR mode for DQ[7:0]"
|
|
bitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "QSNSEL,Select the delayed or non-delayed read data strobe #" "0,1"
|
|
bitfld.long 0x00 13. "QSSEL,Select the delayed or non-delayed read data strobe" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "OEEN,Enables Read Data Strobe in a byte lane" "0,1"
|
|
bitfld.long 0x00 11. "PDREN,Enables PDR in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TEEN,Enables ODT/TE in a byte lane" "0,1"
|
|
bitfld.long 0x00 9. "DSEN,Enables Write Data strobe in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DMEN,Enables DM pin in a byte lane" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DQEN,Enables DQ corresponding to each bit in a byte"
|
|
rgroup.long 0xD08++0x03
|
|
line.long 0x00 "DX6GCR2,DATX8 n General Configuration Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXOEMODE,Enables the OE mode values for DQ[7:0]"
|
|
hexmask.long.word 0x00 0.--15. 1. "DXTEMODE,Enables the TE (ODT) mode values for DQ[7:0]"
|
|
rgroup.long 0xD0C++0x03
|
|
line.long 0x00 "DX6GCR3,DATX8 n General Configuration Register 3"
|
|
bitfld.long 0x00 31. "OEBVT,Output Enable BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 30. "TEBVT,Termination Enable BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RDBVT,Read Data BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 28. "WDBVT,Write Data BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "RGLVT,Read DQS Gating LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 26. "RDLVT,Read DQS LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "WDLVT,Write DQ LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 24. "WLLVT,Write Leveling LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RGSLVT,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 22. "PDRBVT,Power Down Receiver BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DSNOEMODE,Enables the OE mode for DQs" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "DSNTEMODE,Enables the TE mode for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "DSNPDRMODE,Enables the PDR mode for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "DMOEMODE,Enables the OE mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "DMTEMODE,Enables the TE mode values for DM" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "DMPDRMODE,Enables the PDR mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "RESERVED_9,Reserved" "0,1"
|
|
bitfld.long 0x00 8. "WDSBVT,Write Data Strobe BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "DSOEMODE,Enables the OE mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "DSTEMODE,Enables the TE mode values for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "DSPDRMODE,Enables the PDR mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 1. "RDMBVT,Read Data Mask BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDMBVT,Write Data Mask BDL VT Compensation" "0,1"
|
|
rgroup.long 0xD10++0x03
|
|
line.long 0x00 "DX6GCR4,DATX8 n General Configuration Register 4"
|
|
bitfld.long 0x00 29.--31. "RESERVED_31_29,Byte lane VREF IOM (Used only by D4MU IOs)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "DXREFPEN,Byte Lane VREF Pad Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "DXREFEEN,Byte Lane Internal VREF Enable" "0,1,2,3"
|
|
bitfld.long 0x00 25. "DXREFSEN,Byte Lane Single-End VREF Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RESERVED_24,Reserved" "0,1"
|
|
bitfld.long 0x00 23. "DXREFESELRANGE,External VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFESEL,Byte Lane External VREF Select"
|
|
bitfld.long 0x00 15. "DXREFSSELRANGE,Single ended VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFSSEL,Byte Lane Single-End VREF Select"
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--5. "DXREFIEN,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "DXREFIMON,VRMON control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3"
|
|
rgroup.long 0xD14++0x03
|
|
line.long 0x00 "DX6GCR5,DATX8 n General Configuration Register 5"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "DXREFISELR3,Byte Lane internal VREF Select for Rank 3"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFISELR2,Byte Lane internal VREF Select for Rank 2"
|
|
newline
|
|
bitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFISELR1,Byte Lane internal VREF Select for Rank 1"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DXREFISELR0,Byte Lane internal VREF Select for Rank 0"
|
|
rgroup.long 0xD18++0x03
|
|
line.long 0x00 "DX6GCR6,DATX8 n General Configuration Register 6"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DXDQVREFR3,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DXDQVREFR2,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DXDQVREFR1,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DXDQVREFR0,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xD1C++0x03
|
|
line.long 0x00 "DX6GCR7,DATX8 n General Configuration Register 7"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED_31_19,Reserved"
|
|
bitfld.long 0x00 18. "RESERVED_18,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--17. 1. "RESERVED_17_10,Reserved"
|
|
bitfld.long 0x00 9. "DCALTYPE,DDL Calibration Type" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "DCALSVAL,DDL Calibration Starting Value"
|
|
repeat 2. (strings "8" "9" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xD20)++0x03
|
|
line.long 0x00 "DX6GCR$1,DATX8 n General Configuration Register $1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "RESERVED_29_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
rgroup.long 0xD28++0x03
|
|
line.long 0x00 "DX6DQMAP0,DATX8 n DQ/DM Mapping Register 0"
|
|
bitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED_30_20,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DQ4MAP,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "DQ3MAP,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DQ2MAP,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "DQ1MAP,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DQ0MAP,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xD2C++0x03
|
|
line.long 0x00 "DX6DQMAP1,DATX8 n DQ/DM Mapping Register 1"
|
|
bitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "RESERVED_30_16,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DMMAP,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "DQ7MAP,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQ6MAP,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQ5MAP,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xD40++0x03
|
|
line.long 0x00 "DX6BDLR0,DATX8 n Bit Delay Line Register 0"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3WBD,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2WBD,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1WBD,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0WBD,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xD44++0x03
|
|
line.long 0x00 "DX6BDLR1,DATX8 n Bit Delay Line Register 1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7WBD,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6WBD,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5WBD,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4WBD,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xD48++0x03
|
|
line.long 0x00 "DX6BDLR2,DATX8 n Bit Delay Line Register 2"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DSNWBD,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DSOEBD,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DSWBD,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DMWBD,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "DX6BDLR3,DATX8 n Bit Delay Line Register 3"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3RBD,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2RBD,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1RBD,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0RBD,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xD54++0x03
|
|
line.long 0x00 "DX6BDLR4,DATX8 n Bit Delay Line Register 4"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7RBD,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6RBD,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5RBD,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4RBD,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "DX6BDLR5,DATX8 n Bit Delay Line Register 5"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED_31_6,Reserved"
|
|
bitfld.long 0x00 0.--5. "DMRBD,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xD60++0x03
|
|
line.long 0x00 "DX6BDLR6,DATX8 n Bit Delay Line Register 6"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "TERBD,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "PDRBD,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED_7_0,Reserved"
|
|
repeat 3. (strings "7" "8" "9" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xD64)++0x03
|
|
line.long 0x00 "DX6BDLR$1,DATX8 n Bit Delay Line Register $1"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
rgroup.long 0xD80++0x03
|
|
line.long 0x00 "DX6LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WLD,Write Leveling Delay"
|
|
rgroup.long 0xD84++0x03
|
|
line.long 0x00 "DX6LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WDQD,Write Data Delay"
|
|
rgroup.long 0xD88++0x03
|
|
line.long 0x00 "DX6LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGD,Read DQS Gating Delay"
|
|
rgroup.long 0xD8C++0x03
|
|
line.long 0x00 "DX6LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSD,Read DQS Delay"
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "DX6LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSND,Read DQSN Delay"
|
|
rgroup.long 0xD94++0x03
|
|
line.long 0x00 "DX6LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGSD,DQS Gating Status Delay"
|
|
rgroup.long 0xDA0++0x03
|
|
line.long 0x00 "DX6MDLR0,DATX8 n Master Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "TPRD,Target Period"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "IPRD,Initial Period"
|
|
rgroup.long 0xDA4++0x03
|
|
line.long 0x00 "DX6MDLR1,DATX8 n Master Delay Line Register 1"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED_31_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "MDLD,MDL Delay"
|
|
rgroup.long 0xDC0++0x03
|
|
line.long 0x00 "DX6GTR0,DATX8 n General Timing Register 0"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "WDQSL,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WLSL,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "RESERVED_12_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "DGSL,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xDD0++0x03
|
|
line.long 0x00 "DX6RSR0,DATX8 n Rank Status Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "QSGERR,DQS Gate Training Error"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "DX6RSR1,DATX8 n Rank Status Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVLERR,Read Leveling Error"
|
|
rgroup.long 0xDD8++0x03
|
|
line.long 0x00 "DX6RSR2,DATX8 n Rank Status Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAWN,Write Latency Adjustment (DQS off on some DQ lines) Warning"
|
|
rgroup.long 0xDDC++0x03
|
|
line.long 0x00 "DX6RSR3,DATX8 n Rank Status Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAERR,Write Leveling Adjustment Error"
|
|
rgroup.long 0xDE0++0x03
|
|
line.long 0x00 "DX6GSR0,DATX8 n General Status Register 0"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "WLDQ,Write Leveling DQ Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--29. "RESERVED_29_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 17.--25. 1. "GDQSPRD,Read DQS gating Period"
|
|
newline
|
|
bitfld.long 0x00 16. "DPLOCK,DATX8 PLL Lock" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "WLPRD,Write Leveling Period"
|
|
newline
|
|
bitfld.long 0x00 6. "WLERR,Write Leveling Error" "0,1"
|
|
bitfld.long 0x00 5. "WLDONE,Write Leveling Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "WLCAL,Write Leveling Calibration" "0,1"
|
|
bitfld.long 0x00 3. "GDQSCAL,Read DQS gating Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RDQSNCAL,Read DQS# Calibration" "0,1"
|
|
bitfld.long 0x00 1. "RDQSCAL,Read DQS Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDQCAL,Write DQ Calibration" "0,1"
|
|
rgroup.long 0xDE4++0x03
|
|
line.long 0x00 "DX6GSR1,DATX8 n General Status Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.tbyte 0x00 1.--24. 1. "DLTCODE,Delay Line Test Code"
|
|
newline
|
|
bitfld.long 0x00 0. "DLTDONE,Delay Line Test Done" "0,1"
|
|
rgroup.long 0xDE8++0x03
|
|
line.long 0x00 "DX6GSR2,DATX8 n General Status Register 2"
|
|
hexmask.long.word 0x00 23.--31. 1. "GSDQSPRD,Read DQS gating Status Period"
|
|
bitfld.long 0x00 22. "GSDQSCAL,Read DQS Gating Status Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "SRDERR,Static Read Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "DQS2DQERR,Write DQS2DQ Training Error"
|
|
bitfld.long 0x00 8.--11. "ESTAT,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "WEWN,Write Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 6. "WEERR,Write Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "REWN,Read Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 4. "REERR,Read Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "WDWN,Write Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 2. "WDERR,Write Bit Deskew Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RDWN,Read Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 0. "RDERR,Read Bit Deskew Error" "0,1"
|
|
rgroup.long 0xDEC++0x03
|
|
line.long 0x00 "DX6GSR3,DATX8 n General Status Register 3"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "ESTAT,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DVWRN,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "DVERR,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HVWRN,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HVERR,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "RESERVED_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. "SRDPC,Static Read Delay Pass Count" "0,1,2,3"
|
|
rgroup.long 0xDF0++0x03
|
|
line.long 0x00 "DX6GSR4,DATX8 n General Status Register 4"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 17.--25. 1. "RESERVED_25_17,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "RESERVED_16,Reserved" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "RESERVED_15_7,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DX6GSR5,DATX8 n General Status Register 5"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED_31_23,Reserved"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "RESERVED_20,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "RESERVED_19_12,Reserved"
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0xDF8++0x03
|
|
line.long 0x00 "DX6GSR6,DATX8 n General Status Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "RESERVED_19_15,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "RESERVED_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "DX7GCR0,DATX8 n General Configuration Register 0"
|
|
bitfld.long 0x00 31. "CALBYP,Calibration Bypass" "0,1"
|
|
bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "CODTSHFT,Configurable ODT(TE) Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DQSDCC,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RDDLY,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--19. "RESERVED_19_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 13. "DQSNSEPDR,DQSNSE Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 12. "DQSSEPDR,DQSSE Power Down Receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RTTOAL,RTT On Additive Latency" "0,1"
|
|
bitfld.long 0x00 9.--10. "RTTOH,RTT Output Hold" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "CPDRSHFT,Configurable PDR Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 6. "DQSRPD,DQSR Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DQSGPDR,DQSG Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DQSGODT,DQSG On-Die Termination" "0,1"
|
|
bitfld.long 0x00 2. "DQSGOE,DQSG Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
rgroup.long 0xE04++0x03
|
|
line.long 0x00 "DX7GCR1,DATX8 n General Configuration Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXPDRMODE,Enables the PDR mode for DQ[7:0]"
|
|
bitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "QSNSEL,Select the delayed or non-delayed read data strobe #" "0,1"
|
|
bitfld.long 0x00 13. "QSSEL,Select the delayed or non-delayed read data strobe" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "OEEN,Enables Read Data Strobe in a byte lane" "0,1"
|
|
bitfld.long 0x00 11. "PDREN,Enables PDR in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TEEN,Enables ODT/TE in a byte lane" "0,1"
|
|
bitfld.long 0x00 9. "DSEN,Enables Write Data strobe in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DMEN,Enables DM pin in a byte lane" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DQEN,Enables DQ corresponding to each bit in a byte"
|
|
rgroup.long 0xE08++0x03
|
|
line.long 0x00 "DX7GCR2,DATX8 n General Configuration Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXOEMODE,Enables the OE mode values for DQ[7:0]"
|
|
hexmask.long.word 0x00 0.--15. 1. "DXTEMODE,Enables the TE (ODT) mode values for DQ[7:0]"
|
|
rgroup.long 0xE0C++0x03
|
|
line.long 0x00 "DX7GCR3,DATX8 n General Configuration Register 3"
|
|
bitfld.long 0x00 31. "OEBVT,Output Enable BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 30. "TEBVT,Termination Enable BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RDBVT,Read Data BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 28. "WDBVT,Write Data BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "RGLVT,Read DQS Gating LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 26. "RDLVT,Read DQS LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "WDLVT,Write DQ LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 24. "WLLVT,Write Leveling LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RGSLVT,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 22. "PDRBVT,Power Down Receiver BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DSNOEMODE,Enables the OE mode for DQs" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "DSNTEMODE,Enables the TE mode for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "DSNPDRMODE,Enables the PDR mode for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "DMOEMODE,Enables the OE mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "DMTEMODE,Enables the TE mode values for DM" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "DMPDRMODE,Enables the PDR mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "RESERVED_9,Reserved" "0,1"
|
|
bitfld.long 0x00 8. "WDSBVT,Write Data Strobe BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "DSOEMODE,Enables the OE mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "DSTEMODE,Enables the TE mode values for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "DSPDRMODE,Enables the PDR mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 1. "RDMBVT,Read Data Mask BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDMBVT,Write Data Mask BDL VT Compensation" "0,1"
|
|
rgroup.long 0xE10++0x03
|
|
line.long 0x00 "DX7GCR4,DATX8 n General Configuration Register 4"
|
|
bitfld.long 0x00 29.--31. "RESERVED_31_29,Byte lane VREF IOM (Used only by D4MU IOs)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "DXREFPEN,Byte Lane VREF Pad Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "DXREFEEN,Byte Lane Internal VREF Enable" "0,1,2,3"
|
|
bitfld.long 0x00 25. "DXREFSEN,Byte Lane Single-End VREF Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RESERVED_24,Reserved" "0,1"
|
|
bitfld.long 0x00 23. "DXREFESELRANGE,External VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFESEL,Byte Lane External VREF Select"
|
|
bitfld.long 0x00 15. "DXREFSSELRANGE,Single ended VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFSSEL,Byte Lane Single-End VREF Select"
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--5. "DXREFIEN,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "DXREFIMON,VRMON control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3"
|
|
rgroup.long 0xE14++0x03
|
|
line.long 0x00 "DX7GCR5,DATX8 n General Configuration Register 5"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "DXREFISELR3,Byte Lane internal VREF Select for Rank 3"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFISELR2,Byte Lane internal VREF Select for Rank 2"
|
|
newline
|
|
bitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFISELR1,Byte Lane internal VREF Select for Rank 1"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DXREFISELR0,Byte Lane internal VREF Select for Rank 0"
|
|
rgroup.long 0xE18++0x03
|
|
line.long 0x00 "DX7GCR6,DATX8 n General Configuration Register 6"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DXDQVREFR3,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DXDQVREFR2,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DXDQVREFR1,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DXDQVREFR0,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xE1C++0x03
|
|
line.long 0x00 "DX7GCR7,DATX8 n General Configuration Register 7"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED_31_19,Reserved"
|
|
bitfld.long 0x00 18. "RESERVED_18,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--17. 1. "RESERVED_17_10,Reserved"
|
|
bitfld.long 0x00 9. "DCALTYPE,DDL Calibration Type" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "DCALSVAL,DDL Calibration Starting Value"
|
|
repeat 2. (strings "8" "9" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xE20)++0x03
|
|
line.long 0x00 "DX7GCR$1,DATX8 n General Configuration Register $1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "RESERVED_29_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
rgroup.long 0xE28++0x03
|
|
line.long 0x00 "DX7DQMAP0,DATX8 n DQ/DM Mapping Register 0"
|
|
bitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED_30_20,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DQ4MAP,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "DQ3MAP,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DQ2MAP,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "DQ1MAP,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DQ0MAP,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xE2C++0x03
|
|
line.long 0x00 "DX7DQMAP1,DATX8 n DQ/DM Mapping Register 1"
|
|
bitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "RESERVED_30_16,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DMMAP,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "DQ7MAP,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQ6MAP,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQ5MAP,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xE40++0x03
|
|
line.long 0x00 "DX7BDLR0,DATX8 n Bit Delay Line Register 0"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3WBD,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2WBD,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1WBD,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0WBD,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xE44++0x03
|
|
line.long 0x00 "DX7BDLR1,DATX8 n Bit Delay Line Register 1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7WBD,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6WBD,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5WBD,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4WBD,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xE48++0x03
|
|
line.long 0x00 "DX7BDLR2,DATX8 n Bit Delay Line Register 2"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DSNWBD,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DSOEBD,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DSWBD,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DMWBD,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xE50++0x03
|
|
line.long 0x00 "DX7BDLR3,DATX8 n Bit Delay Line Register 3"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3RBD,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2RBD,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1RBD,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0RBD,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xE54++0x03
|
|
line.long 0x00 "DX7BDLR4,DATX8 n Bit Delay Line Register 4"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7RBD,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6RBD,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5RBD,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4RBD,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xE58++0x03
|
|
line.long 0x00 "DX7BDLR5,DATX8 n Bit Delay Line Register 5"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED_31_6,Reserved"
|
|
bitfld.long 0x00 0.--5. "DMRBD,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xE60++0x03
|
|
line.long 0x00 "DX7BDLR6,DATX8 n Bit Delay Line Register 6"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "TERBD,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "PDRBD,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED_7_0,Reserved"
|
|
repeat 3. (strings "7" "8" "9" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xE64)++0x03
|
|
line.long 0x00 "DX7BDLR$1,DATX8 n Bit Delay Line Register $1"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
rgroup.long 0xE80++0x03
|
|
line.long 0x00 "DX7LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WLD,Write Leveling Delay"
|
|
rgroup.long 0xE84++0x03
|
|
line.long 0x00 "DX7LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WDQD,Write Data Delay"
|
|
rgroup.long 0xE88++0x03
|
|
line.long 0x00 "DX7LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGD,Read DQS Gating Delay"
|
|
rgroup.long 0xE8C++0x03
|
|
line.long 0x00 "DX7LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSD,Read DQS Delay"
|
|
rgroup.long 0xE90++0x03
|
|
line.long 0x00 "DX7LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSND,Read DQSN Delay"
|
|
rgroup.long 0xE94++0x03
|
|
line.long 0x00 "DX7LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGSD,DQS Gating Status Delay"
|
|
rgroup.long 0xEA0++0x03
|
|
line.long 0x00 "DX7MDLR0,DATX8 n Master Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "TPRD,Target Period"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "IPRD,Initial Period"
|
|
rgroup.long 0xEA4++0x03
|
|
line.long 0x00 "DX7MDLR1,DATX8 n Master Delay Line Register 1"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED_31_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "MDLD,MDL Delay"
|
|
rgroup.long 0xEC0++0x03
|
|
line.long 0x00 "DX7GTR0,DATX8 n General Timing Register 0"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "WDQSL,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WLSL,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "RESERVED_12_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "DGSL,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xED0++0x03
|
|
line.long 0x00 "DX7RSR0,DATX8 n Rank Status Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "QSGERR,DQS Gate Training Error"
|
|
rgroup.long 0xED4++0x03
|
|
line.long 0x00 "DX7RSR1,DATX8 n Rank Status Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVLERR,Read Leveling Error"
|
|
rgroup.long 0xED8++0x03
|
|
line.long 0x00 "DX7RSR2,DATX8 n Rank Status Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAWN,Write Latency Adjustment (DQS off on some DQ lines) Warning"
|
|
rgroup.long 0xEDC++0x03
|
|
line.long 0x00 "DX7RSR3,DATX8 n Rank Status Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAERR,Write Leveling Adjustment Error"
|
|
rgroup.long 0xEE0++0x03
|
|
line.long 0x00 "DX7GSR0,DATX8 n General Status Register 0"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "WLDQ,Write Leveling DQ Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--29. "RESERVED_29_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 17.--25. 1. "GDQSPRD,Read DQS gating Period"
|
|
newline
|
|
bitfld.long 0x00 16. "DPLOCK,DATX8 PLL Lock" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "WLPRD,Write Leveling Period"
|
|
newline
|
|
bitfld.long 0x00 6. "WLERR,Write Leveling Error" "0,1"
|
|
bitfld.long 0x00 5. "WLDONE,Write Leveling Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "WLCAL,Write Leveling Calibration" "0,1"
|
|
bitfld.long 0x00 3. "GDQSCAL,Read DQS gating Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RDQSNCAL,Read DQS# Calibration" "0,1"
|
|
bitfld.long 0x00 1. "RDQSCAL,Read DQS Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDQCAL,Write DQ Calibration" "0,1"
|
|
rgroup.long 0xEE4++0x03
|
|
line.long 0x00 "DX7GSR1,DATX8 n General Status Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.tbyte 0x00 1.--24. 1. "DLTCODE,Delay Line Test Code"
|
|
newline
|
|
bitfld.long 0x00 0. "DLTDONE,Delay Line Test Done" "0,1"
|
|
rgroup.long 0xEE8++0x03
|
|
line.long 0x00 "DX7GSR2,DATX8 n General Status Register 2"
|
|
hexmask.long.word 0x00 23.--31. 1. "GSDQSPRD,Read DQS gating Status Period"
|
|
bitfld.long 0x00 22. "GSDQSCAL,Read DQS Gating Status Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "SRDERR,Static Read Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "DQS2DQERR,Write DQS2DQ Training Error"
|
|
bitfld.long 0x00 8.--11. "ESTAT,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "WEWN,Write Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 6. "WEERR,Write Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "REWN,Read Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 4. "REERR,Read Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "WDWN,Write Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 2. "WDERR,Write Bit Deskew Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RDWN,Read Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 0. "RDERR,Read Bit Deskew Error" "0,1"
|
|
rgroup.long 0xEEC++0x03
|
|
line.long 0x00 "DX7GSR3,DATX8 n General Status Register 3"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "ESTAT,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DVWRN,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "DVERR,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HVWRN,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HVERR,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "RESERVED_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. "SRDPC,Static Read Delay Pass Count" "0,1,2,3"
|
|
rgroup.long 0xEF0++0x03
|
|
line.long 0x00 "DX7GSR4,DATX8 n General Status Register 4"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 17.--25. 1. "RESERVED_25_17,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "RESERVED_16,Reserved" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "RESERVED_15_7,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0xEF4++0x03
|
|
line.long 0x00 "DX7GSR5,DATX8 n General Status Register 5"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED_31_23,Reserved"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "RESERVED_20,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "RESERVED_19_12,Reserved"
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0xEF8++0x03
|
|
line.long 0x00 "DX7GSR6,DATX8 n General Status Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "RESERVED_19_15,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "RESERVED_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
rgroup.long 0xF00++0x03
|
|
line.long 0x00 "DX8GCR0,DATX8 n General Configuration Register 0"
|
|
bitfld.long 0x00 31. "CALBYP,Calibration Bypass" "0,1"
|
|
bitfld.long 0x00 30. "MDLEN,Master Delay Line Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "CODTSHFT,Configurable ODT(TE) Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "DQSDCC,DQS Duty Cycle Correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RDDLY,Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--19. "RESERVED_19_14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 13. "DQSNSEPDR,DQSNSE Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 12. "DQSSEPDR,DQSSE Power Down Receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RTTOAL,RTT On Additive Latency" "0,1"
|
|
bitfld.long 0x00 9.--10. "RTTOH,RTT Output Hold" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 7.--8. "CPDRSHFT,Configurable PDR Phase Shift" "0,1,2,3"
|
|
bitfld.long 0x00 6. "DQSRPD,DQSR Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "DQSGPDR,DQSG Power Down Receiver" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DQSGODT,DQSG On-Die Termination" "0,1"
|
|
bitfld.long 0x00 2. "DQSGOE,DQSG Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
rgroup.long 0xF04++0x03
|
|
line.long 0x00 "DX8GCR1,DATX8 n General Configuration Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXPDRMODE,Enables the PDR mode for DQ[7:0]"
|
|
bitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "QSNSEL,Select the delayed or non-delayed read data strobe #" "0,1"
|
|
bitfld.long 0x00 13. "QSSEL,Select the delayed or non-delayed read data strobe" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "OEEN,Enables Read Data Strobe in a byte lane" "0,1"
|
|
bitfld.long 0x00 11. "PDREN,Enables PDR in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "TEEN,Enables ODT/TE in a byte lane" "0,1"
|
|
bitfld.long 0x00 9. "DSEN,Enables Write Data strobe in a byte lane" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "DMEN,Enables DM pin in a byte lane" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DQEN,Enables DQ corresponding to each bit in a byte"
|
|
rgroup.long 0xF08++0x03
|
|
line.long 0x00 "DX8GCR2,DATX8 n General Configuration Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "DXOEMODE,Enables the OE mode values for DQ[7:0]"
|
|
hexmask.long.word 0x00 0.--15. 1. "DXTEMODE,Enables the TE (ODT) mode values for DQ[7:0]"
|
|
rgroup.long 0xF0C++0x03
|
|
line.long 0x00 "DX8GCR3,DATX8 n General Configuration Register 3"
|
|
bitfld.long 0x00 31. "OEBVT,Output Enable BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 30. "TEBVT,Termination Enable BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RDBVT,Read Data BDL VT Compensation" "0,1"
|
|
bitfld.long 0x00 28. "WDBVT,Write Data BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "RGLVT,Read DQS Gating LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 26. "RDLVT,Read DQS LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "WDLVT,Write DQ LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 24. "WLLVT,Write Leveling LCDL Delay VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RGSLVT,Read DQS Gating Status LCDL Delay VT Compensation" "0,1"
|
|
bitfld.long 0x00 22. "PDRBVT,Power Down Receiver BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DSNOEMODE,Enables the OE mode for DQs" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. "DSNTEMODE,Enables the TE mode for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "DSNPDRMODE,Enables the PDR mode for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. "DMOEMODE,Enables the OE mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "DMTEMODE,Enables the TE mode values for DM" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. "DMPDRMODE,Enables the PDR mode values for DM" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9. "RESERVED_9,Reserved" "0,1"
|
|
bitfld.long 0x00 8. "WDSBVT,Write Data Strobe BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "DSOEMODE,Enables the OE mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. "DSTEMODE,Enables the TE mode values for DQS" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "DSPDRMODE,Enables the PDR mode values for DQS" "0,1,2,3"
|
|
bitfld.long 0x00 1. "RDMBVT,Read Data Mask BDL VT Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDMBVT,Write Data Mask BDL VT Compensation" "0,1"
|
|
rgroup.long 0xF10++0x03
|
|
line.long 0x00 "DX8GCR4,DATX8 n General Configuration Register 4"
|
|
bitfld.long 0x00 29.--31. "RESERVED_31_29,Byte lane VREF IOM (Used only by D4MU IOs)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. "DXREFPEN,Byte Lane VREF Pad Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "DXREFEEN,Byte Lane Internal VREF Enable" "0,1,2,3"
|
|
bitfld.long 0x00 25. "DXREFSEN,Byte Lane Single-End VREF Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RESERVED_24,Reserved" "0,1"
|
|
bitfld.long 0x00 23. "DXREFESELRANGE,External VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFESEL,Byte Lane External VREF Select"
|
|
bitfld.long 0x00 15. "DXREFSSELRANGE,Single ended VREF generator REFSEL range select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFSSEL,Byte Lane Single-End VREF Select"
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--5. "DXREFIEN,VREF Enable control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. "DXREFIMON,VRMON control for DQ IO (Single Ended) buffers of a byte lane" "0,1,2,3"
|
|
rgroup.long 0xF14++0x03
|
|
line.long 0x00 "DX8GCR5,DATX8 n General Configuration Register 5"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 24.--30. 1. "DXREFISELR3,Byte Lane internal VREF Select for Rank 3"
|
|
newline
|
|
bitfld.long 0x00 23. "RESERVED_23,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 16.--22. 1. "DXREFISELR2,Byte Lane internal VREF Select for Rank 2"
|
|
newline
|
|
bitfld.long 0x00 15. "RESERVED_15,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 8.--14. 1. "DXREFISELR1,Byte Lane internal VREF Select for Rank 1"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "DXREFISELR0,Byte Lane internal VREF Select for Rank 0"
|
|
rgroup.long 0xF18++0x03
|
|
line.long 0x00 "DX8GCR6,DATX8 n General Configuration Register 6"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DXDQVREFR3,DRAM DQ VREF Select for Rank3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DXDQVREFR2,DRAM DQ VREF Select for Rank2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DXDQVREFR1,DRAM DQ VREF Select for Rank1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DXDQVREFR0,DRAM DQ VREF Select for Rank0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xF1C++0x03
|
|
line.long 0x00 "DX8GCR7,DATX8 n General Configuration Register 7"
|
|
hexmask.long.word 0x00 19.--31. 1. "RESERVED_31_19,Reserved"
|
|
bitfld.long 0x00 18. "RESERVED_18,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--17. 1. "RESERVED_17_10,Reserved"
|
|
bitfld.long 0x00 9. "DCALTYPE,DDL Calibration Type" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "DCALSVAL,DDL Calibration Starting Value"
|
|
repeat 2. (strings "8" "9" )(list 0x00 0x04 )
|
|
rgroup.long ($2+0xF20)++0x03
|
|
line.long 0x00 "DX8GCR$1,DATX8 n General Configuration Register $1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "RESERVED_29_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
rgroup.long 0xF28++0x03
|
|
line.long 0x00 "DX8DQMAP0,DATX8 n DQ/DM Mapping Register 0"
|
|
bitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 20.--30. 1. "RESERVED_30_20,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DQ4MAP,DQ bit 4 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "DQ3MAP,DQ bit 3 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "DQ2MAP,DQ bit 2 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "DQ1MAP,DQ bit 1 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DQ0MAP,DQ bit 0 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xF2C++0x03
|
|
line.long 0x00 "DX8DQMAP1,DATX8 n DQ/DM Mapping Register 1"
|
|
bitfld.long 0x00 31. "MAPOK,Checksum bit" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. "RESERVED_30_16,Reserved"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "DMMAP,DM bit DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "DQ7MAP,DQ bit 7 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQ6MAP,DQ bit 6 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQ5MAP,DQ bit 5 DATX8 slice mapping index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xF40++0x03
|
|
line.long 0x00 "DX8BDLR0,DATX8 n Bit Delay Line Register 0"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3WBD,DQ3 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2WBD,DQ2 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1WBD,DQ1 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0WBD,DQ0 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xF44++0x03
|
|
line.long 0x00 "DX8BDLR1,DATX8 n Bit Delay Line Register 1"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7WBD,DQ7 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6WBD,DQ6 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5WBD,DQ5 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4WBD,DQ4 Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xF48++0x03
|
|
line.long 0x00 "DX8BDLR2,DATX8 n Bit Delay Line Register 2"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DSNWBD,DQSN Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DSOEBD,DQS/DM/DQ Output Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DSWBD,DQS Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DMWBD,DM Write Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xF50++0x03
|
|
line.long 0x00 "DX8BDLR3,DATX8 n Bit Delay Line Register 3"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ3RBD,DQ3 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ2RBD,DQ2 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ1RBD,DQ1 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ0RBD,DQ0 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xF54++0x03
|
|
line.long 0x00 "DX8BDLR4,DATX8 n Bit Delay Line Register 4"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 24.--29. "DQ7RBD,DQ7 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 16.--21. "DQ6RBD,DQ6 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "DQ5RBD,DQ5 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "DQ4RBD,DQ4 Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xF58++0x03
|
|
line.long 0x00 "DX8BDLR5,DATX8 n Bit Delay Line Register 5"
|
|
hexmask.long 0x00 6.--31. 1. "RESERVED_31_6,Reserved"
|
|
bitfld.long 0x00 0.--5. "DMRBD,DM Read Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xF60++0x03
|
|
line.long 0x00 "DX8BDLR6,DATX8 n Bit Delay Line Register 6"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "TERBD,Termination Enable Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "PDRBD,Power down receiver Bit Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESERVED_7_0,Reserved"
|
|
repeat 3. (strings "7" "8" "9" )(list 0x00 0x04 0x08 )
|
|
rgroup.long ($2+0xF64)++0x03
|
|
line.long 0x00 "DX8BDLR$1,DATX8 n Bit Delay Line Register $1"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
bitfld.long 0x00 16.--21. "RESERVED_21_16,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 8.--13. "RESERVED_13_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RESERVED_7_6,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "RESERVED_5_0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
rgroup.long 0xF80++0x03
|
|
line.long 0x00 "DX8LCDLR0,DATX8 n Local Calibrated Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WLD,Write Leveling Delay"
|
|
rgroup.long 0xF84++0x03
|
|
line.long 0x00 "DX8LCDLR1,DATX8 n Local Calibrated Delay Line Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "WDQD,Write Data Delay"
|
|
rgroup.long 0xF88++0x03
|
|
line.long 0x00 "DX8LCDLR2,DATX8 n Local Calibrated Delay Line Register 2"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGD,Read DQS Gating Delay"
|
|
rgroup.long 0xF8C++0x03
|
|
line.long 0x00 "DX8LCDLR3,DATX8 n Local Calibrated Delay Line Register 3"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSD,Read DQS Delay"
|
|
rgroup.long 0xF90++0x03
|
|
line.long 0x00 "DX8LCDLR4,DATX8 n Local Calibrated Delay Line Register 4"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "RDQSND,Read DQSN Delay"
|
|
rgroup.long 0xF94++0x03
|
|
line.long 0x00 "DX8LCDLR5,DATX8 n Local Calibrated Delay Line Register 5"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "RESERVED_24_16,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "DQSGSD,DQS Gating Status Delay"
|
|
rgroup.long 0xFA0++0x03
|
|
line.long 0x00 "DX8MDLR0,DATX8 n Master Delay Line Register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.word 0x00 16.--24. 1. "TPRD,Target Period"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "RESERVED_15_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "IPRD,Initial Period"
|
|
rgroup.long 0xFA4++0x03
|
|
line.long 0x00 "DX8MDLR1,DATX8 n Master Delay Line Register 1"
|
|
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED_31_9,Reserved"
|
|
hexmask.long.word 0x00 0.--8. 1. "MDLD,MDL Delay"
|
|
rgroup.long 0xFC0++0x03
|
|
line.long 0x00 "DX8GTR0,DATX8 n General Timing Register 0"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "WDQSL,DQ Write Path Latency Pipeline" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WLSL,Write Leveling System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. "RESERVED_12_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. "DGSL,DQS Gating System Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DX8RSR0,DATX8 n Rank Status Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "QSGERR,DQS Gate Training Error"
|
|
rgroup.long 0xFD4++0x03
|
|
line.long 0x00 "DX8RSR1,DATX8 n Rank Status Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "RDLVLERR,Read Leveling Error"
|
|
rgroup.long 0xFD8++0x03
|
|
line.long 0x00 "DX8RSR2,DATX8 n Rank Status Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAWN,Write Latency Adjustment (DQS off on some DQ lines) Warning"
|
|
rgroup.long 0xFDC++0x03
|
|
line.long 0x00 "DX8RSR3,DATX8 n Rank Status Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "RESERVED_31_16,Reserved"
|
|
hexmask.long.word 0x00 0.--15. 1. "WLAERR,Write Leveling Adjustment Error"
|
|
rgroup.long 0xFE0++0x03
|
|
line.long 0x00 "DX8GSR0,DATX8 n General Status Register 0"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 30. "WLDQ,Write Leveling DQ Status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26.--29. "RESERVED_29_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 17.--25. 1. "GDQSPRD,Read DQS gating Period"
|
|
newline
|
|
bitfld.long 0x00 16. "DPLOCK,DATX8 PLL Lock" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "WLPRD,Write Leveling Period"
|
|
newline
|
|
bitfld.long 0x00 6. "WLERR,Write Leveling Error" "0,1"
|
|
bitfld.long 0x00 5. "WLDONE,Write Leveling Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "WLCAL,Write Leveling Calibration" "0,1"
|
|
bitfld.long 0x00 3. "GDQSCAL,Read DQS gating Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RDQSNCAL,Read DQS# Calibration" "0,1"
|
|
bitfld.long 0x00 1. "RDQSCAL,Read DQS Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "WDQCAL,Write DQ Calibration" "0,1"
|
|
rgroup.long 0xFE4++0x03
|
|
line.long 0x00 "DX8GSR1,DATX8 n General Status Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
hexmask.long.tbyte 0x00 1.--24. 1. "DLTCODE,Delay Line Test Code"
|
|
newline
|
|
bitfld.long 0x00 0. "DLTDONE,Delay Line Test Done" "0,1"
|
|
rgroup.long 0xFE8++0x03
|
|
line.long 0x00 "DX8GSR2,DATX8 n General Status Register 2"
|
|
hexmask.long.word 0x00 23.--31. 1. "GSDQSPRD,Read DQS gating Status Period"
|
|
bitfld.long 0x00 22. "GSDQSCAL,Read DQS Gating Status Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "SRDERR,Static Read Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "DQS2DQERR,Write DQS2DQ Training Error"
|
|
bitfld.long 0x00 8.--11. "ESTAT,Error Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "WEWN,Write Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 6. "WEERR,Write Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "REWN,Read Eye Centering Warning" "0,1"
|
|
bitfld.long 0x00 4. "REERR,Read Eye Centering Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "WDWN,Write Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 2. "WDERR,Write Bit Deskew Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RDWN,Read Bit Deskew Warning" "0,1"
|
|
bitfld.long 0x00 0. "RDERR,Read Bit Deskew Error" "0,1"
|
|
rgroup.long 0xFEC++0x03
|
|
line.long 0x00 "DX8GSR3,DATX8 n General Status Register 3"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. "ESTAT,VREF Training Error Status Code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DVWRN,DRAM VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "DVERR,DRAM VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "HVWRN,Host VREF Training Warning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "HVERR,Host VREF Training Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "RESERVED_7_2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. "SRDPC,Static Read Delay Pass Count" "0,1,2,3"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "DX8GSR4,DATX8 n General Status Register 4"
|
|
bitfld.long 0x00 26.--31. "RESERVED_31_26,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 17.--25. 1. "RESERVED_25_17,Reserved"
|
|
newline
|
|
bitfld.long 0x00 16. "RESERVED_16,Reserved" "0,1"
|
|
hexmask.long.word 0x00 7.--15. 1. "RESERVED_15_7,Reserved"
|
|
newline
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "DX8GSR5,DATX8 n General Status Register 5"
|
|
hexmask.long.word 0x00 23.--31. 1. "RESERVED_31_23,Reserved"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "RESERVED_21,Reserved" "0,1"
|
|
bitfld.long 0x00 20. "RESERVED_20,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 12.--19. 1. "RESERVED_19_12,Reserved"
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "RESERVED_7,Reserved" "0,1"
|
|
bitfld.long 0x00 6. "RESERVED_6,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RESERVED_5,Reserved" "0,1"
|
|
bitfld.long 0x00 4. "RESERVED_4,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RESERVED_3,Reserved" "0,1"
|
|
bitfld.long 0x00 2. "RESERVED_2,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RESERVED_1,Reserved" "0,1"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0xFF8++0x03
|
|
line.long 0x00 "DX8GSR6,DATX8 n General Status Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 20.--23. "RESERVED_23_20,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "RESERVED_19_15,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "RESERVED_15_12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RESERVED_11_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "RESERVED_7_4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3"
|
|
group.long 0x1400++0x03
|
|
line.long 0x00 "DX8SL0OSC,DATX8 0-1 Oscillator Delay Line Test PHY FIFO and High Speed Reset Loopback and Gated Clock Control Register"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "GATEDXRDCLK,Enable Clock Gating for DX ddr_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "GATEDXDDRCLK,Enable Clock Gating for DX ctl_rd_clk" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "GATEDXCTLCLK,Enable Clock Gating for DX ctl_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CLKLEVEL,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3"
|
|
bitfld.long 0x00 21. "LBMODE,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LBGSDQS,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "0,1"
|
|
bitfld.long 0x00 18.--19. "LBGDQS,Loopback DQS Gating" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "LBDQSS,Loopback DQS Shift" "0,1"
|
|
bitfld.long 0x00 16. "PHYHRST,PHY High-Speed Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PHYFRST,PHY FIFO Reset" "0,1"
|
|
bitfld.long 0x00 14. "DLTST,Delay Line Test Start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DLTMODE,Delay Line Test Mode" "0,1"
|
|
bitfld.long 0x00 11.--12. "RESERVED_12_11,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "OSCWDDL,Oscillator Mode Write-Data Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "RESERVED_8_7,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "OSCWDL,Oscillator Mode Write-Leveling Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--4. "OSCDIV,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "OSCEN,Oscillator Enable" "0,1"
|
|
group.long 0x1404++0x03
|
|
line.long 0x00 "DX8SL0PLLCR0,DAXT8 0-1 PLL Control Register 0"
|
|
bitfld.long 0x00 31. "PLLBYP,PLL Bypass" "0,1"
|
|
bitfld.long 0x00 30. "PLLRST,PLL Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PLLPD,PLL Power Down" "0,1"
|
|
bitfld.long 0x00 28. "RSTOPM,Reference Stop Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FRQSEL,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RLOCKM,Relock Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--22. "CPPC,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 13.--16. "CPIC,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "GSHIFT,Gear Shift" "0,1"
|
|
rbitfld.long 0x00 9.--11. "RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "ATOEN,Analog Test Enable (ATOEN)" "0,1"
|
|
bitfld.long 0x00 4.--7. "ATC,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTC,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1408++0x03
|
|
line.long 0x00 "DX8SL0PLLCR1,DAXT8 0-1 PLL Control Register 1 (Type B PLL Only)"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
hexmask.long.word 0x00 6.--21. 1. "PLLPROG,Connects to the PLL PLL_PROG bus"
|
|
newline
|
|
bitfld.long 0x00 5. "BYPVREGCP,Bypass PLL vreg_cp" "0,1"
|
|
bitfld.long 0x00 4. "BYPVREGDIG,Bypass PLL vreg_dig" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BYPVDD,PLL VDD voltage level control" "0,1"
|
|
bitfld.long 0x00 2. "LOCKPS,Lock Detector Phase Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKCS,Lock Detector Counter Select" "0,1"
|
|
bitfld.long 0x00 0. "LOCKDS,Lock Detector Select" "0,1"
|
|
group.long 0x140C++0x03
|
|
line.long 0x00 "DX8SL0PLLCR2,DAXT8 0-1 PLL Control Register 2 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_31_0,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x1410++0x03
|
|
line.long 0x00 "DX8SL0PLLCR3,DAXT8 0-1 PLL Control Register 3 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_63_32,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x1414++0x03
|
|
line.long 0x00 "DX8SL0PLLCR4,DAXT8 0-1 PLL Control Register 4 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_95_64,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x1418++0x03
|
|
line.long 0x00 "DX8SL0PLLCR5,DAXT8 0-1 PLL Control Register 5 (Type B PLL Only)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PLLCTRL_103_96,Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x141C++0x03
|
|
line.long 0x00 "DX8SL0DQSCTL,DATX8 0-1 DQS Control Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "RRRMODE,Read Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WRRMODE,Write Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "DQSGX,DQS Gate Extension" "0,1,2,3"
|
|
bitfld.long 0x00 18. "LPPLLPD,Low Power PLL Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "LPIOPD,Low Power I/O Power Down" "0,1"
|
|
rbitfld.long 0x00 15.--16. "RESERVED_16_15,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14. "QSCNTEN,QS Counter Enable" "0,1"
|
|
bitfld.long 0x00 13. "UDQIOM,Unused DQ I/O Mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10.--12. "RESERVED_12_10,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--9. "DXSR,Data Slew Rate" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQSNRES,DQS_N Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQSRES,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1420++0x03
|
|
line.long 0x00 "DX8SL0TRNCTL,DATX8 0-1 Training Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
group.long 0x1424++0x03
|
|
line.long 0x00 "DX8SL0DDLCTL,DATX8 0-1 DDL Control Register"
|
|
rbitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 26. "DLYLDTM,Delay Load Timing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DXDDLLDT,DX DDL Load Type" "0,1"
|
|
rbitfld.long 0x00 23.--24. "RESERVED_24_23,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--22. "DXDDLLD,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 2.--17. 1. "DXDDLBYP,DATX8 DDL Bypass"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DDLBYPMODE,Controls DDL Bypass Mode" "0,1,2,3"
|
|
group.long 0x1428++0x03
|
|
line.long 0x00 "DX8SL0DXCTL1,DATX8 0-1 DX Control Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "DXCALCLK,DATX Calibration Clock Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "DXRCLKMD,DATX8 Read Clock Mode" "0,1"
|
|
rbitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DXDTOSEL,DATX8 Digital Test Output Select" "0,1,2,3"
|
|
bitfld.long 0x00 19. "DXGSMD,Read DQS Gating Status Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "DXQSDBYP,Read DQS/DQS_N Delay Load Bypass Mode" "0,1"
|
|
bitfld.long 0x00 17. "DXGDBYP,Read DQS Gate Delay Load Bypass Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DXTMODE,DATX8 Test Mode" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RESERVED_15_0,Reserved"
|
|
group.long 0x142C++0x03
|
|
line.long 0x00 "DX8SL0DXCTL2,DATX8 0-1 DX Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 23. "CRDEN,Configurable Read Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "POSOEX,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--19. "PREOEX,OE Extension during Pre-amble" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 17. "RESERVED_17,Reserved" "0,1"
|
|
bitfld.long 0x00 16. "IOAG,I/O Assisted Gate Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IOLB,I/O Loopback Select" "0,1"
|
|
rbitfld.long 0x00 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "LPWAKEUP_THRSH,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. "RDBI,Read Data Bus Inversion Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "WDBI,Write Data Bus Inversion Enable" "0,1"
|
|
bitfld.long 0x00 6. "PRFBYP,PUB Read FIFO Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RDMODE,DATX8 Receive FIFO Read Mode" "0,1,2,3"
|
|
bitfld.long 0x00 3. "DISRST,Disables the Read FIFO Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "DQSGLB,Read DQS Gate I/O Loopback" "0,1,2,3"
|
|
rbitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
group.long 0x1430++0x03
|
|
line.long 0x00 "DX8SL0IOCR,DATX8 0-1 I/O Configuration Register"
|
|
rbitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "DXDACRANGE,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "DXVREFIOM,IOM bits for PVREF PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--24. "DXIOM,DX IO Mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 11.--21. 1. "DXTXM,DX IO Transmitter Mode"
|
|
hexmask.long.word 0x00 0.--10. 1. "DXRXM,DX IO Receiver Mode"
|
|
rgroup.long 0x1434++0x03
|
|
line.long 0x00 "DX4SL0IOCR,DATX4 Slice 0-1 I/O Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
group.long 0x1440++0x03
|
|
line.long 0x00 "DX8SL1OSC,DATX8 0-1 Oscillator Delay Line Test PHY FIFO and High Speed Reset Loopback and Gated Clock Control Register"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "GATEDXRDCLK,Enable Clock Gating for DX ddr_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "GATEDXDDRCLK,Enable Clock Gating for DX ctl_rd_clk" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "GATEDXCTLCLK,Enable Clock Gating for DX ctl_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CLKLEVEL,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3"
|
|
bitfld.long 0x00 21. "LBMODE,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LBGSDQS,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "0,1"
|
|
bitfld.long 0x00 18.--19. "LBGDQS,Loopback DQS Gating" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "LBDQSS,Loopback DQS Shift" "0,1"
|
|
bitfld.long 0x00 16. "PHYHRST,PHY High-Speed Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PHYFRST,PHY FIFO Reset" "0,1"
|
|
bitfld.long 0x00 14. "DLTST,Delay Line Test Start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DLTMODE,Delay Line Test Mode" "0,1"
|
|
bitfld.long 0x00 11.--12. "RESERVED_12_11,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "OSCWDDL,Oscillator Mode Write-Data Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "RESERVED_8_7,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "OSCWDL,Oscillator Mode Write-Leveling Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--4. "OSCDIV,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "OSCEN,Oscillator Enable" "0,1"
|
|
group.long 0x1444++0x03
|
|
line.long 0x00 "DX8SL1PLLCR0,DAXT8 0-1 PLL Control Register 0"
|
|
bitfld.long 0x00 31. "PLLBYP,PLL Bypass" "0,1"
|
|
bitfld.long 0x00 30. "PLLRST,PLL Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PLLPD,PLL Power Down" "0,1"
|
|
bitfld.long 0x00 28. "RSTOPM,Reference Stop Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FRQSEL,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RLOCKM,Relock Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--22. "CPPC,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 13.--16. "CPIC,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "GSHIFT,Gear Shift" "0,1"
|
|
rbitfld.long 0x00 9.--11. "RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "ATOEN,Analog Test Enable (ATOEN)" "0,1"
|
|
bitfld.long 0x00 4.--7. "ATC,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTC,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1448++0x03
|
|
line.long 0x00 "DX8SL1PLLCR1,DAXT8 0-1 PLL Control Register 1 (Type B PLL Only)"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
hexmask.long.word 0x00 6.--21. 1. "PLLPROG,Connects to the PLL PLL_PROG bus"
|
|
newline
|
|
bitfld.long 0x00 5. "BYPVREGCP,Bypass PLL vreg_cp" "0,1"
|
|
bitfld.long 0x00 4. "BYPVREGDIG,Bypass PLL vreg_dig" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BYPVDD,PLL VDD voltage level control" "0,1"
|
|
bitfld.long 0x00 2. "LOCKPS,Lock Detector Phase Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKCS,Lock Detector Counter Select" "0,1"
|
|
bitfld.long 0x00 0. "LOCKDS,Lock Detector Select" "0,1"
|
|
group.long 0x144C++0x03
|
|
line.long 0x00 "DX8SL1PLLCR2,DAXT8 0-1 PLL Control Register 2 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_31_0,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x1450++0x03
|
|
line.long 0x00 "DX8SL1PLLCR3,DAXT8 0-1 PLL Control Register 3 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_63_32,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x1454++0x03
|
|
line.long 0x00 "DX8SL1PLLCR4,DAXT8 0-1 PLL Control Register 4 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_95_64,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x1458++0x03
|
|
line.long 0x00 "DX8SL1PLLCR5,DAXT8 0-1 PLL Control Register 5 (Type B PLL Only)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PLLCTRL_103_96,Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x145C++0x03
|
|
line.long 0x00 "DX8SL1DQSCTL,DATX8 0-1 DQS Control Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "RRRMODE,Read Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WRRMODE,Write Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "DQSGX,DQS Gate Extension" "0,1,2,3"
|
|
bitfld.long 0x00 18. "LPPLLPD,Low Power PLL Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "LPIOPD,Low Power I/O Power Down" "0,1"
|
|
rbitfld.long 0x00 15.--16. "RESERVED_16_15,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14. "QSCNTEN,QS Counter Enable" "0,1"
|
|
bitfld.long 0x00 13. "UDQIOM,Unused DQ I/O Mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10.--12. "RESERVED_12_10,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--9. "DXSR,Data Slew Rate" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQSNRES,DQS_N Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQSRES,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1460++0x03
|
|
line.long 0x00 "DX8SL1TRNCTL,DATX8 0-1 Training Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
group.long 0x1464++0x03
|
|
line.long 0x00 "DX8SL1DDLCTL,DATX8 0-1 DDL Control Register"
|
|
rbitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 26. "DLYLDTM,Delay Load Timing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DXDDLLDT,DX DDL Load Type" "0,1"
|
|
rbitfld.long 0x00 23.--24. "RESERVED_24_23,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--22. "DXDDLLD,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 2.--17. 1. "DXDDLBYP,DATX8 DDL Bypass"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DDLBYPMODE,Controls DDL Bypass Mode" "0,1,2,3"
|
|
group.long 0x1468++0x03
|
|
line.long 0x00 "DX8SL1DXCTL1,DATX8 0-1 DX Control Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "DXCALCLK,DATX Calibration Clock Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "DXRCLKMD,DATX8 Read Clock Mode" "0,1"
|
|
rbitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DXDTOSEL,DATX8 Digital Test Output Select" "0,1,2,3"
|
|
bitfld.long 0x00 19. "DXGSMD,Read DQS Gating Status Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "DXQSDBYP,Read DQS/DQS_N Delay Load Bypass Mode" "0,1"
|
|
bitfld.long 0x00 17. "DXGDBYP,Read DQS Gate Delay Load Bypass Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DXTMODE,DATX8 Test Mode" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RESERVED_15_0,Reserved"
|
|
group.long 0x146C++0x03
|
|
line.long 0x00 "DX8SL1DXCTL2,DATX8 0-1 DX Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 23. "CRDEN,Configurable Read Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "POSOEX,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--19. "PREOEX,OE Extension during Pre-amble" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 17. "RESERVED_17,Reserved" "0,1"
|
|
bitfld.long 0x00 16. "IOAG,I/O Assisted Gate Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IOLB,I/O Loopback Select" "0,1"
|
|
rbitfld.long 0x00 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "LPWAKEUP_THRSH,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. "RDBI,Read Data Bus Inversion Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "WDBI,Write Data Bus Inversion Enable" "0,1"
|
|
bitfld.long 0x00 6. "PRFBYP,PUB Read FIFO Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RDMODE,DATX8 Receive FIFO Read Mode" "0,1,2,3"
|
|
bitfld.long 0x00 3. "DISRST,Disables the Read FIFO Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "DQSGLB,Read DQS Gate I/O Loopback" "0,1,2,3"
|
|
rbitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
group.long 0x1470++0x03
|
|
line.long 0x00 "DX8SL1IOCR,DATX8 0-1 I/O Configuration Register"
|
|
rbitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "DXDACRANGE,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "DXVREFIOM,IOM bits for PVREF PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--24. "DXIOM,DX IO Mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 11.--21. 1. "DXTXM,DX IO Transmitter Mode"
|
|
hexmask.long.word 0x00 0.--10. 1. "DXRXM,DX IO Receiver Mode"
|
|
rgroup.long 0x1474++0x03
|
|
line.long 0x00 "DX4SL1IOCR,DATX4 Slice 0-1 I/O Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
group.long 0x1480++0x03
|
|
line.long 0x00 "DX8SL2OSC,DATX8 0-1 Oscillator Delay Line Test PHY FIFO and High Speed Reset Loopback and Gated Clock Control Register"
|
|
rbitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "GATEDXRDCLK,Enable Clock Gating for DX ddr_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "GATEDXDDRCLK,Enable Clock Gating for DX ctl_rd_clk" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "GATEDXCTLCLK,Enable Clock Gating for DX ctl_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CLKLEVEL,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3"
|
|
bitfld.long 0x00 21. "LBMODE,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LBGSDQS,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "0,1"
|
|
bitfld.long 0x00 18.--19. "LBGDQS,Loopback DQS Gating" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "LBDQSS,Loopback DQS Shift" "0,1"
|
|
bitfld.long 0x00 16. "PHYHRST,PHY High-Speed Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PHYFRST,PHY FIFO Reset" "0,1"
|
|
bitfld.long 0x00 14. "DLTST,Delay Line Test Start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DLTMODE,Delay Line Test Mode" "0,1"
|
|
bitfld.long 0x00 11.--12. "RESERVED_12_11,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "OSCWDDL,Oscillator Mode Write-Data Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "RESERVED_8_7,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "OSCWDL,Oscillator Mode Write-Leveling Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--4. "OSCDIV,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "OSCEN,Oscillator Enable" "0,1"
|
|
group.long 0x1484++0x03
|
|
line.long 0x00 "DX8SL2PLLCR0,DAXT8 0-1 PLL Control Register 0"
|
|
bitfld.long 0x00 31. "PLLBYP,PLL Bypass" "0,1"
|
|
bitfld.long 0x00 30. "PLLRST,PLL Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PLLPD,PLL Power Down" "0,1"
|
|
bitfld.long 0x00 28. "RSTOPM,Reference Stop Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FRQSEL,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RLOCKM,Relock Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--22. "CPPC,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 13.--16. "CPIC,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "GSHIFT,Gear Shift" "0,1"
|
|
rbitfld.long 0x00 9.--11. "RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "ATOEN,Analog Test Enable (ATOEN)" "0,1"
|
|
bitfld.long 0x00 4.--7. "ATC,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTC,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1488++0x03
|
|
line.long 0x00 "DX8SL2PLLCR1,DAXT8 0-1 PLL Control Register 1 (Type B PLL Only)"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
hexmask.long.word 0x00 6.--21. 1. "PLLPROG,Connects to the PLL PLL_PROG bus"
|
|
newline
|
|
bitfld.long 0x00 5. "BYPVREGCP,Bypass PLL vreg_cp" "0,1"
|
|
bitfld.long 0x00 4. "BYPVREGDIG,Bypass PLL vreg_dig" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BYPVDD,PLL VDD voltage level control" "0,1"
|
|
bitfld.long 0x00 2. "LOCKPS,Lock Detector Phase Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKCS,Lock Detector Counter Select" "0,1"
|
|
bitfld.long 0x00 0. "LOCKDS,Lock Detector Select" "0,1"
|
|
group.long 0x148C++0x03
|
|
line.long 0x00 "DX8SL2PLLCR2,DAXT8 0-1 PLL Control Register 2 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_31_0,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x1490++0x03
|
|
line.long 0x00 "DX8SL2PLLCR3,DAXT8 0-1 PLL Control Register 3 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_63_32,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x1494++0x03
|
|
line.long 0x00 "DX8SL2PLLCR4,DAXT8 0-1 PLL Control Register 4 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_95_64,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x1498++0x03
|
|
line.long 0x00 "DX8SL2PLLCR5,DAXT8 0-1 PLL Control Register 5 (Type B PLL Only)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PLLCTRL_103_96,Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL"
|
|
group.long 0x149C++0x03
|
|
line.long 0x00 "DX8SL2DQSCTL,DATX8 0-1 DQS Control Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "RRRMODE,Read Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WRRMODE,Write Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "DQSGX,DQS Gate Extension" "0,1,2,3"
|
|
bitfld.long 0x00 18. "LPPLLPD,Low Power PLL Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "LPIOPD,Low Power I/O Power Down" "0,1"
|
|
rbitfld.long 0x00 15.--16. "RESERVED_16_15,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14. "QSCNTEN,QS Counter Enable" "0,1"
|
|
bitfld.long 0x00 13. "UDQIOM,Unused DQ I/O Mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10.--12. "RESERVED_12_10,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--9. "DXSR,Data Slew Rate" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQSNRES,DQS_N Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQSRES,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x14A0++0x03
|
|
line.long 0x00 "DX8SL2TRNCTL,DATX8 0-1 Training Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
group.long 0x14A4++0x03
|
|
line.long 0x00 "DX8SL2DDLCTL,DATX8 0-1 DDL Control Register"
|
|
rbitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 26. "DLYLDTM,Delay Load Timing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DXDDLLDT,DX DDL Load Type" "0,1"
|
|
rbitfld.long 0x00 23.--24. "RESERVED_24_23,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--22. "DXDDLLD,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 2.--17. 1. "DXDDLBYP,DATX8 DDL Bypass"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DDLBYPMODE,Controls DDL Bypass Mode" "0,1,2,3"
|
|
group.long 0x14A8++0x03
|
|
line.long 0x00 "DX8SL2DXCTL1,DATX8 0-1 DX Control Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "DXCALCLK,DATX Calibration Clock Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "DXRCLKMD,DATX8 Read Clock Mode" "0,1"
|
|
rbitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DXDTOSEL,DATX8 Digital Test Output Select" "0,1,2,3"
|
|
bitfld.long 0x00 19. "DXGSMD,Read DQS Gating Status Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "DXQSDBYP,Read DQS/DQS_N Delay Load Bypass Mode" "0,1"
|
|
bitfld.long 0x00 17. "DXGDBYP,Read DQS Gate Delay Load Bypass Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DXTMODE,DATX8 Test Mode" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RESERVED_15_0,Reserved"
|
|
group.long 0x14AC++0x03
|
|
line.long 0x00 "DX8SL2DXCTL2,DATX8 0-1 DX Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 23. "CRDEN,Configurable Read Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "POSOEX,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--19. "PREOEX,OE Extension during Pre-amble" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 17. "RESERVED_17,Reserved" "0,1"
|
|
bitfld.long 0x00 16. "IOAG,I/O Assisted Gate Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IOLB,I/O Loopback Select" "0,1"
|
|
rbitfld.long 0x00 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "LPWAKEUP_THRSH,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. "RDBI,Read Data Bus Inversion Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "WDBI,Write Data Bus Inversion Enable" "0,1"
|
|
bitfld.long 0x00 6. "PRFBYP,PUB Read FIFO Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RDMODE,DATX8 Receive FIFO Read Mode" "0,1,2,3"
|
|
bitfld.long 0x00 3. "DISRST,Disables the Read FIFO Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "DQSGLB,Read DQS Gate I/O Loopback" "0,1,2,3"
|
|
rbitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
group.long 0x14B0++0x03
|
|
line.long 0x00 "DX8SL2IOCR,DATX8 0-1 I/O Configuration Register"
|
|
rbitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "DXDACRANGE,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "DXVREFIOM,IOM bits for PVREF PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--24. "DXIOM,DX IO Mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 11.--21. 1. "DXTXM,DX IO Transmitter Mode"
|
|
hexmask.long.word 0x00 0.--10. 1. "DXRXM,DX IO Receiver Mode"
|
|
rgroup.long 0x14B4++0x03
|
|
line.long 0x00 "DX4SL2IOCR,DATX4 Slice 0-1 I/O Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
rgroup.long 0x14C0++0x03
|
|
line.long 0x00 "DX8SL3OSC,DATX8 0-1 Oscillator Delay Line Test PHY FIFO and High Speed Reset Loopback and Gated Clock Control Register"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "GATEDXRDCLK,Enable Clock Gating for DX ddr_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "GATEDXDDRCLK,Enable Clock Gating for DX ctl_rd_clk" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "GATEDXCTLCLK,Enable Clock Gating for DX ctl_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CLKLEVEL,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3"
|
|
bitfld.long 0x00 21. "LBMODE,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LBGSDQS,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "0,1"
|
|
bitfld.long 0x00 18.--19. "LBGDQS,Loopback DQS Gating" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "LBDQSS,Loopback DQS Shift" "0,1"
|
|
bitfld.long 0x00 16. "PHYHRST,PHY High-Speed Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PHYFRST,PHY FIFO Reset" "0,1"
|
|
bitfld.long 0x00 14. "DLTST,Delay Line Test Start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DLTMODE,Delay Line Test Mode" "0,1"
|
|
bitfld.long 0x00 11.--12. "RESERVED_12_11,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "OSCWDDL,Oscillator Mode Write-Data Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "RESERVED_8_7,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "OSCWDL,Oscillator Mode Write-Leveling Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--4. "OSCDIV,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "OSCEN,Oscillator Enable" "0,1"
|
|
rgroup.long 0x14C4++0x03
|
|
line.long 0x00 "DX8SL3PLLCR0,DAXT8 0-1 PLL Control Register 0"
|
|
bitfld.long 0x00 31. "PLLBYP,PLL Bypass" "0,1"
|
|
bitfld.long 0x00 30. "PLLRST,PLL Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PLLPD,PLL Power Down" "0,1"
|
|
bitfld.long 0x00 28. "RSTOPM,Reference Stop Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FRQSEL,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RLOCKM,Relock Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--22. "CPPC,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 13.--16. "CPIC,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "GSHIFT,Gear Shift" "0,1"
|
|
bitfld.long 0x00 9.--11. "RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "ATOEN,Analog Test Enable (ATOEN)" "0,1"
|
|
bitfld.long 0x00 4.--7. "ATC,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTC,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x14C8++0x03
|
|
line.long 0x00 "DX8SL3PLLCR1,DAXT8 0-1 PLL Control Register 1 (Type B PLL Only)"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
hexmask.long.word 0x00 6.--21. 1. "PLLPROG,Connects to the PLL PLL_PROG bus"
|
|
newline
|
|
bitfld.long 0x00 5. "BYPVREGCP,Bypass PLL vreg_cp" "0,1"
|
|
bitfld.long 0x00 4. "BYPVREGDIG,Bypass PLL vreg_dig" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BYPVDD,PLL VDD voltage level control" "0,1"
|
|
bitfld.long 0x00 2. "LOCKPS,Lock Detector Phase Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKCS,Lock Detector Counter Select" "0,1"
|
|
bitfld.long 0x00 0. "LOCKDS,Lock Detector Select" "0,1"
|
|
rgroup.long 0x14CC++0x03
|
|
line.long 0x00 "DX8SL3PLLCR2,DAXT8 0-1 PLL Control Register 2 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_31_0,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x14D0++0x03
|
|
line.long 0x00 "DX8SL3PLLCR3,DAXT8 0-1 PLL Control Register 3 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_63_32,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x14D4++0x03
|
|
line.long 0x00 "DX8SL3PLLCR4,DAXT8 0-1 PLL Control Register 4 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_95_64,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x14D8++0x03
|
|
line.long 0x00 "DX8SL3PLLCR5,DAXT8 0-1 PLL Control Register 5 (Type B PLL Only)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PLLCTRL_103_96,Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x14DC++0x03
|
|
line.long 0x00 "DX8SL3DQSCTL,DATX8 0-1 DQS Control Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "RRRMODE,Read Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WRRMODE,Write Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "DQSGX,DQS Gate Extension" "0,1,2,3"
|
|
bitfld.long 0x00 18. "LPPLLPD,Low Power PLL Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "LPIOPD,Low Power I/O Power Down" "0,1"
|
|
bitfld.long 0x00 15.--16. "RESERVED_16_15,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14. "QSCNTEN,QS Counter Enable" "0,1"
|
|
bitfld.long 0x00 13. "UDQIOM,Unused DQ I/O Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RESERVED_12_10,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--9. "DXSR,Data Slew Rate" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQSNRES,DQS_N Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQSRES,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x14E0++0x03
|
|
line.long 0x00 "DX8SL3TRNCTL,DATX8 0-1 Training Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
rgroup.long 0x14E4++0x03
|
|
line.long 0x00 "DX8SL3DDLCTL,DATX8 0-1 DDL Control Register"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 26. "DLYLDTM,Delay Load Timing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DXDDLLDT,DX DDL Load Type" "0,1"
|
|
bitfld.long 0x00 23.--24. "RESERVED_24_23,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--22. "DXDDLLD,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 2.--17. 1. "DXDDLBYP,DATX8 DDL Bypass"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DDLBYPMODE,Controls DDL Bypass Mode" "0,1,2,3"
|
|
rgroup.long 0x14E8++0x03
|
|
line.long 0x00 "DX8SL3DXCTL1,DATX8 0-1 DX Control Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "DXCALCLK,DATX Calibration Clock Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "DXRCLKMD,DATX8 Read Clock Mode" "0,1"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DXDTOSEL,DATX8 Digital Test Output Select" "0,1,2,3"
|
|
bitfld.long 0x00 19. "DXGSMD,Read DQS Gating Status Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "DXQSDBYP,Read DQS/DQS_N Delay Load Bypass Mode" "0,1"
|
|
bitfld.long 0x00 17. "DXGDBYP,Read DQS Gate Delay Load Bypass Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DXTMODE,DATX8 Test Mode" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RESERVED_15_0,Reserved"
|
|
rgroup.long 0x14EC++0x03
|
|
line.long 0x00 "DX8SL3DXCTL2,DATX8 0-1 DX Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 23. "CRDEN,Configurable Read Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "POSOEX,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--19. "PREOEX,OE Extension during Pre-amble" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "RESERVED_17,Reserved" "0,1"
|
|
bitfld.long 0x00 16. "IOAG,I/O Assisted Gate Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IOLB,I/O Loopback Select" "0,1"
|
|
bitfld.long 0x00 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "LPWAKEUP_THRSH,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. "RDBI,Read Data Bus Inversion Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "WDBI,Write Data Bus Inversion Enable" "0,1"
|
|
bitfld.long 0x00 6. "PRFBYP,PUB Read FIFO Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RDMODE,DATX8 Receive FIFO Read Mode" "0,1,2,3"
|
|
bitfld.long 0x00 3. "DISRST,Disables the Read FIFO Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "DQSGLB,Read DQS Gate I/O Loopback" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0x14F0++0x03
|
|
line.long 0x00 "DX8SL3IOCR,DATX8 0-1 I/O Configuration Register"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "DXDACRANGE,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "DXVREFIOM,IOM bits for PVREF PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--24. "DXIOM,DX IO Mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 11.--21. 1. "DXTXM,DX IO Transmitter Mode"
|
|
hexmask.long.word 0x00 0.--10. 1. "DXRXM,DX IO Receiver Mode"
|
|
rgroup.long 0x14F4++0x03
|
|
line.long 0x00 "DX4SL3IOCR,DATX4 Slice 0-1 I/O Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
rgroup.long 0x1500++0x03
|
|
line.long 0x00 "DX8SL4OSC,DATX8 0-1 Oscillator Delay Line Test PHY FIFO and High Speed Reset Loopback and Gated Clock Control Register"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "GATEDXRDCLK,Enable Clock Gating for DX ddr_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "GATEDXDDRCLK,Enable Clock Gating for DX ctl_rd_clk" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "GATEDXCTLCLK,Enable Clock Gating for DX ctl_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CLKLEVEL,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3"
|
|
bitfld.long 0x00 21. "LBMODE,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LBGSDQS,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "0,1"
|
|
bitfld.long 0x00 18.--19. "LBGDQS,Loopback DQS Gating" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "LBDQSS,Loopback DQS Shift" "0,1"
|
|
bitfld.long 0x00 16. "PHYHRST,PHY High-Speed Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PHYFRST,PHY FIFO Reset" "0,1"
|
|
bitfld.long 0x00 14. "DLTST,Delay Line Test Start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DLTMODE,Delay Line Test Mode" "0,1"
|
|
bitfld.long 0x00 11.--12. "RESERVED_12_11,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "OSCWDDL,Oscillator Mode Write-Data Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "RESERVED_8_7,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "OSCWDL,Oscillator Mode Write-Leveling Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--4. "OSCDIV,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "OSCEN,Oscillator Enable" "0,1"
|
|
rgroup.long 0x1504++0x03
|
|
line.long 0x00 "DX8SL4PLLCR0,DAXT8 0-1 PLL Control Register 0"
|
|
bitfld.long 0x00 31. "PLLBYP,PLL Bypass" "0,1"
|
|
bitfld.long 0x00 30. "PLLRST,PLL Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PLLPD,PLL Power Down" "0,1"
|
|
bitfld.long 0x00 28. "RSTOPM,Reference Stop Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FRQSEL,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RLOCKM,Relock Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--22. "CPPC,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 13.--16. "CPIC,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "GSHIFT,Gear Shift" "0,1"
|
|
bitfld.long 0x00 9.--11. "RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "ATOEN,Analog Test Enable (ATOEN)" "0,1"
|
|
bitfld.long 0x00 4.--7. "ATC,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTC,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1508++0x03
|
|
line.long 0x00 "DX8SL4PLLCR1,DAXT8 0-1 PLL Control Register 1 (Type B PLL Only)"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
hexmask.long.word 0x00 6.--21. 1. "PLLPROG,Connects to the PLL PLL_PROG bus"
|
|
newline
|
|
bitfld.long 0x00 5. "BYPVREGCP,Bypass PLL vreg_cp" "0,1"
|
|
bitfld.long 0x00 4. "BYPVREGDIG,Bypass PLL vreg_dig" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BYPVDD,PLL VDD voltage level control" "0,1"
|
|
bitfld.long 0x00 2. "LOCKPS,Lock Detector Phase Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKCS,Lock Detector Counter Select" "0,1"
|
|
bitfld.long 0x00 0. "LOCKDS,Lock Detector Select" "0,1"
|
|
rgroup.long 0x150C++0x03
|
|
line.long 0x00 "DX8SL4PLLCR2,DAXT8 0-1 PLL Control Register 2 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_31_0,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x1510++0x03
|
|
line.long 0x00 "DX8SL4PLLCR3,DAXT8 0-1 PLL Control Register 3 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_63_32,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x1514++0x03
|
|
line.long 0x00 "DX8SL4PLLCR4,DAXT8 0-1 PLL Control Register 4 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_95_64,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x1518++0x03
|
|
line.long 0x00 "DX8SL4PLLCR5,DAXT8 0-1 PLL Control Register 5 (Type B PLL Only)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PLLCTRL_103_96,Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x151C++0x03
|
|
line.long 0x00 "DX8SL4DQSCTL,DATX8 0-1 DQS Control Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "RRRMODE,Read Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WRRMODE,Write Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "DQSGX,DQS Gate Extension" "0,1,2,3"
|
|
bitfld.long 0x00 18. "LPPLLPD,Low Power PLL Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "LPIOPD,Low Power I/O Power Down" "0,1"
|
|
bitfld.long 0x00 15.--16. "RESERVED_16_15,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14. "QSCNTEN,QS Counter Enable" "0,1"
|
|
bitfld.long 0x00 13. "UDQIOM,Unused DQ I/O Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RESERVED_12_10,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--9. "DXSR,Data Slew Rate" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQSNRES,DQS_N Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQSRES,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1520++0x03
|
|
line.long 0x00 "DX8SL4TRNCTL,DATX8 0-1 Training Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
rgroup.long 0x1524++0x03
|
|
line.long 0x00 "DX8SL4DDLCTL,DATX8 0-1 DDL Control Register"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 26. "DLYLDTM,Delay Load Timing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DXDDLLDT,DX DDL Load Type" "0,1"
|
|
bitfld.long 0x00 23.--24. "RESERVED_24_23,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--22. "DXDDLLD,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 2.--17. 1. "DXDDLBYP,DATX8 DDL Bypass"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DDLBYPMODE,Controls DDL Bypass Mode" "0,1,2,3"
|
|
rgroup.long 0x1528++0x03
|
|
line.long 0x00 "DX8SL4DXCTL1,DATX8 0-1 DX Control Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "DXCALCLK,DATX Calibration Clock Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "DXRCLKMD,DATX8 Read Clock Mode" "0,1"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DXDTOSEL,DATX8 Digital Test Output Select" "0,1,2,3"
|
|
bitfld.long 0x00 19. "DXGSMD,Read DQS Gating Status Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "DXQSDBYP,Read DQS/DQS_N Delay Load Bypass Mode" "0,1"
|
|
bitfld.long 0x00 17. "DXGDBYP,Read DQS Gate Delay Load Bypass Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DXTMODE,DATX8 Test Mode" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RESERVED_15_0,Reserved"
|
|
rgroup.long 0x152C++0x03
|
|
line.long 0x00 "DX8SL4DXCTL2,DATX8 0-1 DX Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 23. "CRDEN,Configurable Read Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "POSOEX,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--19. "PREOEX,OE Extension during Pre-amble" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "RESERVED_17,Reserved" "0,1"
|
|
bitfld.long 0x00 16. "IOAG,I/O Assisted Gate Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IOLB,I/O Loopback Select" "0,1"
|
|
bitfld.long 0x00 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "LPWAKEUP_THRSH,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. "RDBI,Read Data Bus Inversion Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "WDBI,Write Data Bus Inversion Enable" "0,1"
|
|
bitfld.long 0x00 6. "PRFBYP,PUB Read FIFO Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RDMODE,DATX8 Receive FIFO Read Mode" "0,1,2,3"
|
|
bitfld.long 0x00 3. "DISRST,Disables the Read FIFO Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "DQSGLB,Read DQS Gate I/O Loopback" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0x1530++0x03
|
|
line.long 0x00 "DX8SL4IOCR,DATX8 0-1 I/O Configuration Register"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "DXDACRANGE,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "DXVREFIOM,IOM bits for PVREF PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--24. "DXIOM,DX IO Mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 11.--21. 1. "DXTXM,DX IO Transmitter Mode"
|
|
hexmask.long.word 0x00 0.--10. 1. "DXRXM,DX IO Receiver Mode"
|
|
rgroup.long 0x1534++0x03
|
|
line.long 0x00 "DX4SL4IOCR,DATX4 Slice 0-1 I/O Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
rgroup.long 0x1540++0x03
|
|
line.long 0x00 "DX8SL5OSC,DATX8 0-1 Oscillator Delay Line Test PHY FIFO and High Speed Reset Loopback and Gated Clock Control Register"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "GATEDXRDCLK,Enable Clock Gating for DX ddr_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "GATEDXDDRCLK,Enable Clock Gating for DX ctl_rd_clk" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "GATEDXCTLCLK,Enable Clock Gating for DX ctl_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CLKLEVEL,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3"
|
|
bitfld.long 0x00 21. "LBMODE,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LBGSDQS,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "0,1"
|
|
bitfld.long 0x00 18.--19. "LBGDQS,Loopback DQS Gating" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "LBDQSS,Loopback DQS Shift" "0,1"
|
|
bitfld.long 0x00 16. "PHYHRST,PHY High-Speed Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PHYFRST,PHY FIFO Reset" "0,1"
|
|
bitfld.long 0x00 14. "DLTST,Delay Line Test Start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DLTMODE,Delay Line Test Mode" "0,1"
|
|
bitfld.long 0x00 11.--12. "RESERVED_12_11,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "OSCWDDL,Oscillator Mode Write-Data Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "RESERVED_8_7,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "OSCWDL,Oscillator Mode Write-Leveling Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--4. "OSCDIV,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "OSCEN,Oscillator Enable" "0,1"
|
|
rgroup.long 0x1544++0x03
|
|
line.long 0x00 "DX8SL5PLLCR0,DAXT8 0-1 PLL Control Register 0"
|
|
bitfld.long 0x00 31. "PLLBYP,PLL Bypass" "0,1"
|
|
bitfld.long 0x00 30. "PLLRST,PLL Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PLLPD,PLL Power Down" "0,1"
|
|
bitfld.long 0x00 28. "RSTOPM,Reference Stop Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FRQSEL,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RLOCKM,Relock Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--22. "CPPC,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 13.--16. "CPIC,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "GSHIFT,Gear Shift" "0,1"
|
|
bitfld.long 0x00 9.--11. "RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "ATOEN,Analog Test Enable (ATOEN)" "0,1"
|
|
bitfld.long 0x00 4.--7. "ATC,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTC,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1548++0x03
|
|
line.long 0x00 "DX8SL5PLLCR1,DAXT8 0-1 PLL Control Register 1 (Type B PLL Only)"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
hexmask.long.word 0x00 6.--21. 1. "PLLPROG,Connects to the PLL PLL_PROG bus"
|
|
newline
|
|
bitfld.long 0x00 5. "BYPVREGCP,Bypass PLL vreg_cp" "0,1"
|
|
bitfld.long 0x00 4. "BYPVREGDIG,Bypass PLL vreg_dig" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BYPVDD,PLL VDD voltage level control" "0,1"
|
|
bitfld.long 0x00 2. "LOCKPS,Lock Detector Phase Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKCS,Lock Detector Counter Select" "0,1"
|
|
bitfld.long 0x00 0. "LOCKDS,Lock Detector Select" "0,1"
|
|
rgroup.long 0x154C++0x03
|
|
line.long 0x00 "DX8SL5PLLCR2,DAXT8 0-1 PLL Control Register 2 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_31_0,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x1550++0x03
|
|
line.long 0x00 "DX8SL5PLLCR3,DAXT8 0-1 PLL Control Register 3 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_63_32,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x1554++0x03
|
|
line.long 0x00 "DX8SL5PLLCR4,DAXT8 0-1 PLL Control Register 4 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_95_64,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x1558++0x03
|
|
line.long 0x00 "DX8SL5PLLCR5,DAXT8 0-1 PLL Control Register 5 (Type B PLL Only)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PLLCTRL_103_96,Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x155C++0x03
|
|
line.long 0x00 "DX8SL5DQSCTL,DATX8 0-1 DQS Control Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "RRRMODE,Read Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WRRMODE,Write Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "DQSGX,DQS Gate Extension" "0,1,2,3"
|
|
bitfld.long 0x00 18. "LPPLLPD,Low Power PLL Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "LPIOPD,Low Power I/O Power Down" "0,1"
|
|
bitfld.long 0x00 15.--16. "RESERVED_16_15,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14. "QSCNTEN,QS Counter Enable" "0,1"
|
|
bitfld.long 0x00 13. "UDQIOM,Unused DQ I/O Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RESERVED_12_10,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--9. "DXSR,Data Slew Rate" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQSNRES,DQS_N Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQSRES,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1560++0x03
|
|
line.long 0x00 "DX8SL5TRNCTL,DATX8 0-1 Training Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
rgroup.long 0x1564++0x03
|
|
line.long 0x00 "DX8SL5DDLCTL,DATX8 0-1 DDL Control Register"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 26. "DLYLDTM,Delay Load Timing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DXDDLLDT,DX DDL Load Type" "0,1"
|
|
bitfld.long 0x00 23.--24. "RESERVED_24_23,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--22. "DXDDLLD,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 2.--17. 1. "DXDDLBYP,DATX8 DDL Bypass"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DDLBYPMODE,Controls DDL Bypass Mode" "0,1,2,3"
|
|
rgroup.long 0x1568++0x03
|
|
line.long 0x00 "DX8SL5DXCTL1,DATX8 0-1 DX Control Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "DXCALCLK,DATX Calibration Clock Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "DXRCLKMD,DATX8 Read Clock Mode" "0,1"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DXDTOSEL,DATX8 Digital Test Output Select" "0,1,2,3"
|
|
bitfld.long 0x00 19. "DXGSMD,Read DQS Gating Status Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "DXQSDBYP,Read DQS/DQS_N Delay Load Bypass Mode" "0,1"
|
|
bitfld.long 0x00 17. "DXGDBYP,Read DQS Gate Delay Load Bypass Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DXTMODE,DATX8 Test Mode" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RESERVED_15_0,Reserved"
|
|
rgroup.long 0x156C++0x03
|
|
line.long 0x00 "DX8SL5DXCTL2,DATX8 0-1 DX Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 23. "CRDEN,Configurable Read Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "POSOEX,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--19. "PREOEX,OE Extension during Pre-amble" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "RESERVED_17,Reserved" "0,1"
|
|
bitfld.long 0x00 16. "IOAG,I/O Assisted Gate Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IOLB,I/O Loopback Select" "0,1"
|
|
bitfld.long 0x00 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "LPWAKEUP_THRSH,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. "RDBI,Read Data Bus Inversion Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "WDBI,Write Data Bus Inversion Enable" "0,1"
|
|
bitfld.long 0x00 6. "PRFBYP,PUB Read FIFO Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RDMODE,DATX8 Receive FIFO Read Mode" "0,1,2,3"
|
|
bitfld.long 0x00 3. "DISRST,Disables the Read FIFO Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "DQSGLB,Read DQS Gate I/O Loopback" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0x1570++0x03
|
|
line.long 0x00 "DX8SL5IOCR,DATX8 0-1 I/O Configuration Register"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "DXDACRANGE,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "DXVREFIOM,IOM bits for PVREF PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--24. "DXIOM,DX IO Mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 11.--21. 1. "DXTXM,DX IO Transmitter Mode"
|
|
hexmask.long.word 0x00 0.--10. 1. "DXRXM,DX IO Receiver Mode"
|
|
rgroup.long 0x1574++0x03
|
|
line.long 0x00 "DX4SL5IOCR,DATX4 Slice 0-1 I/O Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
rgroup.long 0x1580++0x03
|
|
line.long 0x00 "DX8SL6OSC,DATX8 0-1 Oscillator Delay Line Test PHY FIFO and High Speed Reset Loopback and Gated Clock Control Register"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "GATEDXRDCLK,Enable Clock Gating for DX ddr_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "GATEDXDDRCLK,Enable Clock Gating for DX ctl_rd_clk" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "GATEDXCTLCLK,Enable Clock Gating for DX ctl_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CLKLEVEL,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3"
|
|
bitfld.long 0x00 21. "LBMODE,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LBGSDQS,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "0,1"
|
|
bitfld.long 0x00 18.--19. "LBGDQS,Loopback DQS Gating" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "LBDQSS,Loopback DQS Shift" "0,1"
|
|
bitfld.long 0x00 16. "PHYHRST,PHY High-Speed Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PHYFRST,PHY FIFO Reset" "0,1"
|
|
bitfld.long 0x00 14. "DLTST,Delay Line Test Start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DLTMODE,Delay Line Test Mode" "0,1"
|
|
bitfld.long 0x00 11.--12. "RESERVED_12_11,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "OSCWDDL,Oscillator Mode Write-Data Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "RESERVED_8_7,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "OSCWDL,Oscillator Mode Write-Leveling Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--4. "OSCDIV,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "OSCEN,Oscillator Enable" "0,1"
|
|
rgroup.long 0x1584++0x03
|
|
line.long 0x00 "DX8SL6PLLCR0,DAXT8 0-1 PLL Control Register 0"
|
|
bitfld.long 0x00 31. "PLLBYP,PLL Bypass" "0,1"
|
|
bitfld.long 0x00 30. "PLLRST,PLL Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PLLPD,PLL Power Down" "0,1"
|
|
bitfld.long 0x00 28. "RSTOPM,Reference Stop Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FRQSEL,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RLOCKM,Relock Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--22. "CPPC,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 13.--16. "CPIC,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "GSHIFT,Gear Shift" "0,1"
|
|
bitfld.long 0x00 9.--11. "RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "ATOEN,Analog Test Enable (ATOEN)" "0,1"
|
|
bitfld.long 0x00 4.--7. "ATC,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTC,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1588++0x03
|
|
line.long 0x00 "DX8SL6PLLCR1,DAXT8 0-1 PLL Control Register 1 (Type B PLL Only)"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
hexmask.long.word 0x00 6.--21. 1. "PLLPROG,Connects to the PLL PLL_PROG bus"
|
|
newline
|
|
bitfld.long 0x00 5. "BYPVREGCP,Bypass PLL vreg_cp" "0,1"
|
|
bitfld.long 0x00 4. "BYPVREGDIG,Bypass PLL vreg_dig" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BYPVDD,PLL VDD voltage level control" "0,1"
|
|
bitfld.long 0x00 2. "LOCKPS,Lock Detector Phase Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKCS,Lock Detector Counter Select" "0,1"
|
|
bitfld.long 0x00 0. "LOCKDS,Lock Detector Select" "0,1"
|
|
rgroup.long 0x158C++0x03
|
|
line.long 0x00 "DX8SL6PLLCR2,DAXT8 0-1 PLL Control Register 2 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_31_0,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x1590++0x03
|
|
line.long 0x00 "DX8SL6PLLCR3,DAXT8 0-1 PLL Control Register 3 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_63_32,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x1594++0x03
|
|
line.long 0x00 "DX8SL6PLLCR4,DAXT8 0-1 PLL Control Register 4 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_95_64,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x1598++0x03
|
|
line.long 0x00 "DX8SL6PLLCR5,DAXT8 0-1 PLL Control Register 5 (Type B PLL Only)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PLLCTRL_103_96,Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x159C++0x03
|
|
line.long 0x00 "DX8SL6DQSCTL,DATX8 0-1 DQS Control Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "RRRMODE,Read Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WRRMODE,Write Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "DQSGX,DQS Gate Extension" "0,1,2,3"
|
|
bitfld.long 0x00 18. "LPPLLPD,Low Power PLL Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "LPIOPD,Low Power I/O Power Down" "0,1"
|
|
bitfld.long 0x00 15.--16. "RESERVED_16_15,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14. "QSCNTEN,QS Counter Enable" "0,1"
|
|
bitfld.long 0x00 13. "UDQIOM,Unused DQ I/O Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RESERVED_12_10,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--9. "DXSR,Data Slew Rate" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQSNRES,DQS_N Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQSRES,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x15A0++0x03
|
|
line.long 0x00 "DX8SL6TRNCTL,DATX8 0-1 Training Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
rgroup.long 0x15A4++0x03
|
|
line.long 0x00 "DX8SL6DDLCTL,DATX8 0-1 DDL Control Register"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 26. "DLYLDTM,Delay Load Timing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DXDDLLDT,DX DDL Load Type" "0,1"
|
|
bitfld.long 0x00 23.--24. "RESERVED_24_23,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--22. "DXDDLLD,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 2.--17. 1. "DXDDLBYP,DATX8 DDL Bypass"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DDLBYPMODE,Controls DDL Bypass Mode" "0,1,2,3"
|
|
rgroup.long 0x15A8++0x03
|
|
line.long 0x00 "DX8SL6DXCTL1,DATX8 0-1 DX Control Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "DXCALCLK,DATX Calibration Clock Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "DXRCLKMD,DATX8 Read Clock Mode" "0,1"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DXDTOSEL,DATX8 Digital Test Output Select" "0,1,2,3"
|
|
bitfld.long 0x00 19. "DXGSMD,Read DQS Gating Status Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "DXQSDBYP,Read DQS/DQS_N Delay Load Bypass Mode" "0,1"
|
|
bitfld.long 0x00 17. "DXGDBYP,Read DQS Gate Delay Load Bypass Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DXTMODE,DATX8 Test Mode" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RESERVED_15_0,Reserved"
|
|
rgroup.long 0x15AC++0x03
|
|
line.long 0x00 "DX8SL6DXCTL2,DATX8 0-1 DX Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 23. "CRDEN,Configurable Read Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "POSOEX,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--19. "PREOEX,OE Extension during Pre-amble" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "RESERVED_17,Reserved" "0,1"
|
|
bitfld.long 0x00 16. "IOAG,I/O Assisted Gate Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IOLB,I/O Loopback Select" "0,1"
|
|
bitfld.long 0x00 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "LPWAKEUP_THRSH,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. "RDBI,Read Data Bus Inversion Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "WDBI,Write Data Bus Inversion Enable" "0,1"
|
|
bitfld.long 0x00 6. "PRFBYP,PUB Read FIFO Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RDMODE,DATX8 Receive FIFO Read Mode" "0,1,2,3"
|
|
bitfld.long 0x00 3. "DISRST,Disables the Read FIFO Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "DQSGLB,Read DQS Gate I/O Loopback" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0x15B0++0x03
|
|
line.long 0x00 "DX8SL6IOCR,DATX8 0-1 I/O Configuration Register"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "DXDACRANGE,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "DXVREFIOM,IOM bits for PVREF PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--24. "DXIOM,DX IO Mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 11.--21. 1. "DXTXM,DX IO Transmitter Mode"
|
|
hexmask.long.word 0x00 0.--10. 1. "DXRXM,DX IO Receiver Mode"
|
|
rgroup.long 0x15B4++0x03
|
|
line.long 0x00 "DX4SL6IOCR,DATX4 Slice 0-1 I/O Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
rgroup.long 0x15C0++0x03
|
|
line.long 0x00 "DX8SL7OSC,DATX8 0-1 Oscillator Delay Line Test PHY FIFO and High Speed Reset Loopback and Gated Clock Control Register"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "GATEDXRDCLK,Enable Clock Gating for DX ddr_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "GATEDXDDRCLK,Enable Clock Gating for DX ctl_rd_clk" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "GATEDXCTLCLK,Enable Clock Gating for DX ctl_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CLKLEVEL,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3"
|
|
bitfld.long 0x00 21. "LBMODE,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LBGSDQS,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "0,1"
|
|
bitfld.long 0x00 18.--19. "LBGDQS,Loopback DQS Gating" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "LBDQSS,Loopback DQS Shift" "0,1"
|
|
bitfld.long 0x00 16. "PHYHRST,PHY High-Speed Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PHYFRST,PHY FIFO Reset" "0,1"
|
|
bitfld.long 0x00 14. "DLTST,Delay Line Test Start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DLTMODE,Delay Line Test Mode" "0,1"
|
|
bitfld.long 0x00 11.--12. "RESERVED_12_11,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "OSCWDDL,Oscillator Mode Write-Data Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "RESERVED_8_7,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "OSCWDL,Oscillator Mode Write-Leveling Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--4. "OSCDIV,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "OSCEN,Oscillator Enable" "0,1"
|
|
rgroup.long 0x15C4++0x03
|
|
line.long 0x00 "DX8SL7PLLCR0,DAXT8 0-1 PLL Control Register 0"
|
|
bitfld.long 0x00 31. "PLLBYP,PLL Bypass" "0,1"
|
|
bitfld.long 0x00 30. "PLLRST,PLL Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PLLPD,PLL Power Down" "0,1"
|
|
bitfld.long 0x00 28. "RSTOPM,Reference Stop Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FRQSEL,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RLOCKM,Relock Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--22. "CPPC,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 13.--16. "CPIC,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "GSHIFT,Gear Shift" "0,1"
|
|
bitfld.long 0x00 9.--11. "RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "ATOEN,Analog Test Enable (ATOEN)" "0,1"
|
|
bitfld.long 0x00 4.--7. "ATC,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTC,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x15C8++0x03
|
|
line.long 0x00 "DX8SL7PLLCR1,DAXT8 0-1 PLL Control Register 1 (Type B PLL Only)"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
hexmask.long.word 0x00 6.--21. 1. "PLLPROG,Connects to the PLL PLL_PROG bus"
|
|
newline
|
|
bitfld.long 0x00 5. "BYPVREGCP,Bypass PLL vreg_cp" "0,1"
|
|
bitfld.long 0x00 4. "BYPVREGDIG,Bypass PLL vreg_dig" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BYPVDD,PLL VDD voltage level control" "0,1"
|
|
bitfld.long 0x00 2. "LOCKPS,Lock Detector Phase Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKCS,Lock Detector Counter Select" "0,1"
|
|
bitfld.long 0x00 0. "LOCKDS,Lock Detector Select" "0,1"
|
|
rgroup.long 0x15CC++0x03
|
|
line.long 0x00 "DX8SL7PLLCR2,DAXT8 0-1 PLL Control Register 2 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_31_0,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x15D0++0x03
|
|
line.long 0x00 "DX8SL7PLLCR3,DAXT8 0-1 PLL Control Register 3 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_63_32,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x15D4++0x03
|
|
line.long 0x00 "DX8SL7PLLCR4,DAXT8 0-1 PLL Control Register 4 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_95_64,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x15D8++0x03
|
|
line.long 0x00 "DX8SL7PLLCR5,DAXT8 0-1 PLL Control Register 5 (Type B PLL Only)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PLLCTRL_103_96,Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x15DC++0x03
|
|
line.long 0x00 "DX8SL7DQSCTL,DATX8 0-1 DQS Control Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "RRRMODE,Read Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WRRMODE,Write Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "DQSGX,DQS Gate Extension" "0,1,2,3"
|
|
bitfld.long 0x00 18. "LPPLLPD,Low Power PLL Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "LPIOPD,Low Power I/O Power Down" "0,1"
|
|
bitfld.long 0x00 15.--16. "RESERVED_16_15,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14. "QSCNTEN,QS Counter Enable" "0,1"
|
|
bitfld.long 0x00 13. "UDQIOM,Unused DQ I/O Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RESERVED_12_10,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--9. "DXSR,Data Slew Rate" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQSNRES,DQS_N Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQSRES,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x15E0++0x03
|
|
line.long 0x00 "DX8SL7TRNCTL,DATX8 0-1 Training Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
rgroup.long 0x15E4++0x03
|
|
line.long 0x00 "DX8SL7DDLCTL,DATX8 0-1 DDL Control Register"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 26. "DLYLDTM,Delay Load Timing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DXDDLLDT,DX DDL Load Type" "0,1"
|
|
bitfld.long 0x00 23.--24. "RESERVED_24_23,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--22. "DXDDLLD,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 2.--17. 1. "DXDDLBYP,DATX8 DDL Bypass"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DDLBYPMODE,Controls DDL Bypass Mode" "0,1,2,3"
|
|
rgroup.long 0x15E8++0x03
|
|
line.long 0x00 "DX8SL7DXCTL1,DATX8 0-1 DX Control Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "DXCALCLK,DATX Calibration Clock Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "DXRCLKMD,DATX8 Read Clock Mode" "0,1"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DXDTOSEL,DATX8 Digital Test Output Select" "0,1,2,3"
|
|
bitfld.long 0x00 19. "DXGSMD,Read DQS Gating Status Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "DXQSDBYP,Read DQS/DQS_N Delay Load Bypass Mode" "0,1"
|
|
bitfld.long 0x00 17. "DXGDBYP,Read DQS Gate Delay Load Bypass Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DXTMODE,DATX8 Test Mode" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RESERVED_15_0,Reserved"
|
|
rgroup.long 0x15EC++0x03
|
|
line.long 0x00 "DX8SL7DXCTL2,DATX8 0-1 DX Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 23. "CRDEN,Configurable Read Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "POSOEX,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--19. "PREOEX,OE Extension during Pre-amble" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "RESERVED_17,Reserved" "0,1"
|
|
bitfld.long 0x00 16. "IOAG,I/O Assisted Gate Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IOLB,I/O Loopback Select" "0,1"
|
|
bitfld.long 0x00 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "LPWAKEUP_THRSH,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. "RDBI,Read Data Bus Inversion Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "WDBI,Write Data Bus Inversion Enable" "0,1"
|
|
bitfld.long 0x00 6. "PRFBYP,PUB Read FIFO Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RDMODE,DATX8 Receive FIFO Read Mode" "0,1,2,3"
|
|
bitfld.long 0x00 3. "DISRST,Disables the Read FIFO Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "DQSGLB,Read DQS Gate I/O Loopback" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0x15F0++0x03
|
|
line.long 0x00 "DX8SL7IOCR,DATX8 0-1 I/O Configuration Register"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "DXDACRANGE,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "DXVREFIOM,IOM bits for PVREF PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--24. "DXIOM,DX IO Mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 11.--21. 1. "DXTXM,DX IO Transmitter Mode"
|
|
hexmask.long.word 0x00 0.--10. 1. "DXRXM,DX IO Receiver Mode"
|
|
rgroup.long 0x15F4++0x03
|
|
line.long 0x00 "DX4SL7IOCR,DATX4 Slice 0-1 I/O Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
rgroup.long 0x1600++0x03
|
|
line.long 0x00 "DX8SL8OSC,DATX8 0-1 Oscillator Delay Line Test PHY FIFO and High Speed Reset Loopback and Gated Clock Control Register"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "GATEDXRDCLK,Enable Clock Gating for DX ddr_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "GATEDXDDRCLK,Enable Clock Gating for DX ctl_rd_clk" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "GATEDXCTLCLK,Enable Clock Gating for DX ctl_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CLKLEVEL,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3"
|
|
bitfld.long 0x00 21. "LBMODE,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LBGSDQS,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "0,1"
|
|
bitfld.long 0x00 18.--19. "LBGDQS,Loopback DQS Gating" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "LBDQSS,Loopback DQS Shift" "0,1"
|
|
bitfld.long 0x00 16. "PHYHRST,PHY High-Speed Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PHYFRST,PHY FIFO Reset" "0,1"
|
|
bitfld.long 0x00 14. "DLTST,Delay Line Test Start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DLTMODE,Delay Line Test Mode" "0,1"
|
|
bitfld.long 0x00 11.--12. "RESERVED_12_11,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "OSCWDDL,Oscillator Mode Write-Data Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "RESERVED_8_7,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "OSCWDL,Oscillator Mode Write-Leveling Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--4. "OSCDIV,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "OSCEN,Oscillator Enable" "0,1"
|
|
rgroup.long 0x1604++0x03
|
|
line.long 0x00 "DX8SL8PLLCR0,DAXT8 0-1 PLL Control Register 0"
|
|
bitfld.long 0x00 31. "PLLBYP,PLL Bypass" "0,1"
|
|
bitfld.long 0x00 30. "PLLRST,PLL Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PLLPD,PLL Power Down" "0,1"
|
|
bitfld.long 0x00 28. "RSTOPM,Reference Stop Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FRQSEL,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RLOCKM,Relock Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--22. "CPPC,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 13.--16. "CPIC,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "GSHIFT,Gear Shift" "0,1"
|
|
bitfld.long 0x00 9.--11. "RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "ATOEN,Analog Test Enable (ATOEN)" "0,1"
|
|
bitfld.long 0x00 4.--7. "ATC,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTC,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1608++0x03
|
|
line.long 0x00 "DX8SL8PLLCR1,DAXT8 0-1 PLL Control Register 1 (Type B PLL Only)"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
hexmask.long.word 0x00 6.--21. 1. "PLLPROG,Connects to the PLL PLL_PROG bus"
|
|
newline
|
|
bitfld.long 0x00 5. "BYPVREGCP,Bypass PLL vreg_cp" "0,1"
|
|
bitfld.long 0x00 4. "BYPVREGDIG,Bypass PLL vreg_dig" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BYPVDD,PLL VDD voltage level control" "0,1"
|
|
bitfld.long 0x00 2. "LOCKPS,Lock Detector Phase Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKCS,Lock Detector Counter Select" "0,1"
|
|
bitfld.long 0x00 0. "LOCKDS,Lock Detector Select" "0,1"
|
|
rgroup.long 0x160C++0x03
|
|
line.long 0x00 "DX8SL8PLLCR2,DAXT8 0-1 PLL Control Register 2 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_31_0,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x1610++0x03
|
|
line.long 0x00 "DX8SL8PLLCR3,DAXT8 0-1 PLL Control Register 3 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_63_32,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x1614++0x03
|
|
line.long 0x00 "DX8SL8PLLCR4,DAXT8 0-1 PLL Control Register 4 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_95_64,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x1618++0x03
|
|
line.long 0x00 "DX8SL8PLLCR5,DAXT8 0-1 PLL Control Register 5 (Type B PLL Only)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PLLCTRL_103_96,Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL"
|
|
rgroup.long 0x161C++0x03
|
|
line.long 0x00 "DX8SL8DQSCTL,DATX8 0-1 DQS Control Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "RRRMODE,Read Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WRRMODE,Write Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "DQSGX,DQS Gate Extension" "0,1,2,3"
|
|
bitfld.long 0x00 18. "LPPLLPD,Low Power PLL Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "LPIOPD,Low Power I/O Power Down" "0,1"
|
|
bitfld.long 0x00 15.--16. "RESERVED_16_15,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14. "QSCNTEN,QS Counter Enable" "0,1"
|
|
bitfld.long 0x00 13. "UDQIOM,Unused DQ I/O Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RESERVED_12_10,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--9. "DXSR,Data Slew Rate" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQSNRES,DQS_N Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQSRES,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1620++0x03
|
|
line.long 0x00 "DX8SL8TRNCTL,DATX8 0-1 Training Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
rgroup.long 0x1624++0x03
|
|
line.long 0x00 "DX8SL8DDLCTL,DATX8 0-1 DDL Control Register"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 26. "DLYLDTM,Delay Load Timing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DXDDLLDT,DX DDL Load Type" "0,1"
|
|
bitfld.long 0x00 23.--24. "RESERVED_24_23,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--22. "DXDDLLD,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 2.--17. 1. "DXDDLBYP,DATX8 DDL Bypass"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DDLBYPMODE,Controls DDL Bypass Mode" "0,1,2,3"
|
|
rgroup.long 0x1628++0x03
|
|
line.long 0x00 "DX8SL8DXCTL1,DATX8 0-1 DX Control Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "DXCALCLK,DATX Calibration Clock Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "DXRCLKMD,DATX8 Read Clock Mode" "0,1"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DXDTOSEL,DATX8 Digital Test Output Select" "0,1,2,3"
|
|
bitfld.long 0x00 19. "DXGSMD,Read DQS Gating Status Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "DXQSDBYP,Read DQS/DQS_N Delay Load Bypass Mode" "0,1"
|
|
bitfld.long 0x00 17. "DXGDBYP,Read DQS Gate Delay Load Bypass Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DXTMODE,DATX8 Test Mode" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RESERVED_15_0,Reserved"
|
|
rgroup.long 0x162C++0x03
|
|
line.long 0x00 "DX8SL8DXCTL2,DATX8 0-1 DX Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 23. "CRDEN,Configurable Read Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "POSOEX,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--19. "PREOEX,OE Extension during Pre-amble" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "RESERVED_17,Reserved" "0,1"
|
|
bitfld.long 0x00 16. "IOAG,I/O Assisted Gate Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IOLB,I/O Loopback Select" "0,1"
|
|
bitfld.long 0x00 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "LPWAKEUP_THRSH,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. "RDBI,Read Data Bus Inversion Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "WDBI,Write Data Bus Inversion Enable" "0,1"
|
|
bitfld.long 0x00 6. "PRFBYP,PUB Read FIFO Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RDMODE,DATX8 Receive FIFO Read Mode" "0,1,2,3"
|
|
bitfld.long 0x00 3. "DISRST,Disables the Read FIFO Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "DQSGLB,Read DQS Gate I/O Loopback" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
rgroup.long 0x1630++0x03
|
|
line.long 0x00 "DX8SL8IOCR,DATX8 0-1 I/O Configuration Register"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "DXDACRANGE,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "DXVREFIOM,IOM bits for PVREF PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--24. "DXIOM,DX IO Mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 11.--21. 1. "DXTXM,DX IO Transmitter Mode"
|
|
hexmask.long.word 0x00 0.--10. 1. "DXRXM,DX IO Receiver Mode"
|
|
rgroup.long 0x1634++0x03
|
|
line.long 0x00 "DX4SL8IOCR,DATX4 Slice 0-1 I/O Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
wgroup.long 0x17C0++0x03
|
|
line.long 0x00 "DX8SLbOSC,DATX8 0-8 Oscillator Delay Line Test PHY FIFO and High Speed Reset Loopback and Gated Clock Control Register"
|
|
bitfld.long 0x00 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "GATEDXRDCLK,Enable Clock Gating for DX ddr_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "GATEDXDDRCLK,Enable Clock Gating for DX ctl_rd_clk" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. "GATEDXCTLCLK,Enable Clock Gating for DX ctl_clk" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CLKLEVEL,Selects the level to which clocks will be stalled when clock gating is enabled" "0,1,2,3"
|
|
bitfld.long 0x00 21. "LBMODE,Loopback Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "LBGSDQS,Load GSDQS LCDL with 2x the calibrated GSDQSPRD value" "0,1"
|
|
bitfld.long 0x00 18.--19. "LBGDQS,Loopback DQS Gating" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "LBDQSS,Loopback DQS Shift" "0,1"
|
|
bitfld.long 0x00 16. "PHYHRST,PHY High-Speed Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "PHYFRST,PHY FIFO Reset" "0,1"
|
|
bitfld.long 0x00 14. "DLTST,Delay Line Test Start" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "DLTMODE,Delay Line Test Mode" "0,1"
|
|
bitfld.long 0x00 11.--12. "RESERVED_12_11,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "OSCWDDL,Oscillator Mode Write-Data Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. "RESERVED_8_7,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "OSCWDL,Oscillator Mode Write-Leveling Delay Line Select" "0,1,2,3"
|
|
bitfld.long 0x00 1.--4. "OSCDIV,Oscillator Mode Division" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0. "OSCEN,Oscillator Enable" "0,1"
|
|
wgroup.long 0x17C4++0x03
|
|
line.long 0x00 "DX8SLbPLLCR0,DAXT8 0-8 PLL Control Register 0"
|
|
bitfld.long 0x00 31. "PLLBYP,PLL Bypass" "0,1"
|
|
bitfld.long 0x00 30. "PLLRST,PLL Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "PLLPD,PLL Power Down" "0,1"
|
|
bitfld.long 0x00 28. "RSTOPM,Reference Stop Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "FRQSEL,PLL Frequency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "RLOCKM,Relock Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--22. "CPPC,Charge Pump Proportional Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 13.--16. "CPIC,Charge Pump Integrating Current Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "GSHIFT,Gear Shift" "0,1"
|
|
bitfld.long 0x00 9.--11. "RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "ATOEN,Analog Test Enable (ATOEN)" "0,1"
|
|
bitfld.long 0x00 4.--7. "ATC,Analog Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTC,Digital Test Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x17C8++0x03
|
|
line.long 0x00 "DX8SLbPLLCR1,DAXT8 0-8 PLL Control Register 1 (Type B PLL Only)"
|
|
hexmask.long.word 0x00 22.--31. 1. "RESERVED_31_22,Reserved"
|
|
hexmask.long.word 0x00 6.--21. 1. "PLLPROG,Connects to the PLL PLL_PROG bus"
|
|
newline
|
|
bitfld.long 0x00 5. "BYPVREGCP,Bypass PLL vreg_cp" "0,1"
|
|
bitfld.long 0x00 4. "BYPVREGDIG,Bypass PLL vreg_dig" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "BYPVDD,PLL VDD voltage level control" "0,1"
|
|
bitfld.long 0x00 2. "LOCKPS,Lock Detector Phase Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "LOCKCS,Lock Detector Counter Select" "0,1"
|
|
bitfld.long 0x00 0. "LOCKDS,Lock Detector Select" "0,1"
|
|
wgroup.long 0x17CC++0x03
|
|
line.long 0x00 "DX8SLbPLLCR2,DAXT8 0-8 PLL Control Register 2 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_31_0,Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL"
|
|
wgroup.long 0x17D0++0x03
|
|
line.long 0x00 "DX8SLbPLLCR3,DAXT8 0-8 PLL Control Register 3 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_63_32,Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL"
|
|
wgroup.long 0x17D4++0x03
|
|
line.long 0x00 "DX8SLbPLLCR4,DAXT8 0-8 PLL Control Register 4 (Type B PLL Only)"
|
|
hexmask.long 0x00 0.--31. 1. "PLLCTRL_95_64,Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL"
|
|
wgroup.long 0x17D8++0x03
|
|
line.long 0x00 "DX8SLbPLLCR5,DAXT8 0-8 PLL Control Register 5 (Type B PLL Only)"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_31_8,Reserved"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PLLCTRL_103_96,Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL"
|
|
wgroup.long 0x17DC++0x03
|
|
line.long 0x00 "DX8SLbDQSCTL,DATX8 0-8 DQS Control Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "RRRMODE,Read Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "RESERVED_23_22,Reserved" "0,1,2,3"
|
|
bitfld.long 0x00 21. "WRRMODE,Write Path Rise-to-Rise Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. "DQSGX,DQS Gate Extension" "0,1,2,3"
|
|
bitfld.long 0x00 18. "LPPLLPD,Low Power PLL Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "LPIOPD,Low Power I/O Power Down" "0,1"
|
|
bitfld.long 0x00 15.--16. "RESERVED_16_15,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14. "QSCNTEN,QS Counter Enable" "0,1"
|
|
bitfld.long 0x00 13. "UDQIOM,Unused DQ I/O Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RESERVED_12_10,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--9. "DXSR,Data Slew Rate" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DQSNRES,DQS# Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "DQSRES,DQS Resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x17E0++0x03
|
|
line.long 0x00 "DX8SLbTRNCTL,DATX8 0-8 Training Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
wgroup.long 0x17E4++0x03
|
|
line.long 0x00 "DX8SLbDDLCTL,DATX8 0-8 DDL Control Register"
|
|
bitfld.long 0x00 27.--31. "RESERVED_31_27,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 26. "DLYLDTM,Delay Load Timing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DXDDLLDT,DX DDL Load Type" "0,1"
|
|
bitfld.long 0x00 23.--24. "RESERVED_24_23,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--22. "DXDDLLD,DATX8 DDL Delay Select Dymainc Load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 2.--17. 1. "DXDDLBYP,DATX8 DDL Bypass"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DDLBYPMODE,Controls DDL Bypass Mode" "0,1,2,3"
|
|
wgroup.long 0x17E8++0x03
|
|
line.long 0x00 "DX8SLbDXCTL1,DATX8 0-8 DX Control Register 1"
|
|
hexmask.long.byte 0x00 25.--31. 1. "RESERVED_31_25,Reserved"
|
|
bitfld.long 0x00 24. "DXCALCLK,DATX Calibration Clock Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "DXRCLKMD,DATX8 Read Clock Mode" "0,1"
|
|
bitfld.long 0x00 22. "RESERVED_22,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "DXDTOSEL,DATX8 Digital Test Output Select" "0,1,2,3"
|
|
bitfld.long 0x00 19. "DXGSMD,Read DQS Gating Status Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "DXQSDBYP,Read DQS/DQS# Delay Load Bypass Mode" "0,1"
|
|
bitfld.long 0x00 17. "DXGDBYP,Read DQS Gate Delay Load Bypass Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DXTMODE,DATX8 Test Mode" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RESERVED_15_0,Reserved"
|
|
wgroup.long 0x17EC++0x03
|
|
line.long 0x00 "DX8SLbDXCTL2,DATX8 0-8 DX Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESERVED_31_24,Reserved"
|
|
bitfld.long 0x00 23. "CRDEN,Configurable Read Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "POSOEX,OX Extension during Post-amble" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--19. "PREOEX,OE Extension during Pre-amble" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "RESERVED_17,Reserved" "0,1"
|
|
bitfld.long 0x00 16. "IOAG,I/O Assisted Gate Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "IOLB,I/O Loopback Select" "0,1"
|
|
bitfld.long 0x00 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "LPWAKEUP_THRSH,Low Power Wakeup Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. "RDBI,Read Data Bus Inversion Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "WDBI,Write Data Bus Inversion Enable" "0,1"
|
|
bitfld.long 0x00 6. "PRFBYP,PUB Read FIFO Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RDMODE,DATX8 Receive FIFO Read Mode" "0,1,2,3"
|
|
bitfld.long 0x00 3. "DISRST,Disables the Read FIFO Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "DQSGLB,Read DQS Gate I/O Loopback" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RESERVED_0,Reserved" "0,1"
|
|
wgroup.long 0x17F0++0x03
|
|
line.long 0x00 "DX8SLbIOCR,DATX8 0-8 I/O Configuration Register"
|
|
bitfld.long 0x00 31. "RESERVED_31,Reserved" "0,1"
|
|
bitfld.long 0x00 28.--30. "DXDACRANGE,PVREF_DAC REFSEL range select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 25.--27. "DXVREFIOM,IOM bits for PVREF PVREF_DAC and PVREFE cells in DX IO ring" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 22.--24. "DXIOM,DX IO Mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 11.--21. 1. "DXTXM,DX IO Transmitter Mode"
|
|
hexmask.long.word 0x00 0.--10. 1. "DXRXM,DX IO Receiver Mode"
|
|
wgroup.long 0x17F4++0x03
|
|
line.long 0x00 "DX4SLbIOCR,DATX4 0-8 I/O Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "RESERVED_31_0,Reserved"
|
|
tree.end
|
|
tree "DWC_ETHER_QOS (DWC_ether_qos)"
|
|
base ad:0x5B050000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MAC_CONFIGURATION,MAC Configuration Register"
|
|
bitfld.long 0x00 28.--30. "SARC,Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted packets" "0: mti_sa_ctrl_i and ati_sa_ctrl_i input signals..,?,2: Contents of MAC Addr-0 inserted in SA field,3: Contents of MAC Addr-0 replaces SA field,?,?,6: Contents of MAC Addr-1 inserted in SA field,7: Contents of MAC Addr-1 replaces SA field"
|
|
newline
|
|
bitfld.long 0x00 27. "IPC,Checksum Offload When set this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP UDP or ICMP payload checksum checking" "0: IP header/payload checksum checking is disabled,1: IP header/payload checksum checking is enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "IPG,Inter-Packet Gap These bits control the minimum IPG between packets during transmission" "0: 96 bit times IPG,1: 88 bit times IPG,2: 80 bit times IPG,3: 72 bit times IPG,4: 64 bit times IPG,5: 56 bit times IPG,6: 48 bit times IPG,7: 40 bit times IPG"
|
|
newline
|
|
bitfld.long 0x00 23. "GPSLCE,Giant Packet Size Limit Control Enable When this bit is set the MAC considers the value in GPSL field in MAC_EXT_CONFIGURATION register to declare a received packet as Giant packet" "0: Giant Packet Size Limit Control is disabled,1: Giant Packet Size Limit Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 22. "S2KP,IEEE 802" "0: Support upto 2K packet is disabled,1: Support upto 2K packet is Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CST,CRC stripping for Type packets When this bit is set the last four bytes (FCS) of all packets of Ether type (type field greater than 1 536) are stripped and dropped before forwarding the packet to the application" "0: CRC stripping for Type packets is disabled,1: CRC stripping for Type packets is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "ACS,Automatic Pad or CRC Stripping When this bit is set the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1 536 bytes" "0: Automatic Pad or CRC Stripping is disabled,1: Automatic Pad or CRC Stripping is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "WD,Watchdog Disable When this bit is set the MAC disables the watchdog timer on the receiver" "0: Watchdog is enabled,1: Watchdog is disabled"
|
|
newline
|
|
bitfld.long 0x00 18. "BE,Packet Burst Enable When this bit is set the MAC allows packet bursting during transmission in the GMII half-duplex mode" "0: Packet Burst is disabled,1: Packet Burst is enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "JD,Jabber Disable When this bit is set the MAC disables the jabber timer on the transmitter" "0: Jabber is enabled,1: Jabber is disabled"
|
|
newline
|
|
bitfld.long 0x00 16. "JE,Jumbo Packet Enable When this bit is set the MAC allows jumbo packets of 9 018 bytes (9 022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status" "0: Jumbo packet is disabled,1: Jumbo packet is enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "PS,Port Select This bit selects the Ethernet line speed" "0: For 1000 or 2500 Mbps operations,1: For 10 or 100 Mbps operations"
|
|
newline
|
|
bitfld.long 0x00 14. "FES,Speed This bit selects the speed mode" "0: 10 Mbps when PS bit is 1 and 1 Gbps when PS..,1: 100 Mbps when PS bit is 1 and 2.5 Gbps when.."
|
|
newline
|
|
bitfld.long 0x00 13. "DM,Duplex Mode When this bit is set the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously" "0: Half-duplex mode,1: Full-duplex mode"
|
|
newline
|
|
bitfld.long 0x00 12. "LM,Loopback Mode When this bit is set the MAC operates in the loopback mode at GMII or MII" "0: Loopback is disabled,1: Loopback is enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode" "0: ECRSFD is disabled,1: ECRSFD is enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "DO,Disable Receive Own When this bit is set the MAC disables the reception of packets when the gmii_txen_o is asserted in the half-duplex mode" "0: Enable Receive Own,1: Disable Receive Own"
|
|
newline
|
|
bitfld.long 0x00 9. "DCRS,Disable Carrier Sense During Transmission When this bit is set the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode" "0: Enable Carrier Sense During Transmission,1: Disable Carrier Sense During Transmission"
|
|
newline
|
|
bitfld.long 0x00 8. "DR,Disable Retry When this bit is set the MAC attempts only one transmission" "0: Enable Retry,1: Disable Retry"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "BL,Back-Off Limit The back-off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000/2500 Mbps 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after.." "0: k = min(n 10),1: k = min(n 8),2: k = min(n 4),3: k = min(n 1)"
|
|
newline
|
|
bitfld.long 0x00 4. "DC,Deferral Check When this bit is set the deferral check function is enabled in the MAC" "0: Deferral check function is disabled,1: Deferral check function is enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "PRELEN,Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "TE,Transmitter Enable When this bit is set the Tx state machine of the MAC is enabled for transmission on the GMII or MII interface" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "RE,Receiver Enable" "0: Receiver is disabled,1: Receiver is enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MAC_EXT_CONFIGURATION,MAC Extended Configuration Register"
|
|
bitfld.long 0x00 25.--29. "EIPG,Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 24. "EIPGEN,Extended Inter-Packet Gap Enable When this bit is set the MAC interprets EIPG field and IPG field in CONFIGURATION register together as minimum IPG greater than 96 bit times in steps of 8 bit times" "0: Extended Inter-Packet Gap is disabled,1: Extended Inter-Packet Gap is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "PDC,Packet Duplication Control When this bit is set the received packet with Multicast/Broadcast Destination address is routed to multiple Receive DMA Channels" "0: Packet Duplication Control is disabled,1: Packet Duplication Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "USP,Unicast Slow Protocol Packet Detect When this bit is set the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC_ADDRESS0_HIGH and MAC_ADDRESS0_LOW registers" "0: Unicast Slow Protocol Packet Detection is..,1: Unicast Slow Protocol Packet Detection is.."
|
|
newline
|
|
bitfld.long 0x00 17. "SPEN,Slow Protocol Detection Enable When this bit is set MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Rx status" "0: Slow Protocol Detection is disabled,1: Slow Protocol Detection is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "DCRCC,Disable CRC Checking for Received Packets When this bit is set the MAC receiver does not check the CRC field in the received packets" "0: CRC Checking is enabled,1: CRC Checking is disabled"
|
|
newline
|
|
hexmask.long.word 0x00 0.--13. 1. "GPSL,Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes the MAC declares the received packet as Giant packet"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MAC_PACKET_FILTER,MAC_Packet_Filter"
|
|
bitfld.long 0x00 31. "RA,Receive All When this bit is set the MAC Receiver module passes all received packets to the application irrespective of whether they pass the address filter or not" "0: Receive All is disabled,1: Receive All is enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "DNTU,Drop Non-TCP/UDP over IP Packets When this bit is set the MAC drops the non-TCP or UDP over IP packets" "0: Forward Non-TCP/UDP over IP Packets,1: Drop Non-TCP/UDP over IP Packets"
|
|
newline
|
|
bitfld.long 0x00 20. "IPFE,Layer 3 and Layer 4 Filter Enable When this bit is set the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters" "0: Layer 3 and Layer 4 Filters are disabled,1: Layer 3 and Layer 4 Filters are enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "VTFE,VLAN Tag Filter Enable When this bit is set the MAC drops the VLAN tagged packets that do not match the VLAN Tag" "0: VLAN Tag Filter is disabled,1: VLAN Tag Filter is enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "HPF,Hash or Perfect Filter When this bit is set the address filter passes a packet if it matches either the perfect filtering or hash filtering as set by the HMC or HUC bit" "0: Hash or Perfect Filter is disabled,1: Hash or Perfect Filter is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "SAF,Source Address Filter Enable When this bit is set the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers" "0: SA Filtering is disabled,1: SA Filtering is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "SAIF,SA Inverse Filtering When this bit is set the Address Check block operates in the inverse filtering mode for SA address comparison" "0: SA Inverse Filtering is disabled,1: SA Inverse Filtering is enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PCF,Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets)" "0: MAC filters all control packets from reaching..,1: MAC forwards all control packets except Pause..,2: MAC forwards all control packets to the..,3: MAC forwards the control packets that pass.."
|
|
newline
|
|
bitfld.long 0x00 5. "DBF,Disable Broadcast Packets When this bit is set the AFM module blocks all incoming broadcast packets" "0: Enable Broadcast Packets,1: Disable Broadcast Packets"
|
|
newline
|
|
bitfld.long 0x00 4. "PM,Pass All Multicast When this bit is set it indicates that all received packets with a multicast destination address (first bit in the destination address field is '1') are passed" "0: Pass All Multicast is disabled,1: Pass All Multicast is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "DAIF,DA Inverse Filtering When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets" "0: DA Inverse Filtering is disabled,1: DA Inverse Filtering is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HMC,Hash Multicast When this bit is set the MAC performs the destination address filtering of received multicast packets according to the hash table" "0: Hash Multicast is disabled,1: Hash Multicast is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "HUC,Hash Unicast When this bit is set the MAC performs the destination address filtering of unicast packets according to the hash table" "0: Hash Unicast is disabled,1: Hash Unicast is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PR,Promiscuous Mode When this bit is set the Address Filtering module passes all incoming packets irrespective of the destination or source address" "0: Promiscuous Mode is disabled,1: Promiscuous Mode is enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MAC_WATCHDOG_TIMEOUT,Watchdog Timeout"
|
|
bitfld.long 0x00 8. "PWE,Programmable Watchdog Enable When this bit is set and the WD bit of the MAC_CONFIGURATION register is reset the WTO field is used as watchdog timeout for a received packet" "0: Programmable Watchdog is disabled,1: Programmable Watchdog is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "WTO,Watchdog Timeout When the PWE bit is set and the WD bit of the MAC_CONFIGURATION register is reset this field is used as watchdog timeout for a received packet" "0: bf_2KBYTES,1: bf_3KBYTES,2: bf_4KBYTES,3: bf_5KBYTES,4: bf_6KBYTES,5: bf_7KBYTES,6: bf_8KBYTES,7: bf_9KBYTES,8: bf_10KBYTES,9: bf_11KBYTES,10: bf_12KBYTES,11: bf_13KBYTES,12: bf_14KBYTES,13: bf_15KBYTES,14: bf_16383BYTES,?..."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MAC_HASH_TABLE_REG0,MAC Hash Table Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MAC_HASH_TABLE_REG1,MAC Hash Table Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MAC_VLAN_TAG_CTRL,MAC VLAN Tag Control"
|
|
bitfld.long 0x00 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status When this bit is set the MAC provides the inner VLAN Tag in the Rx status" "0: Inner VLAN Tag in Rx status is disabled,1: Inner VLAN Tag in Rx status is enabled"
|
|
newline
|
|
bitfld.long 0x00 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
|
|
newline
|
|
bitfld.long 0x00 27. "ERIVLT,ERIVLT" "0: Inner VLAN tag is disabled,1: Inner VLAN tag is enabled"
|
|
newline
|
|
bitfld.long 0x00 26. "EDVLP,Enable Double VLAN Processing When this bit is set the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present)" "0: Double VLAN Processing is disabled,1: Double VLAN Processing is enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "VTHM,VLAN Tag Hash Table Match Enable When this bit is set the most significant four bits of CRC of VLAN Tag (ones-complement of most significant four bits of CRC of VLAN Tag when ETV bit is reset) are used to index the content of the.." "0: VLAN Tag Hash Table Match is disabled,1: VLAN Tag Hash Table Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 24. "EVLRXS,Enable VLAN Tag in Rx status When this bit is set MAC provides the outer VLAN Tag in the Rx status" "0: VLAN Tag in Rx status is disabled,1: VLAN Tag in Rx status is enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
|
|
newline
|
|
bitfld.long 0x00 18. "ESVL,Enable S-VLAN When this bit is set the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets" "0: S-VLAN is disabled,1: S-VLAN is enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "VTIM,VLAN Tag Inverse Match Enable When this bit is set this bit enables the VLAN Tag inverse matching" "0: VLAN Tag Inverse Match is disabled,1: VLAN Tag Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--6. "OFS,Offset This field holds the address offset of the MAC VLAN Tag Filter Register which the application is trying to access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 1. "CT,Command Type This bit indicates if the current register access is a read or a" "0: Write operation,1: Read operation"
|
|
newline
|
|
bitfld.long 0x00 0. "OB,Operation Busy This bit is set along with a read or write command for initiating the indirect access to per VLAN Tag Filter register" "0: Operation Busy is disabled,1: Operation Busy is enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MAC_VLAN_TAG_DATA,MAC VLAN Tag Data"
|
|
bitfld.long 0x00 25.--27. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled"
|
|
newline
|
|
bitfld.long 0x00 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison"
|
|
newline
|
|
bitfld.long 0x00 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MAC_VLAN_HASH_TABLE,MAC VLAN Hash Table"
|
|
hexmask.long.word 0x00 0.--15. 1. "VLHT,VLAN Hash Table This field contains the 16-bit VLAN Hash Table"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MAC_VLAN_INCL,VLAN Tag Inclusion or Replacement"
|
|
rbitfld.long 0x00 31. "BUSY,Busy This bit indicates the status of the read/write operation of indirect access to the queue/channel specific VLAN inclusion register" "0: Busy status not detected,1: Busy status detected"
|
|
newline
|
|
bitfld.long 0x00 30. "RDWR,Read write control This bit controls the read or write operation for indirectly accessing the queue/channel specific VLAN Inclusion register" "0: Read operation of indirect access,1: Write operation of indirect access"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "ADDR,Address This field selects one of the queue/channel specific VLAN Inclusion register for read/write access" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "CBTI,Channel based tag insertion When this bit is set outer VLAN tag is inserted for every packets transmitted by the MAC" "0: Channel based tag insertion is disabled,1: Channel based tag insertion is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted or replaced,1: S-VLAN type (0x88A8) is inserted or replaced"
|
|
newline
|
|
bitfld.long 0x00 18. "VLP,VLAN Priority Control When this bit is set the control bits[17:16] are used for VLAN deletion insertion or replacement" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "MAC_INNER_VLAN_INCL,MAC Inner VLAN Tag Inclusion or Replacement"
|
|
bitfld.long 0x00 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted"
|
|
newline
|
|
bitfld.long 0x00 18. "VLP,VLAN Priority Control When this bit is set the VLC field is used for VLAN deletion insertion or replacement" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MAC_Q0_TX_FLOW_CTRL,MAC Q0 Tx Flow Control"
|
|
hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet"
|
|
newline
|
|
bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable Full-Duplex Mode: In the full-duplex mode when this bit is set the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.."
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "MAC_Q1_TX_FLOW_CTRL,MAC Q1 Tx Flow Control"
|
|
hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet"
|
|
newline
|
|
bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.."
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "MAC_Q2_TX_FLOW_CTRL,MAC Q2 Tx Flow Control"
|
|
hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet"
|
|
newline
|
|
bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.."
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "MAC_Q3_TX_FLOW_CTRL,MAC Q3 Tx Flow Control"
|
|
hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet"
|
|
newline
|
|
bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.."
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MAC_Q4_TX_FLOW_CTRL,MAC Q0 Tx Flow Control"
|
|
hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet"
|
|
newline
|
|
bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "MAC_RX_FLOW_CTRL,MAC Rx Flow Control"
|
|
bitfld.long 0x00 8. "PFCE,Priority Based Flow Control Enable When this bit is set it enables generation and reception of priority-based flow control (PFC) packets" "0: Priority Based Flow Control is disabled,1: Priority Based Flow Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "UP,Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802" "0: Unicast Pause Packet Detect disabled,1: Unicast Pause Packet Detect enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "RFE,Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time" "0: Receive Flow Control is disabled,1: Receive Flow Control is enabled"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "MAC_RXQ_CTRL4,Receive Queue Control 4"
|
|
bitfld.long 0x00 17.--19. "VFFQ,VLAN Tag Filter Fail Packets Queue This field holds the Rx queue number to which the tagged packets failing the Destination or Source Address filter (and UFFQE/MFFQE not enabled) or failing the VLAN tag filter must be routed to" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable When this bit is set the tagged packets which fail the Destination or Source address filter or fail the VLAN tag filter are routed to the Rx Queue Number programmed in the VFFQ" "0: VLAN tag Filter Fail Packets Queuing is..,1: VLAN tag Filter Fail Packets Queuing is enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "MFFQ,Multicast Address Filter Fail Packets Queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable" "0: Multicast Address Filter Fail Packets Queuing..,1: Multicast Address Filter Fail Packets Queuing.."
|
|
newline
|
|
bitfld.long 0x00 1.--3. "UFFQ,Unicast Address Filter Fail Packets Queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable" "0: Unicast Address Filter Fail Packets Queuing..,1: Unicast Address Filter Fail Packets Queuing.."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "MAC_TXQ_PRTY_MAP0,Transmit Queue Priority Mapping 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PSTQ3,Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "PSTQ2,Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "PSTQ1,Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PSTQ0,Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "MAC_TXQ_PRTY_MAP1,Transmit Queue Priority Mapping 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PSTQ4,Priorities Selected in Transmit Queue 4 This field holds the priorities assigned to Tx Queue 4 by the software"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "MAC_RXQ_CTRL0,Receive Queue Control 0"
|
|
bitfld.long 0x00 8.--9. "RXQ4EN,Receive Queue 4 Enable This field is similar to the RXQ0EN field" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RXQ3EN,Receive Queue 3 Enable This field is similar to the RXQ0EN field" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RXQ2EN,Receive Queue 2 Enable This field is similar to the RXQ0EN field" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RXQ1EN,Receive Queue 1 Enable This field is similar to the RXQ0EN field" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RXQ0EN,Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "MAC_RXQ_CTRL1,Receive Queue Control 1"
|
|
bitfld.long 0x00 24.--26. "FPRQ,Frame Preemption Residue Queue This field holds the Rx queue number to which the residual preemption frames must be forwarded" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 21. "TACPQE,Tagged AV Control Packets Queuing Enable" "0: Tagged AV Control Packets Queuing is disabled,1: Tagged AV Control Packets Queuing is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "MCBCQEN,Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed to Rx Queue specified in MCBCQ field" "0: Multicast and Broadcast Queue is disabled,1: Multicast and Broadcast Queue is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "MCBCQ,Multicast and Broadcast Queue This field specifies the Rx Queue onto which Multicast or Broadcast Packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "UPQ,Untagged Packet Queue This field indicates the Rx Queue to which Untagged Packets are to be routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "DCBCPQ,DCB Control Packets Queue This field specifies the Rx queue on which the received DCB control packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "PTPQ,PTP Packets Queue This field specifies the Rx queue on which the PTP packets sent over the Ethernet payload (not over IPv4 or IPv6) are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "AVCPQ,AV Untagged Control Packets Queue This field specifies the Receive queue on which the received AV tagged and untagged control packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "MAC_RXQ_CTRL2,Receive Queue Control 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PSRQ3,Priorities Selected in the Receive Queue 3 This field decides the priorities assigned to Rx Queue 3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2 This field decides the priorities assigned to Rx Queue 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1 This field decides the priorities assigned to Rx Queue 1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0 This field decides the priorities assigned to Rx Queue 0"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "MAC_RXQ_CTRL3,Receive Queue Control 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PSRQ4,Priorities Selected in the Receive Queue 4 This field decides the priorities assigned to Rx Queue 4"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "MAC_INTERRUPT_STATUS,Interrupt Status"
|
|
bitfld.long 0x00 20. "MFRIS,MMC FPE Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Receive Interrupt Register" "0: MMC FPE Receive Interrupt status not active,1: MMC FPE Receive Interrupt status active"
|
|
newline
|
|
bitfld.long 0x00 19. "MFTIS,MMC FPE Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Transmit Interrupt Register" "0: MMC FPE Transmit Interrupt status not active,1: MMC FPE Transmit Interrupt status active"
|
|
newline
|
|
bitfld.long 0x00 18. "MDIOIS,MDIO Interrupt Status This bit indicates an interrupt event after the completion of MDIO operation" "0: MDIO Interrupt status not active,1: MDIO Interrupt status active"
|
|
newline
|
|
bitfld.long 0x00 17. "FPEIS,Frame Preemption Interrupt Status This bit indicates an interrupt event during the operation of Frame Preemption (Bits[19:16] of MAC_FPE_CTRL_STS register is set)" "0: Frame Preemption Interrupt status not active,1: Frame Preemption Interrupt status active"
|
|
newline
|
|
bitfld.long 0x00 14. "RXSTSIS,Receive Status Interrupt This bit indicates the status of received packets" "0: Receive Interrupt status not active,1: Receive Interrupt status active"
|
|
newline
|
|
bitfld.long 0x00 13. "TXSTSIS,Transmit Status Interrupt This bit indicates the status of transmitted packets" "0: Transmit Interrupt status not active,1: Transmit Interrupt status active"
|
|
newline
|
|
bitfld.long 0x00 12. "TSIS,Timestamp Interrupt Status If the Timestamp feature is enabled this bit is set when any of the following conditions is true: - The system time value is equal to or exceeds the value specified in the Target Time High and Low registers" "0: Timestamp Interrupt status not active,1: Timestamp Interrupt status active"
|
|
newline
|
|
bitfld.long 0x00 11. "MMCRXIPIS,MMC Receive Checksum Offload Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register" "0: MMC Receive Checksum Offload Interrupt status..,1: MMC Receive Checksum Offload Interrupt status.."
|
|
newline
|
|
bitfld.long 0x00 10. "MMCTXIS,MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register" "0: MMC Transmit Interrupt status not active,1: MMC Transmit Interrupt status active"
|
|
newline
|
|
bitfld.long 0x00 9. "MMCRXIS,MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register" "0: MMC Receive Interrupt status not active,1: MMC Receive Interrupt status active"
|
|
newline
|
|
bitfld.long 0x00 8. "MMCIS,MMC Interrupt Status This bit is set high when Bit 11 Bit 10 or Bit 9 is set high" "0: MMC Interrupt status not active,1: MMC Interrupt status active"
|
|
newline
|
|
bitfld.long 0x00 5. "LPIIS,LPI Interrupt Status When the Energy Efficient Ethernet feature is enabled this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver" "0: LPI Interrupt status not active,1: LPI Interrupt status active"
|
|
newline
|
|
bitfld.long 0x00 4. "PMTIS,PMT Interrupt Status This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in MAC_PMT_CONTROL_STATUS register)" "0: PMT Interrupt status not active,1: PMT Interrupt status active"
|
|
newline
|
|
bitfld.long 0x00 3. "PHYIS,PHY Interrupt This bit is set when rising edge is detected on the phy_intr_i input" "0: PHY Interrupt not detected,1: PHY Interrupt detected"
|
|
newline
|
|
bitfld.long 0x00 0. "RGSMIIIS,RGMII or SMII Interrupt Status This bit is set because of any change in value of the Link Status of RGMII or SMII interface (LNKSTS bit in MAC_PHYIF_CONTROL_STATUS register)" "0: RGMII or SMII Interrupt Status is not active,1: RGMII or SMII Interrupt Status is active"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "MAC_INTERRUPT_ENABLE,Interrupt Enable"
|
|
bitfld.long 0x00 18. "MDIOIE,MDIO Interrupt Enable When this bit is set it enables the assertion of the interrupt when MDIOIS field is set in the MAC_INTERRUPT_STATUS register" "0: MDIO Interrupt is disabled,1: MDIO Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "FPEIE,Frame Preemption Interrupt Enable When this bit is set it enables the assertion of the interrupt when FPEIS field is set in the MAC_INTERRUPT_STATUS" "0: Frame Preemption Interrupt is disabled,1: Frame Preemption Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 14. "RXSTSIE,Receive Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[RXSTSIS]" "0: Receive Status Interrupt is disabled,1: Receive Status Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "TXSTSIE,Transmit Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TXSTSIS]" "0: Timestamp Status Interrupt is disabled,1: Timestamp Status Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "TSIE,Timestamp Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TSIS]" "0: Timestamp Interrupt is disabled,1: Timestamp Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "LPIIE,LPI Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[LPIIS]" "0: LPI Interrupt is disabled,1: LPI Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "PMTIE,PMT Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[PMTIS]" "0: PMT Interrupt is disabled,1: PMT Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "PHYIE,PHY Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of MAC_INTERRUPT_STATUS[PHYIS]" "0: PHY Interrupt is disabled,1: PHY Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "RGSMIIIE,RGMII or SMII Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RGSMIIIS bit in MAC_INTERRUPT_STATUS register" "0: RGMII or SMII Interrupt is disabled,1: RGMII or SMII Interrupt is enabled"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "MAC_RX_TX_STATUS,Receive Transmit Status"
|
|
bitfld.long 0x00 8. "RWT,Receive Watchdog Timeout This bit is set when a packet with length greater than 2 048 bytes is received (10 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_CONFIGURATION register" "0: No receive watchdog timeout,1: Receive watchdog timed out"
|
|
newline
|
|
bitfld.long 0x00 5. "EXCOL,Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet" "0: No collision,1: Excessive collision is sensed"
|
|
newline
|
|
bitfld.long 0x00 4. "LCOL,Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode 512 bytes.." "0: No collision,1: Late collision is sensed"
|
|
newline
|
|
bitfld.long 0x00 3. "EXDEF,Excessive Deferral When the DTXSTS bit is set in the MAC_OPERATION_MODE register and the DC bit is set in the MAC_CONFIGURATION register this bit indicates that the transmission ended because of excessive deferral of over 24 288 bit times (155 680.." "0: No Excessive deferral,1: Excessive deferral"
|
|
newline
|
|
bitfld.long 0x00 2. "LCARR,Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register this bit indicates that the loss of carrier occurred during packet transmission that is the phy_crs_i signal was inactive for one or more transmission clock periods.." "0: Carrier is present,1: Loss of carrier"
|
|
newline
|
|
bitfld.long 0x00 1. "NCARR,No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission" "0: Carrier is present,1: No carrier"
|
|
newline
|
|
bitfld.long 0x00 0. "TJT,Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2 048 bytes (10 240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_CONFIGURATION register" "0: No Transmit Jabber Timeout,1: Transmit Jabber Timeout occurred"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "MAC_PMT_CONTROL_STATUS,PMT Control and Status"
|
|
bitfld.long 0x00 31. "RWKFILTRST,Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set the remote wake-up packet filter register pointer is reset to 3'b000" "0: Remote Wake-Up Packet Filter Register Pointer..,1: Remote Wake-Up Packet Filter Register Pointer.."
|
|
newline
|
|
rbitfld.long 0x00 24.--28. "RWKPTR,Remote Wake-up FIFO Pointer This field gives the current value (0 to 7 15 or 31 when 4 8 or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter register pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 10. "RWKPFE,Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN the MAC receiver drops all received frames until it receives the expected Wake-up frame" "0: Remote Wake-up Packet Forwarding is disabled,1: Remote Wake-up Packet Forwarding is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "GLBLUCAST,Global Unicast When this bit set any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wake-up packet" "0: Global unicast is disabled,1: Global unicast is enabled"
|
|
newline
|
|
rbitfld.long 0x00 6. "RWKPRCVD,Remote Wake-Up Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a remote wake-up packet" "0: Remote wake-up packet is received,1: Remote wake-up packet is received"
|
|
newline
|
|
rbitfld.long 0x00 5. "MGKPRCVD,Magic Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a magic packet" "0: No Magic packet is received,1: Magic packet is received"
|
|
newline
|
|
bitfld.long 0x00 2. "RWKPKTEN,Remote Wake-Up Packet Enable When this bit is set a power management event is generated when the MAC receives a remote wake-up packet" "0: Remote wake-up packet is disabled,1: Remote wake-up packet is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "MGKPKTEN,Magic Packet Enable When this bit is set a power management event is generated when the MAC receives a magic packet" "0: Magic Packet is disabled,1: Magic Packet is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PWRDWN,Power Down When this bit is set the MAC receiver drops all received packets until it receives the expected magic packet or remote wake-up packet" "0: Power down is disabled,1: Power down is enabled"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "MAC_RWK_PACKET_FILTER,Remote Wakeup Filter"
|
|
hexmask.long 0x00 0.--31. 1. "WKUPFRMFTR,RWK Packet Filter This field contains the various controls of RWK Packet filter"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "MAC_LPI_CONTROL_STATUS,LPI Control and Status"
|
|
bitfld.long 0x00 21. "LPITCSE,LPI Tx Clock Stop Enable When this bit is set the MAC asserts sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped" "0: LPI Tx Clock Stop is disabled,1: LPI Tx Clock Stop is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "LPIATE,LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state" "0: LPI Timer is disabled,1: LPI Timer is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "LPITXA,LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side" "0: LPI Tx Automate is disabled,1: LPI Tx Automate is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "PLSEN,PHY Link Status Enable This bit enables the link status received on the RGMII SGMII or SMII Receive paths to be used for activating the LPI LS TIMER" "0: PHY Link Status is disabled,1: PHY Link Status is enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "PLS,PHY Link Status This bit indicates the link status of the PHY" "0: link is down,1: link is okay (UP)"
|
|
newline
|
|
bitfld.long 0x00 16. "LPIEN,LPI Enable When this bit is set it instructs the MAC Transmitter to enter the LPI state" "0: LPI state is disabled,1: LPI state is enabled"
|
|
newline
|
|
rbitfld.long 0x00 9. "RLPIST,Receive LPI State When this bit is set it indicates that the MAC is receiving the LPI pattern on the GMII or MII interface" "0: Receive LPI state not detected,1: Receive LPI state detected"
|
|
newline
|
|
rbitfld.long 0x00 8. "TLPIST,Transmit LPI State When this bit is set it indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface" "0: Transmit LPI state not detected,1: Transmit LPI state detected"
|
|
newline
|
|
rbitfld.long 0x00 3. "RLPIEX,Receive LPI Exit When this bit is set it indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface exited the LPI state and resumed the normal reception" "0: Receive LPI exit not detected,1: Receive LPI exit detected"
|
|
newline
|
|
rbitfld.long 0x00 2. "RLPIEN,Receive LPI Entry When this bit is set it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state" "0: Receive LPI entry not detected,1: Receive LPI entry detected"
|
|
newline
|
|
rbitfld.long 0x00 1. "TLPIEX,Transmit LPI Exit When this bit is set it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired" "0: Transmit LPI exit not detected,1: Transmit LPI exit detected"
|
|
newline
|
|
rbitfld.long 0x00 0. "TLPIEN,Transmit LPI Entry When this bit is set it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit" "0: Transmit LPI entry not detected,1: Transmit LPI entry detected"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "MAC_LPI_TIMERS_CONTROL,LPI Timers Control"
|
|
hexmask.long.word 0x00 16.--25. 1. "LST,LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "TWT,LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "MAC_LPI_ENTRY_TIMER,Tx LPI Entry Timer Control"
|
|
hexmask.long.tbyte 0x00 3.--19. 1. "LPIET,LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI mode after it has transmitted all the frames"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "MAC_ONEUS_TIC_COUNTER,One-microsecond Reference Timer"
|
|
hexmask.long.word 0x00 0.--11. 1. "TIC_1US_CNTR,1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "MAC_PHYIF_CONTROL_STATUS,PHY Interface Control and Status"
|
|
rbitfld.long 0x00 19. "LNKSTS,Link Status This bit indicates whether the link is up (1'b1) or down (1'b0)" "0: Link down,1: Link up"
|
|
newline
|
|
rbitfld.long 0x00 17.--18. "LNKSPEED,Link Speed This bit indicates the current speed of the link" "0: bf_2500K,1: bf_25M,2: bf_125M,?..."
|
|
newline
|
|
rbitfld.long 0x00 16. "LNKMOD,Link Mode This bit indicates the current mode of operation of the link" "0: Half-duplex mode,1: Full-duplex mode"
|
|
newline
|
|
bitfld.long 0x00 1. "LUD,Link Up or Down This bit indicates whether the link is up or down during transmission of configuration in the RGMII SGMII or SMII interface" "0: Link down,1: Link up"
|
|
newline
|
|
bitfld.long 0x00 0. "TC,Transmit Configuration in RGMII SGMII or SMII When set this bit enables the transmission of duplex mode link speed and link up or down information to the PHY in the RGMII SMII or SGMII port" "0: Disable Transmit Configuration in RGMII SGMII..,1: Enable Transmit Configuration in RGMII SGMII.."
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "MAC_VERSION,MAC Version"
|
|
hexmask.long.byte 0x00 8.--15. 1. "USERVER,User-defined Version (configured with coreConsultant)"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "SNPSVER,Synopsys-defined Version"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "MAC_DEBUG,MAC Debug"
|
|
bitfld.long 0x00 17.--18. "TFCSTS,MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module" "0: Idle state,1: Waiting for one of the following,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission"
|
|
newline
|
|
bitfld.long 0x00 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and it is not in the Idle state" "0: MAC GMII or MII Transmit Protocol Engine..,1: MAC GMII or MII Transmit Protocol Engine.."
|
|
newline
|
|
bitfld.long 0x00 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status When this bit is set this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII receive protocol engine is actively receiving data and it is not in the Idle state" "0: MAC GMII or MII Receive Protocol Engine..,1: MAC GMII or MII Receive Protocol Engine.."
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "MAC_HW_FEATURE0,Optional Features or Functions 0"
|
|
bitfld.long 0x00 28.--30. "ACTPHYSEL,Active PHY Selected When you have multiple PHY interfaces in your configuration this field indicates the sampled value of phy_intf_sel_i during reset de-assertion" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,7: REVMIII"
|
|
newline
|
|
bitfld.long 0x00 27. "SAVLANINS,Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected" "0: Source Address or VLAN Insertion Enable..,1: Source Address or VLAN Insertion Enable.."
|
|
newline
|
|
bitfld.long 0x00 25.--26. "TSSTSSEL,Timestamp System Time Source This bit indicates the source of the Timestamp system time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: Internal,1: External,2: BOTH,?..."
|
|
newline
|
|
bitfld.long 0x00 24. "MACADR64SEL,MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected" "0: MAC Addresses 64-127 Select option is not..,1: MAC Addresses 64-127 Select option is selected"
|
|
newline
|
|
bitfld.long 0x00 23. "MACADR32SEL,MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected" "0: MAC Addresses 32-63 Select option is not..,1: MAC Addresses 32-63 Select option is selected"
|
|
newline
|
|
bitfld.long 0x00 18.--22. "ADDMACADRSEL,MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is selected for Enable Additional 1-31 MAC Address Registers option" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16. "RXCOESEL,Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected" "0: Receive Checksum Offload Enable option is not..,1: Receive Checksum Offload Enable option is.."
|
|
newline
|
|
bitfld.long 0x00 14. "TXCOESEL,Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected" "0: Transmit Checksum Offload Enable option is..,1: Transmit Checksum Offload Enable option is.."
|
|
newline
|
|
bitfld.long 0x00 13. "EEESEL,Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected" "0: Energy Efficient Ethernet Enable option is..,1: Energy Efficient Ethernet Enable option is.."
|
|
newline
|
|
bitfld.long 0x00 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: IEEE 1588-2008 Timestamp Enable option is not..,1: IEEE 1588-2008 Timestamp Enable option is.."
|
|
newline
|
|
bitfld.long 0x00 9. "ARPOFFSEL,ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected" "0: ARP Offload Enable option is not selected,1: ARP Offload Enable option is selected"
|
|
newline
|
|
bitfld.long 0x00 8. "MMCSEL,RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected" "0: RMON Module Enable option is not selected,1: RMON Module Enable option is selected"
|
|
newline
|
|
bitfld.long 0x00 7. "MGKSEL,PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected" "0: PMT Magic Packet Enable option is not selected,1: PMT Magic Packet Enable option is selected"
|
|
newline
|
|
bitfld.long 0x00 6. "RWKSEL,PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected" "0: PMT Remote Wake-up Packet Enable option is..,1: PMT Remote Wake-up Packet Enable option is.."
|
|
newline
|
|
bitfld.long 0x00 5. "SMASEL,SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected" "0: SMA (MDIO) Interface not selected,1: SMA (MDIO) Interface selected"
|
|
newline
|
|
bitfld.long 0x00 4. "VLHASH,VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected" "0: VLAN Hash Filter not selected,1: VLAN Hash Filter selected"
|
|
newline
|
|
bitfld.long 0x00 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface) This bit is set to 1 when the TBI SGMII or RTBI PHY interface option is selected" "0: No PCS Registers (TBI SGMII or RTBI PHY..,1: PCS Registers (TBI SGMII or RTBI PHY interface)"
|
|
newline
|
|
bitfld.long 0x00 2. "HDSEL,Half-duplex Support This bit is set to 1 when the half-duplex mode is selected" "0: No Half-duplex support,1: Half-duplex support"
|
|
newline
|
|
bitfld.long 0x00 1. "GMIISEL,1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation" "0: No 1000 Mbps support,1: 1000 Mbps support"
|
|
newline
|
|
bitfld.long 0x00 0. "MIISEL,10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation" "0: No 10 or 100 Mbps support,1: 10 or 100 Mbps support"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "MAC_HW_FEATURE1,Optional Features or Functions 1"
|
|
bitfld.long 0x00 27.--30. "L3L4FNUM,Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters" "0: No L3 or L4 Filter,1: 1 L3 or L4 Filter,2: 2 L3 or L4 Filters,3: 3 L3 or L4 Filters,4: 4 L3 or L4 Filters,5: 5 L3 or L4 Filters,6: 6 L3 or L4 Filters,7: 7 L3 or L4 Filters,8: 8 L3 or L4 Filters,?..."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "HASHTBLSZ,Hash Table Size This field indicates the size of the hash table" "0: No hash table,1: bf_64,2: bf_128,3: bf_256"
|
|
newline
|
|
bitfld.long 0x00 23. "POUOST,One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One step timestamp for PTP over UDP/IP feature is selected" "0: One Step for PTP over UDP/IP Feature is not..,1: One Step for PTP over UDP/IP Feature is.."
|
|
newline
|
|
bitfld.long 0x00 21. "RAVSEL,Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected" "0: Rx Side Only AV Feature is not selected,1: Rx Side Only AV Feature is selected"
|
|
newline
|
|
bitfld.long 0x00 20. "AVSEL,AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected" "0: AV Feature is not selected,1: AV Feature is selected"
|
|
newline
|
|
bitfld.long 0x00 19. "DBGMEMA,DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected" "0: DMA Debug Registers option is not selected,1: DMA Debug Registers option is selected"
|
|
newline
|
|
bitfld.long 0x00 18. "TSOEN,TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected" "0: TCP Segmentation Offload Feature is not..,1: TCP Segmentation Offload Feature is selected"
|
|
newline
|
|
bitfld.long 0x00 17. "SPHEN,Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected" "0: Split Header Feature is not selected,1: Split Header Feature is selected"
|
|
newline
|
|
bitfld.long 0x00 16. "DCBEN,DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected" "0: DCB Feature is not selected,1: DCB Feature is selected"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "ADDR64,Address Width" "0: bf_32,1: bf_40,2: bf_48,?..."
|
|
newline
|
|
bitfld.long 0x00 13. "ADVTHWORD,IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected" "0: IEEE 1588 High Word Register option is not..,1: IEEE 1588 High Word Register option is selected"
|
|
newline
|
|
bitfld.long 0x00 12. "PTOEN,PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected" "0: PTP Offload feature is not selected,1: PTP Offload feature is selected"
|
|
newline
|
|
bitfld.long 0x00 11. "OSTEN,One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected" "0: One-Step Timestamping feature is not selected,1: One-Step Timestamping feature is selected"
|
|
newline
|
|
bitfld.long 0x00 6.--10. "TXFIFOSIZE,MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(TXFIFO_SIZE) -7" "0: 128 bytes,1: 256 bytes,2: 512 bytes,3: 1024 bytes,4: 2048 bytes,5: 4096 bytes,6: 8192 bytes,7: 16384 bytes,8: bf_32KB,9: bf_64KB,10: bf_128KB,?..."
|
|
newline
|
|
bitfld.long 0x00 5. "SPRAM,Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected" "0: Single Port RAM feature is not selected,1: Single Port RAM feature is selected"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "RXFIFOSIZE,MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(RXFIFO_SIZE) -7" "0: 128 bytes,1: 256 bytes,2: 512 bytes,3: 1024 bytes,4: 2048 bytes,5: 4096 bytes,6: 8192 bytes,7: 16384 bytes,8: bf_32KB,9: bf_64KB,10: bf_128KB,11: bf_256KB,?..."
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MAC_HW_FEATURE2,Optional Features or Functions 2"
|
|
bitfld.long 0x00 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary input,3: 3 auxiliary input,4: 4 auxiliary input,?..."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PPSOUTNUM,Number of PPS Outputs This field indicates the number of PPS outputs" "0: No PPS output,1: 1 PPS output,2: 2 PPS output,3: 3 PPS output,4: 4 PPS output,?..."
|
|
newline
|
|
bitfld.long 0x00 18.--21. "TXCHCNT,Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels" "0: 1 MTL Tx Channel,1: 2 MTL Tx Channels,2: 3 MTL Tx Channels,3: 4 MTL Tx Channels,4: 5 MTL Tx Channels,5: 6 MTL Tx Channels,6: 7 MTL Tx Channels,7: 8 MTL Tx Channels,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "RXCHCNT,Number of DMA Receive Channels This field indicates the number of DMA Receive channels" "0: 1 MTL Rx Channel,1: 2 MTL Rx Channels,2: 3 MTL Rx Channels,3: 4 MTL Rx Channels,4: 5 MTL Rx Channels,5: 6 MTL Rx Channels,6: 7 MTL Rx Channels,7: 8 MTL Rx Channels,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--9. "TXQCNT,Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues" "0: 1 MTL Tx Queue,1: 2 MTL Tx Queues,2: 3 MTL Tx Queues,3: 4 MTL Tx Queues,4: 5 MTL Tx Queues,5: 6 MTL Tx Queues,6: 7 MTL Tx Queues,7: 8 MTL Tx Queues,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "RXQCNT,Number of MTL Receive Queues This field indicates the number of MTL Receive queues" "0: 1 MTL Rx Queue,1: 2 MTL Rx Queues,2: 3 MTL Rx Queues,3: 4 MTL Rx Queues,4: 5 MTL Rx Queues,5: 6 MTL Rx Queues,6: 7 MTL Rx Queues,7: 8 MTL Rx Queues,?..."
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "MAC_HW_FEATURE3,Optional Features or Functions 3"
|
|
bitfld.long 0x00 28.--29. "ASP,Automotive Safety Package Following are the encoding for the different Safety features" "0: No Safety features selected,1: Only ECC protection for external memory..,2: All the Automotive Safety features are..,3: All the Automotive Safety features are.."
|
|
newline
|
|
bitfld.long 0x00 27. "TBSSEL,Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected" "0: Time Based Scheduling Enable feature is not..,1: Time Based Scheduling Enable feature is.."
|
|
newline
|
|
bitfld.long 0x00 26. "FPESEL,Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected" "0: Frame Preemption Enable feature is not selected,1: Frame Preemption Enable feature is selected"
|
|
newline
|
|
bitfld.long 0x00 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List This field indicates the width of the Configured Time Interval Field" "0: Width not configured,1: WIDTH16,2: WIDTH20,3: WIDTH24"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "ESTDEP,Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5" "0: No Depth configured,1: DEPTH64,2: DEPTH128,3: DEPTH256,4: DEPTH512,5: DEPTH1024,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "ESTSEL,Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable Enhancements to Scheduling Traffic feature is selected" "0: Enable Enhancements to Scheduling Traffic..,1: Enable Enhancements to Scheduling Traffic.."
|
|
newline
|
|
bitfld.long 0x00 13.--14. "FRPES,Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser Entries supported by Flexible Receive Parser" "0: 64 Entries,1: 128 Entries,2: 256 Entries,?..."
|
|
newline
|
|
bitfld.long 0x00 11.--12. "FRPBS,Flexible Receive Parser Buffer size This field indicates the supported Max Number of bytes of the packet data to be Parsed by Flexible Receive Parser" "0: bf_64BYTES,1: bf_128BYTES,2: bf_256BYTES,?..."
|
|
newline
|
|
bitfld.long 0x00 10. "FRPSEL,Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible Programmable Receive Parser option is selected" "0: Flexible Receive Parser feature is not selected,1: Flexible Receive Parser feature is selected"
|
|
newline
|
|
bitfld.long 0x00 9. "PDUPSEL,Broadcast/Multicast Packet Duplication This bit is set to 1 when the Broadcast/Multicast Packet Duplication feature is selected" "0: Broadcast/Multicast Packet Duplication..,1: Broadcast/Multicast Packet Duplication.."
|
|
newline
|
|
bitfld.long 0x00 5. "DVLAN,Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected" "0: Double VLAN option is not selected,1: Double VLAN option is selected"
|
|
newline
|
|
bitfld.long 0x00 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected" "0: Enable Queue/Channel based VLAN tag insertion..,1: Enable Queue/Channel based VLAN tag insertion.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,?..."
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MAC_MDIO_ADDRESS,MDIO Address"
|
|
bitfld.long 0x00 27. "PSE,Preamble Suppression Enable When this bit is set the SMA suppresses the 32-bit preamble and transmits MDIO frames with only 1 preamble bit" "0: Preamble Suppression disabled,1: Preamble Suppression enabled"
|
|
newline
|
|
bitfld.long 0x00 26. "BTB,Back to Back transactions When this bit is set and the NTC has value greater than 0 then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted)" "0: Back to Back transactions disabled,1: Back to Back transactions enabled"
|
|
newline
|
|
bitfld.long 0x00 21.--25. "PA,Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "RDA,Register/Device Address These bits select the PHY register in selected Clause 22 PHY device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "NTC,Number of Trailing Clocks This field controls the number of trailing clock cycles generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "CR,CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design" "0: CSR clock = 60-100 MHz MDC clock = CSR clock/42,1: CSR clock = 100-150 MHz MDC clock = CSR..,2: CSR clock = 20-35 MHz MDC clock = CSR clock/16,3: CSR clock = 35-60 MHz MDC clock = CSR clock/26,4: CSR clock = 150-250 MHz MDC clock = CSR..,5: CSR clock = 250-300 MHz MDC clock = CSR..,6: CSR clock = 300-500 MHz MDC clock = CSR..,7: CSR clock = 500-800 MHz MDC clock = CSR,?,?,?,11: 0) ensures that the MDC clock is approximately,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "SKAP,Skip Address Packet When this bit is set the SMA does not send the address packets before read write or post-read increment address packets" "0: Skip Address Packet is disabled,1: Skip Address Packet is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "GOC_1,GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or RevMII GOC_1 and GOC_O is encoded as follows" "0: GMII Operation Command 1 is disabled,1: GMII Operation Command 1 is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "GOC_0,GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII" "0: GMII Operation Command 0 is disabled,1: GMII Operation Command 0 is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "C45E,Clause 45 PHY Enable When this bit is set Clause 45 capable PHY is connected to MDIO" "0: Clause 45 PHY is disabled,1: Clause 45 PHY is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "GB,GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave" "0: GMII Busy is disabled,1: GMII Busy is enabled"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "MAC_MDIO_DATA,MAC MDIO Data"
|
|
hexmask.long.word 0x00 16.--31. 1. "RA,Register Address This field is valid only when C45E is set"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "GD,GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "MAC_CSR_SW_CTRL,CSR Software Control"
|
|
bitfld.long 0x00 0. "RCWE,Register Clear on Write 1 Enable When this bit is set the access mode of some register fields changes to Clear on Write 1 the application needs to set that respective bit to 1 to clear it" "0: Register Clear on Write 1 is disabled,1: Register Clear on Write 1 is enabled"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "MAC_FPE_CTRL_STS,Frame Preemption Control"
|
|
bitfld.long 0x00 19. "TRSP,Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field)" "0: Not transmitted Respond Frame,1: transmitted Respond Frame"
|
|
newline
|
|
bitfld.long 0x00 18. "TVER,Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field)" "0: Not transmitted Verify Frame,1: transmitted Verify Frame"
|
|
newline
|
|
bitfld.long 0x00 17. "RRSP,Received Respond Frame Set when a Respond mPacket is received" "0: Not received Respond Frame,1: Received Respond Frame"
|
|
newline
|
|
bitfld.long 0x00 16. "RVER,Received Verify Frame Set when a Verify mPacket is received" "0: Not received Verify Frame,1: Received Verify Frame"
|
|
newline
|
|
bitfld.long 0x00 3. "S1_SET_0,Synopsys Reserved Must be set to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SRSP,Send Respond mPacket When set indicates hardware to send a Respond mPacket" "0: Send Respond mPacket is disabled,1: Send Respond mPacket is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "SVER,Send Verify mPacket When set indicates hardware to send a verify mPacket" "0: Send Verify mPacket is disabled,1: Send Verify mPacket is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "EFPE,Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled" "0: Tx Frame Preemption is disabled,1: Tx Frame Preemption is enabled"
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "MAC_PRESN_TIME_NS,32-bit Binary Rollover Equivalent Time"
|
|
hexmask.long 0x00 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary rollover equivalent time of the PTP System Time in ns"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "MAC_PRESN_TIME_UPDT,MAC 1722 Presentation Time"
|
|
hexmask.long 0x00 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "MAC_ADDRESS0_HIGH,MAC Address0 High"
|
|
rbitfld.long 0x00 31. "AE,Address Enable This bit is always set to 1" "0: INVALID,1: This bit is always set to 1"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address0 content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "MAC_ADDRESS0_LOW,MAC Address0 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address0[31:0] This field contains the lower 32 bits of the first 6-byte MAC address"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "MAC_ADDRESS1_HIGH,MAC Address1 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "MAC_ADDRESS1_LOW,MAC Address1 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "MAC_ADDRESS2_HIGH,MAC Address2 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "MAC_ADDRESS2_LOW,MAC Address2 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "MAC_ADDRESS3_HIGH,MAC Address3 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "MAC_ADDRESS3_LOW,MAC Address3 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "MAC_ADDRESS4_HIGH,MAC Address4 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "MAC_ADDRESS4_LOW,MAC Address4 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "MAC_ADDRESS5_HIGH,MAC Address5 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "MAC_ADDRESS5_LOW,MAC Address5 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "MAC_ADDRESS6_HIGH,MAC Address6 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "MAC_ADDRESS6_LOW,MAC Address6 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "MAC_ADDRESS7_HIGH,MAC Address7 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "MAC_ADDRESS7_LOW,MAC Address7 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "MAC_ADDRESS8_HIGH,MAC Address8 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "MAC_ADDRESS8_LOW,MAC Address8 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "MAC_ADDRESS9_HIGH,MAC Address9 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "MAC_ADDRESS9_LOW,MAC Address9 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "MAC_ADDRESS10_HIGH,MAC Address10 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "MAC_ADDRESS10_LOW,MAC Address10 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "MAC_ADDRESS11_HIGH,MAC Address11 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "MAC_ADDRESS11_LOW,MAC Address11 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "MAC_ADDRESS12_HIGH,MAC Address12 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "MAC_ADDRESS12_LOW,MAC Address12 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "MAC_ADDRESS13_HIGH,MAC Address13 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "MAC_ADDRESS13_LOW,MAC Address13 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "MAC_ADDRESS14_HIGH,MAC Address14 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "MAC_ADDRESS14_LOW,MAC Address14 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "MAC_ADDRESS15_HIGH,MAC Address15 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "MAC_ADDRESS15_LOW,MAC Address15 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "MAC_ADDRESS16_HIGH,MAC Address16 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "MAC_ADDRESS16_LOW,MAC Address16 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "MAC_ADDRESS17_HIGH,MAC Address17 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "MAC_ADDRESS17_LOW,MAC Address17 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "MAC_ADDRESS18_HIGH,MAC Address18 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "MAC_ADDRESS18_LOW,MAC Address18 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "MAC_ADDRESS19_HIGH,MAC Address19 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "MAC_ADDRESS19_LOW,MAC Address19 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "MAC_ADDRESS20_HIGH,MAC Address20 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "MAC_ADDRESS20_LOW,MAC Address20 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "MAC_ADDRESS21_HIGH,MAC Address21 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "MAC_ADDRESS21_LOW,MAC Address21 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "MAC_ADDRESS22_HIGH,MAC Address22 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "MAC_ADDRESS22_LOW,MAC Address22 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "MAC_ADDRESS23_HIGH,MAC Address23 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "MAC_ADDRESS23_LOW,MAC Address23 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "MAC_ADDRESS24_HIGH,MAC Address24 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "MAC_ADDRESS24_LOW,MAC Address24 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "MAC_ADDRESS25_HIGH,MAC Address25 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "MAC_ADDRESS25_LOW,MAC Address25 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "MAC_ADDRESS26_HIGH,MAC Address26 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "MAC_ADDRESS26_LOW,MAC Address26 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3D8++0x03
|
|
line.long 0x00 "MAC_ADDRESS27_HIGH,MAC Address27 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3DC++0x03
|
|
line.long 0x00 "MAC_ADDRESS27_LOW,MAC Address27 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "MAC_ADDRESS28_HIGH,MAC Address28 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3E4++0x03
|
|
line.long 0x00 "MAC_ADDRESS28_LOW,MAC Address28 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3E8++0x03
|
|
line.long 0x00 "MAC_ADDRESS29_HIGH,MAC Address29 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3EC++0x03
|
|
line.long 0x00 "MAC_ADDRESS29_LOW,MAC Address29 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "MAC_ADDRESS30_HIGH,MAC Address30 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3F4++0x03
|
|
line.long 0x00 "MAC_ADDRESS30_LOW,MAC Address30 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x3F8++0x03
|
|
line.long 0x00 "MAC_ADDRESS31_HIGH,MAC Address31 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC ADDRESS1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
|
|
newline
|
|
bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "DCS,DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
|
|
group.long 0x3FC++0x03
|
|
line.long 0x00 "MAC_ADDRESS31_LOW,MAC Address31 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "MAC_ADDRESS32_HIGH,MAC Address32 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "MAC_ADDRESS32_LOW,MAC Address32 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "MAC_ADDRESS33_HIGH,MAC Address33 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "MAC_ADDRESS33_LOW,MAC Address33 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "MAC_ADDRESS34_HIGH,MAC Address34 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "MAC_ADDRESS34_LOW,MAC Address34 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "MAC_ADDRESS35_HIGH,MAC Address35 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "MAC_ADDRESS35_LOW,MAC Address35 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "MAC_ADDRESS36_HIGH,MAC Address36 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "MAC_ADDRESS36_LOW,MAC Address36 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "MAC_ADDRESS37_HIGH,MAC Address37 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "MAC_ADDRESS37_LOW,MAC Address37 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "MAC_ADDRESS38_HIGH,MAC Address38 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "MAC_ADDRESS38_LOW,MAC Address38 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "MAC_ADDRESS39_HIGH,MAC Address39 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "MAC_ADDRESS39_LOW,MAC Address39 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "MAC_ADDRESS40_HIGH,MAC Address40 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "MAC_ADDRESS40_LOW,MAC Address40 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "MAC_ADDRESS41_HIGH,MAC Address41 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "MAC_ADDRESS41_LOW,MAC Address41 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "MAC_ADDRESS42_HIGH,MAC Address42 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "MAC_ADDRESS42_LOW,MAC Address42 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "MAC_ADDRESS43_HIGH,MAC Address43 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "MAC_ADDRESS43_LOW,MAC Address43 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "MAC_ADDRESS44_HIGH,MAC Address44 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "MAC_ADDRESS44_LOW,MAC Address44 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "MAC_ADDRESS45_HIGH,MAC Address45 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "MAC_ADDRESS45_LOW,MAC Address45 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "MAC_ADDRESS46_HIGH,MAC Address46 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "MAC_ADDRESS46_LOW,MAC Address46 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "MAC_ADDRESS47_HIGH,MAC Address47 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "MAC_ADDRESS47_LOW,MAC Address47 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "MAC_ADDRESS48_HIGH,MAC Address48 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "MAC_ADDRESS48_LOW,MAC Address48 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "MAC_ADDRESS49_HIGH,MAC Address49 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "MAC_ADDRESS49_LOW,MAC Address49 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "MAC_ADDRESS50_HIGH,MAC Address50 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "MAC_ADDRESS50_LOW,MAC Address50 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "MAC_ADDRESS51_HIGH,MAC Address51 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "MAC_ADDRESS51_LOW,MAC Address51 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "MAC_ADDRESS52_HIGH,MAC Address52 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "MAC_ADDRESS52_LOW,MAC Address52 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "MAC_ADDRESS53_HIGH,MAC Address53 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "MAC_ADDRESS53_LOW,MAC Address53 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "MAC_ADDRESS54_HIGH,MAC Address54 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "MAC_ADDRESS54_LOW,MAC Address54 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "MAC_ADDRESS55_HIGH,MAC Address55 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "MAC_ADDRESS55_LOW,MAC Address55 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "MAC_ADDRESS56_HIGH,MAC Address56 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "MAC_ADDRESS56_LOW,MAC Address56 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "MAC_ADDRESS57_HIGH,MAC Address57 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "MAC_ADDRESS57_LOW,MAC Address57 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "MAC_ADDRESS58_HIGH,MAC Address58 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "MAC_ADDRESS58_LOW,MAC Address58 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "MAC_ADDRESS59_HIGH,MAC Address59 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "MAC_ADDRESS59_LOW,MAC Address59 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "MAC_ADDRESS60_HIGH,MAC Address60 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "MAC_ADDRESS60_LOW,MAC Address60 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "MAC_ADDRESS61_HIGH,MAC Address61 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "MAC_ADDRESS61_LOW,MAC Address61 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "MAC_ADDRESS62_HIGH,MAC Address62 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "MAC_ADDRESS62_LOW,MAC Address62 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "MAC_ADDRESS63_HIGH,MAC Address63 High"
|
|
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC ADDRESS32 content is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address"
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "MAC_ADDRESS63_LOW,MAC Address63 Low"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address"
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "MAC_MMC_CONTROL,MMC Control"
|
|
bitfld.long 0x00 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit" "0: Update MMC Counters for Dropped Broadcast..,1: Update MMC Counters for Dropped Broadcast.."
|
|
newline
|
|
bitfld.long 0x00 5. "CNTPRSTLVL,Full-Half Preset When this bit is low and the CNTPRST bit is set all MMC counters get preset to almost-half value" "0: Full-Half Preset is disabled,1: Full-Half Preset is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "CNTPRST,Counters Preset When this bit is set all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit" "0: Counters Preset is disabled,1: Counters Preset is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "CNTFREEZ,MMC Counter Freeze When this bit is set it freezes all MMC counters to their current value" "0: MMC Counter Freeze is disabled,1: MMC Counter Freeze is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "RSTONRD,Reset on Read When this bit is set the MMC counters are reset to zero after Read (self-clearing after reset)" "0: Reset on Read is disabled,1: Reset on Read is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CNTSTOPRO,Counter Stop Rollover When this bit is set the counter does not roll over to zero after reaching the maximum value" "0: Counter Stop Rollover is disabled,1: Counter Stop Rollover is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "CNTRST,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset"
|
|
rgroup.long 0x704++0x03
|
|
line.long 0x00 "MAC_MMC_RX_INTERRUPT,MMC Rx Interrupt"
|
|
bitfld.long 0x00 27. "RXLPITRCIS,MMC Receive LPI transition counter interrupt status This bit is set when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI transition Counter Interrupt..,1: MMC Receive LPI transition Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 26. "RXLPIUSCIS,MMC Receive LPI microsecond counter interrupt status This bit is set when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI microsecond Counter Interrupt..,1: MMC Receive LPI microsecond Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 25. "RXCTRLPIS,MMC Receive Control Packet Counter Interrupt Status This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 24. "RXRCVERRPIS,MMC Receive Error Packet Counter Interrupt Status This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt..,1: MMC Receive Error Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "RXWDOGPIS,MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 22. "RXVLANGBPIS,MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 21. "RXFOVPIS,MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 20. "RXPAUSPIS,MMC Receive Pause Packet Counter Interrupt Status This bit is set when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt..,1: MMC Receive Pause Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "RXORANGEPIS,MMC Receive Out Of Range Error Packet Counter Interrupt Status" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 18. "RXLENERPIS,MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 16. "RX1024TMAXOCTGBPIS,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.."
|
|
newline
|
|
bitfld.long 0x00 15. "RX512T1023OCTGBPIS,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 14. "RX256T511OCTGBPIS,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 13. "RX128T255OCTGBPIS,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 12. "RX65T127OCTGBPIS,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 11. "RX64OCTGBPIS,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 10. "RXOSIZEGPIS,MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 9. "RXUSIZEGPIS,MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 8. "RXJABERPIS,MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 7. "RXRUNTPIS,MMC Receive Runt Packet Counter Interrupt Status This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt..,1: MMC Receive Runt Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter..,1: MMC Receive CRC Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 4. "RXMCGPIS,MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 3. "RXBCGPIS,MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 2. "RXGOCTIS,MMC Receive Good Octet Counter Interrupt Status This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt..,1: MMC Receive Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 1. "RXGBOCTIS,MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 0. "RXGBPKTIS,MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.."
|
|
rgroup.long 0x708++0x03
|
|
line.long 0x00 "MAC_MMC_TX_INTERRUPT,MMC Tx Interrupt"
|
|
bitfld.long 0x00 27. "TXLPITRCIS,MMC Transmit LPI transition counter interrupt status This bit is set when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI transition Counter Interrupt..,1: MMC Transmit LPI transition Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 26. "TXLPIUSCIS,MMC Transmit LPI microsecond counter interrupt status This bit is set when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI microsecond Counter..,1: MMC Transmit LPI microsecond Counter.."
|
|
newline
|
|
bitfld.long 0x00 25. "TXOSIZEGPIS,MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 24. "TXVLANGPIS,MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter..,1: MMC Transmit VLAN Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 23. "TXPAUSPIS,MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt..,1: MMC Transmit Pause Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 22. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet..,1: MMC Transmit Excessive Deferral Packet.."
|
|
newline
|
|
bitfld.long 0x00 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt..,1: MMC Transmit Good Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 20. "TXGOCTIS,MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt..,1: MMC Transmit Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 18. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet..,1: MMC Transmit Excessive Collision Packet.."
|
|
newline
|
|
bitfld.long 0x00 17. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 16. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter..,1: MMC Transmit Deferred Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.."
|
|
newline
|
|
bitfld.long 0x00 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.."
|
|
newline
|
|
bitfld.long 0x00 13. "TXUFLOWERPIS,MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 12. "TXBCGBPIS,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet..,1: MMC Transmit Broadcast Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 11. "TXMCGBPIS,MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet..,1: MMC Transmit Multicast Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXUCGBPIS,MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 9. "TX1024TMAXOCTGBPIS,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.."
|
|
newline
|
|
bitfld.long 0x00 8. "TX512T1023OCTGBPIS,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad..,1: MMC Transmit 512 to 1023 Octet Good Bad.."
|
|
newline
|
|
bitfld.long 0x00 7. "TX256T511OCTGBPIS,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 6. "TX128T255OCTGBPIS,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 5. "TX65T127OCTGBPIS,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half the maximum value and also when it reaches the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 4. "TX64OCTGBPIS,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 3. "TXMCGPIS,MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 2. "TXBCGPIS,MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 1. "TXGBPKTIS,MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter..,1: MMC Transmit Good Bad Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXGBOCTIS,MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.."
|
|
group.long 0x70C++0x03
|
|
line.long 0x00 "MAC_MMC_RX_INTERRUPT_MASK,MMC Rx Interrupt Mask"
|
|
bitfld.long 0x00 27. "RXLPITRCIM,MMC Receive LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI transition counter interrupt..,1: MMC Receive LPI transition counter interrupt.."
|
|
newline
|
|
bitfld.long 0x00 26. "RXLPIUSCIM,MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI microsecond counter interrupt..,1: MMC Receive LPI microsecond counter interrupt.."
|
|
newline
|
|
bitfld.long 0x00 25. "RXCTRLPIM,MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 24. "RXRCVERRPIM,MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt..,1: MMC Receive Error Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "RXWDOGPIM,MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 22. "RXVLANGBPIM,MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 21. "RXFOVPIM,MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 20. "RXPAUSPIM,MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt..,1: MMC Receive Pause Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "RXORANGEPIM,MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 18. "RXLENERPIM,MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 16. "RX1024TMAXOCTGBPIM,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.."
|
|
newline
|
|
bitfld.long 0x00 15. "RX512T1023OCTGBPIM,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 14. "RX256T511OCTGBPIM,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 13. "RX128T255OCTGBPIM,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 12. "RX65T127OCTGBPIM,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 11. "RX64OCTGBPIM,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 10. "RXOSIZEGPIM,MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 9. "RXUSIZEGPIM,MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 8. "RXJABERPIM,MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 7. "RXRUNTPIM,MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt..,1: MMC Receive Runt Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter..,1: MMC Receive CRC Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 4. "RXMCGPIM,MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 3. "RXBCGPIM,MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 2. "RXGOCTIM,MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt Mask..,1: MMC Receive Good Octet Counter Interrupt Mask.."
|
|
newline
|
|
bitfld.long 0x00 1. "RXGBOCTIM,MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 0. "RXGBPKTIM,MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.."
|
|
group.long 0x710++0x03
|
|
line.long 0x00 "MAC_MMC_TX_INTERRUPT_MASK,MMC Tx Interrupt Mask"
|
|
bitfld.long 0x00 27. "TXLPITRCIM,MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI transition counter interrupt..,1: MMC Transmit LPI transition counter interrupt.."
|
|
newline
|
|
bitfld.long 0x00 26. "TXLPIUSCIM,MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI microsecond counter..,1: MMC Transmit LPI microsecond counter.."
|
|
newline
|
|
bitfld.long 0x00 25. "TXOSIZEGPIM,MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 24. "TXVLANGPIM,MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter..,1: MMC Transmit VLAN Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 23. "TXPAUSPIM,MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt..,1: MMC Transmit Pause Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 22. "TXEXDEFPIM,MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet..,1: MMC Transmit Excessive Deferral Packet.."
|
|
newline
|
|
bitfld.long 0x00 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt..,1: MMC Transmit Good Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 20. "TXGOCTIM,MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt..,1: MMC Transmit Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 19. "TXCARERPIM,MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 18. "TXEXCOLPIM,MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet..,1: MMC Transmit Excessive Collision Packet.."
|
|
newline
|
|
bitfld.long 0x00 17. "TXLATCOLPIM,MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 16. "TXDEFPIM,MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter..,1: MMC Transmit Deferred Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.."
|
|
newline
|
|
bitfld.long 0x00 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.."
|
|
newline
|
|
bitfld.long 0x00 13. "TXUFLOWERPIM,MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 12. "TXBCGBPIM,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet..,1: MMC Transmit Broadcast Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 11. "TXMCGBPIM,MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet..,1: MMC Transmit Multicast Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXUCGBPIM,MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 9. "TX1024TMAXOCTGBPIM,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.."
|
|
newline
|
|
bitfld.long 0x00 8. "TX512T1023OCTGBPIM,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad..,1: MMC Transmit 512 to 1023 Octet Good Bad.."
|
|
newline
|
|
bitfld.long 0x00 7. "TX256T511OCTGBPIM,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 6. "TX128T255OCTGBPIM,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 5. "TX65T127OCTGBPIM,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.."
|
|
newline
|
|
bitfld.long 0x00 4. "TX64OCTGBPIM,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 3. "TXMCGPIM,MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 2. "TXBCGPIM,MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 1. "TXGBPKTIM,MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter..,1: MMC Transmit Good Bad Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXGBOCTIM,MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.."
|
|
rgroup.long 0x714++0x03
|
|
line.long 0x00 "MAC_TX_OCTET_COUNT_GOOD_BAD,Tx Octet Count Good and Bad"
|
|
hexmask.long 0x00 0.--31. 1. "TXOCTGB,Tx Octet Count Good Bad This field indicates the number of bytes transmitted exclusive of preamble and retried bytes in good and bad packets"
|
|
rgroup.long 0x718++0x03
|
|
line.long 0x00 "MAC_TX_PACKET_COUNT_GOOD_BAD,Tx Packet Count Good and Bad"
|
|
hexmask.long 0x00 0.--31. 1. "TXPKTGB,Tx Packet Count Good Bad This field indicates the number of good and bad packets transmitted exclusive of retried packets"
|
|
rgroup.long 0x71C++0x03
|
|
line.long 0x00 "MAC_TX_BROADCAST_PACKETS_GOOD,Tx Broadcast Packets Good"
|
|
hexmask.long 0x00 0.--31. 1. "TXBCASTG,Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted"
|
|
rgroup.long 0x720++0x03
|
|
line.long 0x00 "MAC_TX_MULTICAST_PACKETS_GOOD,Tx Multicast Packets Good"
|
|
hexmask.long 0x00 0.--31. 1. "TXMCASTG,Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted"
|
|
rgroup.long 0x724++0x03
|
|
line.long 0x00 "MAC_TX_64OCTETS_PACKETS_GOOD_BAD,Tx Good and Bad 64-Byte Packets"
|
|
hexmask.long 0x00 0.--31. 1. "TX64OCTGB,Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets transmitted with length 64 bytes exclusive of preamble and retried packets"
|
|
rgroup.long 0x728++0x03
|
|
line.long 0x00 "MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD,Tx Good and Bad 65 to 127-Byte Packets"
|
|
hexmask.long 0x00 0.--31. 1. "TX65_127OCTGB,Tx 65To127Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets"
|
|
rgroup.long 0x72C++0x03
|
|
line.long 0x00 "MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD,Tx Good and Bad 128 to 255-Byte Packets"
|
|
hexmask.long 0x00 0.--31. 1. "TX128_255OCTGB,Tx 128To255Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried packets"
|
|
rgroup.long 0x730++0x03
|
|
line.long 0x00 "MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD,Tx Good and Bad 256 to 511-Byte Packets"
|
|
hexmask.long 0x00 0.--31. 1. "TX256_511OCTGB,Tx 256To511Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 256 and 511 (inclusive) bytes exclusive of preamble and retried packets"
|
|
rgroup.long 0x734++0x03
|
|
line.long 0x00 "MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD,Tx Good and Bad 512 to 1023-Byte Packets"
|
|
hexmask.long 0x00 0.--31. 1. "TX512_1023OCTGB,Tx 512To1023Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 512 and 1023 (inclusive) bytes exclusive of preamble and retried packets"
|
|
rgroup.long 0x738++0x03
|
|
line.long 0x00 "MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD,Tx Good and Bad 1024 to Max-Byte Packets"
|
|
hexmask.long 0x00 0.--31. 1. "TX1024_MAXOCTGB,Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes exclusive of preamble and retried packets"
|
|
rgroup.long 0x73C++0x03
|
|
line.long 0x00 "MAC_TX_UNICAST_PACKETS_GOOD_BAD,Good and Bad Unicast Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXUCASTGB,Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted"
|
|
rgroup.long 0x740++0x03
|
|
line.long 0x00 "MAC_TX_MULTICAST_PACKETS_GOOD_BAD,Good and Bad Multicast Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXMCASTGB,Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted"
|
|
rgroup.long 0x744++0x03
|
|
line.long 0x00 "MAC_TX_BROADCAST_PACKETS_GOOD_BAD,Good and Bad Broadcast Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXBCASTGB,Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted"
|
|
rgroup.long 0x748++0x03
|
|
line.long 0x00 "MAC_TX_UNDERFLOW_ERROR_PACKETS,Tx Packets Aborted By Underflow Error"
|
|
hexmask.long 0x00 0.--31. 1. "TXUNDRFLW,Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error"
|
|
rgroup.long 0x74C++0x03
|
|
line.long 0x00 "MAC_TX_SINGLE_COLLISION_GOOD_PACKETS,Single Collision Good Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode"
|
|
rgroup.long 0x750++0x03
|
|
line.long 0x00 "MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS,Multiple Collision Good Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode"
|
|
rgroup.long 0x754++0x03
|
|
line.long 0x00 "MAC_TX_DEFERRED_PACKETS,Deferred Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXDEFRD,Tx Deferred Packets This field indicates the number of successfully transmitted after a deferral in the half-duplex mode"
|
|
rgroup.long 0x758++0x03
|
|
line.long 0x00 "MAC_TX_LATE_COLLISION_PACKETS,Late Collision Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXLATECOL,Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error"
|
|
rgroup.long 0x75C++0x03
|
|
line.long 0x00 "MAC_TX_EXCESSIVE_COLLISION_PACKETS,Excessive Collision Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXEXSCOL,Tx Excessive Collision Packets This field indicates the number of packets aborted because of excessive (16) collision errors"
|
|
rgroup.long 0x760++0x03
|
|
line.long 0x00 "MAC_TX_CARRIER_ERROR_PACKETS,Carrier Error Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXCARR,Tx Carrier Error Packets This field indicates the number of packets aborted because of carrier sense error (no carrier or loss of carrier)"
|
|
rgroup.long 0x764++0x03
|
|
line.long 0x00 "MAC_TX_OCTET_COUNT_GOOD,Bytes Transmitted in Good Packets"
|
|
hexmask.long 0x00 0.--31. 1. "TXOCTG,Tx Octet Count Good This field indicates the number of bytes transmitted exclusive of preamble only in good packets"
|
|
rgroup.long 0x768++0x03
|
|
line.long 0x00 "MAC_TX_PACKET_COUNT_GOOD,Good Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXPKTG,Tx Packet Count Good This field indicates the number of good packets transmitted"
|
|
rgroup.long 0x76C++0x03
|
|
line.long 0x00 "MAC_TX_EXCESSIVE_DEFERRAL_ERROR,Packets Aborted By Excessive Deferral Error"
|
|
hexmask.long 0x00 0.--31. 1. "TXEXSDEF,Tx Excessive Deferral Error This field indicates the number of packets aborted because of excessive deferral error (deferred for more than two max-sized packet times)"
|
|
rgroup.long 0x770++0x03
|
|
line.long 0x00 "MAC_TX_PAUSE_PACKETS,Pause Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXPAUSE,Tx Pause Packets This field indicates the number of good Pause packets transmitted"
|
|
rgroup.long 0x774++0x03
|
|
line.long 0x00 "MAC_TX_VLAN_PACKETS_GOOD,Good VLAN Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXVLANG,Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted"
|
|
rgroup.long 0x778++0x03
|
|
line.long 0x00 "MAC_TX_OSIZE_PACKETS_GOOD,Good Oversize Packets Transmitted"
|
|
hexmask.long 0x00 0.--31. 1. "TXOSIZG,Tx OSize Packets Good This field indicates the number of packets transmitted without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged packets 2000 bytes if enabled in S2KP bit of the CONFIGURATION register)"
|
|
rgroup.long 0x780++0x03
|
|
line.long 0x00 "MAC_RX_PACKETS_COUNT_GOOD_BAD,Good and Bad Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXPKTGB,Rx Packets Count Good Bad This field indicates the number of good and bad packets received"
|
|
rgroup.long 0x784++0x03
|
|
line.long 0x00 "MAC_RX_OCTET_COUNT_GOOD_BAD,Bytes in Good and Bad Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXOCTGB,Rx Octet Count Good Bad This field indicates the number of bytes received exclusive of preamble in good and bad packets"
|
|
rgroup.long 0x788++0x03
|
|
line.long 0x00 "MAC_RX_OCTET_COUNT_GOOD,Bytes in Good Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXOCTG,Rx Octet Count Good This field indicates the number of bytes received exclusive of preamble only in good packets"
|
|
rgroup.long 0x78C++0x03
|
|
line.long 0x00 "MAC_RX_BROADCAST_PACKETS_GOOD,Good Broadcast Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXBCASTG,Rx Broadcast Packets Good This field indicates the number of good broadcast packets received"
|
|
rgroup.long 0x790++0x03
|
|
line.long 0x00 "MAC_RX_MULTICAST_PACKETS_GOOD,Good Multicast Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXMCASTG,Rx Multicast Packets Good This field indicates the number of good multicast packets received"
|
|
rgroup.long 0x794++0x03
|
|
line.long 0x00 "MAC_RX_CRC_ERROR_PACKETS,CRC Error Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXCRCERR,Rx CRC Error Packets This field indicates the number of packets received with CRC error"
|
|
rgroup.long 0x798++0x03
|
|
line.long 0x00 "MAC_RX_ALIGNMENT_ERROR_PACKETS,Alignment Error Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error"
|
|
rgroup.long 0x79C++0x03
|
|
line.long 0x00 "MAC_RX_RUNT_ERROR_PACKETS,Runt Error Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXRUNTERR,Rx Runt Error Packets This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error"
|
|
rgroup.long 0x7A0++0x03
|
|
line.long 0x00 "MAC_RX_JABBER_ERROR_PACKETS,Jabber Error Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXJABERR,Rx Jabber Error Packets This field indicates the number of giant packets received with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error"
|
|
rgroup.long 0x7A4++0x03
|
|
line.long 0x00 "MAC_RX_UNDERSIZE_PACKETS_GOOD,Good Undersize Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXUNDERSZG,Rx Undersize Packets Good This field indicates the number of packets received with length less than 64 bytes without any errors"
|
|
rgroup.long 0x7A8++0x03
|
|
line.long 0x00 "MAC_RX_OVERSIZE_PACKETS_GOOD,Good Oversize Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXOVERSZG,Rx Oversize Packets Good This field indicates the number of packets received without errors with length greater than the maxsize (1 518 bytes or 1 522 bytes for VLAN tagged packets 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION.."
|
|
rgroup.long 0x7AC++0x03
|
|
line.long 0x00 "MAC_RX_64OCTETS_PACKETS_GOOD_BAD,Good and Bad 64-Byte Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RX64OCTGB,Rx 64 Octets Packets Good Bad This field indicates the number of good and bad packets received with length 64 bytes exclusive of the preamble"
|
|
rgroup.long 0x7B0++0x03
|
|
line.long 0x00 "MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD,Good and Bad 64-to-127 Byte Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RX65_127OCTGB,Rx 65-127 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes exclusive of the preamble"
|
|
rgroup.long 0x7B4++0x03
|
|
line.long 0x00 "MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD,Good and Bad 128-to-255 Byte Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RX128_255OCTGB,Rx 128-255 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes exclusive of the preamble"
|
|
rgroup.long 0x7B8++0x03
|
|
line.long 0x00 "MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD,Good and Bad 256-to-511 Byte Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RX256_511OCTGB,Rx 256-511 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes exclusive of the preamble"
|
|
rgroup.long 0x7BC++0x03
|
|
line.long 0x00 "MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD,Good and Bad 512-to-1023 Byte Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RX512_1023OCTGB,RX 512-1023 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes exclusive of the preamble"
|
|
rgroup.long 0x7C0++0x03
|
|
line.long 0x00 "MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD,Good and Bad 1024-to-Max Byte Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RX1024_MAXOCTGB,Rx 1024-Max Octets Good Bad This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble"
|
|
rgroup.long 0x7C4++0x03
|
|
line.long 0x00 "MAC_RX_UNICAST_PACKETS_GOOD,Good Unicast Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good This field indicates the number of good unicast packets received"
|
|
rgroup.long 0x7C8++0x03
|
|
line.long 0x00 "MAC_RX_LENGTH_ERROR_PACKETS,Length Error Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXLENERR,Rx Length Error Packets This field indicates the number of packets received with length error (Length Type field not equal to packet size) for all packets with valid length field"
|
|
rgroup.long 0x7CC++0x03
|
|
line.long 0x00 "MAC_RX_OUT_OF_RANGE_TYPE_PACKETS,Out-of-range Type Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXOUTOFRNG,Rx Out of Range Type Packet This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1 500 but less than 1 536)"
|
|
rgroup.long 0x7D0++0x03
|
|
line.long 0x00 "MAC_RX_PAUSE_PACKETS,Pause Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXPAUSEPKT,Rx Pause Packets This field indicates the number of good and valid Pause packets received"
|
|
rgroup.long 0x7D4++0x03
|
|
line.long 0x00 "MAC_RX_FIFO_OVERFLOW_PACKETS,Missed Packets Due to FIFO Overflow"
|
|
hexmask.long 0x00 0.--31. 1. "RXFIFOOVFL,Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow"
|
|
rgroup.long 0x7D8++0x03
|
|
line.long 0x00 "MAC_RX_VLAN_PACKETS_GOOD_BAD,Good and Bad VLAN Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXVLANPKTGB,Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received"
|
|
rgroup.long 0x7DC++0x03
|
|
line.long 0x00 "MAC_RX_WATCHDOG_ERROR_PACKETS,Watchdog Error Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXWDGERR,Rx Watchdog Error Packets This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2 048 bytes (when JE and WD bits are reset in MAC_CONFIGURATION register) 10 240.."
|
|
rgroup.long 0x7E0++0x03
|
|
line.long 0x00 "MAC_RX_RECEIVE_ERROR_PACKETS,Receive Error Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXRCVERR,Rx Receive Error Packets This field indicates the number of packets received with Receive error or Packet Extension error on the GMII or MII interface"
|
|
rgroup.long 0x7E4++0x03
|
|
line.long 0x00 "MAC_RX_CONTROL_PACKETS_GOOD,Good Control Packets Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXCTRLG,Rx Control Packets Good This field indicates the number of good control packets received"
|
|
rgroup.long 0x7EC++0x03
|
|
line.long 0x00 "MAC_TX_LPI_USEC_CNTR,Microseconds Tx LPI Asserted"
|
|
hexmask.long 0x00 0.--31. 1. "TXLPIUSC,Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted"
|
|
rgroup.long 0x7F0++0x03
|
|
line.long 0x00 "MAC_TX_LPI_TRAN_CNTR,Number of Times Tx LPI Asserted"
|
|
hexmask.long 0x00 0.--31. 1. "TXLPITRC,Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred"
|
|
rgroup.long 0x7F4++0x03
|
|
line.long 0x00 "MAC_RX_LPI_USEC_CNTR,Microseconds Rx LPI Sampled"
|
|
hexmask.long 0x00 0.--31. 1. "RXLPIUSC,Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted"
|
|
rgroup.long 0x7F8++0x03
|
|
line.long 0x00 "MAC_RX_LPI_TRAN_CNTR,Number of Times Rx LPI Entered"
|
|
hexmask.long 0x00 0.--31. 1. "RXLPITRC,Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "MAC_MMC_IPC_RX_INTERRUPT_MASK,MMC IPC Receive Interrupt Mask"
|
|
bitfld.long 0x00 29. "RXICMPEROIM,MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Error Octet Counter..,1: MMC Receive ICMP Error Octet Counter.."
|
|
newline
|
|
bitfld.long 0x00 28. "RXICMPGOIM,MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Good Octet Counter Interrupt..,1: MMC Receive ICMP Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "RXTCPEROIM,MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Error Octet Counter Interrupt..,1: MMC Receive TCP Error Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 26. "RXTCPGOIM,MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Good Octet Counter Interrupt..,1: MMC Receive TCP Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 25. "RXUDPEROIM,MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Good Octet Counter Interrupt..,1: MMC Receive UDP Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 24. "RXUDPGOIM,MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 No Payload Octet Counter..,1: MMC Receive IPV6 No Payload Octet Counter.."
|
|
newline
|
|
bitfld.long 0x00 23. "RXIPV6NOPAYOIM,MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Header Error Octet Counter..,1: MMC Receive IPV6 Header Error Octet Counter.."
|
|
newline
|
|
bitfld.long 0x00 22. "RXIPV6HEROIM,MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Good Octet Counter Interrupt..,1: MMC Receive IPV6 Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 21. "RXIPV6GOIM,MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Good Octet Counter Interrupt..,1: MMC Receive IPV6 Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 20. "RXIPV4UDSBLOIM,MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 UDP Checksum Disabled Octet..,1: MMC Receive IPV4 UDP Checksum Disabled Octet.."
|
|
newline
|
|
bitfld.long 0x00 19. "RXIPV4FRAGOIM,MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Fragmented Octet Counter..,1: MMC Receive IPV4 Fragmented Octet Counter.."
|
|
newline
|
|
bitfld.long 0x00 18. "RXIPV4NOPAYOIM,MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 No Payload Octet Counter..,1: MMC Receive IPV4 No Payload Octet Counter.."
|
|
newline
|
|
bitfld.long 0x00 17. "RXIPV4HEROIM,MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Header Error Octet Counter..,1: MMC Receive IPV4 Header Error Octet Counter.."
|
|
newline
|
|
bitfld.long 0x00 16. "RXIPV4GOIM,MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Good Octet Counter Interrupt..,1: MMC Receive IPV4 Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 13. "RXICMPERPIM,MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Error Packet Counter..,1: MMC Receive ICMP Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 12. "RXICMPGPIM,MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Good Packet Counter..,1: MMC Receive ICMP Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 11. "RXTCPERPIM,MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Error Packet Counter..,1: MMC Receive TCP Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 10. "RXTCPGPIM,MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Good Packet Counter Interrupt..,1: MMC Receive TCP Good Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 9. "RXUDPERPIM,MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Error Packet Counter..,1: MMC Receive UDP Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 8. "RXUDPGPIM,MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Good Packet Counter Interrupt..,1: MMC Receive UDP Good Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 7. "RXIPV6NOPAYPIM,MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 No Payload Packet Counter..,1: MMC Receive IPV6 No Payload Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 6. "RXIPV6HERPIM,MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Header Error Packet Counter..,1: MMC Receive IPV6 Header Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 5. "RXIPV6GPIM,MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Good Packet Counter..,1: MMC Receive IPV6 Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 4. "RXIPV4UDSBLPIM,MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 UDP Checksum Disabled Packet..,1: MMC Receive IPV4 UDP Checksum Disabled Packet.."
|
|
newline
|
|
bitfld.long 0x00 3. "RXIPV4FRAGPIM,MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Fragmented Packet Counter..,1: MMC Receive IPV4 Fragmented Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 2. "RXIPV4NOPAYPIM,MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 No Payload Packet Counter..,1: MMC Receive IPV4 No Payload Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 1. "RXIPV4HERPIM,MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Header Error Packet Counter..,1: MMC Receive IPV4 Header Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 0. "RXIPV4GPIM,MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Good Packet Counter..,1: MMC Receive IPV4 Good Packet Counter.."
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "MAC_MMC_IPC_RX_INTERRUPT,MMC IPC Receive Interrupt"
|
|
bitfld.long 0x00 29. "RXICMPEROIS,MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Error Octet Counter..,1: MMC Receive ICMP Error Octet Counter.."
|
|
newline
|
|
bitfld.long 0x00 28. "RXICMPGOIS,MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Good Octet Counter Interrupt..,1: MMC Receive ICMP Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 27. "RXTCPEROIS,MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Error Octet Counter Interrupt..,1: MMC Receive TCP Error Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 26. "RXTCPGOIS,MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Good Octet Counter Interrupt..,1: MMC Receive TCP Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 25. "RXUDPEROIS,MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Error Octet Counter Interrupt..,1: MMC Receive UDP Error Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 24. "RXUDPGOIS,MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Good Octet Counter Interrupt..,1: MMC Receive UDP Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 23. "RXIPV6NOPAYOIS,MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 No Payload Octet Counter..,1: MMC Receive IPV6 No Payload Octet Counter.."
|
|
newline
|
|
bitfld.long 0x00 22. "RXIPV6HEROIS,MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Header Error Octet Counter..,1: MMC Receive IPV6 Header Error Octet Counter.."
|
|
newline
|
|
bitfld.long 0x00 21. "RXIPV6GOIS,MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Good Octet Counter Interrupt..,1: MMC Receive IPV6 Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 20. "RXIPV4UDSBLOIS,MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 UDP Checksum Disabled Octet..,1: MMC Receive IPV4 UDP Checksum Disabled Octet.."
|
|
newline
|
|
bitfld.long 0x00 19. "RXIPV4FRAGOIS,MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Fragmented Octet Counter..,1: MMC Receive IPV4 Fragmented Octet Counter.."
|
|
newline
|
|
bitfld.long 0x00 18. "RXIPV4NOPAYOIS,MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 No Payload Octet Counter..,1: MMC Receive IPV4 No Payload Octet Counter.."
|
|
newline
|
|
bitfld.long 0x00 17. "RXIPV4HEROIS,MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Header Error Octet Counter..,1: MMC Receive IPV4 Header Error Octet Counter.."
|
|
newline
|
|
bitfld.long 0x00 16. "RXIPV4GOIS,MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Good Octet Counter Interrupt..,1: MMC Receive IPV4 Good Octet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 13. "RXICMPERPIS,MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Error Packet Counter..,1: MMC Receive ICMP Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 12. "RXICMPGPIS,MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive ICMP Good Packet Counter..,1: MMC Receive ICMP Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 11. "RXTCPERPIS,MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Error Packet Counter..,1: MMC Receive TCP Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 10. "RXTCPGPIS,MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive TCP Good Packet Counter Interrupt..,1: MMC Receive TCP Good Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 9. "RXUDPERPIS,MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Error Packet Counter..,1: MMC Receive UDP Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 8. "RXUDPGPIS,MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive UDP Good Packet Counter Interrupt..,1: MMC Receive UDP Good Packet Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 7. "RXIPV6NOPAYPIS,MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 No Payload Packet Counter..,1: MMC Receive IPV6 No Payload Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 6. "RXIPV6HERPIS,MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Header Error Packet Counter..,1: MMC Receive IPV6 Header Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 5. "RXIPV6GPIS,MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV6 Good Packet Counter..,1: MMC Receive IPV6 Good Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 4. "RXIPV4UDSBLPIS,MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 UDP Checksum Disabled Packet..,1: MMC Receive IPV4 UDP Checksum Disabled Packet.."
|
|
newline
|
|
bitfld.long 0x00 3. "RXIPV4FRAGPIS,MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Fragmented Packet Counter..,1: MMC Receive IPV4 Fragmented Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 2. "RXIPV4NOPAYPIS,MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 No Payload Packet Counter..,1: MMC Receive IPV4 No Payload Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 1. "RXIPV4HERPIS,MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Header Error Packet Counter..,1: MMC Receive IPV4 Header Error Packet Counter.."
|
|
newline
|
|
bitfld.long 0x00 0. "RXIPV4GPIS,MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value" "0: MMC Receive IPV4 Good Packet Counter..,1: MMC Receive IPV4 Good Packet Counter.."
|
|
rgroup.long 0x810++0x03
|
|
line.long 0x00 "MAC_RXIPV4_GOOD_PACKETS,Good IPv4 Datagrams Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV4GDPKT,RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP UDP or ICMP payload"
|
|
rgroup.long 0x814++0x03
|
|
line.long 0x00 "MAC_RXIPV4_HEADER_ERROR_PACKETS,IPv4 Datagrams Received with Header Errors"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV4HDRERRPKT,RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams received with header (checksum length or version mismatch) errors"
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "MAC_RXIPV4_NO_PAYLOAD_PACKETS,IPv4 Datagrams Received with No Payload"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV4NOPAYPKT,RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets received that did not have a TCP UDP or ICMP payload"
|
|
rgroup.long 0x81C++0x03
|
|
line.long 0x00 "MAC_RXIPV4_FRAGMENTED_PACKETS,IPv4 Datagrams Received with Fragmentation"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV4FRAGPKT,RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation"
|
|
rgroup.long 0x820++0x03
|
|
line.long 0x00 "MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS,IPv4 Datagrams Received with UDP Checksum Disabled"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV4UDSBLPKT,RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good IPv4 datagrams received that had a UDP payload with checksum disabled"
|
|
rgroup.long 0x824++0x03
|
|
line.long 0x00 "MAC_RXIPV6_GOOD_PACKETS,Good IPv6 Datagrams Received"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV6GDPKT,RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP UDP or ICMP payload"
|
|
rgroup.long 0x828++0x03
|
|
line.long 0x00 "MAC_RXIPV6_HEADER_ERROR_PACKETS,IPv6 Datagrams Received with Header Errors"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV6HDRERRPKT,RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams received with header (length or version mismatch) errors"
|
|
rgroup.long 0x82C++0x03
|
|
line.long 0x00 "MAC_RXIPV6_NO_PAYLOAD_PACKETS,IPv6 Datagrams Received with No Payload"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV6NOPAYPKT,RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets received that did not have a TCP UDP or ICMP payload"
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "MAC_RXUDP_GOOD_PACKETS,IPv6 Datagrams Received with Good UDP"
|
|
hexmask.long 0x00 0.--31. 1. "RXUDPGDPKT,RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload"
|
|
rgroup.long 0x834++0x03
|
|
line.long 0x00 "MAC_RXUDP_ERROR_PACKETS,IPv6 Datagrams Received with UDP Checksum Error"
|
|
hexmask.long 0x00 0.--31. 1. "RXUDPERRPKT,RxUDP Error Packets This field indicates the number of good IP datagrams received whose UDP payload has a checksum error"
|
|
rgroup.long 0x838++0x03
|
|
line.long 0x00 "MAC_RXTCP_GOOD_PACKETS,IPv6 Datagrams Received with Good TCP Payload"
|
|
hexmask.long 0x00 0.--31. 1. "RXTCPGDPKT,RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload"
|
|
rgroup.long 0x83C++0x03
|
|
line.long 0x00 "MAC_RXTCP_ERROR_PACKETS,IPv6 Datagrams Received with TCP Checksum Error"
|
|
hexmask.long 0x00 0.--31. 1. "RXTCPERRPKT,RxTCP Error Packets This field indicates the number of good IP datagrams received whose TCP payload has a checksum error"
|
|
rgroup.long 0x840++0x03
|
|
line.long 0x00 "MAC_RXICMP_GOOD_PACKETS,IPv6 Datagrams Received with Good ICMP Payload"
|
|
hexmask.long 0x00 0.--31. 1. "RXICMPGDPKT,RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload"
|
|
rgroup.long 0x844++0x03
|
|
line.long 0x00 "MAC_RXICMP_ERROR_PACKETS,IPv6 Datagrams Received with ICMP Checksum Error"
|
|
hexmask.long 0x00 0.--31. 1. "RXICMPERRPKT,RxICMP Error Packets This field indicates the number of good IP datagrams received whose ICMP payload has a checksum error"
|
|
rgroup.long 0x850++0x03
|
|
line.long 0x00 "MAC_RXIPV4_GOOD_OCTETS,Good Bytes Received in IPv4 Datagrams"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV4GDOCT,RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP UDP or ICMP data"
|
|
rgroup.long 0x854++0x03
|
|
line.long 0x00 "MAC_RXIPV4_HEADER_ERROR_OCTETS,Bytes Received in IPv4 Datagrams with Header Errors"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV4HDRERROCT,RxIPv4 Header Error Octets This field indicates the number of bytes received in IPv4 datagrams with header errors (checksum length version mismatch)"
|
|
rgroup.long 0x858++0x03
|
|
line.long 0x00 "MAC_RXIPV4_NO_PAYLOAD_OCTETS,Bytes Received in IPv4 Datagrams with No Payload"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV4NOPAYOCT,RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP UDP or ICMP payload"
|
|
rgroup.long 0x85C++0x03
|
|
line.long 0x00 "MAC_RXIPV4_FRAGMENTED_OCTETS,Bytes Received in Fragmented IPv4 Datagrams"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV4FRAGOCT,RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams"
|
|
rgroup.long 0x860++0x03
|
|
line.long 0x00 "MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS,Bytes Received with UDP Checksum Disabled"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV4UDSBLOCT,RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled"
|
|
rgroup.long 0x864++0x03
|
|
line.long 0x00 "MAC_RXIPV6_GOOD_OCTETS,Bytes Received in Good IPv6 Datagrams"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV6GDOCT,RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP UDP or ICMP data"
|
|
rgroup.long 0x868++0x03
|
|
line.long 0x00 "MAC_RXIPV6_HEADER_ERROR_OCTETS,Bytes Received in IPv6 Datagrams with Data Errors"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV6HDRERROCT,RxIPv6 Header Error Octets This field indicates the number of bytes received in IPv6 datagrams with header errors (length version mismatch)"
|
|
rgroup.long 0x86C++0x03
|
|
line.long 0x00 "MAC_RXIPV6_NO_PAYLOAD_OCTETS,Bytes Received in IPv6 Datagrams with No Payload"
|
|
hexmask.long 0x00 0.--31. 1. "RXIPV6NOPAYOCT,RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP UDP or ICMP payload"
|
|
rgroup.long 0x870++0x03
|
|
line.long 0x00 "MAC_RXUDP_GOOD_OCTETS,Bytes Received in Good UDP Segment"
|
|
hexmask.long 0x00 0.--31. 1. "RXUDPGDOCT,RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment"
|
|
rgroup.long 0x874++0x03
|
|
line.long 0x00 "MAC_RXUDP_ERROR_OCTETS,Bytes Received in UDP Segment with Checksum Errors"
|
|
hexmask.long 0x00 0.--31. 1. "RXUDPERROCT,RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors"
|
|
rgroup.long 0x878++0x03
|
|
line.long 0x00 "MAC_RXTCP_GOOD_OCTETS,Bytes Received in Good TCP Segment"
|
|
hexmask.long 0x00 0.--31. 1. "RXTCPGDOCT,RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment"
|
|
rgroup.long 0x87C++0x03
|
|
line.long 0x00 "MAC_RXTCP_ERROR_OCTETS,Bytes Received in TCP Segment with Checksum Errors"
|
|
hexmask.long 0x00 0.--31. 1. "RXTCPERROCT,RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors"
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "MAC_RXICMP_GOOD_OCTETS,Bytes Received in Good ICMP Segment"
|
|
hexmask.long 0x00 0.--31. 1. "RXICMPGDOCT,RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment"
|
|
rgroup.long 0x884++0x03
|
|
line.long 0x00 "MAC_RXICMP_ERROR_OCTETS,Bytes Received in ICMP Segment with Checksum Errors"
|
|
hexmask.long 0x00 0.--31. 1. "RXICMPERROCT,RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors"
|
|
rgroup.long 0x8A0++0x03
|
|
line.long 0x00 "MAC_MMC_FPE_TX_INTERRUPT,MMC FPE Transmit Interrupt"
|
|
bitfld.long 0x00 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx Hold Request Counter Interrupt Status..,1: MMC Tx Hold Request Counter Interrupt Status.."
|
|
newline
|
|
bitfld.long 0x00 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status This bit is set when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx FPE Fragment Counter Interrupt status..,1: MMC Tx FPE Fragment Counter Interrupt status.."
|
|
group.long 0x8A4++0x03
|
|
line.long 0x00 "MAC_MMC_FPE_TX_INTERRUPT_MASK,MMC FPE Transmit Mask Interrupt"
|
|
bitfld.long 0x00 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Hold Request Counter Interrupt..,1: MMC Transmit Hold Request Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Fragment Counter Interrupt Mask..,1: MMC Transmit Fragment Counter Interrupt Mask.."
|
|
rgroup.long 0x8A8++0x03
|
|
line.long 0x00 "MAC_MMC_TX_FPE_FRAGMENT_CNTR,MMC FPE Transmitted Fragment Counter"
|
|
hexmask.long 0x00 0.--31. 1. "TXFFC,Tx FPE Fragment counter This field indicates the number of additional mPackets that has been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled during FPE Enabled configuration"
|
|
rgroup.long 0x8AC++0x03
|
|
line.long 0x00 "MAC_MMC_TX_HOLD_REQ_CNTR,MMC FPE Transmitted Hold Request Counter"
|
|
hexmask.long 0x00 0.--31. 1. "TXHRC,Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC"
|
|
rgroup.long 0x8C0++0x03
|
|
line.long 0x00 "MAC_MMC_FPE_RX_INTERRUPT,MMC FPE Receive Interrupt"
|
|
bitfld.long 0x00 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Status..,1: MMC Rx FPE Fragment Counter Interrupt Status.."
|
|
newline
|
|
bitfld.long 0x00 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt..,1: MMC Rx Packet Assembly OK Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt..,1: MMC Rx Packet SMD Error Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter..,1: MMC Rx Packet Assembly Error Counter.."
|
|
group.long 0x8C4++0x03
|
|
line.long 0x00 "MAC_MMC_FPE_RX_INTERRUPT_MASK,MMC FPE Receive Interrupt Mask"
|
|
bitfld.long 0x00 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Mask is..,1: MMC Rx FPE Fragment Counter Interrupt Mask is.."
|
|
newline
|
|
bitfld.long 0x00 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt..,1: MMC Rx Packet Assembly OK Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt..,1: MMC Rx Packet SMD Error Counter Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter..,1: MMC Rx Packet Assembly Error Counter.."
|
|
rgroup.long 0x8C8++0x03
|
|
line.long 0x00 "MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR,MMC Receive Packet Reassembly Error Counter"
|
|
hexmask.long 0x00 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter This field indicates the number of MAC frames with reassembly errors on the Receiver due to mismatch in the Fragment Count value"
|
|
rgroup.long 0x8CC++0x03
|
|
line.long 0x00 "MAC_MMC_RX_PACKET_SMD_ERR_CNTR,MMC Receive Packet SMD Error Counter"
|
|
hexmask.long 0x00 0.--31. 1. "PSEC,Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame"
|
|
rgroup.long 0x8D0++0x03
|
|
line.long 0x00 "MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR,MMC Receive Packet Successful Reassembly Counter"
|
|
hexmask.long 0x00 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were successfully reassembled and delivered to MAC"
|
|
rgroup.long 0x8D4++0x03
|
|
line.long 0x00 "MAC_MMC_RX_FPE_FRAGMENT_CNTR,MMC FPE Received Fragment Counter"
|
|
hexmask.long 0x00 0.--31. 1. "FFC,Rx FPE Fragment Counter This field indicates the number of additional mPackets received due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE Enabled configuration"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "MAC_L3_L4_CONTROL0,Layer 3 and Layer 4 Control of Filter 0"
|
|
bitfld.long 0x00 28. "DMCHEN0,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "DMCHN0,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
|
|
newline
|
|
bitfld.long 0x00 20. "L4DPM0,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "L4SPM0,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "L4PEN0,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "L3HDBM0,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 6.--10. "L3HSBM0,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "L3DAM0,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "L3SAM0,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "L3PEN0,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
|
|
group.long 0x904++0x03
|
|
line.long 0x00 "MAC_LAYER4_ADDRESS0,Layer 4 Address 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR0_REG0,Layer 3 Address 0 Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "L3A00,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x914++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR1_REG0,Layer 3 Address 1 Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "L3A10,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR2_REG0,Layer 3 Address 2 Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "L3A20,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x91C++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR3_REG0,Layer 3 Address 3 Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "L3A30,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "MAC_L3_L4_CONTROL1,Layer 3 and Layer 4 Control of Filter 1"
|
|
bitfld.long 0x00 28. "DMCHEN1,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "DMCHN1,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
|
|
newline
|
|
bitfld.long 0x00 20. "L4DPM1,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "L4SPM1,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "L4PEN1,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "L3HDBM1,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 6.--10. "L3HSBM1,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "L3DAM1,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "L3SAM1,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "L3PEN1,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
|
|
group.long 0x934++0x03
|
|
line.long 0x00 "MAC_LAYER4_ADDRESS1,Layer 4 Address 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR0_REG1,Layer 3 Address 0 Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "L3A01,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x944++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR1_REG1,Layer 3 Address 1 Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "L3A11,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR2_REG1,Layer 3 Address 2 Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "L3A21,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x94C++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR3_REG1,Layer 3 Address 3 Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "L3A31,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "MAC_L3_L4_CONTROL2,Layer 3 and Layer 4 Control of Filter 2"
|
|
bitfld.long 0x00 28. "DMCHEN2,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "DMCHN2,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "L4DPIM2,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
|
|
newline
|
|
bitfld.long 0x00 20. "L4DPM2,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "L4SPIM2,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "L4SPM2,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "L4PEN2,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "L3HDBM2,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 6.--10. "L3HSBM2,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5. "L3DAIM2,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "L3DAM2,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "L3SAIM2,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "L3SAM2,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "L3PEN2,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
|
|
group.long 0x964++0x03
|
|
line.long 0x00 "MAC_LAYER4_ADDRESS2,Layer 4 Address 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "L4DP2,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "L4SP2,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR0_REG2,Layer 3 Address 0 Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "L3A02,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x974++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR1_REG2,Layer 3 Address 0 Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "L3A12,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR2_REG2,Layer 3 Address 2 Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "L3A22,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x97C++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR3_REG2,Layer 3 Address 3 Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "L3A32,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "MAC_L3_L4_CONTROL3,Layer 3 and Layer 4 Control of Filter 3"
|
|
bitfld.long 0x00 28. "DMCHEN3,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "DMCHN3,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "L4DPIM3,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
|
|
newline
|
|
bitfld.long 0x00 20. "L4DPM3,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "L4SPIM3,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "L4SPM3,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "L4PEN3,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "L3HDBM3,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 6.--10. "L3HSBM3,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5. "L3DAIM3,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "L3DAM3,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "L3SAIM3,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "L3SAM3,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "L3PEN3,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
|
|
group.long 0x994++0x03
|
|
line.long 0x00 "MAC_LAYER4_ADDRESS3,Layer 4 Address 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "L4DP3,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "L4SP3,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR0_REG3,Layer 3 Address 0 Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "L3A03,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x9A4++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR1_REG3,Layer 3 Address 1 Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "L3A13,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR2_REG3,Layer 3 Address 2 Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "L3A23,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x9AC++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR3_REG3,Layer 3 Address 3 Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "L3A33,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "MAC_L3_L4_CONTROL4,Layer 3 and Layer 4 Control of Filter 4"
|
|
bitfld.long 0x00 28. "DMCHEN4,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "DMCHN4,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "L4DPIM4,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
|
|
newline
|
|
bitfld.long 0x00 20. "L4DPM4,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "L4SPIM4,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "L4SPM4,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "L4PEN4,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "L3HDBM4,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 6.--10. "L3HSBM4,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5. "L3DAIM4,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "L3DAM4,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "L3SAIM4,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "L3SAM4,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "L3PEN4,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
|
|
group.long 0x9C4++0x03
|
|
line.long 0x00 "MAC_LAYER4_ADDRESS4,Layer 4 Address 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "L4DP4,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "L4SP4,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR0_REG4,Layer 3 Address 0 Register 4"
|
|
hexmask.long 0x00 0.--31. 1. "L3A04,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x9D4++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR1_REG4,Layer 3 Address 1 Register 4"
|
|
hexmask.long 0x00 0.--31. 1. "L3A14,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR2_REG4,Layer 3 Address 2 Register 4"
|
|
hexmask.long 0x00 0.--31. 1. "L3A24,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x9DC++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR3_REG4,Layer 3 Address 3 Register 4"
|
|
hexmask.long 0x00 0.--31. 1. "L3A34,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "MAC_L3_L4_CONTROL5,Layer 3 and Layer 4 Control of Filter 5"
|
|
bitfld.long 0x00 28. "DMCHEN5,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "DMCHN5,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "L4DPIM5,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
|
|
newline
|
|
bitfld.long 0x00 20. "L4DPM5,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "L4SPIM5,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "L4SPM5,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "L4PEN5,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "L3HDBM5,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 6.--10. "L3HSBM5,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5. "L3DAIM5,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "L3DAM5,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "L3SAIM5,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "L3SAM5,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "L3PEN5,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
|
|
group.long 0x9F4++0x03
|
|
line.long 0x00 "MAC_LAYER4_ADDRESS5,Layer 4 Address 5"
|
|
hexmask.long.word 0x00 16.--31. 1. "L4DP5,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "L4SP5,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR0_REG5,Layer 3 Address 0 Register 5"
|
|
hexmask.long 0x00 0.--31. 1. "L3A05,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR1_REG5,Layer 3 Address 1 Register 5"
|
|
hexmask.long 0x00 0.--31. 1. "L3A15,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR2_REG5,Layer 3 Address 2 Register 5"
|
|
hexmask.long 0x00 0.--31. 1. "L3A25,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR3_REG5,Layer 3 Address 3 Register 5"
|
|
hexmask.long 0x00 0.--31. 1. "L3A35,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "MAC_L3_L4_CONTROL6,Layer 3 and Layer 4 Control of Filter 6"
|
|
bitfld.long 0x00 28. "DMCHEN6,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "DMCHN6,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "L4DPIM6,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
|
|
newline
|
|
bitfld.long 0x00 20. "L4DPM6,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "L4SPIM6,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "L4SPM6,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "L4PEN6,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "L3HDBM6,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 6.--10. "L3HSBM6,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5. "L3DAIM6,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "L3DAM6,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "L3SAIM6,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "L3SAM6,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "L3PEN6,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
|
|
group.long 0xA24++0x03
|
|
line.long 0x00 "MAC_LAYER4_ADDRESS6,Layer 4 Address 6"
|
|
hexmask.long.word 0x00 16.--31. 1. "L4DP6,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "L4SP6,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR0_REG6,Layer 3 Address 0 Register 6"
|
|
hexmask.long 0x00 0.--31. 1. "L3A06,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR1_REG6,Layer 3 Address 1 Register 6"
|
|
hexmask.long 0x00 0.--31. 1. "L3A16,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR2_REG6,Layer 3 Address 2 Register 6"
|
|
hexmask.long 0x00 0.--31. 1. "L3A26,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0xA3C++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR3_REG6,Layer 3 Address 3 Register 6"
|
|
hexmask.long 0x00 0.--31. 1. "L3A36,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "MAC_L3_L4_CONTROL7,Layer 3 and Layer 4 Control of Filter 0"
|
|
bitfld.long 0x00 28. "DMCHEN7,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "DMCHN7,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 21. "L4DPIM7,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
|
|
newline
|
|
bitfld.long 0x00 20. "L4DPM7,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "L4SPIM7,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "L4SPM7,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "L4PEN7,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
|
|
newline
|
|
bitfld.long 0x00 11.--15. "L3HDBM7,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 6.--10. "L3HSBM7,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 5. "L3DAIM7,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "L3DAM7,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "L3SAIM7,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "L3SAM7,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "L3PEN7,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
|
|
group.long 0xA54++0x03
|
|
line.long 0x00 "MAC_LAYER4_ADDRESS7,Layer 4 Address 7"
|
|
hexmask.long.word 0x00 16.--31. 1. "L4DP7,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "L4SP7,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR0_REG7,Layer 3 Address 0 Register 7"
|
|
hexmask.long 0x00 0.--31. 1. "L3A07,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0xA64++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR1_REG7,Layer 3 Address 1 Register 7"
|
|
hexmask.long 0x00 0.--31. 1. "L3A17,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR2_REG7,Layer 3 Address 2 Register 7"
|
|
hexmask.long 0x00 0.--31. 1. "L3A27,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0xA6C++0x03
|
|
line.long 0x00 "MAC_LAYER3_ADDR3_REG7,Layer 3 Address 3 Register 7"
|
|
hexmask.long 0x00 0.--31. 1. "L3A37,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_CONTROL0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "MAC_TIMESTAMP_CONTROL,Timestamp Control"
|
|
bitfld.long 0x00 28. "AV8021ASMEN,AV 802" "0: AV 802.1AS Mode is disabled,1: AV 802.1AS Mode is enabled"
|
|
newline
|
|
bitfld.long 0x00 24. "TXTSSTSM,Transmit Timestamp Status Mode When this bit is set the MAC overwrites the earlier transmit timestamp status even if it is not read by the software" "0: Transmit Timestamp Status Mode is disabled,1: Transmit Timestamp Status Mode is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "ESTI,External System Time Input When this bit is set the MAC uses the external 64-bit reference System Time input for the following: - To take the timestamp provided as status - To insert the timestamp in transmit PTP packets when One-step Timestamp or.." "0: External System Time Input is disabled,1: External System Time Input is enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "CSC,Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum correct for changes made to origin timestamp and/or correction field as.." "0: checksum correction during OST for PTP over..,1: checksum correction during OST for PTP over.."
|
|
newline
|
|
bitfld.long 0x00 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering When this bit is set the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet" "0: MAC Address for PTP Packet Filtering is..,1: MAC Address for PTP Packet Filtering is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master When this bit is set the snapshot is taken only for the messages that are relevant to the master node" "0: Snapshot for Messages Relevant to Master is..,1: Snapshot for Messages Relevant to Master is.."
|
|
newline
|
|
bitfld.long 0x00 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages When this bit is set the timestamp snapshot is taken only for event messages (SYNC Delay_Req Pdelay_Req or Pdelay_Resp)" "0: Timestamp Snapshot for Event Messages is..,1: Timestamp Snapshot for Event Messages is.."
|
|
newline
|
|
bitfld.long 0x00 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets" "0: Processing of PTP Packets Sent over IPv4-UDP..,1: Processing of PTP Packets Sent over IPv4-UDP.."
|
|
newline
|
|
bitfld.long 0x00 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets" "0: Processing of PTP Packets Sent over IPv6-UDP..,1: Processing of PTP Packets Sent over IPv6-UDP.."
|
|
newline
|
|
bitfld.long 0x00 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets When this bit is set the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets" "0: Processing of PTP over Ethernet Packets is..,1: Processing of PTP over Ethernet Packets is.."
|
|
newline
|
|
bitfld.long 0x00 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format When this bit is set the IEEE 1588 version 2 format is used to process the PTP packets" "0: PTP Packet Processing for Version 2 Format is..,1: PTP Packet Processing for Version 2 Format is.."
|
|
newline
|
|
bitfld.long 0x00 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control When this bit is set the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is 1 nanosecond accuracy) and increments the timestamp (High) seconds" "0: Timestamp Digital or Binary Rollover Control..,1: Timestamp Digital or Binary Rollover Control.."
|
|
newline
|
|
bitfld.long 0x00 8. "TSENALL,Enable Timestamp for All Packets When this bit is set the timestamp snapshot is enabled for all packets received by the MAC" "0: Timestamp for All Packets disabled,1: Timestamp for All Packets enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "PTGE,Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled" "0: Presentation Time Generation is disabled,1: Presentation Time Generation is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "TSADDREG,Update Addend Register When this bit is set the content of the Timestamp Addend register is updated in the PTP block for fine correction" "0: Addend Register is not updated,1: Addend Register is updated"
|
|
newline
|
|
bitfld.long 0x00 3. "TSUPDT,Update Timestamp When this bit is set the system time is updated (added or subtracted) with the value specified in MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not updated,1: Timestamp is updated"
|
|
newline
|
|
bitfld.long 0x00 2. "TSINIT,Initialize Timestamp When this bit is set the system time is initialized (overwritten) with the value specified in the MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not initialized,1: Timestamp is initialized"
|
|
newline
|
|
bitfld.long 0x00 1. "TSCFUPDT,Fine or Coarse Timestamp Update When this bit is set the Fine method is used to update system timestamp" "0: Coarse method is used to update system..,1: Fine method is used to update system timestamp"
|
|
newline
|
|
bitfld.long 0x00 0. "TSENA,Enable Timestamp When this bit is set the timestamp is added for Transmit and Receive packets" "0: Timestamp is disabled,1: Timestamp is enabled"
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "MAC_SUB_SECOND_INCREMENT,Subsecond Increment"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SSINC,Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "SNSINC,Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value represented in nanoseconds multiplied by 2^8"
|
|
rgroup.long 0xB08++0x03
|
|
line.long 0x00 "MAC_SYSTEM_TIME_SECONDS,System Time Seconds"
|
|
hexmask.long 0x00 0.--31. 1. "TSS,Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC"
|
|
rgroup.long 0xB0C++0x03
|
|
line.long 0x00 "MAC_SYSTEM_TIME_NANOSECONDS,System Time Nanoseconds"
|
|
hexmask.long 0x00 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field has the sub-second representation of time with an accuracy of 0"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "MAC_SYSTEM_TIME_SECONDS_UPDATE,System Time Seconds Update"
|
|
hexmask.long 0x00 0.--31. 1. "TSS,Timestamp Seconds The value in this field is the seconds part of the update"
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "MAC_SYSTEM_TIME_NANOSECONDS_UPDATE,System Time Nanoseconds Update"
|
|
bitfld.long 0x00 31. "ADDSUB,Add or Subtract Time When this bit is set the time value is subtracted with the contents of the update register" "0: Add time,1: Subtract time"
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field is the sub-seconds part of the update"
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "MAC_TIMESTAMP_ADDEND,Timestamp Addend"
|
|
hexmask.long 0x00 0.--31. 1. "TSAR,Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization"
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS,System Time - Higher Word Seconds"
|
|
hexmask.long.word 0x00 0.--15. 1. "TSHWR,Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value"
|
|
rgroup.long 0xB20++0x03
|
|
line.long 0x00 "MAC_TIMESTAMP_STATUS,Timestamp Status"
|
|
bitfld.long 0x00 25.--29. "ATSNS,Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set" "0: Auxiliary Timestamp Snapshot Trigger Missed..,1: Auxiliary Timestamp Snapshot Trigger Missed.."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15. "TXTSSIS,Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop transmit status is enabled in MTL this bit is set when the captured transmit timestamp is updated in the MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and.." "0: Tx Timestamp Status Interrupt status not..,1: Tx Timestamp Status Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 9. "TSTRGTERR3,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
|
|
newline
|
|
bitfld.long 0x00 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3 When this bit is set it indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers" "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.."
|
|
newline
|
|
bitfld.long 0x00 7. "TSTRGTERR2,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
|
|
newline
|
|
bitfld.long 0x00 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2 When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers" "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.."
|
|
newline
|
|
bitfld.long 0x00 5. "TSTRGTERR1,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
|
|
newline
|
|
bitfld.long 0x00 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1 When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers" "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.."
|
|
newline
|
|
bitfld.long 0x00 3. "TSTRGTERR0,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
|
|
newline
|
|
bitfld.long 0x00 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO" "0: Auxiliary Timestamp Trigger Snapshot status..,1: Auxiliary Timestamp Trigger Snapshot status.."
|
|
newline
|
|
bitfld.long 0x00 1. "TSTARGT0,Timestamp Target Time Reached When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers" "0: Timestamp Target Time Reached status not..,1: Timestamp Target Time Reached status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "TSSOVF,Timestamp Seconds Overflow When this bit is set it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF" "0: Timestamp Seconds Overflow status not detected,1: Timestamp Seconds Overflow status detected"
|
|
rgroup.long 0xB30++0x03
|
|
line.long 0x00 "MAC_TX_TIMESTAMP_STATUS_NANOSECONDS,Transmit Timestamp Status Nanoseconds"
|
|
bitfld.long 0x00 31. "TXTSSMIS,Transmit Timestamp Status Missed When this bit is set it indicates one of the following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the TIMESTAMP_CONTROL register is reset - The timestamp of the previous packet is.." "0: Transmit Timestamp Status Missed status not..,1: Transmit Timestamp Status Missed status.."
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp"
|
|
rgroup.long 0xB34++0x03
|
|
line.long 0x00 "MAC_TX_TIMESTAMP_STATUS_SECONDS,Transmit Timestamp Status Seconds"
|
|
hexmask.long 0x00 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp"
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "MAC_AUXILIARY_CONTROL,Auxiliary Timestamp Control"
|
|
bitfld.long 0x00 7. "ATSEN3,Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "ATSEN2,Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "ATSEN1,Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "ATSEN0,Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ATSFC,Auxiliary Snapshot FIFO Clear When set this bit resets the pointers of the Auxiliary Snapshot FIFO" "0: Auxiliary Snapshot FIFO Clear is disabled,1: Auxiliary Snapshot FIFO Clear is enabled"
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "MAC_AUXILIARY_TIMESTAMP_NANOSECONDS,Auxiliary Timestamp Nanoseconds"
|
|
hexmask.long 0x00 0.--30. 1. "AUXTSLO,Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp"
|
|
rgroup.long 0xB4C++0x03
|
|
line.long 0x00 "MAC_AUXILIARY_TIMESTAMP_SECONDS,Auxiliary Timestamp Seconds"
|
|
hexmask.long 0x00 0.--31. 1. "AUXTSHI,Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp"
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "MAC_TIMESTAMP_INGRESS_ASYM_CORR,Timestamp Ingress Asymmetry Correction"
|
|
hexmask.long 0x00 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet"
|
|
group.long 0xB54++0x03
|
|
line.long 0x00 "MAC_TIMESTAMP_EGRESS_ASYM_CORR,imestamp Egress Asymmetry Correction"
|
|
hexmask.long 0x00 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet"
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND,Timestamp Ingress Correction Nanosecond"
|
|
hexmask.long 0x00 0.--31. 1. "TSIC,Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression"
|
|
group.long 0xB5C++0x03
|
|
line.long 0x00 "MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND,Timestamp Egress Correction Nanosecond"
|
|
hexmask.long 0x00 0.--31. 1. "TSEC,Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression"
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC,Timestamp Ingress Correction Subnanosecond"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TSICSNS,Timestamp Ingress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the ingress path correction value as defined by the Ingress Correction expression"
|
|
group.long 0xB64++0x03
|
|
line.long 0x00 "MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC,Timestamp Egress Correction Subnanosecond"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TSECSNS,Timestamp Egress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the egress path correction value as defined by the Egress Correction expression"
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "MAC_TIMESTAMP_INGRESS_LATENCY,Timestamp Ingress Latency"
|
|
hexmask.long.word 0x00 16.--27. 1. "ITLNS,Ingress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken"
|
|
rgroup.long 0xB6C++0x03
|
|
line.long 0x00 "MAC_TIMESTAMP_EGRESS_LATENCY,Timestamp Egress Latency"
|
|
hexmask.long.word 0x00 16.--27. 1. "ETLNS,Egress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "ETLSNS,Egress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC"
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "MAC_PPS_CONTROL,PPS Control"
|
|
bitfld.long 0x00 31. "MCGREN3,MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29.--30. "TRGTMODSEL3,Target Time Register Mode for PPS3 Output This field indicates the Target Time registers (MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS) mode for PPS3 output signal" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
|
|
newline
|
|
bitfld.long 0x00 24.--27. "PPSCMD3,Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 23. "MCGREN2,MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode" "0: 2nd PPS instance is disabled to operate in..,1: 2nd PPS instance is enabled to operate in PPS.."
|
|
newline
|
|
bitfld.long 0x00 21.--22. "TRGTMODSEL2,Target Time Register Mode for PPS2 Output This field indicates the Target Time registers (MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS) mode for PPS2 output signal" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "PPSCMD2,Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15. "MCGREN1,MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode" "0: 1st PPS instance is disabled to operate in..,1: 1st PPS instance is enabled to operate in PPS.."
|
|
newline
|
|
bitfld.long 0x00 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS1 Output This field indicates the Target Time registers (MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS) mode for PPS1 output signal" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PPSCMD1,Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "MCGREN0,MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode" "0: 0th PPS instance is enabled to operate in PPS..,1: 0th PPS instance is enabled to operate in.."
|
|
newline
|
|
bitfld.long 0x00 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output This field indicates the Target Time registers (MAC_PPS0_TARGET_TIME_SECONDS and MAC_PPS0_TARGET_TIME_NANOSECONDS) mode for PPS0 output signal" "0: Target Time registers are programmed only for..,?,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
|
|
newline
|
|
bitfld.long 0x00 4. "PPSEN0,Flexible PPS Output Mode Enable When this bit is set Bits[3:0] function as PPSCMD" "0: Flexible PPS Output Mode is disabled,1: Flexible PPS Output Mode is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "PPSCTRL_PPSCMD,PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "MAC_PPS0_TARGET_TIME_SECONDS,PPS0 Target Time Seconds"
|
|
hexmask.long 0x00 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register This field stores the time in seconds"
|
|
group.long 0xB84++0x03
|
|
line.long 0x00 "MAC_PPS0_TARGET_TIME_NANOSECONDS,PPS0 Target Time Nanoseconds"
|
|
bitfld.long 0x00 31. "TRGTBUSY0,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS_CONTROL register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "TTSL0,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "MAC_PPS0_INTERVAL,PPS0 Interval"
|
|
hexmask.long 0x00 0.--31. 1. "PPSINT0,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
|
|
group.long 0xB8C++0x03
|
|
line.long 0x00 "MAC_PPS0_WIDTH,PPS0 Width"
|
|
hexmask.long 0x00 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "MAC_PPS1_TARGET_TIME_SECONDS,PPS1 Target Time Seconds"
|
|
hexmask.long 0x00 0.--31. 1. "TSTRH1,PPS Target Time Seconds Register This field stores the time in seconds"
|
|
group.long 0xB94++0x03
|
|
line.long 0x00 "MAC_PPS1_TARGET_TIME_NANOSECONDS,PPS1 Target Time Nanoseconds"
|
|
bitfld.long 0x00 31. "TRGTBUSY1,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS_CONTROL register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "TTSL1,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "MAC_PPS1_INTERVAL,PPS1 Interval"
|
|
hexmask.long 0x00 0.--31. 1. "PPSINT1,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
|
|
group.long 0xB9C++0x03
|
|
line.long 0x00 "MAC_PPS1_WIDTH,PPS1 Width"
|
|
hexmask.long 0x00 0.--31. 1. "PPSWIDTH1,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "MAC_PPS2_TARGET_TIME_SECONDS,PPS2 Target Time Seconds"
|
|
hexmask.long 0x00 0.--31. 1. "TSTRH2,PPS Target Time Seconds Register This field stores the time in seconds"
|
|
group.long 0xBA4++0x03
|
|
line.long 0x00 "MAC_PPS2_TARGET_TIME_NANOSECONDS,PPS2 Target Time Nanoseconds"
|
|
bitfld.long 0x00 31. "TRGTBUSY2,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS_CONTROL register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "TTSL2,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "MAC_PPS2_INTERVAL,PPS2 Interval"
|
|
hexmask.long 0x00 0.--31. 1. "PPSINT2,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
|
|
group.long 0xBAC++0x03
|
|
line.long 0x00 "MAC_PPS2_WIDTH,PPS2 Width"
|
|
hexmask.long 0x00 0.--31. 1. "PPSWIDTH2,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "MAC_PPS3_TARGET_TIME_SECONDS,PPS3 Target Time Seconds"
|
|
hexmask.long 0x00 0.--31. 1. "TSTRH3,PPS Target Time Seconds Register This field stores the time in seconds"
|
|
group.long 0xBB4++0x03
|
|
line.long 0x00 "MAC_PPS3_TARGET_TIME_NANOSECONDS,PPS3 Target Time Nanoseconds"
|
|
bitfld.long 0x00 31. "TRGTBUSY3,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the PPS_CONTROL register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "TTSL3,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "MAC_PPS3_INTERVAL,PPS3 Interval"
|
|
hexmask.long 0x00 0.--31. 1. "PPSINT3,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
|
|
group.long 0xBBC++0x03
|
|
line.long 0x00 "MAC_PPS3_WIDTH,PPS3 Width"
|
|
hexmask.long 0x00 0.--31. 1. "PPSWIDTH3,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "MAC_PTO_CONTROL,PTP Offload Engine Control"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DN,Domain Number This field indicates the domain Number in which the PTP node is operating"
|
|
newline
|
|
bitfld.long 0x00 7. "PDRDIS,Disable Peer Delay Response response generation When this bit is set the Peer Delay Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req) request packet as required by the programmed mode" "0: Peer Delay Response response generation is..,1: Peer Delay Response response generation is.."
|
|
newline
|
|
bitfld.long 0x00 6. "DRRDIS,Disable PTO Delay Request/Response response generation When this bit is set the Delay Request and Delay response is not generated for received SYNC and Delay request packet respectively as required by the programmed mode" "0: PTO Delay Request/Response response..,1: PTO Delay Request/Response response.."
|
|
newline
|
|
bitfld.long 0x00 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger When this bit is set one PTP Pdelay_Req message is transmitted" "0: Automatic PTP Pdelay_Req message Trigger is..,1: Automatic PTP Pdelay_Req message Trigger is.."
|
|
newline
|
|
bitfld.long 0x00 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger When this bit is set one PTP SYNC message is transmitted" "0: Automatic PTP SYNC message Trigger is disabled,1: Automatic PTP SYNC message Trigger is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable When this bit is set PTP Pdelay_Req message is generated periodically based on interval programmed or trigger from application when the MAC is programmed to be in Peer-to-Peer Transparent mode" "0: Automatic PTP Pdelay_Req message is disabled,1: Automatic PTP Pdelay_Req message is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "ASYNCEN,Automatic PTP SYNC message Enable When this bit is set PTP SYNC message is generated periodically based on interval programmed or trigger from application when the MAC is programmed to be in Clock Master mode" "0: Automatic PTP SYNC message is disabled,1: Automatic PTP SYNC message is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PTOEN,PTP Offload Enable When this bit is set the PTP Offload feature is enabled" "0: PTP Offload feature is disabled,1: PTP Offload feature is enabled"
|
|
group.long 0xBC4++0x03
|
|
line.long 0x00 "MAC_SOURCE_PORT_IDENTITY0,Source Port Identity 0"
|
|
hexmask.long 0x00 0.--31. 1. "SPI0,Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node"
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "MAC_SOURCE_PORT_IDENTITY1,Source Port Identity 1"
|
|
hexmask.long 0x00 0.--31. 1. "SPI1,Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node"
|
|
group.long 0xBCC++0x03
|
|
line.long 0x00 "MAC_SOURCE_PORT_IDENTITY2,Source Port Identity 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "SPI2,Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node"
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "MAC_LOG_MESSAGE_INTERVAL,Log Message Interval"
|
|
hexmask.long.byte 0x00 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio In Slave mode it is used for controlling frequency of Delay_Req messages transmitted" "0: DelayReq generated for every received SYNC,1: DelayReq generated every alternate reception..,2: for every 4 SYNC messages,3: for every 8 SYNC messages,4: for every 16 SYNC messages,5: for every 32 SYNC messages,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "LSI,Log Sync Interval This field indicates the periodicity of the automatically generated SYNC message when the PTP node is Master"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "MTL_OPERATION_MODE,MTL Operation Mode"
|
|
bitfld.long 0x00 15. "FRPE,Flexible Rx parser Enable When this bit is set to 1 the Programmable Rx Parser functionality is enabled" "0: Flexible Rx parser is disabled,1: Flexible Rx parser is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "CNTCLR,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset"
|
|
newline
|
|
bitfld.long 0x00 8. "CNTPRST,Counters Preset When this bit is set - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0" "0: Counters Preset is disabled,1: Counters Preset is enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "SCHALG,Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling" "0: WRR algorithm,1: WFQ algorithm when DCB feature is..,2: DWRR algorithm when DCB feature is..,3: Strict priority algorithm"
|
|
newline
|
|
bitfld.long 0x00 2. "RAA,Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side" "0: Strict priority (SP),1: Weighted Strict Priority (WSP)"
|
|
newline
|
|
bitfld.long 0x00 1. "DTXSTS,Drop Transmit Status When this bit is set the Tx packet status received from the MAC is dropped in the MTL" "0: Drop Transmit Status is disabled,1: Drop Transmit Status is enabled"
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "MTL_DBG_CTL,FIFO Debug Access Control and Status"
|
|
bitfld.long 0x00 15. "STSIE,Transmit Status Available Interrupt Status Enable When this bit is set an interrupt is generated when Transmit status is available in slave mode" "0: Transmit Packet Available Interrupt Status is..,1: Transmit Packet Available Interrupt Status is.."
|
|
newline
|
|
bitfld.long 0x00 14. "PKTIE,Receive Packet Available Interrupt Status Enable When this bit is set an interrupt is generated when EOP of received packet is written to the Rx FIFO" "0: Receive Packet Available Interrupt Status is..,1: Receive Packet Available Interrupt Status is.."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "FIFOSEL,FIFO Selected for Access This field indicates the FIFO selected for debug access" "0: Tx FIFO,1: Tx Status FIFO (only read access when SLVMOD..,2: TSO FIFO (cannot be accessed when SLVMOD is..,3: Rx FIFO"
|
|
newline
|
|
bitfld.long 0x00 11. "FIFOWREN,FIFO Write Enable When this bit is set it enables the Write operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Write is disabled,1: FIFO Write is enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "FIFORDEN,FIFO Read Enable When this bit is set it enables the Read operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Read is disabled,1: FIFO Read is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "RSTSEL,Reset Pointers of Selected FIFO When this bit is set the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled" "0: Reset Pointers of Selected FIFO is disabled,1: Reset Pointers of Selected FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "RSTALL,Reset All Pointers When this bit is set the pointers of all FIFOs are reset when FIFO Debug Access is enabled" "0: Reset All Pointers is disabled,1: Reset All Pointers is enabled"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "PKTSTATE,Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Write operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid"
|
|
newline
|
|
bitfld.long 0x00 1. "DBGMOD,Debug Mode Access to FIFO When this bit is set it indicates that the current access to the FIFO is read write and debug access" "0: Debug Mode Access to FIFO is disabled,1: Debug Mode Access to FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FDBGEN,FIFO Debug Access Enable When this bit is set it indicates that the debug mode access to the FIFO is enabled" "0: FIFO Debug Access is disabled,1: FIFO Debug Access is enabled"
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "MTL_DBG_STS,FIFO Debug Status"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. "LOCR,Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO"
|
|
newline
|
|
bitfld.long 0x00 9. "STSI,Transmit Status Available Interrupt Status When set this bit indicates that the Slave mode Tx packet is transmitted and the status is available in Tx Status FIFO" "0: Transmit Status Available Interrupt Status..,1: Transmit Status Available Interrupt Status.."
|
|
newline
|
|
bitfld.long 0x00 8. "PKTI,Receive Packet Available Interrupt Status When set this bit indicates that MAC layer has written the EOP of received packet to the Rx FIFO" "0: Receive Packet Available Interrupt Status not..,1: Receive Packet Available Interrupt Status.."
|
|
newline
|
|
rbitfld.long 0x00 3.--4. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Read operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid"
|
|
newline
|
|
rbitfld.long 0x00 1.--2. "PKTSTATE,Encoded Packet State This field is used to get the control or status information of the selected FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP"
|
|
newline
|
|
rbitfld.long 0x00 0. "FIFOBUSY,FIFO Busy When set this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid: - All other fields of this register - All fields of the MTL_FIFO_DEBUG_DATA register" "0: FIFO Busy not detected,1: FIFO Busy detected"
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "MTL_FIFO_DEBUG_DATA,FIFO Debug Data"
|
|
hexmask.long 0x00 0.--31. 1. "FDBGDATA,FIFO Debug Data During debug or slave access write operation this field contains the data to be written to the Tx FIFO Rx FIFO or TSO FIFO"
|
|
rgroup.long 0xC20++0x03
|
|
line.long 0x00 "MTL_INTERRUPT_STATUS,MTL Interrupt Status"
|
|
bitfld.long 0x00 23. "MTLPIS,MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block" "0: MTL Rx Parser Interrupt status not detected,1: MTL Rx Parser Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 18. "ESTIS,EST (TAS- 802" "0: EST (TAS- 802.1Qbv) Interrupt status not..,1: EST (TAS- 802.1Qbv) Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 17. "DBGIS,Debug Interrupt status This bit indicates an interrupt event during the slave access" "0: Debug Interrupt status not detected,1: Debug Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 4. "Q4IS,Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4" "0: Queue 4 Interrupt status not detected,1: Queue 4 Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 3. "Q3IS,Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3" "0: Queue 3 Interrupt status not detected,1: Queue 3 Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 2. "Q2IS,Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2" "0: Queue 2 Interrupt status not detected,1: Queue 2 Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 1. "Q1IS,Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1" "0: Queue 1 Interrupt status not detected,1: Queue 1 Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "Q0IS,Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0" "0: Queue 0 Interrupt status not detected,1: Queue 0 Interrupt status detected"
|
|
group.long 0xC30++0x03
|
|
line.long 0x00 "MTL_RXQ_DMA_MAP0,Receive Queue and DMA Channel Mapping 0"
|
|
bitfld.long 0x00 28. "Q3DDMACH,Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set this bit indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in.." "0: Queue 3 disabled for DA-based DMA Channel..,1: Queue 3 enabled for DA-based DMA Channel.."
|
|
newline
|
|
bitfld.long 0x00 24.--26. "Q3MDMACH,Queue 3 Mapped to DMA Channel This field controls the routing of the received packet in Queue 3 to the DMA channel" "0: DMA Channel,1: DMA Channel,2: DMA Channel,3: DMA Channel,4: DMA Channel,5: DMA Channel,6: DMA Channel,7: DMA Channel 7 This field is valid when the"
|
|
newline
|
|
bitfld.long 0x00 20. "Q2DDMACH,Queue 2 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 2 disabled for DA-based DMA Channel..,1: Queue 2 enabled for DA-based DMA Channel.."
|
|
newline
|
|
bitfld.long 0x00 16.--18. "Q2MDMACH,Queue 2 Mapped to DMA Channel This field controls the routing of the received packet in Queue 2 to the DMA channel" "0: DMA Channel,1: DMA Channel,2: DMA Channel,3: DMA Channel,4: DMA Channel,5: DMA Channel,6: DMA Channel,7: DMA Channel 7 This field is valid when the"
|
|
newline
|
|
bitfld.long 0x00 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 1 disabled for DA-based DMA Channel..,1: Queue 1 enabled for DA-based DMA Channel.."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "Q1MDMACH,Queue 1 Mapped to DMA Channel This field controls the routing of the received packet in Queue 1 to the DMA channel" "0: DMA Channel,1: DMA Channel,2: DMA Channel,3: DMA Channel,4: DMA Channel,5: DMA Channel,6: DMA Channel,7: DMA Channel 7 This field is valid when the"
|
|
newline
|
|
bitfld.long 0x00 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 0 disabled for DA-based DMA Channel..,1: Queue 0 enabled for DA-based DMA Channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "Q0MDMACH,Queue 0 Mapped to DMA Channel This field controls the routing of the packet received in Queue 0 to the DMA channel" "0: DMA Channel,1: DMA Channel,2: DMA Channel,3: DMA Channel,4: DMA Channel,5: DMA Channel,6: DMA Channel,7: DMA Channel 7 This field is valid when the"
|
|
group.long 0xC34++0x03
|
|
line.long 0x00 "MTL_RXQ_DMA_MAP1,Receive Queue and DMA Channel Mapping 1"
|
|
bitfld.long 0x00 4. "Q4DDMACH,Queue 4 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 4 disabled for DA-based DMA Channel..,1: Queue 4 enabled for DA-based DMA Channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "Q4MDMACH,Queue 4 Mapped to DMA Channel This field controls the routing of the packet received in Queue 4 to the DMA channel" "0: DMA Channel,1: DMA Channel,2: DMA Channel,3: DMA Channel,4: DMA Channel,5: DMA Channel,6: DMA Channel,7: DMA Channel 7 This field is valid when the"
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "MTL_TBS_CTRL,Time Based Scheduling Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "LEOS,Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the Launch time to compute the Launch Expiry time"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "LEGOS,Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 1. "LEOV,Launch Expiry Offset Valid When set indicates the LEOS field is valid" "0: LEOS field is invalid,1: LEOS field is valid"
|
|
newline
|
|
bitfld.long 0x00 0. "ESTM,EST offset Mode When this bit is set the Launch Time value used in Time Based Scheduling is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the current list" "0: EST offset Mode is disabled,1: EST offset Mode is enabled"
|
|
group.long 0xC50++0x03
|
|
line.long 0x00 "MTL_EST_CONTROL,Enhancements to Scheduled Transmission Control"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PTOV,PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds"
|
|
newline
|
|
hexmask.long.word 0x00 12.--23. 1. "CTOV,Current Time Offset Value Provides a 12 bit time offset value in nano second that is added to the current time to compensate for all the implementation pipeline delays such as the CDC sync delay buffering delays data path delays etc"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TILS,Time Interval Left Shift Amount This field provides the left shift amount for the programmed Time Interval values used in the Gate Control Lists" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "LCSE,Loop Count to report Scheduling Error Programmable number of GCL list iterations before reporting an HLBS error defined in EST_STATUS register" "0: 4 iterations,1: 8 iterations,2: 16 iterations,3: 32 iterations"
|
|
newline
|
|
bitfld.long 0x00 5. "DFBS,Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due to not getting scheduled (HLBS field of EST_STATUS register) after 4 8 16 32 (based on LCSE field of this register) GCL iterations are dropped" "0: Do not Drop Frames causing Scheduling Error,1: Drop Frames causing Scheduling Error"
|
|
newline
|
|
bitfld.long 0x00 4. "DDBF,Do not Drop frames during Frame Size Error When set frames are not be dropped during Head-of-Line blocking due to Frame Size Error (HLBF field of MTL_EST_STATUS register)" "0: Drop frames during Frame Size Error,1: Do not Drop frames during Frame Size Error"
|
|
newline
|
|
bitfld.long 0x00 1. "SSWL,Switch to S/W owned list When set indicates that the software has programmed that list that it currently owns (SWOL) and the hardware should switch to the new list based on the new BTR" "0: Switch to S/W owned list is disabled,1: Switch to S/W owned list is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "EEST,Enable EST When reset the gate control list processing is halted and all gates are assumed to be in Open state" "0: EST is disabled,1: EST is enabled"
|
|
group.long 0xC58++0x03
|
|
line.long 0x00 "MTL_EST_STATUS,Enhancements to Scheduled Transmission Status"
|
|
rbitfld.long 0x00 16.--19. "CGSN,Current GCL Slot Number Indicates the slot number of the GCL list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "BTRL,BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 7. "SWOL,S/W owned list When '0' indicates Gate control list number 0 is owned by software and when 1 indicates the Gate Control list 1 is owned by the software" "0: Gate control list number 0 is owned by software,1: Gate control list number 1 is owned by software"
|
|
newline
|
|
bitfld.long 0x00 4. "CGCE,Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the Cycle Time (CTR)" "0: Constant Gate Control Error not detected,1: Constant Gate Control Error detected"
|
|
newline
|
|
rbitfld.long 0x00 3. "HLBS,Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL" "0: Head-Of-Line Blocking due to Scheduling not..,1: Head-Of-Line Blocking due to Scheduling.."
|
|
newline
|
|
rbitfld.long 0x00 2. "HLBF,Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or equal to the duration needed for frame size (or frame fragment.." "0: Head-Of-Line Blocking due to Frame Size not..,1: Head-Of-Line Blocking due to Frame Size.."
|
|
newline
|
|
bitfld.long 0x00 1. "BTRE,BTR Error When 1 indicates a programming error in the BTR of SWOL where the programmed value is less than current time" "0: BTR Error not detected,1: BTR Error detected"
|
|
newline
|
|
bitfld.long 0x00 0. "SWLC,Switch to S/W owned list Complete When 1 indicates the hardware has successfully switched to the SWOL and the SWOL bit has been updated to that effect" "0: Switch to S/W owned list Complete not detected,1: Switch to S/W owned list Complete detected"
|
|
group.long 0xC60++0x03
|
|
line.long 0x00 "MTL_EST_SCH_ERROR,EST Scheduling Error"
|
|
bitfld.long 0x00 0.--4. "SEQN,Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced error/timeout described in HLBS field of status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC64++0x03
|
|
line.long 0x00 "MTL_EST_FRM_SIZE_ERROR,EST Frame Size Error"
|
|
bitfld.long 0x00 0.--4. "FEQN,Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced error described in HLBF field of status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xC68++0x03
|
|
line.long 0x00 "MTL_EST_FRM_SIZE_CAPTURE,EST Frame Size Capture"
|
|
bitfld.long 0x00 16.--18. "HBFQ,Queue Number of HLBF Captures the binary value of the of the first Queue (number) experiencing HLBF error (see HLBF field of status register)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x00 0.--14. 1. "HBFS,Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number indicated in HBFQ field of this register"
|
|
group.long 0xC70++0x03
|
|
line.long 0x00 "MTL_EST_INTR_ENABLE,EST Interrupt Enable"
|
|
bitfld.long 0x00 4. "CGCE,Interrupt Enable for CGCE When set generates interrupt when the Constant Gate Control Error occurs and is indicated in the status" "0: Interrupt for CGCE is disabled,1: Interrupt for CGCE is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEHS,Interrupt Enable for HLBS When set generates interrupt when the Head-of-Line Blocking due to Scheduling issue and is indicated in the status" "0: Interrupt for HLBS is disabled,1: Interrupt for HLBS is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "IEHF,Interrupt Enable for HLBF When set generates interrupt when the Head-of-Line Blocking due to Frame Size error occurs and is indicated in the status" "0: Interrupt for HLBF is disabled,1: Interrupt for HLBF is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEBE,Interrupt Enable for BTR Error When set generates interrupt when the BTR Error occurs and is indicated in the status" "0: Interrupt for BTR Error is disabled,1: Interrupt for BTR Error is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "IECC,Interrupt Enable for Switch List When set generates interrupt when the configuration change is successful and the hardware has switched to the new list" "0: Interrupt for Switch List is disabled,1: Interrupt for Switch List is enabled"
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "MTL_EST_GCL_CONTROL,EST GCL Control"
|
|
rbitfld.long 0x00 22.--23. "ESTEIEC,ECC Inject Error Control for EST Memory When EIEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: Insert 2 bit errors,2: Insert 3 bit errors,3: Insert 1 bit error in address field"
|
|
newline
|
|
rbitfld.long 0x00 21. "ESTEIEE,EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_CONTROL register enables the ECC error injection feature" "0: EST ECC Inject Error is disabled,1: EST ECC Inject Error is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "ERR0,When set indicates the last write operation was aborted as software writes to GCL and GCL registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set" "0: ERR0 is disabled,1: ERR1 is enabled"
|
|
newline
|
|
hexmask.long.word 0x00 8.--16. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is 0 )"
|
|
newline
|
|
bitfld.long 0x00 5. "DBGB,Debug Mode Bank Select When set to 0 indicates R/W in debug mode should be directed to Bank 0 (GCL0 and corresponding Time related registers)" "0: R/W in debug mode should be directed to Bank 0,1: R/W in debug mode should be directed to Bank 1"
|
|
newline
|
|
bitfld.long 0x00 4. "DBGM,Debug Mode When set to 1 indicates R/W in debug mode where the memory bank (for GCL and Time related registers) is explicitly provided by DBGB value when set to 0 SWOL bit is used to determine which bank to use" "0: Debug Mode is disabled,1: Debug Mode is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "GCRR,Gate Control Related Registers When set to 1 indicates the R/W access is for the GCL related registers (BTR CTR TER LLR) whose address is provided by GCRA" "0: Gate Control Related Registers are disabled,1: Gate Control Related Registers are enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "R1W0,Read '1' Write '0': When set to '1': Read Operation When set to '0': Write Operation" "0: Write Operation,1: Read Operation"
|
|
newline
|
|
bitfld.long 0x00 0. "SRWO,Start Read/Write Op When set indicates a Read/Write Op has started and is in progress" "0: Start Read/Write Op disabled,1: Start Read/Write Op enabled"
|
|
group.long 0xC84++0x03
|
|
line.long 0x00 "MTL_EST_GCL_DATA,EST GCL Data"
|
|
hexmask.long 0x00 0.--31. 1. "GCD,Gate Control Data The data corresponding to the address selected in the MTL_GCL_CONTROL register"
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "MTL_FPE_CTRL_STS,Frame Preemption Control and Status"
|
|
rbitfld.long 0x00 28. "HRS,Hold/Release Status" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was.."
|
|
newline
|
|
bitfld.long 0x00 8.--12. "PEC,Preemption Classification When set indicates the corresponding Queue must be classified as preemptable when '0' Queue is classified as express" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "AFSZ,Additional Fragment Size used to indicate in units of 64 bytes the minimum number of bytes over 64 bytes required in non-final fragments of preempted frames" "0,1,2,3"
|
|
group.long 0xC94++0x03
|
|
line.long 0x00 "MTL_FPE_ADVANCE,Frame Preemption Hold and Release Advance"
|
|
hexmask.long.word 0x00 16.--31. 1. "RADV,Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE to the MAC and the MAC being ready to resume transmission of preemptable frames in the absence of there being any express frames available for transmission"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "HADV,Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of transmission or any preemptable frames that are queued for transmission"
|
|
group.long 0xCA0++0x03
|
|
line.long 0x00 "MTL_RXP_CONTROL_STATUS,RXP Control Status"
|
|
rbitfld.long 0x00 31. "RXPI,RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State and waiting for a new packet for processing" "0: RX Parser not in Idle state,1: RX Parser in Idle state"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "NPE,Number of parsable entries in the Instruction table This control indicates the number of parsable entries in the Instruction Memory"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "NVE,Number of valid entries in the Instruction table This control indicates the number of valid entries in the Instruction Memory"
|
|
group.long 0xCA4++0x03
|
|
line.long 0x00 "MTL_RXP_INTERRUPT_CONTROL_STATUS,RXP Interrupt Control Status"
|
|
bitfld.long 0x00 19. "PDRFIE,Packet Drop due to RF Interrupt Enable When this bit is set the PDRFIS interrupt is enabled" "0: Packet Drop due to RF Interrupt is disabled,1: Packet Drop due to RF Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "FOOVIE,Frame Offset Overflow Interrupt Enable When this bit is set the FOOVIS interrupt is enabled" "0: Frame Offset Overflow Interrupt is disabled,1: Frame Offset Overflow Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "NPEOVIE,Number of Parsable Entries Overflow Interrupt Enable When this bit is set the NPEOVIS interrupt is enabled" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 16. "NVEOVIE,Number of Valid Entries Overflow Interrupt Enable When this bit is set the NVEOVIS interrupt is enabled" "0: Number of Valid Entries Overflow Interrupt is..,1: Number of Valid Entries Overflow Interrupt is.."
|
|
newline
|
|
bitfld.long 0x00 3. "PDRFIS,Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the packet by setting RF=1 in the instruction memory then this bit is set to 1" "0: Packet Dropped due to RF Interrupt Status not..,1: Packet Dropped due to RF Interrupt Status.."
|
|
newline
|
|
bitfld.long 0x00 2. "FOOVIS,Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's 'Frame Offset' found to be more than EOF offset then then this bit is set" "0: Frame Offset Overflow Interrupt Status not..,1: Frame Offset Overflow Interrupt Status detected"
|
|
newline
|
|
bitfld.long 0x00 1. "NPEOVIS,Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the number of parsed entries found to be more than NPE[] (Number of Parseable Entries in MTL_RXP_CONTROL register) then this bit is set to 1" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.."
|
|
newline
|
|
bitfld.long 0x00 0. "NVEOVIS,Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction address found to be more than NVE (Number of Valid Entries in MTL_RXP_CONTROL register) then this bit is set to 1" "0: Number of Valid Entries Overflow Interrupt..,1: Number of Valid Entries Overflow Interrupt.."
|
|
rgroup.long 0xCA8++0x03
|
|
line.long 0x00 "MTL_RXP_DROP_CNT,RXP Drop Count"
|
|
bitfld.long 0x00 31. "RXPDCOVF,Rx Parser Drop Counter Overflow Bit When set this bit indicates that the MTL_RXP_DROP_CNT (RXPDC) Counter field crossed the maximum limit" "0: Rx Parser Drop count overflow not occurred,1: Rx Parser Drop count overflow occurred"
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "RXPDC,Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1"
|
|
rgroup.long 0xCAC++0x03
|
|
line.long 0x00 "MTL_RXP_ERROR_CNT,RXP Error Count"
|
|
bitfld.long 0x00 31. "RXPECOVF,Rx Parser Error Counter Overflow Bit When set this bit indicates that the MTL_RXP_ERROR_CNT (RXPEC) Counter field crossed the maximum limit" "0: Rx Parser Error count overflow not occurred,1: Rx Parser Error count overflow occurred"
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "RXPEC,Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry address > EOF data entry address The counter is cleared when the.."
|
|
group.long 0xCB0++0x03
|
|
line.long 0x00 "MTL_RXP_INDIRECT_ACC_CONTROL_STATUS,RXP Indirect Access Control and Status"
|
|
bitfld.long 0x00 31. "STARTBUSY,FRP Instruction Table Access Busy When this bit is set to 1 by the software then it indicates to start the Read/Write operation from/to the Rx Parser Memory" "0: hardware not busy,1: hardware is busy (Read/Write operation.."
|
|
newline
|
|
bitfld.long 0x00 16. "WRRDN,Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory" "0: Read operation to the Rx Parser Memory,1: Write operation to the Rx Parser Memory"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "ADDR,FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table"
|
|
group.long 0xCB4++0x03
|
|
line.long 0x00 "MTL_RXP_INDIRECT_ACC_DATA,RXP Indirect Access Data"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,FRP Instruction Table Write/Read Data Software should write this register before issuing any write command"
|
|
group.long 0xD00++0x03
|
|
line.long 0x00 "MTL_TXQ0_OPERATION_MODE,Queue 0 Transmit Operation Mode"
|
|
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: bf_32BYTES,1: bf_64BYTES,2: bf_96BYTES,3: bf_128BYTES,4: bf_192BYTES,5: bf_256BYTES,6: bf_384BYTES,7: bf_512BYTES"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
|
|
rgroup.long 0xD04++0x03
|
|
line.long 0x00 "MTL_TXQ0_UNDERFLOW,Queue 0 Underflow Counter"
|
|
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
|
|
rgroup.long 0xD08++0x03
|
|
line.long 0x00 "MTL_TXQ0_DEBUG,Queue 0 Transmit Debug"
|
|
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
|
|
newline
|
|
bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
|
|
newline
|
|
bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
|
|
newline
|
|
bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
|
|
rgroup.long 0xD14++0x03
|
|
line.long 0x00 "MTL_TXQ0_ETS_STATUS,Queue 0 ETS Status"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
|
|
group.long 0xD18++0x03
|
|
line.long 0x00 "MTL_TXQ0_QUANTUM_WEIGHT,Queue 0 Quantum or Weights"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 traffic this field contains the quantum value in bytes to be added to credit during every queue scanning cycle"
|
|
group.long 0xD2C++0x03
|
|
line.long 0x00 "MTL_Q0_INTERRUPT_CONTROL_STATUS,Queue 0 Interrupt Control Status"
|
|
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
|
|
newline
|
|
bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
|
|
newline
|
|
bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "MTL_RXQ0_OPERATION_MODE,Queue 0 Receive Operation Mode"
|
|
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
|
|
newline
|
|
bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: bf_64BYTE,1: bf_32BYTE,2: bf_96BYTE,3: bf_128BYTE"
|
|
rgroup.long 0xD34++0x03
|
|
line.long 0x00 "MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT,Queue 0 Missed Packet and Overflow Counter"
|
|
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
|
|
newline
|
|
hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
|
|
newline
|
|
bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
|
|
rgroup.long 0xD38++0x03
|
|
line.long 0x00 "MTL_RXQ0_DEBUG,Queue 0 Receive Debug"
|
|
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
|
|
newline
|
|
bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
|
|
group.long 0xD3C++0x03
|
|
line.long 0x00 "MTL_RXQ0_CONTROL,Queue 0 Receive Control"
|
|
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD40++0x03
|
|
line.long 0x00 "MTL_TXQ1_OPERATION_MODE,Queue 1 Transmit Operation Mode"
|
|
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: bf_32BYTES,1: bf_64BYTES,2: bf_96BYTES,3: bf_128BYTES,4: bf_192BYTES,5: bf_256BYTES,6: bf_384BYTES,7: bf_512BYTES"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
|
|
rgroup.long 0xD44++0x03
|
|
line.long 0x00 "MTL_TXQ1_UNDERFLOW,Queue 1 Underflow Counter"
|
|
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
|
|
rgroup.long 0xD48++0x03
|
|
line.long 0x00 "MTL_TXQ1_DEBUG,Queue 1 Transmit Debug"
|
|
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
|
|
newline
|
|
bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
|
|
newline
|
|
bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
|
|
newline
|
|
bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
|
|
group.long 0xD50++0x03
|
|
line.long 0x00 "MTL_TXQ1_ETS_CONTROL,Queue 1 ETS Control"
|
|
bitfld.long 0x00 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "0: bf_1_SLOT,1: bf_2_SLOT,2: bf_4_SLOT,3: bf_8_SLOT,4: bf_16_SLOT,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled"
|
|
rgroup.long 0xD54++0x03
|
|
line.long 0x00 "MTL_TXQ1_ETS_STATUS,Queue 1 ETS Status"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
|
|
group.long 0xD58++0x03
|
|
line.long 0x00 "MTL_TXQ1_QUANTUM_WEIGHT,Queue 1 idleSlopeCredit Quantum or Weights"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1"
|
|
group.long 0xD5C++0x03
|
|
line.long 0x00 "MTL_TXQ1_SENDSLOPECREDIT,Queue 1 sendSlopeCredit"
|
|
hexmask.long.word 0x00 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1"
|
|
group.long 0xD60++0x03
|
|
line.long 0x00 "MTL_TXQ1_HICREDIT,Queue 1 hiCredit"
|
|
hexmask.long 0x00 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm"
|
|
group.long 0xD64++0x03
|
|
line.long 0x00 "MTL_TXQ1_LOCREDIT,Queue 1 loCredit"
|
|
hexmask.long 0x00 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm"
|
|
group.long 0xD6C++0x03
|
|
line.long 0x00 "MTL_Q1_INTERRUPT_CONTROL_STATUS,Queue 1 Interrupt Control Status"
|
|
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
|
|
newline
|
|
bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
|
|
newline
|
|
bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
|
|
group.long 0xD70++0x03
|
|
line.long 0x00 "MTL_RXQ1_OPERATION_MODE,Queue 1 Receive Operation Mode"
|
|
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
|
|
newline
|
|
bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: bf_64BYTE,1: bf_32BYTE,2: bf_96BYTE,3: bf_128BYTE"
|
|
rgroup.long 0xD74++0x03
|
|
line.long 0x00 "MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT,Queue 1 Missed Packet and Overflow Counter"
|
|
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
|
|
newline
|
|
hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
|
|
newline
|
|
bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
|
|
rgroup.long 0xD78++0x03
|
|
line.long 0x00 "MTL_RXQ1_DEBUG,Queue 1 Receive Debug"
|
|
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
|
|
newline
|
|
bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
|
|
group.long 0xD7C++0x03
|
|
line.long 0x00 "MTL_RXQ1_CONTROL,Queue 1 Receive Control"
|
|
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD80++0x03
|
|
line.long 0x00 "MTL_TXQ2_OPERATION_MODE,Queue 2 Transmit Operation Mode"
|
|
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: bf_32BYTES,1: bf_64BYTES,2: bf_96BYTES,3: bf_128BYTES,4: bf_192BYTES,5: bf_256BYTES,6: bf_384BYTES,7: bf_512BYTES"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
|
|
rgroup.long 0xD84++0x03
|
|
line.long 0x00 "MTL_TXQ2_UNDERFLOW,Queue 2 Underflow Counter"
|
|
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
|
|
rgroup.long 0xD88++0x03
|
|
line.long 0x00 "MTL_TXQ2_DEBUG,Queue 2 Transmit Debug"
|
|
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
|
|
newline
|
|
bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
|
|
newline
|
|
bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
|
|
newline
|
|
bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
|
|
group.long 0xD90++0x03
|
|
line.long 0x00 "MTL_TXQ2_ETS_CONTROL,Queue 2 ETS Control"
|
|
bitfld.long 0x00 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[N]_SLOT_INTERVAL register) over which the average transmitted bits per slot provided in the.." "0: bf_1_SLOT,1: bf_2_SLOT,2: bf_4_SLOT,3: bf_8_SLOT,4: bf_16_SLOT,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled"
|
|
rgroup.long 0xD94++0x03
|
|
line.long 0x00 "MTL_TXQ2_ETS_STATUS,Queue 2 ETS Status"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MTL_TXQ2_QUANTUM_WEIGHT,Queue 2 idleSlopeCredit Quantum or Weights"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1"
|
|
group.long 0xD9C++0x03
|
|
line.long 0x00 "MTL_TXQ2_SENDSLOPECREDIT,Queue 2 sendSlopeCredit"
|
|
hexmask.long.word 0x00 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1"
|
|
group.long 0xDA0++0x03
|
|
line.long 0x00 "MTL_TXQ2_HICREDIT,Queue 2 hiCredit"
|
|
hexmask.long 0x00 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm"
|
|
group.long 0xDA4++0x03
|
|
line.long 0x00 "MTL_TXQ2_LOCREDIT,Queue 2 loCredit"
|
|
hexmask.long 0x00 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm"
|
|
group.long 0xDAC++0x03
|
|
line.long 0x00 "MTL_Q2_INTERRUPT_CONTROL_STATUS,Queue 2 Interrupt Control Status"
|
|
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
|
|
newline
|
|
bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
|
|
newline
|
|
bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
|
|
group.long 0xDB0++0x03
|
|
line.long 0x00 "MTL_RXQ2_OPERATION_MODE,Queue 2 Receive Operation Mode"
|
|
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
|
|
newline
|
|
bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: bf_64BYTE,1: bf_32BYTE,2: bf_96BYTE,3: bf_128BYTE"
|
|
rgroup.long 0xDB4++0x03
|
|
line.long 0x00 "MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT,Queue 2 Missed Packet and Overflow Counter"
|
|
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
|
|
newline
|
|
hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
|
|
newline
|
|
bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
|
|
rgroup.long 0xDB8++0x03
|
|
line.long 0x00 "MTL_RXQ2_DEBUG,Queue 2 Receive Debug"
|
|
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
|
|
newline
|
|
bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
|
|
group.long 0xDBC++0x03
|
|
line.long 0x00 "MTL_RXQ2_CONTROL,Queue 2 Receive Control"
|
|
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xDC0++0x03
|
|
line.long 0x00 "MTL_TXQ3_OPERATION_MODE,Queue 3 Transmit Operation Mode"
|
|
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: bf_32BYTES,1: bf_64BYTES,2: bf_96BYTES,3: bf_128BYTES,4: bf_192BYTES,5: bf_256BYTES,6: bf_384BYTES,7: bf_512BYTES"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
|
|
rgroup.long 0xDC4++0x03
|
|
line.long 0x00 "MTL_TXQ3_UNDERFLOW,Queue 3 Underflow Counter"
|
|
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
|
|
rgroup.long 0xDC8++0x03
|
|
line.long 0x00 "MTL_TXQ3_DEBUG,Queue 3 Transmit Debug"
|
|
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
|
|
newline
|
|
bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
|
|
newline
|
|
bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
|
|
newline
|
|
bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "MTL_TXQ3_ETS_CONTROL,Queue 3 ETS Control"
|
|
bitfld.long 0x00 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[N]_SLOT_INTERVAL register) over which the average transmitted bits per slot provided in the.." "0: bf_1_SLOT,1: bf_2_SLOT,2: bf_4_SLOT,3: bf_8_SLOT,4: bf_16_SLOT,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "MTL_TXQ3_ETS_STATUS,Queue 3 ETS Status"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "MTL_TXQ3_QUANTUM_WEIGHT,Queue 3 idleSlopeCredit Quantum or Weights"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1"
|
|
group.long 0xDDC++0x03
|
|
line.long 0x00 "MTL_TXQ3_SENDSLOPECREDIT,Queue 3 sendSlopeCredit"
|
|
hexmask.long.word 0x00 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1"
|
|
group.long 0xDE0++0x03
|
|
line.long 0x00 "MTL_TXQ3_HICREDIT,Queue 3 hiCredit"
|
|
hexmask.long 0x00 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm"
|
|
group.long 0xDE4++0x03
|
|
line.long 0x00 "MTL_TXQ3_LOCREDIT,Queue 3 loCredit"
|
|
hexmask.long 0x00 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm"
|
|
group.long 0xDEC++0x03
|
|
line.long 0x00 "MTL_Q3_INTERRUPT_CONTROL_STATUS,Queue 3 Interrupt Control Status"
|
|
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
|
|
newline
|
|
bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
|
|
newline
|
|
bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "MTL_RXQ3_OPERATION_MODE,Queue 3 Receive Operation Mode"
|
|
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
|
|
newline
|
|
bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: bf_64BYTE,1: bf_32BYTE,2: bf_96BYTE,3: bf_128BYTE"
|
|
rgroup.long 0xDF4++0x03
|
|
line.long 0x00 "MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT,Queue 3 Missed Packet and Overflow Counter"
|
|
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
|
|
newline
|
|
hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
|
|
newline
|
|
bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
|
|
rgroup.long 0xDF8++0x03
|
|
line.long 0x00 "MTL_RXQ3_DEBUG,Queue 3 Receive Debug"
|
|
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
|
|
newline
|
|
bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "MTL_RXQ3_CONTROL,Queue 3 Receive Control"
|
|
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "MTL_TXQ4_OPERATION_MODE,Queue 4 Transmit Operation Mode"
|
|
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: bf_32BYTES,1: bf_64BYTES,2: bf_96BYTES,3: bf_128BYTES,4: bf_192BYTES,5: bf_256BYTES,6: bf_384BYTES,7: bf_512BYTES"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
|
|
rgroup.long 0xE04++0x03
|
|
line.long 0x00 "MTL_TXQ4_UNDERFLOW,Queue 4 Underflow Counter"
|
|
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
|
|
rgroup.long 0xE08++0x03
|
|
line.long 0x00 "MTL_TXQ4_DEBUG,Queue 4 Transmit Debug"
|
|
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
|
|
newline
|
|
bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
|
|
newline
|
|
bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
|
|
newline
|
|
bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
|
|
group.long 0xE10++0x03
|
|
line.long 0x00 "MTL_TXQ4_ETS_CONTROL,Queue 4 ETS Control"
|
|
bitfld.long 0x00 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[N]_SLOT_INTERVAL register) over which the average transmitted bits per slot provided in the.." "0: bf_1_SLOT,1: bf_2_SLOT,2: bf_4_SLOT,3: bf_8_SLOT,4: bf_16_SLOT,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled"
|
|
rgroup.long 0xE14++0x03
|
|
line.long 0x00 "MTL_TXQ4_ETS_STATUS,Queue 4 ETS Status"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
|
|
group.long 0xE18++0x03
|
|
line.long 0x00 "MTL_TXQ4_QUANTUM_WEIGHT,Queue 4 idleSlopeCredit Quantum or Weights"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1"
|
|
group.long 0xE1C++0x03
|
|
line.long 0x00 "MTL_TXQ4_SENDSLOPECREDIT,Queue 4 sendSlopeCredit"
|
|
hexmask.long.word 0x00 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1"
|
|
group.long 0xE20++0x03
|
|
line.long 0x00 "MTL_TXQ4_HICREDIT,Queue 4 hiCredit"
|
|
hexmask.long 0x00 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm"
|
|
group.long 0xE24++0x03
|
|
line.long 0x00 "MTL_TXQ4_LOCREDIT,Queue 4 loCredit"
|
|
hexmask.long 0x00 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm"
|
|
group.long 0xE2C++0x03
|
|
line.long 0x00 "MTL_Q4_INTERRUPT_CONTROL_STATUS,Queue 4 Interrupt Control Status"
|
|
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
|
|
newline
|
|
bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
|
|
newline
|
|
bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
|
|
group.long 0xE30++0x03
|
|
line.long 0x00 "MTL_RXQ4_OPERATION_MODE,Queue 4 Receive Operation Mode"
|
|
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
|
|
newline
|
|
bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: bf_64BYTE,1: bf_32BYTE,2: bf_96BYTE,3: bf_128BYTE"
|
|
rgroup.long 0xE34++0x03
|
|
line.long 0x00 "MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT,Queue 4 Missed Packet and Overflow Counter"
|
|
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
|
|
newline
|
|
hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
|
|
newline
|
|
bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
|
|
rgroup.long 0xE38++0x03
|
|
line.long 0x00 "MTL_RXQ4_DEBUG,Queue 4 Receive Debug"
|
|
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
|
|
newline
|
|
bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
|
|
group.long 0xE3C++0x03
|
|
line.long 0x00 "MTL_RXQ4_CONTROL,Queue 4 Receive Control"
|
|
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "DMA_MODE,DMA Bus Mode"
|
|
bitfld.long 0x00 16.--17. "INTM,Interrupt Mode This field defines the interrupt mode of DWC_ether_qos" "0: See above description,1: See above description,2: See above description,?..."
|
|
newline
|
|
bitfld.long 0x00 8. "DSPW,Descriptor Posted Write When this bit is set to 0 the descriptor writes are always non-posted" "0: Descriptor Posted Write is disabled,1: Descriptor Posted Write is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "SWR,Software Reset When this bit is set the MAC and the DMA controller reset the logic and all internal registers of the DMA MTL and MAC" "0: Software Reset is disabled,1: Software Reset is enabled"
|
|
group.long 0x1004++0x03
|
|
line.long 0x00 "DMA_SYSBUS_MODE,DMA System Bus Mode"
|
|
bitfld.long 0x00 31. "EN_LPI,Enable Low Power Interface (LPI) When set to 1 this bit enables the LPI mode supported by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock controller" "0: Low Power Interface (LPI) is disabled,1: Low Power Interface (LPI) is enabled"
|
|
newline
|
|
bitfld.long 0x00 30. "LPI_XIT_PKT,Unlock on Magic Packet or Remote Wake-Up Packet When set to 1 this bit enables the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet is received" "0: Unlock on Magic Packet or Remote Wake-Up..,1: Unlock on Magic Packet or Remote Wake-Up.."
|
|
newline
|
|
bitfld.long 0x00 24.--27. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit This value limits the maximum outstanding request on the AXI write interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 13. "ONEKBBE,1 KB Boundary Crossing Enable for the EQOS-AXI Master When set the burst transfers performed by the EQOS-AXI master do not cross 1 KB boundary" "0: 1 KB Boundary Crossing for the EQOS-AXI..,1: 1 KB Boundary Crossing for the EQOS-AXI.."
|
|
newline
|
|
bitfld.long 0x00 12. "AAL,Address-Aligned Beats When this bit is set to 1 the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels" "0: Address-Aligned Beats is disabled,1: Address-Aligned Beats is enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "AALE,Automatic AXI LPI enable When set to 1 enables the AXI master to enter into LPI state when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in the LPIEI field of DMA_AXI_LPI_ENTRY_INTERVAL register" "0: Automatic AXI LPI is disabled,1: Automatic AXI LPI is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "BLEN16,AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 16 on the AXI interface" "0: No effect,1: AXI Burst Length 16"
|
|
newline
|
|
bitfld.long 0x00 2. "BLEN8,AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 8 on the AXI interface" "0: No effect,1: AXI Burst Length 8"
|
|
newline
|
|
bitfld.long 0x00 1. "BLEN4,AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 4 on the AXI interface" "0: No effect,1: AXI Burst Length 4"
|
|
newline
|
|
bitfld.long 0x00 0. "FB,Fixed Burst Length When this bit is set to 1 the EQOS-AXI master initiates burst transfers of specified lengths as given below" "0: Fixed Burst Length is disabled,1: Fixed Burst Length is enabled"
|
|
rgroup.long 0x1008++0x03
|
|
line.long 0x00 "DMA_INTERRUPT_STATUS,DMA Interrupt Status"
|
|
bitfld.long 0x00 17. "MACIS,MAC Interrupt Status This bit indicates an interrupt event in the MAC" "0: MAC Interrupt Status not detected,1: MAC Interrupt Status detected"
|
|
newline
|
|
bitfld.long 0x00 16. "MTLIS,MTL Interrupt Status This bit indicates an interrupt event in the MTL" "0: MTL Interrupt Status not detected,1: MTL Interrupt Status detected"
|
|
newline
|
|
bitfld.long 0x00 4. "DC4IS,DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4" "0: DMA Channel 4 Interrupt Status not detected,1: DMA Channel 4 Interrupt Status detected"
|
|
newline
|
|
bitfld.long 0x00 3. "DC3IS,DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3" "0: DMA Channel 3 Interrupt Status not detected,1: DMA Channel 3 Interrupt Status detected"
|
|
newline
|
|
bitfld.long 0x00 2. "DC2IS,DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2" "0: DMA Channel 2 Interrupt Status not detected,1: DMA Channel 2 Interrupt Status detected"
|
|
newline
|
|
bitfld.long 0x00 1. "DC1IS,DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1" "0: DMA Channel 1 Interrupt Status not detected,1: DMA Channel 1 Interrupt Status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "DC0IS,DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0" "0: DMA Channel 0 Interrupt Status not detected,1: DMA Channel 0 Interrupt Status detected"
|
|
rgroup.long 0x100C++0x03
|
|
line.long 0x00 "DMA_DEBUG_STATUS0,DMA Debug Status 0"
|
|
bitfld.long 0x00 28.--31. "TPS2,DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
|
|
newline
|
|
bitfld.long 0x00 24.--27. "RPS2,DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TPS1,DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "RPS1,DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "TPS0,DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RPS0,DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
|
|
newline
|
|
bitfld.long 0x00 1. "AXRHSTS,AXI Master Read Channel Status When high this bit indicates that the read channel of the AXI master is active and it is transferring the data" "0: AXI Master Read Channel Status not detected,1: AXI Master Read Channel Status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "AXWHSTS,AXI Master Write Channel When high this bit indicates that the write channel of the AXI master is active and it is transferring data" "0: AXI Master Write Channel or AHB Master Status..,1: AXI Master Write Channel or AHB Master Status.."
|
|
rgroup.long 0x1010++0x03
|
|
line.long 0x00 "DMA_DEBUG_STATUS1,DMA Debug Status 1"
|
|
bitfld.long 0x00 12.--15. "TPS4,DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "RPS4,DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "TPS3,DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "RPS3,DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "DMA_AXI_LPI_ENTRY_INTERVAL,AXI LPI Entry Interval Control"
|
|
bitfld.long 0x00 0.--3. "LPIEI,LPI Entry Interval Contains the number of system clock cycles multiplied by 64 to wait for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1050++0x03
|
|
line.long 0x00 "DMA_TBS_CTRL,TBS Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid"
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "DMA_CH0_CONTROL,DMA Channel 0 Control"
|
|
bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_TX_CONTROL and Bits[21:16] in DMA_CH0_RX_CONTROL is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
|
|
group.long 0x1104++0x03
|
|
line.long 0x00 "DMA_CH0_TX_CONTROL,DMA Channel 0 Transmit Control"
|
|
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "DMA_CH0_RX_CONTROL,DMA Channel 0 Receive Control"
|
|
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
|
|
newline
|
|
rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
|
|
group.long 0x1114++0x03
|
|
line.long 0x00 "DMA_CH0_TXDESC_LIST_ADDRESS,Channel 0 Tx Descriptor List Address register"
|
|
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
|
|
group.long 0x111C++0x03
|
|
line.long 0x00 "DMA_CH0_RXDESC_LIST_ADDRESS,Channel 0 Rx Descriptor List Address register"
|
|
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
|
|
group.long 0x1120++0x03
|
|
line.long 0x00 "DMA_CH0_TXDESC_TAIL_POINTER,Channel 0 Tx Descriptor Tail Pointer"
|
|
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "DMA_CH0_RXDESC_TAIL_POINTER,Channel 0 Rx Descriptor Tail Pointer"
|
|
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
|
|
group.long 0x112C++0x03
|
|
line.long 0x00 "DMA_CH0_TXDESC_RING_LENGTH,Channel 0 Tx Descriptor Ring Length"
|
|
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
|
|
group.long 0x1130++0x03
|
|
line.long 0x00 "DMA_CH0_RXDESC_RING_LENGTH,Channel 0 Rx Descriptor Ring Length"
|
|
hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
|
|
group.long 0x1134++0x03
|
|
line.long 0x00 "DMA_CH0_INTERRUPT_ENABLE,Channel 0 Interrupt Enable"
|
|
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
|
|
newline
|
|
bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
|
|
group.long 0x1138++0x03
|
|
line.long 0x00 "DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER,Channel 0 Receive Interrupt Watchdog Timer"
|
|
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
|
|
group.long 0x113C++0x03
|
|
line.long 0x00 "DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS,Channel 0 Slot Function Control and Status"
|
|
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
|
|
newline
|
|
bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
|
|
rgroup.long 0x1144++0x03
|
|
line.long 0x00 "DMA_CH0_CURRENT_APP_TXDESC,Channel 0 Current Application Transmit Descriptor"
|
|
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
|
|
rgroup.long 0x114C++0x03
|
|
line.long 0x00 "DMA_CH0_CURRENT_APP_RXDESC,Channel 0 Current Application Receive Descriptor"
|
|
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
|
|
rgroup.long 0x1154++0x03
|
|
line.long 0x00 "DMA_CH0_CURRENT_APP_TXBUFFER,Channel 0 Current Application Transmit Buffer Address"
|
|
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
|
|
rgroup.long 0x115C++0x03
|
|
line.long 0x00 "DMA_CH0_CURRENT_APP_RXBUFFER,Channel 0 Current Application Receive Buffer Address"
|
|
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
|
|
group.long 0x1160++0x03
|
|
line.long 0x00 "DMA_CH0_STATUS,DMA Channel 0 Status"
|
|
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_INTERRUPT_ENABLE register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
|
|
newline
|
|
bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
|
|
newline
|
|
bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow (intermediate descriptor) or all ones descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
|
|
newline
|
|
bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
|
|
newline
|
|
bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
|
|
newline
|
|
bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
|
|
newline
|
|
bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
|
|
newline
|
|
bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
|
|
newline
|
|
bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
|
|
rgroup.long 0x1164++0x03
|
|
line.long 0x00 "DMA_CH0_MISS_FRAME_CNT,Channel 0 Missed Frame Counter"
|
|
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in DMA_CH0_RX_CONTROL register"
|
|
rgroup.long 0x1168++0x03
|
|
line.long 0x00 "DMA_CH0_RXP_ACCEPT_CNT,Channel 0 RXP Frames Accepted Counter"
|
|
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1"
|
|
rgroup.long 0x116C++0x03
|
|
line.long 0x00 "DMA_CH0_RX_ERI_CNT,Channel 0 Receive ERI Counter"
|
|
hexmask.long.word 0x00 0.--11. 1. "ECNT,ERI Counter When ERIC bit of RX_CONTROL register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer"
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "DMA_CH1_CONTROL,DMA Channel 1 Control"
|
|
bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in TX_CONTROL and Bits[21:16] in DMA_CH1_RX_CONTROL is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
|
|
group.long 0x1184++0x03
|
|
line.long 0x00 "DMA_CH1_TX_CONTROL,DMA Channel 1 Transmit Control"
|
|
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "DMA_CH1_RX_CONTROL,DMA Channel 1 Receive Control"
|
|
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
|
|
newline
|
|
rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
|
|
group.long 0x1194++0x03
|
|
line.long 0x00 "DMA_CH1_TXDESC_LIST_ADDRESS,Channel 1 Tx Descriptor List Address"
|
|
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
|
|
group.long 0x119C++0x03
|
|
line.long 0x00 "DMA_CH1_RXDESC_LIST_ADDRESS,Channel 1 Rx Descriptor List Address"
|
|
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
|
|
group.long 0x11A0++0x03
|
|
line.long 0x00 "DMA_CH1_TXDESC_TAIL_POINTER,Channel 1 Tx Descriptor Tail Pointer"
|
|
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "DMA_CH1_RXDESC_TAIL_POINTER,Channel 1 Rx Descriptor Tail Pointer"
|
|
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
|
|
group.long 0x11AC++0x03
|
|
line.long 0x00 "DMA_CH1_TXDESC_RING_LENGTH,Channel 1 Tx Descriptor Ring Length"
|
|
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
|
|
group.long 0x11B0++0x03
|
|
line.long 0x00 "DMA_CH1_RXDESC_RING_LENGTH,Channel 1 Rx Descriptor Ring Length"
|
|
hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
|
|
group.long 0x11B4++0x03
|
|
line.long 0x00 "DMA_CH1_INTERRUPT_ENABLE,Channel 1 Interrupt Enable"
|
|
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
|
|
newline
|
|
bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
|
|
group.long 0x11B8++0x03
|
|
line.long 0x00 "DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER,Channel 1 Receive Interrupt Watchdog Timer"
|
|
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
|
|
group.long 0x11BC++0x03
|
|
line.long 0x00 "DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS,Channel 1 Slot Function Control and Status"
|
|
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
|
|
newline
|
|
bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
|
|
rgroup.long 0x11C4++0x03
|
|
line.long 0x00 "DMA_CH1_CURRENT_APP_TXDESC,Channel 1 Current Application Transmit Descriptor"
|
|
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
|
|
rgroup.long 0x11CC++0x03
|
|
line.long 0x00 "DMA_CH1_CURRENT_APP_RXDESC,Channel 1 Current Application Receive Descriptor"
|
|
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
|
|
rgroup.long 0x11D4++0x03
|
|
line.long 0x00 "DMA_CH1_CURRENT_APP_TXBUFFER,Channel 1 Current Application Transmit Buffer Address"
|
|
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
|
|
rgroup.long 0x11DC++0x03
|
|
line.long 0x00 "DMA_CH1_CURRENT_APP_RXBUFFER,Channel 1 Current Application Receive Buffer Address"
|
|
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
|
|
group.long 0x11E0++0x03
|
|
line.long 0x00 "DMA_CH1_STATUS,DMA Channel 1 Status"
|
|
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
|
|
newline
|
|
bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
|
|
newline
|
|
bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
|
|
newline
|
|
bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
|
|
newline
|
|
bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
|
|
newline
|
|
bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
|
|
newline
|
|
bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
|
|
newline
|
|
bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
|
|
newline
|
|
bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
|
|
rgroup.long 0x11E4++0x03
|
|
line.long 0x00 "DMA_CH1_MISS_FRAME_CNT,Channel 1 Missed Frame Counter"
|
|
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in RX_CONTROL register"
|
|
rgroup.long 0x11E8++0x03
|
|
line.long 0x00 "DMA_CH1_RXP_ACCEPT_CNT,Channel 1 RXP Frames Accepted Counter"
|
|
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1"
|
|
rgroup.long 0x11EC++0x03
|
|
line.long 0x00 "DMA_CH1_RX_ERI_CNT,Channel 1 Receive ERI Counter"
|
|
hexmask.long.word 0x00 0.--11. 1. "ECNT,ERI Counter When ERIC bit of RX_CONTROL register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer"
|
|
group.long 0x1200++0x03
|
|
line.long 0x00 "DMA_CH2_CONTROL,DMA Channel 2 Control"
|
|
bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH2_TX_CONTROL and Bits[21:16] in DMA_CH2_RX_CONTROL is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
|
|
group.long 0x1204++0x03
|
|
line.long 0x00 "DMA_CH2_TX_CONTROL,DMA Channel 2 Transmit Control"
|
|
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
|
|
group.long 0x1208++0x03
|
|
line.long 0x00 "DMA_CH2_RX_CONTROL,DMA Channel 2 Receive Control"
|
|
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
|
|
newline
|
|
rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
|
|
group.long 0x1214++0x03
|
|
line.long 0x00 "DMA_CH2_TXDESC_LIST_ADDRESS,Channel 2 Tx Descriptor List Address"
|
|
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
|
|
group.long 0x121C++0x03
|
|
line.long 0x00 "DMA_CH2_RXDESC_LIST_ADDRESS,Channel 2 Rx Descriptor List Address"
|
|
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
|
|
group.long 0x1220++0x03
|
|
line.long 0x00 "DMA_CH2_TXDESC_TAIL_POINTER,Channel 2 Tx Descriptor Tail Pointer"
|
|
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
|
|
group.long 0x1228++0x03
|
|
line.long 0x00 "DMA_CH2_RXDESC_TAIL_POINTER,Channel 2 Rx Descriptor Tail Pointer"
|
|
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
|
|
group.long 0x122C++0x03
|
|
line.long 0x00 "DMA_CH2_TXDESC_RING_LENGTH,Channel 2 Tx Descriptor Ring Length"
|
|
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
|
|
group.long 0x1230++0x03
|
|
line.long 0x00 "DMA_CH2_RXDESC_RING_LENGTH,Channel 2 Rx Descriptor Ring Length"
|
|
hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
|
|
group.long 0x1234++0x03
|
|
line.long 0x00 "DMA_CH2_INTERRUPT_ENABLE,Channel 2 Interrupt Enable"
|
|
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
|
|
newline
|
|
bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
|
|
group.long 0x1238++0x03
|
|
line.long 0x00 "DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER,Channel 2 Receive Interrupt Watchdog Timer"
|
|
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
|
|
group.long 0x123C++0x03
|
|
line.long 0x00 "DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS,Channel 2 Slot Function Control and Status"
|
|
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
|
|
newline
|
|
bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
|
|
rgroup.long 0x1244++0x03
|
|
line.long 0x00 "DMA_CH2_CURRENT_APP_TXDESC,Channel 2 Current Application Transmit Descriptor"
|
|
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
|
|
rgroup.long 0x124C++0x03
|
|
line.long 0x00 "DMA_CH2_CURRENT_APP_RXDESC,Channel 2 Current Application Receive Descriptor"
|
|
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
|
|
rgroup.long 0x1254++0x03
|
|
line.long 0x00 "DMA_CH2_CURRENT_APP_TXBUFFER,Channel 2 Current Application Transmit Buffer Address"
|
|
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
|
|
rgroup.long 0x125C++0x03
|
|
line.long 0x00 "DMA_CH2_CURRENT_APP_RXBUFFER,Channel 2 Current Application Receive Buffer Address"
|
|
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
|
|
group.long 0x1260++0x03
|
|
line.long 0x00 "DMA_CH2_STATUS,DMA Channel 2 Status"
|
|
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
|
|
newline
|
|
bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH2_INTERRUPT_ENABLE register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
|
|
newline
|
|
bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
|
|
newline
|
|
bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
|
|
newline
|
|
bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
|
|
newline
|
|
bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
|
|
newline
|
|
bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
|
|
newline
|
|
bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
|
|
newline
|
|
bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
|
|
rgroup.long 0x1264++0x03
|
|
line.long 0x00 "DMA_CH2_MISS_FRAME_CNT,Channel 2 Missed Frame Counter"
|
|
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in DMA_CH2_RX_CONTROL register"
|
|
rgroup.long 0x1268++0x03
|
|
line.long 0x00 "DMA_CH2_RXP_ACCEPT_CNT,Channel 2 RXP Frames Accepted Counter"
|
|
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1"
|
|
rgroup.long 0x126C++0x03
|
|
line.long 0x00 "DMA_CH2_RX_ERI_CNT,Channel 2 Receive ERI Counter"
|
|
hexmask.long.word 0x00 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH2_RX_CONTROL register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer"
|
|
group.long 0x1280++0x03
|
|
line.long 0x00 "DMA_CH3_CONTROL,DMA Channel 3 Control"
|
|
bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH3_TX_CONTROL and Bits[21:16] in DMA_CH3_RX_CONTROL is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
|
|
group.long 0x1284++0x03
|
|
line.long 0x00 "DMA_CH3_TX_CONTROL,DMA Channel 3 Transmit Control"
|
|
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
|
|
group.long 0x1288++0x03
|
|
line.long 0x00 "DMA_CH3_RX_CONTROL,DMA Channel 3 Receive Control"
|
|
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
|
|
newline
|
|
rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
|
|
group.long 0x1294++0x03
|
|
line.long 0x00 "DMA_CH3_TXDESC_LIST_ADDRESS,Channel 3 Tx Descriptor List Address"
|
|
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
|
|
group.long 0x129C++0x03
|
|
line.long 0x00 "DMA_CH3_RXDESC_LIST_ADDRESS,Channel 3 Rx Descriptor List Address"
|
|
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
|
|
group.long 0x12A0++0x03
|
|
line.long 0x00 "DMA_CH3_TXDESC_TAIL_POINTER,Channel 3 Tx Descriptor Tail Pointer"
|
|
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
|
|
group.long 0x12A8++0x03
|
|
line.long 0x00 "DMA_CH3_RXDESC_TAIL_POINTER,Channel 3 Rx Descriptor Tail Pointer"
|
|
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
|
|
group.long 0x12AC++0x03
|
|
line.long 0x00 "DMA_CH3_TXDESC_RING_LENGTH,Channel 3 Tx Descriptor Ring Length"
|
|
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
|
|
group.long 0x12B0++0x03
|
|
line.long 0x00 "DMA_CH3_RXDESC_RING_LENGTH,Channel 3 Rx Descriptor Ring Length"
|
|
hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
|
|
group.long 0x12B4++0x03
|
|
line.long 0x00 "DMA_CH3_INTERRUPT_ENABLE,Channel 3 Interrupt Enable"
|
|
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
|
|
newline
|
|
bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
|
|
group.long 0x12B8++0x03
|
|
line.long 0x00 "DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER,Channel 3 Receive Interrupt Watchdog Time"
|
|
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
|
|
group.long 0x12BC++0x03
|
|
line.long 0x00 "DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS,Channel 3 Slot Function Control and Status"
|
|
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
|
|
newline
|
|
bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
|
|
rgroup.long 0x12C4++0x03
|
|
line.long 0x00 "DMA_CH3_CURRENT_APP_TXDESC,Channel 3 Current Application Transmit Descriptor"
|
|
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
|
|
rgroup.long 0x12CC++0x03
|
|
line.long 0x00 "DMA_CH3_CURRENT_APP_RXDESC,Channel 3 Current Application Receive Descriptor"
|
|
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
|
|
rgroup.long 0x12D4++0x03
|
|
line.long 0x00 "DMA_CH3_CURRENT_APP_TXBUFFER,Channel 3 Current Application Transmit Buffer Address"
|
|
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
|
|
rgroup.long 0x12DC++0x03
|
|
line.long 0x00 "DMA_CH3_CURRENT_APP_RXBUFFER,Channel 3 Current Application Receive Buffer Address"
|
|
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
|
|
group.long 0x12E0++0x03
|
|
line.long 0x00 "DMA_CH3_STATUS,DMA Channel 3 Status"
|
|
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
|
|
newline
|
|
bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
|
|
newline
|
|
bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
|
|
newline
|
|
bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
|
|
newline
|
|
bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
|
|
newline
|
|
bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
|
|
newline
|
|
bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
|
|
newline
|
|
bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
|
|
newline
|
|
bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
|
|
rgroup.long 0x12E4++0x03
|
|
line.long 0x00 "DMA_CH3_MISS_FRAME_CNT,Channel 3 Missed Frame Counter"
|
|
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in RX_CONTROL register"
|
|
rgroup.long 0x12E8++0x03
|
|
line.long 0x00 "DMA_CH3_RXP_ACCEPT_CNT,Channel 3 RXP Frames Accepted Counter"
|
|
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1"
|
|
rgroup.long 0x12EC++0x03
|
|
line.long 0x00 "DMA_CH3_RX_ERI_CNT,Channel 3 Receive ERI Counter"
|
|
hexmask.long.word 0x00 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH3_RX_CONTROL register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer"
|
|
group.long 0x1300++0x03
|
|
line.long 0x00 "DMA_CH4_CONTROL,DMA Channel 4 Control"
|
|
bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH4_TX_CONTROL and Bits[21:16] in DMA_CH4_RX_CONTROL is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
|
|
group.long 0x1304++0x03
|
|
line.long 0x00 "DMA_CH4_TX_CONTROL,DMA Channel 4 Transmit Control"
|
|
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
|
|
group.long 0x1308++0x03
|
|
line.long 0x00 "DMA_CH4_RX_CONTROL,DMA Channel 4 Receive Control"
|
|
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
|
|
newline
|
|
rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
|
|
group.long 0x1314++0x03
|
|
line.long 0x00 "DMA_CH4_TXDESC_LIST_ADDRESS,Channel 4 Tx Descriptor List Address"
|
|
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
|
|
group.long 0x131C++0x03
|
|
line.long 0x00 "DMA_CH4_RXDESC_LIST_ADDRESS,Channel 4 Rx Descriptor List Address"
|
|
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
|
|
group.long 0x1320++0x03
|
|
line.long 0x00 "DMA_CH4_TXDESC_TAIL_POINTER,Channel 4 Tx Descriptor Tail Pointer"
|
|
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
|
|
group.long 0x1328++0x03
|
|
line.long 0x00 "DMA_CH4_RXDESC_TAIL_POINTER,Channel 4 Rx Descriptor Tail Pointer"
|
|
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
|
|
group.long 0x132C++0x03
|
|
line.long 0x00 "DMA_CH4_TXDESC_RING_LENGTH,Channel 4 Tx Descriptor Ring Length"
|
|
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
|
|
group.long 0x1330++0x03
|
|
line.long 0x00 "DMA_CH4_RXDESC_RING_LENGTH,Channel 4 Rx Descriptor Ring Length"
|
|
hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
|
|
group.long 0x1334++0x03
|
|
line.long 0x00 "DMA_CH4_INTERRUPT_ENABLE,Channel 4 Interrupt Enable"
|
|
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
|
|
newline
|
|
bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
|
|
group.long 0x1338++0x03
|
|
line.long 0x00 "DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER,Channel 4 Receive Interrupt Watchdog Timer"
|
|
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
|
|
group.long 0x133C++0x03
|
|
line.long 0x00 "DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS,Channel 4 Slot Function Control and Status"
|
|
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
|
|
newline
|
|
bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
|
|
rgroup.long 0x1344++0x03
|
|
line.long 0x00 "DMA_CH4_CURRENT_APP_TXDESC,Channel 4 Current Application Transmit Descriptor"
|
|
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
|
|
rgroup.long 0x134C++0x03
|
|
line.long 0x00 "DMA_CH4_CURRENT_APP_RXDESC,Channel 4 Current Application Receive Descriptor"
|
|
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
|
|
rgroup.long 0x1354++0x03
|
|
line.long 0x00 "DMA_CH4_CURRENT_APP_TXBUFFER,Channel 4 Current Application Transmit Buffer Address"
|
|
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
|
|
rgroup.long 0x135C++0x03
|
|
line.long 0x00 "DMA_CH4_CURRENT_APP_RXBUFFER,Channel 4 Current Application Receive Buffer Address"
|
|
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
|
|
group.long 0x1360++0x03
|
|
line.long 0x00 "DMA_CH4_STATUS,DMA Channel 4 Status"
|
|
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
|
|
newline
|
|
bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the INTERRUPT_ENABLE register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
|
|
newline
|
|
bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
|
|
newline
|
|
bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
|
|
newline
|
|
bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
|
|
newline
|
|
bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
|
|
newline
|
|
bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
|
|
newline
|
|
bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
|
|
newline
|
|
bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
|
|
newline
|
|
bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
|
|
newline
|
|
bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
|
|
rgroup.long 0x1364++0x03
|
|
line.long 0x00 "DMA_CH4_MISS_FRAME_CNT,Channel 4 Missed Frame Counter"
|
|
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
|
|
newline
|
|
hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programming RPF field in RX_CONTROL register"
|
|
rgroup.long 0x1368++0x03
|
|
line.long 0x00 "DMA_CH4_RXP_ACCEPT_CNT,Channel 4 RXP Frames Accepted Counter"
|
|
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
|
|
newline
|
|
hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1"
|
|
rgroup.long 0x136C++0x03
|
|
line.long 0x00 "DMA_CH4_RX_ERI_CNT,Channel 4 Receive ERI Counter"
|
|
hexmask.long.word 0x00 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH4_RX_CONTROL register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer"
|
|
tree.end
|
|
tree "ENET_MACAXI_1G (ENET)"
|
|
base ad:0x5B040000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EIR,Interrupt Event Register"
|
|
eventfld.long 0x00 30. "BABR,Babbling Receive Error" "0,1"
|
|
eventfld.long 0x00 29. "BABT,Babbling Transmit Error" "0,1"
|
|
newline
|
|
eventfld.long 0x00 28. "GRA,Graceful Stop Complete" "0,1"
|
|
eventfld.long 0x00 27. "TXF,Transmit Frame Interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 26. "TXB,Transmit Buffer Interrupt" "0,1"
|
|
eventfld.long 0x00 25. "RXF,Receive Frame Interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 24. "RXB,Receive Buffer Interrupt" "0,1"
|
|
eventfld.long 0x00 23. "MII,MII Interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 22. "EBERR,Ethernet Bus Error" "0,1"
|
|
eventfld.long 0x00 21. "LC,Late Collision" "0,1"
|
|
newline
|
|
eventfld.long 0x00 20. "RL,Collision Retry Limit" "0,1"
|
|
eventfld.long 0x00 19. "UN,Transmit FIFO Underrun" "0,1"
|
|
newline
|
|
eventfld.long 0x00 18. "PLR,Payload Receive Error" "0,1"
|
|
eventfld.long 0x00 17. "WAKEUP,Node Wakeup Request Indication" "0,1"
|
|
newline
|
|
eventfld.long 0x00 16. "TS_AVAIL,Transmit Timestamp Available" "0,1"
|
|
eventfld.long 0x00 15. "TS_TIMER,Timestamp Timer" "0,1"
|
|
newline
|
|
eventfld.long 0x00 14. "RXFLUSH_2,RX DMA Ring 2 flush indication" "0,1"
|
|
eventfld.long 0x00 13. "RXFLUSH_1,RX DMA Ring 1 flush indication" "0,1"
|
|
newline
|
|
eventfld.long 0x00 12. "RXFLUSH_0,RX DMA Ring 0 flush indication" "0,1"
|
|
eventfld.long 0x00 10. "PARSERR,Receive parser error or all entries of the match table checked without any match" "0,1"
|
|
newline
|
|
eventfld.long 0x00 9. "PARSRF,Receive frame rejected due to the match with the table entry with MCONFIG[RF] = 1" "0,1"
|
|
eventfld.long 0x00 7. "TXF2,Transmit frame interrupt class 2" "0,1"
|
|
newline
|
|
eventfld.long 0x00 6. "TXB2,Transmit buffer interrupt class 2" "0,1"
|
|
eventfld.long 0x00 5. "RXF2,Receive frame interrupt class 2" "0,1"
|
|
newline
|
|
eventfld.long 0x00 4. "RXB2,Receive buffer interrupt class 2" "0,1"
|
|
eventfld.long 0x00 3. "TXF1,Transmit frame interrupt class 1" "0,1"
|
|
newline
|
|
eventfld.long 0x00 2. "TXB1,Transmit buffer interrupt class 1" "0,1"
|
|
eventfld.long 0x00 1. "RXF1,Receive frame interrupt class 1" "0,1"
|
|
newline
|
|
eventfld.long 0x00 0. "RXB1,Receive buffer interrupt class 1" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EIMR,Interrupt Mask Register"
|
|
bitfld.long 0x00 30. "BABR,BABR Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
|
|
bitfld.long 0x00 29. "BABT,BABT Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
|
|
newline
|
|
bitfld.long 0x00 28. "GRA,GRA Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
|
|
bitfld.long 0x00 27. "TXF,TXF Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
|
|
newline
|
|
bitfld.long 0x00 26. "TXB,TXB Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
|
|
bitfld.long 0x00 25. "RXF,RXF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RXB,RXB Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 23. "MII,MII Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "EBERR,EBERR Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 21. "LC,LC Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "RL,RL Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 19. "UN,UN Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "PLR,PLR Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 17. "WAKEUP,WAKEUP Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "TS_AVAIL,TS_AVAIL Interrupt Mask" "0,1"
|
|
bitfld.long 0x00 15. "TS_TIMER,TS_TIMER Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "RXFLUSH_2,Corresponds to interrupt source EIR[RXFLUSH_2] and determines whether an interrupt condition can generate an interrupt" "0,1"
|
|
bitfld.long 0x00 13. "RXFLUSH_1,Corresponds to interrupt source EIR[RXFLUSH_1] and determines whether an interrupt condition can generate an interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "RXFLUSH_0,Corresponds to interrupt source EIR[RXFLUSH_0] and determines whether an interrupt condition can generate an interrupt" "0,1"
|
|
bitfld.long 0x00 10. "PARSERR,Interrupt mask bit corresponding to EIR[PARSERR]" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "PARSRF,Interrupt mask bit corresponding to EIR[PARSRF]" "0,1"
|
|
bitfld.long 0x00 7. "TXF2,Transmit frame interrupt class 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TXB2,Transmit buffer interrupt class 2" "0,1"
|
|
bitfld.long 0x00 5. "RXF2,Receive frame interrupt class 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "RXB2,Receive buffer interrupt class 2" "0,1"
|
|
bitfld.long 0x00 3. "TXF1,Transmit frame interrupt class 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TXB1,Transmit buffer interrupt class 1" "0,1"
|
|
bitfld.long 0x00 1. "RXF1,Receive frame interrupt class 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "RXB1,Receive buffer interrupt class 1" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RDAR,Receive Descriptor Active Register - Ring 0"
|
|
bitfld.long 0x00 24. "RDAR,Receive Descriptor Active" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TDAR,Transmit Descriptor Active Register - Ring 0"
|
|
bitfld.long 0x00 24. "TDAR,Transmit Descriptor Active" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ECR,Ethernet Control Register"
|
|
bitfld.long 0x00 17. "RXC_DLY,Receive clock delay" "0: Use non-delayed version of RGMII_RXC,1: Use delayed version of RGMII_RXC"
|
|
bitfld.long 0x00 16. "TXC_DLY,Transmit clock delay" "0: RGMII_TXC is not delayed,1: Generate delayed version of RGMII_TXC"
|
|
newline
|
|
bitfld.long 0x00 11. "SVLANDBL,S-VLAN double tag" "0,1"
|
|
bitfld.long 0x00 10. "VLANUSE2ND,VLAN use second tag" "0: Always extract data from the first VLAN tag..,1: When a double-tagged frame is detected the.."
|
|
newline
|
|
bitfld.long 0x00 9. "SVLANEN,S-VLAN enable" "0: Only the EtherType 0x8100 will be considered..,1: The EtherType 0x88a8 will be considered in.."
|
|
bitfld.long 0x00 8. "DBSWP,Descriptor Byte Swapping Enable" "0: The buffer descriptor bytes are not swapped..,1: The buffer descriptor bytes are swapped to.."
|
|
newline
|
|
bitfld.long 0x00 6. "DBGEN,Debug Enable" "0: MAC continues operation in debug mode,1: MAC enters hardware freeze mode when the.."
|
|
bitfld.long 0x00 5. "SPEED,Selects between 10/100-Mbit/s and 1000-Mbit/s modes of operation" "0: 10/100-Mbit/s mode,1: 1000-Mbit/s mode"
|
|
newline
|
|
bitfld.long 0x00 4. "EN1588,EN1588 Enable" "0: Legacy FEC buffer descriptors and functions..,1: Enhanced frame time-stamping functions enabled"
|
|
bitfld.long 0x00 3. "SLEEP,Sleep Mode Enable" "0: Normal operating mode,1: Sleep mode"
|
|
newline
|
|
bitfld.long 0x00 2. "MAGICEN,Magic Packet Detection Enable" "0: Magic detection logic disabled,1: The MAC core detects magic packets and.."
|
|
bitfld.long 0x00 1. "ETHEREN,Ethernet Enable" "0: Reception immediately stops and transmission..,1: MAC is enabled and reception and transmission.."
|
|
newline
|
|
bitfld.long 0x00 0. "RESET,Ethernet MAC Reset" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MMFR,MII Management Frame Register"
|
|
bitfld.long 0x00 30.--31. "ST,Start Of Frame Delimiter" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. "OP,Operation Code" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 23.--27. "PA,PHY Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18.--22. "RA,Register Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "TA,Turn Around" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--15. 1. "DATA,Management Frame Data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MSCR,MII Speed Control Register"
|
|
bitfld.long 0x00 8.--10. "HOLDTIME,Hold time On MDIO Output" "0: 1 internal module clock cycle,1: 2 internal module clock cycles,2: 3 internal module clock cycles,?,?,?,?,7: 8 internal module clock cycles"
|
|
bitfld.long 0x00 7. "DIS_PRE,Disable Preamble" "0: Preamble enabled,1: Preamble (32 ones) is not prepended to the.."
|
|
newline
|
|
bitfld.long 0x00 1.--6. "MII_SPEED,MII Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "MIBC,MIB Control Register"
|
|
bitfld.long 0x00 31. "MIB_DIS,Disable MIB Logic" "0: MIB logic is enabled,1: MIB logic is disabled"
|
|
rbitfld.long 0x00 30. "MIB_IDLE,MIB Idle" "0: The MIB block is updating MIB counters,1: The MIB block is not currently updating any.."
|
|
newline
|
|
bitfld.long 0x00 29. "MIB_CLEAR,MIB Clear" "0: See note above,1: All statistics counters are reset to 0"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RCR,Receive Control Register"
|
|
rbitfld.long 0x00 31. "GRS,Graceful Receive Stopped" "0,1"
|
|
bitfld.long 0x00 30. "NLC,Payload Length Check Disable" "0: The payload length check is disabled,1: The core checks the frame's payload length.."
|
|
newline
|
|
hexmask.long.word 0x00 16.--29. 1. "MAX_FL,Maximum Frame Length"
|
|
bitfld.long 0x00 15. "CFEN,MAC Control Frame Enable" "0: MAC control frames with any opcode other than..,1: MAC control frames with any opcode other than.."
|
|
newline
|
|
bitfld.long 0x00 14. "CRCFWD,Terminate/Forward Received CRC" "0: The CRC field of received frames is..,1: The CRC field is stripped from the frame"
|
|
bitfld.long 0x00 13. "PAUFWD,Terminate/Forward Pause Frames" "0: Pause frames are terminated and discarded in..,1: Pause frames are forwarded to the user.."
|
|
newline
|
|
bitfld.long 0x00 12. "PADEN,Enable Frame Padding Remove On Receive" "0: No padding is removed on receive by the MAC,1: Padding is removed from received frames"
|
|
bitfld.long 0x00 9. "RMII_10T,Enables 10-Mbit/s mode of the RMII or RGMII" "0: 100-Mbit/s operation,1: 10-Mbit/s operation"
|
|
newline
|
|
bitfld.long 0x00 8. "RMII_MODE,RMII Mode Enable" "0: MAC configured for MII mode,1: MAC configured for RMII operation"
|
|
bitfld.long 0x00 6. "RGMII_EN,RGMII Mode Enable" "0: MAC configured for non-RGMII operation,1: MAC configured for RGMII operation"
|
|
newline
|
|
bitfld.long 0x00 5. "FCE,Flow Control Enable" "0,1"
|
|
bitfld.long 0x00 4. "BC_REJ,Broadcast Frame Reject" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "PROM,Promiscuous Mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "MII_MODE,Media Independent Interface Mode" "?,1: MII or RMII mode as indicated by the.."
|
|
newline
|
|
bitfld.long 0x00 1. "DRT,Disable Receive On Transmit" "0: Receive path operates independently of..,1: Disable reception of frames while transmitting"
|
|
bitfld.long 0x00 0. "LOOP,Internal Loopback" "0: Loopback disabled,1: Transmitted frames are looped back internal.."
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TCR,Transmit Control Register"
|
|
bitfld.long 0x00 9. "CRCFWD,Forward Frame From Application With CRC" "0: TxBD[TC] controls whether the frame has a CRC..,1: The transmitter does not append any CRC to.."
|
|
bitfld.long 0x00 8. "ADDINS,Set MAC Address On Transmit" "0: The source MAC address is not modified by the..,1: The MAC overwrites the source MAC address.."
|
|
newline
|
|
bitfld.long 0x00 5.--7. "ADDSEL,Source MAC Address Select On Transmit" "0: Node MAC address programmed on PADDR1/2..,?..."
|
|
rbitfld.long 0x00 4. "RFC_PAUSE,Receive Frame Control Pause" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TFC_PAUSE,Transmit Frame Control Pause" "0: No PAUSE frame transmitted,1: The MAC stops transmission of data frames.."
|
|
bitfld.long 0x00 2. "FDEN,Full-Duplex Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GTS,Graceful Transmit Stop" "0,1"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PALR,Physical Address Lower Register"
|
|
hexmask.long 0x00 0.--31. 1. "PADDR1,Pause Address"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "PAUR,Physical Address Upper Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PADDR2,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match and the source address field in PAUSE frames"
|
|
hexmask.long.word 0x00 0.--15. 1. "TYPE,Type Field In PAUSE Frames"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "OPD,Opcode/Pause Duration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "OPCODE,Opcode Field In PAUSE Frames"
|
|
hexmask.long.word 0x00 0.--15. 1. "PAUSE_DUR,Pause Duration"
|
|
repeat 3. (increment 0 1) (increment 0 0x4)
|
|
group.long ($2+0xF0)++0x03
|
|
line.long 0x00 "TXIC[$1],Transmit Interrupt Coalescing Register $1"
|
|
bitfld.long 0x00 31. "ICEN,Interrupt Coalescing Enable" "0: Disable Interrupt coalescing,1: Enable Interrupt coalescing"
|
|
bitfld.long 0x00 30. "ICCS,Interrupt Coalescing Timer Clock Source Select" "0: Use MII/GMII TX clocks,1: Use ENET system clock"
|
|
newline
|
|
hexmask.long.byte 0x00 20.--27. 1. "ICFT,Interrupt coalescing frame count threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. "ICTT,Interrupt coalescing timer threshold"
|
|
repeat.end
|
|
repeat 3. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "RXIC[$1],Receive Interrupt Coalescing Register $1"
|
|
bitfld.long 0x00 31. "ICEN,Interrupt Coalescing Enable" "0: Disable Interrupt coalescing,1: Enable Interrupt coalescing"
|
|
bitfld.long 0x00 30. "ICCS,Interrupt Coalescing Timer Clock Source Select" "0: Use MII/GMII TX clocks,1: Use ENET system clock"
|
|
newline
|
|
hexmask.long.byte 0x00 20.--27. 1. "ICFT,Interrupt coalescing frame count threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. "ICTT,Interrupt coalescing timer threshold"
|
|
repeat.end
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IAUR,Descriptor Individual Upper Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "IADDR1,Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IALR,Descriptor Individual Lower Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "IADDR2,Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "GAUR,Descriptor Group Upper Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "GADDR1,Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "GALR,Descriptor Group Lower Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "GADDR2,Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "TFWR,Transmit FIFO Watermark Register"
|
|
bitfld.long 0x00 8. "STRFWD,Store And Forward Enable" "0: Reset,1: Enabled"
|
|
bitfld.long 0x00 0.--5. "TFWR,Transmit FIFO" "0: 64 bytes written,1: 64 bytes written,2: 128 bytes written,3: 192 bytes written,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: 4032 bytes written"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "RDSR1,Receive Descriptor Ring 1 Start Register"
|
|
hexmask.long 0x00 3.--31. 1. "R_DES_START,Pointer to the beginning of the receive buffer descriptor queue 1"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TDSR1,Transmit Buffer Descriptor Ring 1 Start Register"
|
|
hexmask.long 0x00 3.--31. 1. "X_DES_START,Pointer to the beginning of transmit buffer descriptor queue 1"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "MRBR1,Maximum Receive Buffer Size Register - Ring 1"
|
|
hexmask.long.word 0x00 4.--13. 1. "R_BUF_SIZE,no description available"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "RDSR2,Receive Descriptor Ring 2 Start Register"
|
|
hexmask.long 0x00 3.--31. 1. "R_DES_START,Pointer to the beginning of receive buffer descriptor queue 2"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "TDSR2,Transmit Buffer Descriptor Ring 2 Start Register"
|
|
hexmask.long 0x00 3.--31. 1. "X_DES_START,Pointer to the beginning of transmit buffer descriptor queue 2"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "MRBR2,Maximum Receive Buffer Size Register - Ring 2"
|
|
hexmask.long.word 0x00 4.--13. 1. "R_BUF_SIZE,no description available"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "RDSR,Receive Descriptor Ring 0 Start Register"
|
|
hexmask.long 0x00 3.--31. 1. "R_DES_START,Pointer to the beginning of the receive buffer descriptor queue"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "TDSR,Transmit Buffer Descriptor Ring 0 Start Register"
|
|
hexmask.long 0x00 3.--31. 1. "X_DES_START,Pointer to the beginning of the transmit buffer descriptor queue"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "MRBR,Maximum Receive Buffer Size Register - Ring 0"
|
|
hexmask.long.word 0x00 4.--13. 1. "R_BUF_SIZE,Receive buffer size in bytes"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "RSFL,Receive FIFO Section Full Threshold"
|
|
hexmask.long.word 0x00 0.--9. 1. "RX_SECTION_FULL,Value Of Receive FIFO Section Full Threshold"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "RSEM,Receive FIFO Section Empty Threshold"
|
|
bitfld.long 0x00 16.--20. "STAT_SECTION_EMPTY,RX Status FIFO Section Empty Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--9. 1. "RX_SECTION_EMPTY,Value Of The Receive FIFO Section Empty Threshold"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "RAEM,Receive FIFO Almost Empty Threshold"
|
|
hexmask.long.word 0x00 0.--9. 1. "RX_ALMOST_EMPTY,Value Of The Receive FIFO Almost Empty Threshold"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "RAFL,Receive FIFO Almost Full Threshold"
|
|
hexmask.long.word 0x00 0.--9. 1. "RX_ALMOST_FULL,Value Of The Receive FIFO Almost Full Threshold"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TSEM,Transmit FIFO Section Empty Threshold"
|
|
hexmask.long.word 0x00 0.--9. 1. "TX_SECTION_EMPTY,Value Of The Transmit FIFO Section Empty Threshold"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "TAEM,Transmit FIFO Almost Empty Threshold"
|
|
hexmask.long.word 0x00 0.--9. 1. "TX_ALMOST_EMPTY,Value of Transmit FIFO Almost Empty Threshold"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "TAFL,Transmit FIFO Almost Full Threshold"
|
|
hexmask.long.word 0x00 0.--9. 1. "TX_ALMOST_FULL,Value Of The Transmit FIFO Almost Full Threshold"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "TIPG,Transmit Inter-Packet Gap"
|
|
bitfld.long 0x00 0.--4. "IPG,Transmit Inter-Packet Gap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "FTRL,Frame Truncation Length"
|
|
hexmask.long.word 0x00 0.--13. 1. "TRUNC_FL,Frame Truncation Length"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TACC,Transmit Accelerator Function Configuration"
|
|
bitfld.long 0x00 4. "PROCHK,Enables insertion of protocol checksum" "0: Checksum not inserted,1: If an IP frame with a known protocol is.."
|
|
bitfld.long 0x00 3. "IPCHK,Enables insertion of IP header checksum" "0: Checksum is not inserted,1: If an IP frame is transmitted the checksum is.."
|
|
newline
|
|
bitfld.long 0x00 0. "SHIFT16,TX FIFO Shift-16" "0: Disabled,1: Indicates to the transmit data FIFO that the.."
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "RACC,Receive Accelerator Function Configuration"
|
|
bitfld.long 0x00 7. "SHIFT16,RX FIFO Shift-16" "0: Disabled,1: Instructs the MAC to write two additional.."
|
|
bitfld.long 0x00 6. "LINEDIS,Enable Discard Of Frames With MAC Layer Errors" "0: Frames with errors are not discarded,1: Any frame received with a CRC length or PHY.."
|
|
newline
|
|
bitfld.long 0x00 2. "PRODIS,Enable Discard Of Frames With Wrong Protocol Checksum" "0: Frames with wrong checksum are not discarded,1: If a TCP/IP UDP/IP or ICMP/IP frame is.."
|
|
bitfld.long 0x00 1. "IPDIS,Enable Discard Of Frames With Wrong IPv4 Header Checksum" "0: Frames with wrong IPv4 header checksum are..,1: If an IPv4 frame is received with a.."
|
|
newline
|
|
bitfld.long 0x00 0. "PADREM,Enable Padding Removal For Short IP Frames" "0: Padding not removed,1: Any bytes following the IP payload section of.."
|
|
repeat 2. (strings "1" "2" )(list 0x00 0x04 )
|
|
group.long ($2+0x1C8)++0x03
|
|
line.long 0x00 "RCMR$1,Receive Classification Match Register for Class n"
|
|
bitfld.long 0x00 16. "MATCHEN,Match Enable" "0: Disabled (default),1: The register contents are valid and a.."
|
|
bitfld.long 0x00 12.--14. "CMP3,Compare 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "CMP2,Compare 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. "CMP1,Compare 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "CMP0,Compare 0" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 2. (strings "1" "2" )(list 0x00 0x04 )
|
|
group.long ($2+0x1D8)++0x03
|
|
line.long 0x00 "DMACFG$1,DMA Class Based Configuration"
|
|
bitfld.long 0x00 17. "CALC_NOIPG,Calculate no IPG" "0: The traffic shaper function should consider..,1: Addition of 12 bytes for the IPG should be.."
|
|
bitfld.long 0x00 16. "DMA_CLASS_EN,DMA class enable" "0: The DMA controller's channel for the class is..,1: Enable the DMA controller to support the.."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "IDLE_SLOPE,Idle slope"
|
|
repeat.end
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "RDAR1,Receive Descriptor Active Register - Ring 1"
|
|
bitfld.long 0x00 24. "RDAR,Receive Descriptor Active" "0,1"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "TDAR1,Transmit Descriptor Active Register - Ring 1"
|
|
bitfld.long 0x00 24. "TDAR,Transmit Descriptor Active" "0,1"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "RDAR2,Receive Descriptor Active Register - Ring 2"
|
|
bitfld.long 0x00 24. "RDAR,Receive Descriptor Active" "0,1"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "TDAR2,Transmit Descriptor Active Register - Ring 2"
|
|
bitfld.long 0x00 24. "TDAR,Transmit Descriptor Active" "0,1"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "QOS,QOS Scheme"
|
|
bitfld.long 0x00 5. "RX_FLUSH2,RX Flush Ring 2" "0: Disable,1: Enable"
|
|
bitfld.long 0x00 4. "RX_FLUSH1,RX Flush Ring 1" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 3. "RX_FLUSH0,RX Flush Ring 0" "0: Disable,1: Enable"
|
|
bitfld.long 0x00 0.--2. "TX_SCHEME,TX scheme configuration" "0: Credit-based scheme,1: Round-robin scheme,?..."
|
|
rgroup.long 0x200++0x03
|
|
line.long 0x00 "RMON_T_DROP,Reserved Statistic Register"
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "RMON_T_PACKETS,Tx Packet Count Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Packet count"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Broadcast packets"
|
|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "RMON_T_MC_PKT,Tx Multicast Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Multicast packets"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "RMON_T_CRC_ALIGN,Tx Packets with CRC/Align Error Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Packets with CRC/align error"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "RMON_T_UNDERSIZE,Tx Packets Less Than Bytes and Good CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit packets less than 64 bytes with good CRC"
|
|
rgroup.long 0x218++0x03
|
|
line.long 0x00 "RMON_T_OVERSIZE,Tx Packets GT MAX_FL bytes and Good CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit packets greater than MAX_FL bytes with good CRC"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "RMON_T_FRAG,Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of packets less than 64 bytes with bad CRC"
|
|
rgroup.long 0x220++0x03
|
|
line.long 0x00 "RMON_T_JAB,Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit packets greater than MAX_FL bytes and bad CRC"
|
|
rgroup.long 0x224++0x03
|
|
line.long 0x00 "RMON_T_COL,Tx Collision Count Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit collisions"
|
|
rgroup.long 0x228++0x03
|
|
line.long 0x00 "RMON_T_P64,Tx 64-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 64-byte transmit packets"
|
|
rgroup.long 0x22C++0x03
|
|
line.long 0x00 "RMON_T_P65TO127,Tx 65- to 127-byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 65- to 127-byte transmit packets"
|
|
rgroup.long 0x230++0x03
|
|
line.long 0x00 "RMON_T_P128TO255,Tx 128- to 255-byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 128- to 255-byte transmit packets"
|
|
rgroup.long 0x234++0x03
|
|
line.long 0x00 "RMON_T_P256TO511,Tx 256- to 511-byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 256- to 511-byte transmit packets"
|
|
rgroup.long 0x238++0x03
|
|
line.long 0x00 "RMON_T_P512TO1023,Tx 512- to 1023-byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 512- to 1023-byte transmit packets"
|
|
rgroup.long 0x23C++0x03
|
|
line.long 0x00 "RMON_T_P1024TO2047,Tx 1024- to 2047-byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 1024- to 2047-byte transmit packets"
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "RMON_T_P_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit packets greater than 2048 bytes"
|
|
rgroup.long 0x244++0x03
|
|
line.long 0x00 "RMON_T_OCTETS,Tx Octets Statistic Register"
|
|
hexmask.long 0x00 0.--31. 1. "TXOCTS,Number of transmit octets"
|
|
rgroup.long 0x248++0x03
|
|
line.long 0x00 "IEEE_T_DROP,Reserved Statistic Register"
|
|
rgroup.long 0x24C++0x03
|
|
line.long 0x00 "IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted OK"
|
|
rgroup.long 0x250++0x03
|
|
line.long 0x00 "IEEE_T_1COL,Frames Transmitted with Single Collision Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with one collision"
|
|
rgroup.long 0x254++0x03
|
|
line.long 0x00 "IEEE_T_MCOL,Frames Transmitted with Multiple Collisions Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with multiple collisions"
|
|
rgroup.long 0x258++0x03
|
|
line.long 0x00 "IEEE_T_DEF,Frames Transmitted after Deferral Delay Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with deferral delay"
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "IEEE_T_LCOL,Frames Transmitted with Late Collision Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with late collision"
|
|
rgroup.long 0x260++0x03
|
|
line.long 0x00 "IEEE_T_EXCOL,Frames Transmitted with Excessive Collisions Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with excessive collisions"
|
|
rgroup.long 0x264++0x03
|
|
line.long 0x00 "IEEE_T_MACERR,Frames Transmitted with Tx FIFO Underrun Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with transmit FIFO underrun"
|
|
rgroup.long 0x268++0x03
|
|
line.long 0x00 "IEEE_T_CSERR,Frames Transmitted with Carrier Sense Error Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with carrier sense error"
|
|
rgroup.long 0x26C++0x03
|
|
line.long 0x00 "IEEE_T_SQE,Reserved Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,This read-only field is reserved and always has the value 0"
|
|
rgroup.long 0x270++0x03
|
|
line.long 0x00 "IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of flow-control pause frames transmitted"
|
|
rgroup.long 0x274++0x03
|
|
line.long 0x00 "IEEE_T_OCTETS_OK,Octet Count for Frames Transmitted w/o Error Statistic Register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Octet count for frames transmitted without error Counts total octets (includes header and FCS fields)"
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "RMON_R_PACKETS,Rx Packet Count Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of packets received"
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive broadcast packets"
|
|
rgroup.long 0x28C++0x03
|
|
line.long 0x00 "RMON_R_MC_PKT,Rx Multicast Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive multicast packets"
|
|
rgroup.long 0x290++0x03
|
|
line.long 0x00 "RMON_R_CRC_ALIGN,Rx Packets with CRC/Align Error Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets with CRC or align error"
|
|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "RMON_R_UNDERSIZE,Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets with less than 64 bytes and good CRC"
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "RMON_R_OVERSIZE,Rx Packets Greater Than MAX_FL and Good CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets greater than MAX_FL and good CRC"
|
|
rgroup.long 0x29C++0x03
|
|
line.long 0x00 "RMON_R_FRAG,Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets with less than 64 bytes and bad CRC"
|
|
rgroup.long 0x2A0++0x03
|
|
line.long 0x00 "RMON_R_JAB,Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets greater than MAX_FL and bad CRC"
|
|
rgroup.long 0x2A4++0x03
|
|
line.long 0x00 "RMON_R_RESVD_0,Reserved Statistic Register"
|
|
rgroup.long 0x2A8++0x03
|
|
line.long 0x00 "RMON_R_P64,Rx 64-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 64-byte receive packets"
|
|
rgroup.long 0x2AC++0x03
|
|
line.long 0x00 "RMON_R_P65TO127,Rx 65- to 127-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 65- to 127-byte recieve packets"
|
|
rgroup.long 0x2B0++0x03
|
|
line.long 0x00 "RMON_R_P128TO255,Rx 128- to 255-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 128- to 255-byte recieve packets"
|
|
rgroup.long 0x2B4++0x03
|
|
line.long 0x00 "RMON_R_P256TO511,Rx 256- to 511-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 256- to 511-byte recieve packets"
|
|
rgroup.long 0x2B8++0x03
|
|
line.long 0x00 "RMON_R_P512TO1023,Rx 512- to 1023-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 512- to 1023-byte recieve packets"
|
|
rgroup.long 0x2BC++0x03
|
|
line.long 0x00 "RMON_R_P1024TO2047,Rx 1024- to 2047-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 1024- to 2047-byte recieve packets"
|
|
rgroup.long 0x2C0++0x03
|
|
line.long 0x00 "RMON_R_P_GTE2048,Rx Packets Greater than 2048 Bytes Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of greater-than-2048-byte recieve packets"
|
|
rgroup.long 0x2C4++0x03
|
|
line.long 0x00 "RMON_R_OCTETS,Rx Octets Statistic Register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Number of receive octets"
|
|
rgroup.long 0x2C8++0x03
|
|
line.long 0x00 "IEEE_R_DROP,Frames not Counted Correctly Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Frame count"
|
|
rgroup.long 0x2CC++0x03
|
|
line.long 0x00 "IEEE_R_FRAME_OK,Frames Received OK Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames received OK"
|
|
rgroup.long 0x2D0++0x03
|
|
line.long 0x00 "IEEE_R_CRC,Frames Received with CRC Error Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames received with CRC error"
|
|
rgroup.long 0x2D4++0x03
|
|
line.long 0x00 "IEEE_R_ALIGN,Frames Received with Alignment Error Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames received with alignment error"
|
|
rgroup.long 0x2D8++0x03
|
|
line.long 0x00 "IEEE_R_MACERR,Receive FIFO Overflow Count Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Receive FIFO overflow count"
|
|
rgroup.long 0x2DC++0x03
|
|
line.long 0x00 "IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of flow-control pause frames received"
|
|
rgroup.long 0x2E0++0x03
|
|
line.long 0x00 "IEEE_R_OCTETS_OK,Octet Count for Frames Received without Error Statistic Register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Number of octets for frames received without error"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "ATCR,Adjustable Timer Control Register"
|
|
bitfld.long 0x00 13. "SLAVE,Enable Timer Slave Mode" "0: The timer is active and all configuration..,1: The internal timer is disabled and the.."
|
|
bitfld.long 0x00 11. "CAPTURE,Capture Timer Value" "0: No effect,1: The current time is captured and can be read.."
|
|
newline
|
|
bitfld.long 0x00 9. "RESTART,Reset Timer" "0,1"
|
|
bitfld.long 0x00 7. "PINPER,Enables event signal output external pin frc_evt_period assertion on period event" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 4. "PEREN,Enable Periodical Event" "0: Disable,1: A period event interrupt can be generated.."
|
|
bitfld.long 0x00 3. "OFFRST,Reset Timer On Offset Event" "0: The timer is not affected and no action..,1: If OFFEN is set the timer resets to zero when.."
|
|
newline
|
|
bitfld.long 0x00 2. "OFFEN,Enable One-Shot Offset Event" "0: Disable,1: The timer can be reset to zero when the given.."
|
|
bitfld.long 0x00 0. "EN,Enable Timer" "0: The timer stops at the current value,1: The timer starts incrementing"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "ATVR,Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "ATIME,A write sets the timer"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "ATOFF,Timer Offset Register"
|
|
hexmask.long 0x00 0.--31. 1. "OFFSET,Offset value for one-shot event generation"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "ATPER,Timer Period Register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Value for generating periodic events"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "ATCOR,Timer Correction Register"
|
|
hexmask.long 0x00 0.--30. 1. "COR,Correction Counter Wrap-Around Value"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "ATINC,Time-Stamping Clock Period Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. "INC_CORR,Correction Increment Value"
|
|
hexmask.long.byte 0x00 0.--6. 1. "INC,Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds"
|
|
rgroup.long 0x418++0x03
|
|
line.long 0x00 "ATSTMP,Timestamp of Last Transmitted Frame"
|
|
hexmask.long 0x00 0.--31. 1. "TIMESTAMP,Timestamp of the last frame transmitted by the core that had TxBD[TS] set the ff_tx_ts_frm signal asserted from the user application"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "MDATA,Pattern Match Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "MATCHDATA,Match Data"
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "MMASK,Match Entry Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. "MATCHMASK,Match Mask"
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "MCONFIG,Match Entry Rules Configuration Register"
|
|
bitfld.long 0x00 31. "AF,Accept Frame" "0,1"
|
|
bitfld.long 0x00 30. "RF,Reject Frame" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "IM,Invert Match" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "OK_INDEX,When AF = 0 and RF = 0 this value shows the next entry of the matching table to be used for comparison instead of using the next entry sequentially"
|
|
newline
|
|
bitfld.long 0x00 2.--7. "FRMOFF,Frame Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "MENTRYRW,Match Entry Read/Write Command Register"
|
|
bitfld.long 0x00 9. "RD,Entry Read Command" "0,1"
|
|
bitfld.long 0x00 8. "WR,Entry write command" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "ENTRYADD,Entry Address"
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "RXPCTL,Receive Parser Control Register"
|
|
bitfld.long 0x00 24. "ACPTEERR,Accept End Error" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ENDERRQ,End Error Queue"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MAXINDEX,Maximum Index"
|
|
bitfld.long 0x00 4. "PRSRSCLR,Clear Parser Statistics Counter" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "INVBYTORD,Inverse Frame Byte Order" "0,1"
|
|
bitfld.long 0x00 0. "ENPARSER,Enable Receive Parser" "0: Parser is disabled,1: Parser is enabled"
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "MAXFRMOFF,Maximum Frame Offset"
|
|
bitfld.long 0x00 0.--5. "MXFRMOFF,Max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x598++0x03
|
|
line.long 0x00 "RXPARST,Receive Parser Status"
|
|
bitfld.long 0x00 8. "RXPRSDN,Receive Parser Done" "0,1"
|
|
bitfld.long 0x00 5. "INVMAXIDX,Invalid Value of MAXINDEX" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "PRSENDERR,Parser End Error" "0,1"
|
|
bitfld.long 0x00 3. "FMOFFERR,Maximum Frame Offset Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "NOMTCERR,No Match Error" "0,1"
|
|
bitfld.long 0x00 1. "TBLDPTERR,Table Depth Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "MXINDERR,Maximum Index Error" "0,1"
|
|
rgroup.long 0x5A0++0x03
|
|
line.long 0x00 "PARSDSCD,Parser Discard Count"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Count"
|
|
rgroup.long 0x5A4++0x03
|
|
line.long 0x00 "PRSACPT0,Parser Accept Count 0"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Count"
|
|
rgroup.long 0x5A8++0x03
|
|
line.long 0x00 "PRSRJCT0,Parser Reject Count 0"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Count"
|
|
rgroup.long 0x5AC++0x03
|
|
line.long 0x00 "PRSACPT1,Parser Accept Count 1"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Count"
|
|
rgroup.long 0x5B0++0x03
|
|
line.long 0x00 "PRSRJCT1,Parser Reject Count 1"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Count"
|
|
rgroup.long 0x5B4++0x03
|
|
line.long 0x00 "PRSACPT2,Parser Accept Count 2"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Count"
|
|
rgroup.long 0x5B8++0x03
|
|
line.long 0x00 "PRSRJCT2,Parser Reject Count 2"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Count"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "TGSR,Timer Global Status Register"
|
|
eventfld.long 0x00 3. "TF3,Copy Of Timer Flag For Channel 3" "0: Timer Flag for Channel 3 is clear,1: Timer Flag for Channel 3 is set"
|
|
eventfld.long 0x00 2. "TF2,Copy Of Timer Flag For Channel 2" "0: Timer Flag for Channel 2 is clear,1: Timer Flag for Channel 2 is set"
|
|
newline
|
|
eventfld.long 0x00 1. "TF1,Copy Of Timer Flag For Channel 1" "0: Timer Flag for Channel 1 is clear,1: Timer Flag for Channel 1 is set"
|
|
eventfld.long 0x00 0. "TF0,Copy Of Timer Flag For Channel 0" "0: Timer Flag for Channel 0 is clear,1: Timer Flag for Channel 0 is set"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "TCSR0,Timer Control Status Register"
|
|
bitfld.long 0x00 11.--15. "TPWC,Timer PulseWidth Control" "0: Pulse width is one 1588-clock cycle,1: Pulse width is two 1588-clock cycles,2: Pulse width is three 1588-clock cycles,3: Pulse width is four 1588-clock cycles,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Pulse width is 32 1588-clock cycles"
|
|
eventfld.long 0x00 7. "TF,Timer Flag" "0: Input Capture or Output Compare has not..,1: Input Capture or Output Compare has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.long 0x00 2.--5. "TMODE,Timer Mode" "0: Timer Channel is disabled,1: Timer Channel is configured for Input Capture..,2: Timer Channel is configured for Input Capture..,3: Timer Channel is configured for Input Capture..,4: Timer Channel is configured for Output..,5: Timer Channel is configured for Output..,6: Timer Channel is configured for Output..,7: Timer Channel is configured for Output..,?,9: Timer Channel is configured for Output..,10: Timer Channel is configured for Output..,11: Timer Channel is configured for Output..,?,?,14: Timer Channel is configured for Output..,15: Timer Channel is configured for Output.."
|
|
newline
|
|
bitfld.long 0x00 0. "TDRE,Timer DMA Request Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "TCCR0,Timer Compare Capture Register"
|
|
hexmask.long 0x00 0.--31. 1. "TCC,Timer Capture Compare"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "TCSR1,Timer Control Status Register"
|
|
bitfld.long 0x00 11.--15. "TPWC,Timer PulseWidth Control" "0: Pulse width is one 1588-clock cycle,1: Pulse width is two 1588-clock cycles,2: Pulse width is three 1588-clock cycles,3: Pulse width is four 1588-clock cycles,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Pulse width is 32 1588-clock cycles"
|
|
eventfld.long 0x00 7. "TF,Timer Flag" "0: Input Capture or Output Compare has not..,1: Input Capture or Output Compare has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.long 0x00 2.--5. "TMODE,Timer Mode" "0: Timer Channel is disabled,1: Timer Channel is configured for Input Capture..,2: Timer Channel is configured for Input Capture..,3: Timer Channel is configured for Input Capture..,4: Timer Channel is configured for Output..,5: Timer Channel is configured for Output..,6: Timer Channel is configured for Output..,7: Timer Channel is configured for Output..,?,9: Timer Channel is configured for Output..,10: Timer Channel is configured for Output..,11: Timer Channel is configured for Output..,?,?,14: Timer Channel is configured for Output..,15: Timer Channel is configured for Output.."
|
|
newline
|
|
bitfld.long 0x00 0. "TDRE,Timer DMA Request Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "TCCR1,Timer Compare Capture Register"
|
|
hexmask.long 0x00 0.--31. 1. "TCC,Timer Capture Compare"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "TCSR2,Timer Control Status Register"
|
|
bitfld.long 0x00 11.--15. "TPWC,Timer PulseWidth Control" "0: Pulse width is one 1588-clock cycle,1: Pulse width is two 1588-clock cycles,2: Pulse width is three 1588-clock cycles,3: Pulse width is four 1588-clock cycles,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Pulse width is 32 1588-clock cycles"
|
|
eventfld.long 0x00 7. "TF,Timer Flag" "0: Input Capture or Output Compare has not..,1: Input Capture or Output Compare has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.long 0x00 2.--5. "TMODE,Timer Mode" "0: Timer Channel is disabled,1: Timer Channel is configured for Input Capture..,2: Timer Channel is configured for Input Capture..,3: Timer Channel is configured for Input Capture..,4: Timer Channel is configured for Output..,5: Timer Channel is configured for Output..,6: Timer Channel is configured for Output..,7: Timer Channel is configured for Output..,?,9: Timer Channel is configured for Output..,10: Timer Channel is configured for Output..,11: Timer Channel is configured for Output..,?,?,14: Timer Channel is configured for Output..,15: Timer Channel is configured for Output.."
|
|
newline
|
|
bitfld.long 0x00 0. "TDRE,Timer DMA Request Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "TCCR2,Timer Compare Capture Register"
|
|
hexmask.long 0x00 0.--31. 1. "TCC,Timer Capture Compare"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "TCSR3,Timer Control Status Register"
|
|
bitfld.long 0x00 11.--15. "TPWC,Timer PulseWidth Control" "0: Pulse width is one 1588-clock cycle,1: Pulse width is two 1588-clock cycles,2: Pulse width is three 1588-clock cycles,3: Pulse width is four 1588-clock cycles,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Pulse width is 32 1588-clock cycles"
|
|
eventfld.long 0x00 7. "TF,Timer Flag" "0: Input Capture or Output Compare has not..,1: Input Capture or Output Compare has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.long 0x00 2.--5. "TMODE,Timer Mode" "0: Timer Channel is disabled,1: Timer Channel is configured for Input Capture..,2: Timer Channel is configured for Input Capture..,3: Timer Channel is configured for Input Capture..,4: Timer Channel is configured for Output..,5: Timer Channel is configured for Output..,6: Timer Channel is configured for Output..,7: Timer Channel is configured for Output..,?,9: Timer Channel is configured for Output..,10: Timer Channel is configured for Output..,11: Timer Channel is configured for Output..,?,?,14: Timer Channel is configured for Output..,15: Timer Channel is configured for Output.."
|
|
newline
|
|
bitfld.long 0x00 0. "TDRE,Timer DMA Request Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "TCCR3,Timer Compare Capture Register"
|
|
hexmask.long 0x00 0.--31. 1. "TCC,Timer Capture Compare"
|
|
tree.end
|
|
tree "FLEXSPI (FlexSPI)"
|
|
repeat 2. (list 0. 1.) (list ad:0x5D120000 ad:0x5D130000)
|
|
tree "LSIO__FLEXSPI$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR0,Module Control Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "AHBGRANTWAIT,Timeout wait cycle for AHB command grant"
|
|
hexmask.long.byte 0x00 16.--23. 1. "IPGRANTWAIT,Time out wait cycle for IP command grant"
|
|
newline
|
|
bitfld.long 0x00 15. "LEARNEN,This bit is used to enable/disable data learning feature" "0: LEARNEN_0,1: LEARNEN_1"
|
|
bitfld.long 0x00 14. "SCKFREERUNEN,This bit is used to force SCLK output free-running" "0: SCKFREERUNEN_0,1: SCKFREERUNEN_1"
|
|
newline
|
|
bitfld.long 0x00 13. "COMBINATIONEN,This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0])" "0: COMBINATIONEN_0,1: COMBINATIONEN_1"
|
|
bitfld.long 0x00 12. "DOZEEN,Doze mode enable bit" "0: Doze mode support disabled,1: Doze mode support enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "HSEN,Half Speed Serial Flash access Enable" "0: Disable divide by 2 of serial flash clock for..,1: Enable divide by 2 of serial flash clock for.."
|
|
bitfld.long 0x00 8.--10. "SERCLKDIV,The serial root clock could be divided inside FlexSPI" "0: Divided by 1,1: Divided by 2,2: Divided by 3,3: Divided by 4,4: Divided by 5,5: Divided by 6,6: Divided by 7,7: Divided by 8"
|
|
newline
|
|
bitfld.long 0x00 7. "ATDFEN,Enable AHB bus Write Access to IP TX FIFO" "0: IP TX FIFO should be written by IP Bus,1: IP TX FIFO should be written by AHB Bus"
|
|
bitfld.long 0x00 6. "ARDFEN,Enable AHB bus Read Access to IP RX FIFO" "0: IP RX FIFO should be read by IP Bus,1: IP RX FIFO should be read by AHB Bus"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "RXCLKSRC,Sample Clock source selection for Flash Reading" "0: Dummy Read strobe generated by FlexSPI..,1: Dummy Read strobe generated by FlexSPI..,?,3: Flash provided Read strobe and input from DQS.."
|
|
bitfld.long 0x00 1. "MDIS,Module Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SWRESET,Software Reset" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MCR1,Module Control Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "SEQWAIT,Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles"
|
|
hexmask.long.word 0x00 0.--15. 1. "AHBBUSWAIT,AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles AHB Bus will get an error response"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MCR2,Module Control Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RESUMEWAIT,Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed"
|
|
bitfld.long 0x00 19. "SCKBDIFFOPT,B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK)" "0: B_SCLK pad is used as port B SCLK clock output,1: B_SCLK pad is used as port A SCLK inverted.."
|
|
newline
|
|
bitfld.long 0x00 15. "SAMEDEVICEEN,All external devices are same devices (both in types and size) for A1/A2/B1/B2" "0: In Individual mode..,1: FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register.."
|
|
bitfld.long 0x00 14. "CLRLEARNPHASE,The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "CLRAHBBUFOPT,This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK" "0: AHB RX/TX Buffer will not be cleaned..,1: AHB RX/TX Buffer will be cleaned.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "AHBCR,AHB Bus Control Register"
|
|
bitfld.long 0x00 6. "READADDROPT,AHB Read Address option bit" "0: There is AHB read burst start address..,1: There is no AHB read burst start address.."
|
|
bitfld.long 0x00 5. "PREFETCHEN,AHB Read Prefetch Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "BUFFERABLEEN,Enable AHB bus bufferable write access support" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 3. "CACHABLEEN,Enable AHB bus cachable read access support" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "APAREN,Parallel mode enabled for AHB triggered Command (both read and write)" "0: Flash will be accessed in Individual mode,1: Flash will be accessed in Parallel mode"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INTEN,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. "SEQTIMEOUTEN,Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details" "0,1"
|
|
bitfld.long 0x00 10. "AHBBUSTIMEOUTEN,AHB Bus timeout interrupt.Refer Interrupts chapter for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SCKSTOPBYWREN,SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable" "0,1"
|
|
bitfld.long 0x00 8. "SCKSTOPBYRDEN,SCLK is stopped during command sequence because Async RX FIFO full interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "DATALEARNFAILEN,Data Learning failed interrupt enable" "0,1"
|
|
bitfld.long 0x00 6. "IPTXWEEN,IP TX FIFO WaterMark empty interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "IPRXWAEN,IP RX FIFO WaterMark available interrupt enable" "0,1"
|
|
bitfld.long 0x00 4. "AHBCMDERREN,AHB triggered Command Sequences Error Detected interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "IPCMDERREN,IP triggered Command Sequences Error Detected interrupt enable" "0,1"
|
|
bitfld.long 0x00 2. "AHBCMDGEEN,AHB triggered Command Sequences Grant Timeout interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IPCMDGEEN,IP triggered Command Sequences Grant Timeout interrupt enable" "0,1"
|
|
bitfld.long 0x00 0. "IPCMDDONEEN,IP triggered Command Sequences Execution finished interrupt enable" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "INTR,Interrupt Register"
|
|
eventfld.long 0x00 11. "SEQTIMEOUT,Sequence execution timeout interrupt" "0,1"
|
|
eventfld.long 0x00 10. "AHBBUSTIMEOUT,AHB Bus timeout interrupt.Refer Interrupts chapter for more details" "0,1"
|
|
newline
|
|
eventfld.long 0x00 9. "SCKSTOPBYWR,SCLK is stopped during command sequence because Async TX FIFO empty interrupt" "0,1"
|
|
eventfld.long 0x00 8. "SCKSTOPBYRD,SCLK is stopped during command sequence because Async RX FIFO full interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 7. "DATALEARNFAIL,Data Learning failed interrupt" "0,1"
|
|
eventfld.long 0x00 6. "IPTXWE,IP TX FIFO watermark empty interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 5. "IPRXWA,IP RX FIFO watermark available interrupt" "0,1"
|
|
eventfld.long 0x00 4. "AHBCMDERR,AHB triggered Command Sequences Error Detected interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 3. "IPCMDERR,IP triggered Command Sequences Error Detected interrupt" "0,1"
|
|
eventfld.long 0x00 2. "AHBCMDGE,AHB triggered Command Sequences Grant Timeout interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 1. "IPCMDGE,IP triggered Command Sequences Grant Timeout interrupt" "0,1"
|
|
eventfld.long 0x00 0. "IPCMDDONE,IP triggered Command Sequences Execution finished interrupt" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "LUTKEY,LUT Key Register"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,The Key to lock or unlock LUT"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LUTCR,LUT Control Register"
|
|
bitfld.long 0x00 1. "UNLOCK,Unlock LUT" "0,1"
|
|
bitfld.long 0x00 0. "LOCK,Lock LUT" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AHBRXBUF0CR0,AHB RX Buffer 0 Control Register 0"
|
|
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
|
|
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AHBRXBUF1CR0,AHB RX Buffer 1 Control Register 0"
|
|
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
|
|
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "AHBRXBUF2CR0,AHB RX Buffer 2 Control Register 0"
|
|
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
|
|
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "AHBRXBUF3CR0,AHB RX Buffer 3 Control Register 0"
|
|
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
|
|
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "AHBRXBUF4CR0,AHB RX Buffer 4 Control Register 0"
|
|
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
|
|
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "AHBRXBUF5CR0,AHB RX Buffer 5 Control Register 0"
|
|
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
|
|
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "AHBRXBUF6CR0,AHB RX Buffer 6 Control Register 0"
|
|
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
|
|
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "AHBRXBUF7CR0,AHB RX Buffer 7 Control Register 0"
|
|
bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1"
|
|
bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--8. 1. "BUFSZ,AHB RX Buffer Size in 64 bits"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "FLSHA1CR0,Flash Control Register 0"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FLSHA2CR0,Flash Control Register 0"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "FLSHB1CR0,Flash Control Register 0"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FLSHB2CR0,Flash Control Register 0"
|
|
hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte"
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x70)++0x03
|
|
line.long 0x00 "FLSHCR1A$1,Flash Control Register $1"
|
|
hexmask.long.word 0x00 16.--31. 1. "CSINTERVAL,This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion"
|
|
bitfld.long 0x00 15. "CSINTERVALUNIT,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "CAS,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10. "WA,Word Addressable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "TCSH,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TCSS,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x78)++0x03
|
|
line.long 0x00 "FLSHCR1B$1,Flash Control Register $1"
|
|
hexmask.long.word 0x00 16.--31. 1. "CSINTERVAL,This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion"
|
|
bitfld.long 0x00 15. "CSINTERVALUNIT,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle"
|
|
newline
|
|
bitfld.long 0x00 11.--14. "CAS,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10. "WA,Word Addressable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "TCSH,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TCSS,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "FLSHCR2A$1,Flash Control Register 2"
|
|
bitfld.long 0x00 31. "CLRINSTRPTR,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
|
|
bitfld.long 0x00 28.--30. "AWRWAITUNIT,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "AWRWAIT,For certain devices (such as FPGA) it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"
|
|
bitfld.long 0x00 13.--15. "AWRSEQNUM,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AWRSEQID,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. "ARDSEQNUM,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ARDSEQID,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x88)++0x03
|
|
line.long 0x00 "FLSHCR2B$1,Flash Control Register 2"
|
|
bitfld.long 0x00 31. "CLRINSTRPTR,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1"
|
|
bitfld.long 0x00 28.--30. "AWRWAITUNIT,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle"
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "AWRWAIT,For certain devices (such as FPGA) it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"
|
|
bitfld.long 0x00 13.--15. "AWRSEQNUM,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "AWRSEQID,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. "ARDSEQNUM,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ARDSEQID,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FLSHCR4,Flash Control Register 4"
|
|
bitfld.long 0x00 3. "WMENB,Write mask enable bit for flash device on port B" "0: Write mask is disabled DQS(RWDS) pin will be..,1: Write mask is enabled DQS(RWDS) pin will be.."
|
|
bitfld.long 0x00 2. "WMENA,Write mask enable bit for flash device on port A" "0: Write mask is disabled DQS(RWDS) pin will be..,1: Write mask is enabled DQS(RWDS) pin will be.."
|
|
newline
|
|
bitfld.long 0x00 0. "WMOPT1,Write mask option bit 1" "0: DQS pin will be used as Write Mask when..,1: DQS pin will not be used as Write Mask when.."
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "IPCR0,IP Control Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "SFAR,Serial Flash Address for IP command"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "IPCR1,IP Control Register 1"
|
|
bitfld.long 0x00 31. "IPAREN,Parallel mode Enabled for IP command" "0: Flash will be accessed in Individual mode,1: Flash will be accessed in Parallel mode"
|
|
bitfld.long 0x00 24.--26. "ISEQNUM,Sequence Number for IP command: ISEQNUM+1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "ISEQID,Sequence Index in LUT for IP command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--15. 1. "IDATSZ,Flash Read/Program Data Size (in Bytes) for IP command"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "IPCMD,IP Command Register"
|
|
bitfld.long 0x00 0. "TRG,Setting this bit will trigger an IP Command" "0,1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DLPR,Data Learn Pattern Register"
|
|
hexmask.long 0x00 0.--31. 1. "DLP,Data Learning Pattern"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "IPRXFCR,IP RX FIFO Control Register"
|
|
bitfld.long 0x00 2.--7. "RXWMRK,Watermark level is (RXWMRK+1)*64 Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 1. "RXDMAEN,IP RX FIFO reading by DMA enabled" "0: IP RX FIFO would be read by processor,1: IP RX FIFO would be read by DMA"
|
|
newline
|
|
bitfld.long 0x00 0. "CLRIPRXF,Clear all valid data entries in IP RX FIFO" "0,1"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "IPTXFCR,IP TX FIFO Control Register"
|
|
hexmask.long.byte 0x00 2.--8. 1. "TXWMRK,Watermark level is (TXWMRK+1)*64 Bits"
|
|
bitfld.long 0x00 1. "TXDMAEN,IP TX FIFO filling by DMA enabled" "0: IP TX FIFO would be filled by processor,1: IP TX FIFO would be filled by DMA"
|
|
newline
|
|
bitfld.long 0x00 0. "CLRIPTXF,Clear all valid data entries in IP TX FIFO" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DLLCRA,DLL Control Register 0"
|
|
bitfld.long 0x00 9.--14. "OVRDVAL,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. "OVRDEN,Slave clock delay line delay cell number selection override enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--6. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz DLLEN set to 0x1 OVRDEN set to =0x0 then SLVDLYTARGET setting of 0xF is recommended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. "DLLRESET,Software could force a reset on DLL by setting this field to 0x1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DLLEN,DLL calibration enable" "0,1"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DLLCRB,DLL Control Register 0"
|
|
bitfld.long 0x00 9.--14. "OVRDVAL,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. "OVRDEN,Slave clock delay line delay cell number selection override enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--6. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz DLLEN set to 0x1 OVRDEN set to =0x0 then SLVDLYTARGET setting of 0xF is recommended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. "DLLRESET,Software could force a reset on DLL by setting this field to 0x1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DLLEN,DLL calibration enable" "0,1"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "STS0,Status Register 0"
|
|
bitfld.long 0x00 8.--11. "DATALEARNPHASEB,Indicate the sampling clock phase selection on Port B after Data Learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "DATALEARNPHASEA,Indicate the sampling clock phase selection on Port A after Data Learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "ARBCMDSRC,This status field indicates the trigger source of current command sequence granted by arbitrator" "0: Triggered by AHB read command (triggered by..,1: Triggered by AHB write command (triggered by..,2: Triggered by IP command (triggered by setting..,3: Triggered by suspended command (resumed)"
|
|
bitfld.long 0x00 1. "ARBIDLE,This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SEQIDLE,This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface" "0,1"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "STS1,Status Register 1"
|
|
bitfld.long 0x00 24.--27. "IPCMDERRCODE,Indicates the Error Code when IP command Error detected" "0: IPCMDERRCODE_0,?,2: IP command with JMP_ON_CS instruction used in..,3: There is unknown instruction opcode in the..,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in..,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in..,6: Flash access start address exceed the whole..,?,?,?,?,?,?,?,14: Sequence execution timeout,15: Flash boundary crossed"
|
|
bitfld.long 0x00 16.--20. "IPCMDERRID,Indicates the sequence Index when IP command error detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "AHBCMDERRCODE,Indicates the Error Code when AHB command Error detected" "0: AHBCMDERRCODE_0,?,2: AHB Write command with JMP_ON_CS instruction..,3: There is unknown instruction opcode in the..,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in..,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in..,?,?,?,?,?,?,?,?,14: Sequence execution timeout,?..."
|
|
bitfld.long 0x00 0.--4. "AHBCMDERRID,Indicates the sequence index when an AHB command error is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "STS2,Status Register 2"
|
|
bitfld.long 0x00 24.--29. "BREFSEL,Flash B sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 18.--23. "BSLVSEL,Flash B sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 17. "BREFLOCK,Flash B sample clock reference delay line locked" "0,1"
|
|
bitfld.long 0x00 16. "BSLVLOCK,Flash B sample clock slave delay line locked" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "AREFSEL,Flash A sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 2.--7. "ASLVSEL,Flash A sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 1. "AREFLOCK,Flash A sample clock reference delay line locked" "0,1"
|
|
bitfld.long 0x00 0. "ASLVLOCK,Flash A sample clock slave delay line locked" "0,1"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "AHBSPNDSTS,AHB Suspend Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DATLFT,Left Data size for suspended command sequence (in byte)"
|
|
bitfld.long 0x00 1.--3. "BUFID,AHB RX BUF ID for suspended command sequence" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "ACTIVE,Indicates if an AHB read prefetch command sequence has been suspended" "0,1"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "IPRXFSTS,IP RX FIFO Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDCNTR,Total Read Data Counter: RDCNTR * 64 Bits"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FILL,Fill level of IP RX FIFO"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "IPTXFSTS,IP TX FIFO Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "WRCNTR,Total Write Data Counter: WRCNTR * 64 Bits"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FILL,Fill level of IP TX FIFO"
|
|
repeat 32. (increment 0 1) (increment 0 0x04)
|
|
rgroup.long ($2+0x100)++0x03
|
|
line.long 0x00 "RFDR[$1],IP RX FIFO Data Register x $1"
|
|
hexmask.long 0x00 0.--31. 1. "RXDATA,RX Data"
|
|
repeat.end
|
|
repeat 32. (increment 0 1) (increment 0 0x04)
|
|
wgroup.long ($2+0x180)++0x03
|
|
line.long 0x00 "TFDR[$1],IP TX FIFO Data Register x $1"
|
|
hexmask.long 0x00 0.--31. 1. "TXDATA,TX Data"
|
|
repeat.end
|
|
repeat 128. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "LUT[$1],LUT x $1"
|
|
bitfld.long 0x00 26.--31. "OPCODE1,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 24.--25. "NUM_PADS1,NUM_PADS1" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "OPERAND1,OPERAND1"
|
|
bitfld.long 0x00 10.--15. "OPCODE0,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "NUM_PADS0,NUM_PADS0" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OPERAND0,OPERAND0"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
tree "HSIO__GPIO"
|
|
base ad:0x5F170000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,GPIO data register"
|
|
hexmask.long 0x00 0.--31. 1. "DR,DR"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GDIR,GPIO direction register"
|
|
hexmask.long 0x00 0.--31. 1. "GDIR,GDIR"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,GPIO pad status register"
|
|
hexmask.long 0x00 0.--31. 1. "PSR,PSR"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ICR1,GPIO interrupt configuration register1"
|
|
bitfld.long 0x00 30.--31. "ICR15,ICR15" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 28.--29. "ICR14,ICR14" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "ICR13,ICR13" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 24.--25. "ICR12,ICR12" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "ICR11,ICR11" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 20.--21. "ICR10,ICR10" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "ICR9,ICR9" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 16.--17. "ICR8,ICR8" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "ICR7,ICR7" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 12.--13. "ICR6,ICR6" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "ICR5,ICR5" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 8.--9. "ICR4,ICR4" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "ICR3,ICR3" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 4.--5. "ICR2,ICR2" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "ICR1,ICR1" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 0.--1. "ICR0,ICR0" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ICR2,GPIO interrupt configuration register2"
|
|
bitfld.long 0x00 30.--31. "ICR31,ICR31" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 28.--29. "ICR30,ICR30" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "ICR29,ICR29" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 24.--25. "ICR28,ICR28" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "ICR27,ICR27" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 20.--21. "ICR26,ICR26" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "ICR25,ICR25" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 16.--17. "ICR24,ICR24" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "ICR23,ICR23" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 12.--13. "ICR22,ICR22" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "ICR21,ICR21" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 8.--9. "ICR20,ICR20" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "ICR19,ICR19" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 4.--5. "ICR18,ICR18" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "ICR17,ICR17" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 0.--1. "ICR16,ICR16" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IMR,GPIO interrupt mask register"
|
|
hexmask.long 0x00 0.--31. 1. "IMR,IMR"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ISR,GPIO interrupt status register"
|
|
hexmask.long 0x00 0.--31. 1. "ISR,ISR"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EDGE_SEL,GPIO edge select register"
|
|
hexmask.long 0x00 0.--31. 1. "GPIO_EDGE_SEL,GPIO_EDGE_SEL"
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "DR_SET,GPIO data register SET"
|
|
hexmask.long 0x00 0.--31. 1. "DR_SET,DR_SET"
|
|
wgroup.long 0x88++0x03
|
|
line.long 0x00 "DR_CLEAR,GPIO data register CLEAR"
|
|
hexmask.long 0x00 0.--31. 1. "DR_CLEAR,DR_CLEAR"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "DR_TOGGLE,GPIO data register TOGGLE"
|
|
hexmask.long 0x00 0.--31. 1. "DR_TOGGLE,DR_TOGGLE"
|
|
tree.end
|
|
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7.) (list ad:0x5D080000 ad:0x5D090000 ad:0x5D0A0000 ad:0x5D0B0000 ad:0x5D0C0000 ad:0x5D0D0000 ad:0x5D0E0000 ad:0x5D0F0000)
|
|
tree "LSIO__GPIO$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,GPIO data register"
|
|
hexmask.long 0x00 0.--31. 1. "DR,DR"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GDIR,GPIO direction register"
|
|
hexmask.long 0x00 0.--31. 1. "GDIR,GDIR"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,GPIO pad status register"
|
|
hexmask.long 0x00 0.--31. 1. "PSR,PSR"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ICR1,GPIO interrupt configuration register1"
|
|
bitfld.long 0x00 30.--31. "ICR15,ICR15" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 28.--29. "ICR14,ICR14" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "ICR13,ICR13" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 24.--25. "ICR12,ICR12" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "ICR11,ICR11" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 20.--21. "ICR10,ICR10" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "ICR9,ICR9" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 16.--17. "ICR8,ICR8" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "ICR7,ICR7" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 12.--13. "ICR6,ICR6" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "ICR5,ICR5" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 8.--9. "ICR4,ICR4" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "ICR3,ICR3" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 4.--5. "ICR2,ICR2" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "ICR1,ICR1" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 0.--1. "ICR0,ICR0" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ICR2,GPIO interrupt configuration register2"
|
|
bitfld.long 0x00 30.--31. "ICR31,ICR31" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 28.--29. "ICR30,ICR30" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "ICR29,ICR29" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 24.--25. "ICR28,ICR28" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "ICR27,ICR27" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 20.--21. "ICR26,ICR26" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "ICR25,ICR25" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 16.--17. "ICR24,ICR24" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "ICR23,ICR23" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 12.--13. "ICR22,ICR22" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "ICR21,ICR21" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 8.--9. "ICR20,ICR20" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "ICR19,ICR19" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 4.--5. "ICR18,ICR18" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "ICR17,ICR17" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
bitfld.long 0x00 0.--1. "ICR16,ICR16" "0: Interrupt n is low-level sensitive,1: Interrupt n is high-level sensitive,2: Interrupt n is rising-edge sensitive,3: Interrupt n is falling-edge sensitive"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IMR,GPIO interrupt mask register"
|
|
hexmask.long 0x00 0.--31. 1. "IMR,IMR"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ISR,GPIO interrupt status register"
|
|
hexmask.long 0x00 0.--31. 1. "ISR,ISR"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EDGE_SEL,GPIO edge select register"
|
|
hexmask.long 0x00 0.--31. 1. "GPIO_EDGE_SEL,GPIO_EDGE_SEL"
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "DR_SET,GPIO data register SET"
|
|
hexmask.long 0x00 0.--31. 1. "DR_SET,DR_SET"
|
|
wgroup.long 0x88++0x03
|
|
line.long 0x00 "DR_CLEAR,GPIO data register CLEAR"
|
|
hexmask.long 0x00 0.--31. 1. "DR_CLEAR,DR_CLEAR"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "DR_TOGGLE,GPIO data register TOGGLE"
|
|
hexmask.long 0x00 0.--31. 1. "DR_TOGGLE,DR_TOGGLE"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "GPMI2 (GPMI)"
|
|
base ad:0x5B812000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL0,GPMI Control Register 0 Description"
|
|
bitfld.long 0x00 31. "SFTRST,SFTRST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,CLKGATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RUN,RUN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "WR_DATA_EN,WR_DATA_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "LOCK_CS,LOCK_CS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "UDMA,UDMA" "0: Use ATA-PIO mode on the external bus,1: Use ATA-Ultra DMA mode on the external bus"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "COMMAND_MODE,COMMAND_MODE" "0: COMMAND_MODE_0,1: COMMAND_MODE_1,2: Read and Compare Mode (setting sense flop),3: Wait for Ready"
|
|
newline
|
|
bitfld.long 0x00 23. "WORD_LENGTH,WORD_LENGTH" "?,1: 8-bit Data Bus mode"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "CS,CS" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "ADDRESS,ADDRESS" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "ADDRESS_INCREMENT,ADDRESS_INCREMENT" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "XFER_COUNT,XFER_COUNT"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL0_SET,GPMI Control Register 0 Description"
|
|
bitfld.long 0x00 31. "SFTRST,SFTRST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,CLKGATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RUN,RUN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "WR_DATA_EN,WR_DATA_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "LOCK_CS,LOCK_CS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "UDMA,UDMA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "COMMAND_MODE,COMMAND_MODE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 23. "WORD_LENGTH,WORD_LENGTH" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "CS,CS" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "ADDRESS,ADDRESS" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "ADDRESS_INCREMENT,ADDRESS_INCREMENT" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "XFER_COUNT,XFER_COUNT"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL0_CLR,GPMI Control Register 0 Description"
|
|
eventfld.long 0x00 31. "SFTRST,SFTRST" "0,1"
|
|
newline
|
|
eventfld.long 0x00 30. "CLKGATE,CLKGATE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 29. "RUN,RUN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 28. "WR_DATA_EN,WR_DATA_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 27. "LOCK_CS,LOCK_CS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 26. "UDMA,UDMA" "0,1"
|
|
newline
|
|
eventfld.long 0x00 24.--25. "COMMAND_MODE,COMMAND_MODE" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 23. "WORD_LENGTH,WORD_LENGTH" "0,1"
|
|
newline
|
|
eventfld.long 0x00 20.--22. "CS,CS" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
eventfld.long 0x00 17.--19. "ADDRESS,ADDRESS" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
eventfld.long 0x00 16. "ADDRESS_INCREMENT,ADDRESS_INCREMENT" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "XFER_COUNT,XFER_COUNT"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTRL0_TOG,GPMI Control Register 0 Description"
|
|
bitfld.long 0x00 31. "SFTRST,SFTRST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,CLKGATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "RUN,RUN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "WR_DATA_EN,WR_DATA_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "LOCK_CS,LOCK_CS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "UDMA,UDMA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "COMMAND_MODE,COMMAND_MODE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 23. "WORD_LENGTH,WORD_LENGTH" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "CS,CS" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "ADDRESS,ADDRESS" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16. "ADDRESS_INCREMENT,ADDRESS_INCREMENT" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "XFER_COUNT,XFER_COUNT"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "COMPARE,GPMI Compare Register Description"
|
|
hexmask.long.word 0x00 16.--31. 1. "MASK,MASK"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "REFERENCE,REFERENCE"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ECCCTRL,GPMI Integrated ECC Control Register Description"
|
|
hexmask.long.word 0x00 16.--31. 1. "HANDLE,HANDLE"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "ECC_CMD,ECC_CMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12. "ENABLE_ECC,ENABLE_ECC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RANDOMIZER_ENABLE,RANDOMIZER_ENABLE" "0: RANDOMIZER_ENABLE_0,1: RANDOMIZER_ENABLE_1"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "RANDOMIZER_TYPE,RANDOMIZER_TYPE" "0: RANDOMIZER_TYPE_0,1: RANDOMIZER_TYPE_1,2: RANDOMIZER_TYPE_2,?..."
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "BUFFER_MASK,BUFFER_MASK"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ECCCTRL_SET,GPMI Integrated ECC Control Register Description"
|
|
hexmask.long.word 0x00 16.--31. 1. "HANDLE,HANDLE"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "ECC_CMD,ECC_CMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12. "ENABLE_ECC,ENABLE_ECC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RANDOMIZER_ENABLE,RANDOMIZER_ENABLE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "RANDOMIZER_TYPE,RANDOMIZER_TYPE" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "BUFFER_MASK,BUFFER_MASK"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ECCCTRL_CLR,GPMI Integrated ECC Control Register Description"
|
|
hexmask.long.word 0x00 16.--31. 1. "HANDLE,HANDLE"
|
|
newline
|
|
eventfld.long 0x00 13.--14. "ECC_CMD,ECC_CMD" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 12. "ENABLE_ECC,ENABLE_ECC" "0,1"
|
|
newline
|
|
eventfld.long 0x00 11. "RANDOMIZER_ENABLE,RANDOMIZER_ENABLE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 9.--10. "RANDOMIZER_TYPE,RANDOMIZER_TYPE" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "BUFFER_MASK,BUFFER_MASK"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ECCCTRL_TOG,GPMI Integrated ECC Control Register Description"
|
|
hexmask.long.word 0x00 16.--31. 1. "HANDLE,HANDLE"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "ECC_CMD,ECC_CMD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 12. "ENABLE_ECC,ENABLE_ECC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "RANDOMIZER_ENABLE,RANDOMIZER_ENABLE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "RANDOMIZER_TYPE,RANDOMIZER_TYPE" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "BUFFER_MASK,BUFFER_MASK"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ECCCOUNT,GPMI Integrated ECC Transfer Count Register Description"
|
|
hexmask.long.byte 0x00 16.--23. 1. "RANDOMIZER_PAGE,RANDOMIZER_PAGE"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,COUNT"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PAYLOAD,GPMI Payload Address Register Description"
|
|
hexmask.long 0x00 2.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "AUXILIARY,GPMI Auxiliary Address Register Description"
|
|
hexmask.long 0x00 2.--31. 1. "ADDRESS,ADDRESS"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CTRL1,GPMI Control Register 1 Description"
|
|
bitfld.long 0x00 31. "DEV_CLK_STOP,DEV_CLK_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SSYNC_CLK_STOP,SSYNC_CLK_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "WRITE_CLK_STOP,WRITE_CLK_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "TOGGLE_MODE,TOGGLE_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "GPMI_CLK_DIV2_EN,GPMI_CLK_DIV2_EN" "0: internal factor-2 clock divider is disabled,1: internal factor-2 clock divider is enabled"
|
|
newline
|
|
bitfld.long 0x00 26. "UPDATE_CS,UPDATE_CS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "SSYNCMODE,SSYNCMODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "DECOUPLE_CS,DECOUPLE_CS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "WRN_DLY_SEL,WRN_DLY_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 21. "TEST_TRIGGER,TEST_TRIGGER" "0: TEST_TRIGGER_0,1: TEST_TRIGGER_1"
|
|
newline
|
|
bitfld.long 0x00 20. "TIMEOUT_IRQ_EN,TIMEOUT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "GANGED_RDYBUSY,GANGED_RDYBUSY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "BCH_MODE,BCH_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DLL_ENABLE,DLL_ENABLE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "HALF_PERIOD,HALF_PERIOD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "RDN_DELAY,RDN_DELAY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11. "DMA2ECC_MODE,DMA2ECC_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "DEV_IRQ,DEV_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TIMEOUT_IRQ,TIMEOUT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "BURST_EN,BURST_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ABORT_WAIT_REQUEST,ABORT_WAIT_REQUEST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "ABORT_WAIT_FOR_READY_CHANNEL,ABORT_WAIT_FOR_READY_CHANNEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "DEV_RESET,DEV_RESET" "0: NANDF_WP_B pin is held low (asserted),1: NANDF_WP_B pin is held high (de-asserted)"
|
|
newline
|
|
bitfld.long 0x00 2. "ATA_IRQRDY_POLARITY,ATA_IRQRDY_POLARITY" "0: External RDY_BUSY[1] and RDY_BUSY[0] pins are..,1: External RDY_BUSY[1] and RDY_BUSY[0] pins are.."
|
|
newline
|
|
bitfld.long 0x00 1. "CAMERA_MODE,CAMERA_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GPMI_MODE,GPMI_MODE" "0: GPMI_MODE_0,1: GPMI_MODE_1"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CTRL1_SET,GPMI Control Register 1 Description"
|
|
bitfld.long 0x00 31. "DEV_CLK_STOP,DEV_CLK_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SSYNC_CLK_STOP,SSYNC_CLK_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "WRITE_CLK_STOP,WRITE_CLK_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "TOGGLE_MODE,TOGGLE_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "GPMI_CLK_DIV2_EN,GPMI_CLK_DIV2_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "UPDATE_CS,UPDATE_CS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "SSYNCMODE,SSYNCMODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "DECOUPLE_CS,DECOUPLE_CS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "WRN_DLY_SEL,WRN_DLY_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 21. "TEST_TRIGGER,TEST_TRIGGER" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "TIMEOUT_IRQ_EN,TIMEOUT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "GANGED_RDYBUSY,GANGED_RDYBUSY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "BCH_MODE,BCH_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DLL_ENABLE,DLL_ENABLE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "HALF_PERIOD,HALF_PERIOD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "RDN_DELAY,RDN_DELAY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11. "DMA2ECC_MODE,DMA2ECC_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "DEV_IRQ,DEV_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TIMEOUT_IRQ,TIMEOUT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "BURST_EN,BURST_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ABORT_WAIT_REQUEST,ABORT_WAIT_REQUEST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "ABORT_WAIT_FOR_READY_CHANNEL,ABORT_WAIT_FOR_READY_CHANNEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "DEV_RESET,DEV_RESET" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ATA_IRQRDY_POLARITY,ATA_IRQRDY_POLARITY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CAMERA_MODE,CAMERA_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GPMI_MODE,GPMI_MODE" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CTRL1_CLR,GPMI Control Register 1 Description"
|
|
eventfld.long 0x00 31. "DEV_CLK_STOP,DEV_CLK_STOP" "0,1"
|
|
newline
|
|
eventfld.long 0x00 30. "SSYNC_CLK_STOP,SSYNC_CLK_STOP" "0,1"
|
|
newline
|
|
eventfld.long 0x00 29. "WRITE_CLK_STOP,WRITE_CLK_STOP" "0,1"
|
|
newline
|
|
eventfld.long 0x00 28. "TOGGLE_MODE,TOGGLE_MODE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 27. "GPMI_CLK_DIV2_EN,GPMI_CLK_DIV2_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 26. "UPDATE_CS,UPDATE_CS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 25. "SSYNCMODE,SSYNCMODE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 24. "DECOUPLE_CS,DECOUPLE_CS" "0,1"
|
|
newline
|
|
eventfld.long 0x00 22.--23. "WRN_DLY_SEL,WRN_DLY_SEL" "0,1,2,3"
|
|
newline
|
|
eventfld.long 0x00 21. "TEST_TRIGGER,TEST_TRIGGER" "0,1"
|
|
newline
|
|
eventfld.long 0x00 20. "TIMEOUT_IRQ_EN,TIMEOUT_IRQ_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 19. "GANGED_RDYBUSY,GANGED_RDYBUSY" "0,1"
|
|
newline
|
|
eventfld.long 0x00 18. "BCH_MODE,BCH_MODE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 17. "DLL_ENABLE,DLL_ENABLE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 16. "HALF_PERIOD,HALF_PERIOD" "0,1"
|
|
newline
|
|
eventfld.long 0x00 12.--15. "RDN_DELAY,RDN_DELAY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
eventfld.long 0x00 11. "DMA2ECC_MODE,DMA2ECC_MODE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 10. "DEV_IRQ,DEV_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 9. "TIMEOUT_IRQ,TIMEOUT_IRQ" "0,1"
|
|
newline
|
|
eventfld.long 0x00 8. "BURST_EN,BURST_EN" "0,1"
|
|
newline
|
|
eventfld.long 0x00 7. "ABORT_WAIT_REQUEST,ABORT_WAIT_REQUEST" "0,1"
|
|
newline
|
|
eventfld.long 0x00 4.--6. "ABORT_WAIT_FOR_READY_CHANNEL,ABORT_WAIT_FOR_READY_CHANNEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
eventfld.long 0x00 3. "DEV_RESET,DEV_RESET" "0,1"
|
|
newline
|
|
eventfld.long 0x00 2. "ATA_IRQRDY_POLARITY,ATA_IRQRDY_POLARITY" "0,1"
|
|
newline
|
|
eventfld.long 0x00 1. "CAMERA_MODE,CAMERA_MODE" "0,1"
|
|
newline
|
|
eventfld.long 0x00 0. "GPMI_MODE,GPMI_MODE" "0,1"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CTRL1_TOG,GPMI Control Register 1 Description"
|
|
bitfld.long 0x00 31. "DEV_CLK_STOP,DEV_CLK_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "SSYNC_CLK_STOP,SSYNC_CLK_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "WRITE_CLK_STOP,WRITE_CLK_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "TOGGLE_MODE,TOGGLE_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "GPMI_CLK_DIV2_EN,GPMI_CLK_DIV2_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "UPDATE_CS,UPDATE_CS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "SSYNCMODE,SSYNCMODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "DECOUPLE_CS,DECOUPLE_CS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "WRN_DLY_SEL,WRN_DLY_SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 21. "TEST_TRIGGER,TEST_TRIGGER" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "TIMEOUT_IRQ_EN,TIMEOUT_IRQ_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "GANGED_RDYBUSY,GANGED_RDYBUSY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "BCH_MODE,BCH_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DLL_ENABLE,DLL_ENABLE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "HALF_PERIOD,HALF_PERIOD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "RDN_DELAY,RDN_DELAY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11. "DMA2ECC_MODE,DMA2ECC_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "DEV_IRQ,DEV_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "TIMEOUT_IRQ,TIMEOUT_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "BURST_EN,BURST_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ABORT_WAIT_REQUEST,ABORT_WAIT_REQUEST" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "ABORT_WAIT_FOR_READY_CHANNEL,ABORT_WAIT_FOR_READY_CHANNEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. "DEV_RESET,DEV_RESET" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ATA_IRQRDY_POLARITY,ATA_IRQRDY_POLARITY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "CAMERA_MODE,CAMERA_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "GPMI_MODE,GPMI_MODE" "0,1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TIMING0,GPMI Timing Register 0 Description"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ADDRESS_SETUP,ADDRESS_SETUP"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_HOLD,DATA_HOLD"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_SETUP,DATA_SETUP"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TIMING1,GPMI Timing Register 1 Description"
|
|
hexmask.long.word 0x00 16.--31. 1. "DEVICE_BUSY_TIMEOUT,DEVICE_BUSY_TIMEOUT"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TIMING2,GPMI Timing Register 2 Description"
|
|
bitfld.long 0x00 29.--31. "TRPSTH,TRPSTH" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27.--28. "TCR,TCR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "READ_LATENCY,READ_LATENCY" "0: READ LATENCY is 0,1: READ LATENCY is 1,2: READ LATENCY is 2,3: READ LATENCY is 3,4: READ LATENCY is 4,5: READ LATENCY is 5,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--20. "CE_DELAY,CE_DELAY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PREAMBLE_DELAY,PREAMBLE_DELAY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "POSTAMBLE_DELAY,POSTAMBLE_DELAY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CMDADD_PAUSE,CMDADD_PAUSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DATA_PAUSE,DATA_PAUSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DATA,GPMI DMA Data Transfer Register Description"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,DATA"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "STAT,GPMI Status Register Description"
|
|
hexmask.long.byte 0x00 24.--31. 1. "READY_BUSY,READY_BUSY"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "RDY_TIMEOUT,RDY_TIMEOUT"
|
|
newline
|
|
bitfld.long 0x00 15. "DEV7_ERROR,DEV7_ERROR" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
|
|
newline
|
|
bitfld.long 0x00 14. "DEV6_ERROR,DEV6_ERROR" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
|
|
newline
|
|
bitfld.long 0x00 13. "DEV5_ERROR,DEV5_ERROR" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
|
|
newline
|
|
bitfld.long 0x00 12. "DEV4_ERROR,DEV4_ERROR" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
|
|
newline
|
|
bitfld.long 0x00 11. "DEV3_ERROR,DEV3_ERROR" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
|
|
newline
|
|
bitfld.long 0x00 10. "DEV2_ERROR,DEV2_ERROR" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
|
|
newline
|
|
bitfld.long 0x00 9. "DEV1_ERROR,DEV1_ERROR" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
|
|
newline
|
|
bitfld.long 0x00 8. "DEV0_ERROR,DEV0_ERROR" "0: No error condition present on ATA/NAND Device..,1: An Error has occurred on ATA/NAND Device.."
|
|
newline
|
|
bitfld.long 0x00 4. "ATA_IRQ,ATA_IRQ" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "INVALID_BUFFER_MASK,INVALID_BUFFER_MASK" "0: ECC Buffer Mask is not invalid,1: ECC Buffer Mask is invalid"
|
|
newline
|
|
bitfld.long 0x00 2. "FIFO_EMPTY,FIFO_EMPTY" "0: FIFO is not empty,1: FIFO is empty"
|
|
newline
|
|
bitfld.long 0x00 1. "FIFO_FULL,FIFO_FULL" "0: FIFO is not full,1: FIFO is full"
|
|
newline
|
|
bitfld.long 0x00 0. "PRESENT,PRESENT" "0: GPMI is not present in this product,1: GPMI is present is in this product"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "DEBUG,GPMI Debug Information Register Description"
|
|
hexmask.long.byte 0x00 24.--31. 1. "WAIT_FOR_READY_END,WAIT_FOR_READY_END"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "DMA_SENSE,DMA_SENSE"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DMAREQ,DMAREQ"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CMD_END,CMD_END"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "VERSION,GPMI Version Register Description"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,MAJOR"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,MINOR"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "STEP,STEP"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DEBUG2,GPMI Debug2 Information Register Description"
|
|
rbitfld.long 0x00 24.--27. "UDMA_STATE,UDMA_STATE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 23. "BUSY,BUSY" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20.--22. "PIN_STATE,PIN_STATE" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 16.--19. "MAIN_STATE,MAIN_STATE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "SYND2GPMI_BE,SYND2GPMI_BE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 11. "GPMI2SYND_VALID,GPMI2SYND_VALID" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. "GPMI2SYND_READY,GPMI2SYND_READY" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 9. "SYND2GPMI_VALID,SYND2GPMI_VALID" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8. "SYND2GPMI_READY,SYND2GPMI_READY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "VIEW_DELAYED_RDN,VIEW_DELAYED_RDN" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 6. "UPDATE_WINDOW,UPDATE_WINDOW" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--5. "RDN_TAP,RDN_TAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "DEBUG3,GPMI Debug3 Information Register Description"
|
|
hexmask.long.word 0x00 16.--31. 1. "APB_WORD_CNTR,APB_WORD_CNTR"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "DEV_WORD_CNTR,DEV_WORD_CNTR"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "READ_DDR_DLL_CTRL,GPMI Double Rate Read DLL Control Register Description"
|
|
bitfld.long 0x00 28.--31. "REF_UPDATE_INT,REF_UPDATE_INT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 20.--27. 1. "SLV_UPDATE_INT,SLV_UPDATE_INT"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--17. 1. "SLV_OVERRIDE_VAL,SLV_OVERRIDE_VAL"
|
|
newline
|
|
bitfld.long 0x00 9. "SLV_OVERRIDE,SLV_OVERRIDE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "REFCLK_ON,REFCLK_ON" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "GATE_UPDATE,GATE_UPDATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--6. "SLV_DLY_TARGET,SLV_DLY_TARGET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2. "SLV_FORCE_UPD,SLV_FORCE_UPD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RESET,RESET" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE,ENABLE" "0,1"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "WRITE_DDR_DLL_CTRL,GPMI Double Rate Write DLL Control Register Description"
|
|
bitfld.long 0x00 28.--31. "REF_UPDATE_INT,REF_UPDATE_INT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 20.--27. 1. "SLV_UPDATE_INT,SLV_UPDATE_INT"
|
|
newline
|
|
hexmask.long.byte 0x00 10.--17. 1. "SLV_OVERRIDE_VAL,SLV_OVERRIDE_VAL"
|
|
newline
|
|
bitfld.long 0x00 9. "SLV_OVERRIDE,SLV_OVERRIDE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "REFCLK_ON,REFCLK_ON" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "GATE_UPDATE,GATE_UPDATE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--6. "SLV_DLY_TARGET,SLV_DLY_TARGET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2. "SLV_FORCE_UPD,SLV_FORCE_UPD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "RESET,RESET" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENABLE,ENABLE" "0,1"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "READ_DDR_DLL_STS,GPMI Double Rate Read DLL Status Register Description"
|
|
hexmask.long.byte 0x00 17.--24. 1. "REF_SEL,REF_SEL"
|
|
newline
|
|
bitfld.long 0x00 16. "REF_LOCK,REF_LOCK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--8. 1. "SLV_SEL,SLV_SEL"
|
|
newline
|
|
bitfld.long 0x00 0. "SLV_LOCK,SLV_LOCK" "0,1"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "WRITE_DDR_DLL_STS,GPMI Double Rate Write DLL Status Register Description"
|
|
hexmask.long.byte 0x00 17.--24. 1. "REF_SEL,REF_SEL"
|
|
newline
|
|
bitfld.long 0x00 16. "REF_LOCK,REF_LOCK" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 1.--8. 1. "SLV_SEL,SLV_SEL"
|
|
newline
|
|
bitfld.long 0x00 0. "SLV_LOCK,SLV_LOCK" "0,1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TIMING3,GPMI Timing Register 3 Description"
|
|
bitfld.long 0x00 8.--12. "TRWARMUP,TRWARMUP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "TWWARMUP,TWWARMUP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CTRL2,GPMI Control Register 2 Description"
|
|
bitfld.long 0x00 3. "CEN_REDUCTION,CEN_REDUCTION" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "WARMUP_EN,WARMUP_EN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TOGGLE20_MODE,TOGGLE20_MODE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "NVDDR2_MODE,NVDDR2_MODE" "0,1"
|
|
tree.end
|
|
tree "GPT (General Purpose Timer)"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x590B0000 ad:0x590C0000 ad:0x590D0000 ad:0x590E0000)
|
|
tree "ADMA__GPT$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,GPT Control Register"
|
|
bitfld.long 0x00 31. "FO3,Force Output Compare for Channel 3" "0: No effect,1: Trigger the programmed response on the pin"
|
|
bitfld.long 0x00 30. "FO2,Force Output Compare for Channel 2" "0: No effect,1: Trigger the programmed response on the pin"
|
|
newline
|
|
bitfld.long 0x00 29. "FO1,Force Output Compare for Channel 1" "0: No effect,1: Trigger the programmed response on the pin"
|
|
bitfld.long 0x00 26.--28. "OM3,Output Compare Operating Mode for Channel 3" "0: Output disabled,1: Toggle output pin,2: Clear output pin,3: Set output pin,4: Generate a low pulse that is one input clock..,5: Generate a low pulse that is one input clock..,6: Generate a low pulse that is one input clock..,7: Generate a low pulse that is one input clock.."
|
|
newline
|
|
bitfld.long 0x00 23.--25. "OM2,Output Compare Operating Mode for Channel 2" "0: Output disabled,1: Toggle output pin,2: Clear output pin,3: Set output pin,4: Generate a low pulse that is one input clock..,5: Generate a low pulse that is one input clock..,6: Generate a low pulse that is one input clock..,7: Generate a low pulse that is one input clock.."
|
|
bitfld.long 0x00 20.--22. "OM1,Output Compare Operating Mode for Channel 1" "0: Output disabled,1: Toggle output pin,2: Clear output pin,3: Set output pin,4: Generate a low pulse that is one input clock..,5: Generate a low pulse that is one input clock..,6: Generate a low pulse that is one input clock..,7: Generate a low pulse that is one input clock.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "IM2,Input Capture Operating Mode for Channel 2" "0: Capture disabled,1: Capture on rising edge only,2: Capture on falling edge only,3: Capture on both edges"
|
|
bitfld.long 0x00 16.--17. "IM1,Input Capture Operating Mode for Channel 1" "0: Capture disabled,1: Capture on rising edge only,2: Capture on falling edge only,3: Capture on both edges"
|
|
newline
|
|
bitfld.long 0x00 15. "SWR,Software Reset" "0: GPT is not in software reset state,1: GPT is in software reset state"
|
|
bitfld.long 0x00 10. "EN_24M,Enable 24 MHz Clock Input" "0: 24-MHz clock disabled,1: 24-MHz clock enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FRR,Free-Run or Restart Mode" "0: Restart mode,1: Free-Run mode"
|
|
bitfld.long 0x00 6.--8. "CLKSRC,Clock Source Select" "0: NO_CLOCK,1: Peripheral Clock (ipg_clk),2: High Frequency Reference Clock..,3: External Clock,4: Low Frequency Reference Clock (ipg_clk_32k),5: Crystal oscillator as Reference Clock..,?..."
|
|
newline
|
|
bitfld.long 0x00 5. "STOPEN,GPT Stop Mode Enable" "0: GPT is disabled in Stop mode,1: GPT is enabled in Stop mode"
|
|
bitfld.long 0x00 4. "DOZEEN,GPT Doze Mode Enable" "0: GPT is disabled in Doze mode,1: GPT is enabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 3. "WAITEN,GPT Wait Mode Enable" "0: GPT is disabled in Wait mode,1: GPT is enabled in Wait mode"
|
|
bitfld.long 0x00 2. "DBGEN,GPT Debug Mode Enable" "0: GPT is disabled in Debug mode,1: GPT is enabled in Debug mode"
|
|
newline
|
|
bitfld.long 0x00 1. "ENMOD,GPT Enable Mode" "0: The Main Counter and Prescaler Counter..,1: The Main Counter and Prescaler Counter values.."
|
|
bitfld.long 0x00 0. "EN,GPT Enable" "0: GPT is disabled,1: GPT is enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PR,GPT Prescaler Register"
|
|
bitfld.long 0x00 12.--15. "PRESCALER24M,Prescaler divide value for the 24 MHz crystal clock" "0: Divide by 1,1: Divide by 2,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Divide by 16"
|
|
hexmask.long.word 0x00 0.--11. 1. "PRESCALER,Prescaler divide value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR,GPT Status Register"
|
|
eventfld.long 0x00 5. "ROV,Rollover Flag" "0: Rollover has not occurred,1: Rollover has occurred"
|
|
eventfld.long 0x00 4. "IF2,Input Capture Flag for Channel 2" "0: Capture event has not occurred,1: Capture event has occurred"
|
|
newline
|
|
eventfld.long 0x00 3. "IF1,Input Capture Flag for Channel 1" "0: Capture event has not occurred,1: Capture event has occurred"
|
|
eventfld.long 0x00 2. "OF3,Output Compare Flag for Channel 3" "0: Compare event has not occurred,1: Compare event has occurred"
|
|
newline
|
|
eventfld.long 0x00 1. "OF2,Output Compare Flag for Channel 2" "0: Compare event has not occurred,1: Compare event has occurred"
|
|
eventfld.long 0x00 0. "OF1,Output Compare Flag for Channel 1" "0: Compare event has not occurred,1: Compare event has occurred"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IR,GPT Interrupt Register"
|
|
bitfld.long 0x00 5. "ROVIE,Rollover Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 4. "IF2IE,Input Capture for Channel 2 Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. "IF1IE,Input Capture for Channel 1 Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 2. "OF3IE,Output Compare for Channel 3 Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "OF2IE,Output Compare for Channel 2 Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 0. "OF1IE,Output Compare for Channel 1 Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "OCR$1,GPT Output Compare Register"
|
|
hexmask.long 0x00 0.--31. 1. "COMP,Compare Value"
|
|
repeat.end
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
rgroup.long ($2+0x1C)++0x03
|
|
line.long 0x00 "ICR$1,GPT Input Capture Register"
|
|
hexmask.long 0x00 0.--31. 1. "CAPT,Capture Value"
|
|
repeat.end
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CNT,GPT Counter Register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Counter Value"
|
|
tree.end
|
|
repeat.end
|
|
repeat 5. (list 0. 1. 2. 3. 4.) (list ad:0x5D140000 ad:0x5D150000 ad:0x5D160000 ad:0x5D170000 ad:0x5D180000)
|
|
tree "LSIO__GPT$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,GPT Control Register"
|
|
bitfld.long 0x00 31. "FO3,Force Output Compare for Channel 3" "0: No effect,1: Trigger the programmed response on the pin"
|
|
bitfld.long 0x00 30. "FO2,Force Output Compare for Channel 2" "0: No effect,1: Trigger the programmed response on the pin"
|
|
newline
|
|
bitfld.long 0x00 29. "FO1,Force Output Compare for Channel 1" "0: No effect,1: Trigger the programmed response on the pin"
|
|
bitfld.long 0x00 26.--28. "OM3,Output Compare Operating Mode for Channel 3" "0: Output disabled,1: Toggle output pin,2: Clear output pin,3: Set output pin,4: Generate a low pulse that is one input clock..,5: Generate a low pulse that is one input clock..,6: Generate a low pulse that is one input clock..,7: Generate a low pulse that is one input clock.."
|
|
newline
|
|
bitfld.long 0x00 23.--25. "OM2,Output Compare Operating Mode for Channel 2" "0: Output disabled,1: Toggle output pin,2: Clear output pin,3: Set output pin,4: Generate a low pulse that is one input clock..,5: Generate a low pulse that is one input clock..,6: Generate a low pulse that is one input clock..,7: Generate a low pulse that is one input clock.."
|
|
bitfld.long 0x00 20.--22. "OM1,Output Compare Operating Mode for Channel 1" "0: Output disabled,1: Toggle output pin,2: Clear output pin,3: Set output pin,4: Generate a low pulse that is one input clock..,5: Generate a low pulse that is one input clock..,6: Generate a low pulse that is one input clock..,7: Generate a low pulse that is one input clock.."
|
|
newline
|
|
bitfld.long 0x00 18.--19. "IM2,Input Capture Operating Mode for Channel 2" "0: Capture disabled,1: Capture on rising edge only,2: Capture on falling edge only,3: Capture on both edges"
|
|
bitfld.long 0x00 16.--17. "IM1,Input Capture Operating Mode for Channel 1" "0: Capture disabled,1: Capture on rising edge only,2: Capture on falling edge only,3: Capture on both edges"
|
|
newline
|
|
bitfld.long 0x00 15. "SWR,Software Reset" "0: GPT is not in software reset state,1: GPT is in software reset state"
|
|
bitfld.long 0x00 10. "EN_24M,Enable 24 MHz Clock Input" "0: 24-MHz clock disabled,1: 24-MHz clock enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FRR,Free-Run or Restart Mode" "0: Restart mode,1: Free-Run mode"
|
|
bitfld.long 0x00 6.--8. "CLKSRC,Clock Source Select" "0: NO_CLOCK,1: Peripheral Clock (ipg_clk),2: High Frequency Reference Clock..,3: External Clock,4: Low Frequency Reference Clock (ipg_clk_32k),5: Crystal oscillator as Reference Clock..,?..."
|
|
newline
|
|
bitfld.long 0x00 5. "STOPEN,GPT Stop Mode Enable" "0: GPT is disabled in Stop mode,1: GPT is enabled in Stop mode"
|
|
bitfld.long 0x00 4. "DOZEEN,GPT Doze Mode Enable" "0: GPT is disabled in Doze mode,1: GPT is enabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 3. "WAITEN,GPT Wait Mode Enable" "0: GPT is disabled in Wait mode,1: GPT is enabled in Wait mode"
|
|
bitfld.long 0x00 2. "DBGEN,GPT Debug Mode Enable" "0: GPT is disabled in Debug mode,1: GPT is enabled in Debug mode"
|
|
newline
|
|
bitfld.long 0x00 1. "ENMOD,GPT Enable Mode" "0: The Main Counter and Prescaler Counter..,1: The Main Counter and Prescaler Counter values.."
|
|
bitfld.long 0x00 0. "EN,GPT Enable" "0: GPT is disabled,1: GPT is enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PR,GPT Prescaler Register"
|
|
bitfld.long 0x00 12.--15. "PRESCALER24M,Prescaler divide value for the 24 MHz crystal clock" "0: Divide by 1,1: Divide by 2,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Divide by 16"
|
|
hexmask.long.word 0x00 0.--11. 1. "PRESCALER,Prescaler divide value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR,GPT Status Register"
|
|
eventfld.long 0x00 5. "ROV,Rollover Flag" "0: Rollover has not occurred,1: Rollover has occurred"
|
|
eventfld.long 0x00 4. "IF2,Input Capture Flag for Channel 2" "0: Capture event has not occurred,1: Capture event has occurred"
|
|
newline
|
|
eventfld.long 0x00 3. "IF1,Input Capture Flag for Channel 1" "0: Capture event has not occurred,1: Capture event has occurred"
|
|
eventfld.long 0x00 2. "OF3,Output Compare Flag for Channel 3" "0: Compare event has not occurred,1: Compare event has occurred"
|
|
newline
|
|
eventfld.long 0x00 1. "OF2,Output Compare Flag for Channel 2" "0: Compare event has not occurred,1: Compare event has occurred"
|
|
eventfld.long 0x00 0. "OF1,Output Compare Flag for Channel 1" "0: Compare event has not occurred,1: Compare event has occurred"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IR,GPT Interrupt Register"
|
|
bitfld.long 0x00 5. "ROVIE,Rollover Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 4. "IF2IE,Input Capture for Channel 2 Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. "IF1IE,Input Capture for Channel 1 Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 2. "OF3IE,Output Compare for Channel 3 Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "OF2IE,Output Compare for Channel 2 Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 0. "OF1IE,Output Compare for Channel 1 Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "OCR$1,GPT Output Compare Register"
|
|
hexmask.long 0x00 0.--31. 1. "COMP,Compare Value"
|
|
repeat.end
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
rgroup.long ($2+0x1C)++0x03
|
|
line.long 0x00 "ICR$1,GPT Input Capture Register"
|
|
hexmask.long 0x00 0.--31. 1. "CAPT,Capture Value"
|
|
repeat.end
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CNT,GPT Counter Register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Counter Value"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "HSIO_MISC_REGS (HSIO CRR module for MISC)"
|
|
base ad:0x5F160000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MISC_Ctrl0,no description available"
|
|
bitfld.long 0x00 28. "CLKREQN_IN_OVERRIDE_1,no description available" "0,1"
|
|
bitfld.long 0x00 26. "CLKREQN_IN_1,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "CLKREQN_OUT_OVERRIDE_1,no description available" "0,1"
|
|
bitfld.long 0x00 22. "CLKREQN_OUT_1,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "FAST_INIT,no description available" "0,1"
|
|
bitfld.long 0x00 3.--4. "IOB_A_0_M1M0,no description available" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2. "IOB_A_0_TXOE,no description available" "0,1"
|
|
bitfld.long 0x00 1. "IOB_TXENA,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "IOB_RXENA,no description available" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MISC_Stts0,no description available"
|
|
tree.end
|
|
tree "HSIO_PCIEX1_REGS (HSIO CRR module for PCIe)"
|
|
base ad:0x5F140000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCIex1_Ctrl0,no description available"
|
|
bitfld.long 0x00 24.--27. "DEVICE_TYPE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PS_REVISION_ID,no description available"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "PS_DEVICE_ID,no description available"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PCIex1_Ctrl1,no description available"
|
|
bitfld.long 0x00 14. "CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN,no description available" "0,1"
|
|
bitfld.long 0x00 11. "PS_SAMPLING_VALID,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "POR_SAMPLING_VALID,no description available" "0,1"
|
|
bitfld.long 0x00 6.--9. "PS_CFG_PCIE_MAX_LINK_SPEED,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "PS_CFG_PCIE_MAX_LINK_WIDTH,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCIex1_Ctrl2,no description available"
|
|
bitfld.long 0x00 26. "GPR_CRS_CLEAR,no description available" "0,1"
|
|
bitfld.long 0x00 23. "POWER_UP_RST_N,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "PERST_N,no description available" "0,1"
|
|
bitfld.long 0x00 21. "BUTTON_RST_N,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17.--19. "DIAG_CTRL_BUS,no description available" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--16. "DIAG_STATUS_BUS_SELECT,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 11. "APP_XFER_PENDING,no description available" "0,1"
|
|
bitfld.long 0x00 10. "APP_CLK_PM_EN,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "APPS_PM_XMT_TURNOFF,no description available" "0,1"
|
|
bitfld.long 0x00 8. "APPS_PM_XMT_PME,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "APP_REQ_EXIT_L1,no description available" "0,1"
|
|
bitfld.long 0x00 6. "APP_REQ_ENTR_L1,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "APP_READY_ENTR_L23,no description available" "0,1"
|
|
bitfld.long 0x00 4. "APP_LTSSM_ENABLE,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "APP_INIT_RST,no description available" "0,1"
|
|
bitfld.long 0x00 2. "APP_CLK_REQ_N,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SYS_INT,no description available" "0,1,2,3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PCIex1_Stts0,no description available"
|
|
bitfld.long 0x00 22. "CPL_CRS_RCVD,no description available" "0,1"
|
|
bitfld.long 0x00 19. "PM_REQ_CORE_RST,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "DBI_XFER_PENDING,no description available" "0,1"
|
|
bitfld.long 0x00 17. "RADM_XFER_PENDING,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "EDMA_XFER_PENDING,no description available" "0,1"
|
|
bitfld.long 0x00 15. "BRDG_SLV_XFER_PENDING,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "PM_LINKST_L2_EXIT,no description available" "0,1"
|
|
bitfld.long 0x00 13. "PM_LINKST_IN_L2,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "PM_LINKST_IN_L1,no description available" "0,1"
|
|
bitfld.long 0x00 11. "PM_LINKST_IN_L1SUB,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "PM_LINKST_IN_L0S,no description available" "0,1"
|
|
bitfld.long 0x00 7.--9. "PM_DSTATE,no description available" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6. "CFG_L1SUB_EN,no description available" "0,1"
|
|
bitfld.long 0x00 0.--5. "SMLH_LTSSM_STATE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PCIex1_Stts1,no description available"
|
|
hexmask.long.word 0x00 0.--15. 1. "CXPL_DEBUG_INFO_EI,no description available"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PCIex1_Stts2,no description available"
|
|
hexmask.long 0x00 0.--31. 1. "DIAG_STATUS_BUS_MUX,no description available"
|
|
tree.end
|
|
tree "HSIO_PHYX1_REGS (HSIO CRR module for PHY)"
|
|
base ad:0x5F120000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PHYx1_Ctrl0,no description available"
|
|
bitfld.long 0x00 25. "PIPE_RSTN_OVERRIDE_0,no description available" "0,1"
|
|
bitfld.long 0x00 24. "PIPE_RSTN_0,no description available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "EI4_CHANGE_REQ_0,no description available" "0,1"
|
|
bitfld.long 0x00 17.--20. "PHY_MODE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10. "AIDDQ_0,no description available" "0,1"
|
|
bitfld.long 0x00 0. "APB_RSTN,no description available" "0,1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PHYx1_Stts0,no description available"
|
|
bitfld.long 0x00 18. "EPCS_READY,no description available" "0,1"
|
|
bitfld.long 0x00 16. "EI4_CHANGE_ACK,no description available" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEST_OUT,TEST_OUT[7:0]"
|
|
tree.end
|
|
tree "INT_MUX (INTMUX)"
|
|
tree "CM4__INTMUX"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x41400000
|
|
else
|
|
base ad:0x37400000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CH0_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CH0_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CH0_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CH1_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH1_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "CH1_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH2_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "CH2_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH2_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "CH2_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CH3_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CH3_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CH3_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "CH3_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CH4_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CH4_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CH4_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "CH4_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CH5_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "CH5_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CH5_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "CH5_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CH6_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "CH6_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CH6_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "CH6_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CH7_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "CH7_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "CH7_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "CH7_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
tree.end
|
|
tree "SCU__INTMUX"
|
|
base ad:0x33400000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CH0_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CH0_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CH0_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CH1_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH1_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "CH1_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH2_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "CH2_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH2_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "CH2_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CH3_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CH3_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CH3_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "CH3_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CH4_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CH4_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CH4_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "CH4_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CH5_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "CH5_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CH5_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "CH5_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CH6_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "CH6_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CH6_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "CH6_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CH7_CSR,Channel n Control Status Register"
|
|
rbitfld.long 0x00 31. "IRQP,Channel Interrupt Request Pending" "0: No interrupt is pending,1: The interrupt output of this channel is pending"
|
|
rbitfld.long 0x00 8.--11. "CHIN,Channel Instance Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "IRQN,Channel Input Number" "0: 32 interrupt inputs,?..."
|
|
bitfld.long 0x00 1. "AND,Logic AND" "0: Logic OR all enabled interrupt inputs,1: Logic AND all enabled interrupt inputs"
|
|
newline
|
|
bitfld.long 0x00 0. "RST,Software Reset" "0: No operation,1: Perform a software reset on this channel"
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "CH7_VEC,Channel n Vector Number Register"
|
|
hexmask.long.word 0x00 2.--13. 1. "VECN,Vector Number"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "CH7_IER_31_0,Channel n Interrupt Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTE,Interrupt Enable"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "CH7_IPR_31_0,Channel n Interrupt Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "INTP,Interrupt Pending"
|
|
tree.end
|
|
tree.end
|
|
tree "IOMUXD"
|
|
base ad:0x33F80000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCIE_CTRL0_PERST_B,PCIE_CTRL0_PERST_B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: HSIO_PCIE0_PERST_B,?,?,?,4: LSIO_GPIO4_IO00,5: LSIO_GPIO7_IO00,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCIE_CTRL0_CLKREQ_B,PCIE_CTRL0_CLKREQ_B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: HSIO_PCIE0_CLKREQ_B,?,?,?,4: LSIO_GPIO4_IO01,5: LSIO_GPIO7_IO01,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PCIE_CTRL0_WAKE_B,PCIE_CTRL0_WAKE_B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: HSIO_PCIE0_WAKE_B,?,?,?,4: LSIO_GPIO4_IO02,5: LSIO_GPIO7_IO02,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP,IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "iomuxd_group_0_0,na"
|
|
bitfld.long 0x00 2. "PCIE_CTRL0_WAKE_B,wakeup from PCIE_CTRL0_WAKE_B" "0,1"
|
|
bitfld.long 0x00 1. "PCIE_CTRL0_CLKREQ_B,wakeup from PCIE_CTRL0_CLKREQ_B" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "PCIE_CTRL0_PERST_B,wakeup from PCIE_CTRL0_PERST_B" "0,1"
|
|
group.long 0x20000++0x03
|
|
line.long 0x00 "USB_SS3_TC0,USB_SS3_TC0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_I2C1_SCL,1: CONN_USB_OTG1_PWR,2: CONN_USB_OTG2_PWR,?,4: LSIO_GPIO4_IO03,5: LSIO_GPIO7_IO03,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DSE,Drive" "0: drive 2mA,1: drive 4mA,2: drive 8mA,3: drive 12mA"
|
|
group.long 0x20040++0x03
|
|
line.long 0x00 "USB_SS3_TC1,USB_SS3_TC1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_I2C1_SCL,1: CONN_USB_OTG2_PWR,?,?,4: LSIO_GPIO4_IO04,5: LSIO_GPIO7_IO04,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DSE,Drive" "0: drive 2mA,1: drive 4mA,2: drive 8mA,3: drive 12mA"
|
|
group.long 0x20080++0x03
|
|
line.long 0x00 "USB_SS3_TC2,USB_SS3_TC2"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_I2C1_SDA,1: CONN_USB_OTG1_OC,2: CONN_USB_OTG2_OC,?,4: LSIO_GPIO4_IO05,5: LSIO_GPIO7_IO05,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DSE,Drive" "0: drive 2mA,1: drive 4mA,2: drive 8mA,3: drive 12mA"
|
|
group.long 0x200C0++0x03
|
|
line.long 0x00 "USB_SS3_TC3,USB_SS3_TC3"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_I2C1_SDA,1: CONN_USB_OTG2_OC,?,?,4: LSIO_GPIO4_IO06,5: LSIO_GPIO7_IO06,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DSE,Drive" "0: drive 2mA,1: drive 4mA,2: drive 8mA,3: drive 12mA"
|
|
group.long 0x20100++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_3V3_USB3IO,IOMUXD_COMP_CTL_GPIO_3V3_USB3IO"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
group.long 0x20140++0x03
|
|
line.long 0x00 "EMMC0_CLK,EMMC0_CLK"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_EMMC0_CLK,1: CONN_NAND_READY_B,?,?,4: LSIO_GPIO4_IO07,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x20180++0x03
|
|
line.long 0x00 "EMMC0_CMD,EMMC0_CMD"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_EMMC0_CMD,1: CONN_NAND_DQS,?,?,4: LSIO_GPIO4_IO08,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x201C0++0x03
|
|
line.long 0x00 "EMMC0_DATA0,EMMC0_DATA0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_EMMC0_DATA0,1: CONN_NAND_DATA00,?,?,4: LSIO_GPIO4_IO09,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x20200++0x03
|
|
line.long 0x00 "EMMC0_DATA1,EMMC0_DATA1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_EMMC0_DATA1,1: CONN_NAND_DATA01,?,?,4: LSIO_GPIO4_IO10,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x20240++0x03
|
|
line.long 0x00 "EMMC0_DATA2,EMMC0_DATA2"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_EMMC0_DATA2,1: CONN_NAND_DATA02,?,?,4: LSIO_GPIO4_IO11,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x20280++0x03
|
|
line.long 0x00 "EMMC0_DATA3,EMMC0_DATA3"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_EMMC0_DATA3,1: CONN_NAND_DATA03,?,?,4: LSIO_GPIO4_IO12,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x202C0++0x03
|
|
line.long 0x00 "EMMC0_DATA4,EMMC0_DATA4"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_EMMC0_DATA4,1: CONN_NAND_DATA04,?,?,4: LSIO_GPIO4_IO13,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x20300++0x03
|
|
line.long 0x00 "EMMC0_DATA5,EMMC0_DATA5"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_EMMC0_DATA5,1: CONN_NAND_DATA05,?,?,4: LSIO_GPIO4_IO14,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x20340++0x03
|
|
line.long 0x00 "EMMC0_DATA6,EMMC0_DATA6"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_EMMC0_DATA6,1: CONN_NAND_DATA06,?,?,4: LSIO_GPIO4_IO15,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x20380++0x03
|
|
line.long 0x00 "EMMC0_DATA7,EMMC0_DATA7"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_EMMC0_DATA7,1: CONN_NAND_DATA07,?,?,4: LSIO_GPIO4_IO16,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x203C0++0x03
|
|
line.long 0x00 "EMMC0_STROBE,EMMC0_STROBE"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_EMMC0_STROBE,1: CONN_NAND_CLE,?,?,4: LSIO_GPIO4_IO17,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
rgroup.long 0x20400++0x03
|
|
line.long 0x00 "iomuxd_group_1_0,na"
|
|
bitfld.long 0x00 15. "EMMC0_STROBE,wakeup from EMMC0_STROBE" "0,1"
|
|
bitfld.long 0x00 14. "EMMC0_DATA7,wakeup from EMMC0_DATA7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "EMMC0_DATA6,wakeup from EMMC0_DATA6" "0,1"
|
|
bitfld.long 0x00 12. "EMMC0_DATA5,wakeup from EMMC0_DATA5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "EMMC0_DATA4,wakeup from EMMC0_DATA4" "0,1"
|
|
bitfld.long 0x00 10. "EMMC0_DATA3,wakeup from EMMC0_DATA3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "EMMC0_DATA2,wakeup from EMMC0_DATA2" "0,1"
|
|
bitfld.long 0x00 8. "EMMC0_DATA1,wakeup from EMMC0_DATA1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "EMMC0_DATA0,wakeup from EMMC0_DATA0" "0,1"
|
|
bitfld.long 0x00 6. "EMMC0_CMD,wakeup from EMMC0_CMD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "EMMC0_CLK,wakeup from EMMC0_CLK" "0,1"
|
|
bitfld.long 0x00 3. "USB_SS3_TC3,wakeup from USB_SS3_TC3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "USB_SS3_TC2,wakeup from USB_SS3_TC2" "0,1"
|
|
bitfld.long 0x00 1. "USB_SS3_TC1,wakeup from USB_SS3_TC1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "USB_SS3_TC0,wakeup from USB_SS3_TC0" "0,1"
|
|
group.long 0x21000++0x03
|
|
line.long 0x00 "EMMC0_RESET_B,EMMC0_RESET_B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_EMMC0_RESET_B,1: CONN_NAND_WP_B,?,?,4: LSIO_GPIO4_IO18,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x21040++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0,IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
group.long 0x21080++0x03
|
|
line.long 0x00 "USDHC1_RESET_B,USDHC1_RESET_B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_USDHC1_RESET_B,1: CONN_NAND_RE_N,2: ADMA_SPI2_SCK,3: CONN_NAND_WE_B,4: LSIO_GPIO4_IO19,5: LSIO_GPIO7_IO08,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x210C0++0x03
|
|
line.long 0x00 "USDHC1_VSELECT,USDHC1_VSELECT"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_USDHC1_VSELECT,1: CONN_NAND_RE_P,2: ADMA_SPI2_SDO,3: CONN_NAND_RE_B,4: LSIO_GPIO4_IO20,5: LSIO_GPIO7_IO09,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x21100++0x03
|
|
line.long 0x00 "IOMUXD_CTL_NAND_RE_P_N,IOMUXD_CTL_NAND_RE_P_N"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "P_N_SELECT,P_N_SELECT" "0: no description available,1: no description available"
|
|
group.long 0x21140++0x03
|
|
line.long 0x00 "USDHC1_WP,USDHC1_WP"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_USDHC1_WP,1: CONN_NAND_DQS_N,2: ADMA_SPI2_SDI,3: CONN_NAND_ALE,4: LSIO_GPIO4_IO21,5: LSIO_GPIO7_IO10,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x21180++0x03
|
|
line.long 0x00 "USDHC1_CD_B,USDHC1_CD_B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_USDHC1_CD_B,1: CONN_NAND_DQS_P,2: ADMA_SPI2_CS0,3: CONN_NAND_DQS,4: LSIO_GPIO4_IO22,5: LSIO_GPIO7_IO11,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x211C0++0x03
|
|
line.long 0x00 "IOMUXD_CTL_NAND_DQS_P_N,IOMUXD_CTL_NAND_DQS_P_N"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "P_N_SELECT,P_N_SELECT" "0: no description available,1: no description available"
|
|
group.long 0x21200++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP,IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
group.long 0x21240++0x03
|
|
line.long 0x00 "ENET0_RGMII_TXC,ENET0_RGMII_TXC"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_RGMII_TXC,1: CONN_ENET0_RCLK50M_OUT,2: CONN_ENET0_RCLK50M_IN,3: CONN_NAND_CE1_B,4: LSIO_GPIO4_IO29,5: CONN_USDHC2_CLK,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x21280++0x03
|
|
line.long 0x00 "ENET0_RGMII_TX_CTL,ENET0_RGMII_TX_CTL"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_RGMII_TX_CTL,?,?,3: CONN_USDHC1_RESET_B,4: LSIO_GPIO4_IO30,5: CONN_USDHC2_CMD,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x212C0++0x03
|
|
line.long 0x00 "ENET0_RGMII_TXD0,ENET0_RGMII_TXD0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_RGMII_TXD0,?,?,3: CONN_USDHC1_VSELECT,4: LSIO_GPIO4_IO31,5: CONN_USDHC2_DATA0,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x21300++0x03
|
|
line.long 0x00 "ENET0_RGMII_TXD1,ENET0_RGMII_TXD1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_RGMII_TXD1,?,?,3: CONN_USDHC1_WP,4: LSIO_GPIO5_IO00,5: CONN_USDHC2_DATA1,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x21340++0x03
|
|
line.long 0x00 "ENET0_RGMII_TXD2,ENET0_RGMII_TXD2"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_RGMII_TXD2,?,2: CONN_NAND_CE0_B,3: CONN_USDHC1_CD_B,4: LSIO_GPIO5_IO01,5: CONN_USDHC2_DATA2,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x21380++0x03
|
|
line.long 0x00 "ENET0_RGMII_TXD3,ENET0_RGMII_TXD3"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_RGMII_TXD3,?,2: CONN_NAND_RE_B,?,4: LSIO_GPIO5_IO02,5: CONN_USDHC2_DATA3,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x213C0++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0,IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
rgroup.long 0x21400++0x03
|
|
line.long 0x00 "iomuxd_group_1_1,na"
|
|
bitfld.long 0x00 14. "ENET0_RGMII_TXD3,wakeup from ENET0_RGMII_TXD3" "0,1"
|
|
bitfld.long 0x00 13. "ENET0_RGMII_TXD2,wakeup from ENET0_RGMII_TXD2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "ENET0_RGMII_TXD1,wakeup from ENET0_RGMII_TXD1" "0,1"
|
|
bitfld.long 0x00 11. "ENET0_RGMII_TXD0,wakeup from ENET0_RGMII_TXD0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "ENET0_RGMII_TX_CTL,wakeup from ENET0_RGMII_TX_CTL" "0,1"
|
|
bitfld.long 0x00 9. "ENET0_RGMII_TXC,wakeup from ENET0_RGMII_TXC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "USDHC1_CD_B,wakeup from USDHC1_CD_B" "0,1"
|
|
bitfld.long 0x00 5. "USDHC1_WP,wakeup from USDHC1_WP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "USDHC1_VSELECT,wakeup from USDHC1_VSELECT" "0,1"
|
|
bitfld.long 0x00 2. "USDHC1_RESET_B,wakeup from USDHC1_RESET_B" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "EMMC0_RESET_B,wakeup from EMMC0_RESET_B" "0,1"
|
|
group.long 0x22000++0x03
|
|
line.long 0x00 "ENET0_RGMII_RXC,ENET0_RGMII_RXC"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_RGMII_RXC,?,2: CONN_NAND_WE_B,3: CONN_USDHC1_CLK,4: LSIO_GPIO5_IO03,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x22040++0x03
|
|
line.long 0x00 "ENET0_RGMII_RX_CTL,ENET0_RGMII_RX_CTL"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_RGMII_RX_CTL,?,?,3: CONN_USDHC1_CMD,4: LSIO_GPIO5_IO04,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x22080++0x03
|
|
line.long 0x00 "ENET0_RGMII_RXD0,ENET0_RGMII_RXD0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_RGMII_RXD0,?,?,3: CONN_USDHC1_DATA0,4: LSIO_GPIO5_IO05,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x220C0++0x03
|
|
line.long 0x00 "ENET0_RGMII_RXD1,ENET0_RGMII_RXD1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_RGMII_RXD1,?,?,3: CONN_USDHC1_DATA1,4: LSIO_GPIO5_IO06,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x22100++0x03
|
|
line.long 0x00 "ENET0_RGMII_RXD2,ENET0_RGMII_RXD2"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_RGMII_RXD2,1: CONN_ENET0_RMII_RX_ER,?,3: CONN_USDHC1_DATA2,4: LSIO_GPIO5_IO07,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x22140++0x03
|
|
line.long 0x00 "ENET0_RGMII_RXD3,ENET0_RGMII_RXD3"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_RGMII_RXD3,?,2: CONN_NAND_ALE,3: CONN_USDHC1_DATA3,4: LSIO_GPIO5_IO08,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x22180++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1,IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
group.long 0x221C0++0x03
|
|
line.long 0x00 "ENET0_REFCLK_125M_25M,ENET0_REFCLK_125M_25M"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_REFCLK_125M_25M,1: CONN_ENET0_PPS,2: CONN_EQOS_PPS_IN,3: CONN_EQOS_PPS_OUT,4: LSIO_GPIO5_IO09,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x22200++0x03
|
|
line.long 0x00 "ENET0_MDIO,ENET0_MDIO"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_MDIO,1: ADMA_I2C3_SDA,2: CONN_EQOS_MDIO,?,4: LSIO_GPIO5_IO10,5: LSIO_GPIO7_IO16,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x22240++0x03
|
|
line.long 0x00 "ENET0_MDC,ENET0_MDC"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: CONN_ENET0_MDC,1: ADMA_I2C3_SCL,2: CONN_EQOS_MDC,?,4: LSIO_GPIO5_IO11,5: LSIO_GPIO7_IO17,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x22280++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT,IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
rgroup.long 0x22400++0x03
|
|
line.long 0x00 "iomuxd_group_1_2,na"
|
|
bitfld.long 0x00 9. "ENET0_MDC,wakeup from ENET0_MDC" "0,1"
|
|
bitfld.long 0x00 8. "ENET0_MDIO,wakeup from ENET0_MDIO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ENET0_REFCLK_125M_25M,wakeup from ENET0_REFCLK_125M_25M" "0,1"
|
|
bitfld.long 0x00 5. "ENET0_RGMII_RXD3,wakeup from ENET0_RGMII_RXD3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ENET0_RGMII_RXD2,wakeup from ENET0_RGMII_RXD2" "0,1"
|
|
bitfld.long 0x00 3. "ENET0_RGMII_RXD1,wakeup from ENET0_RGMII_RXD1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENET0_RGMII_RXD0,wakeup from ENET0_RGMII_RXD0" "0,1"
|
|
bitfld.long 0x00 1. "ENET0_RGMII_RX_CTL,wakeup from ENET0_RGMII_RX_CTL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENET0_RGMII_RXC,wakeup from ENET0_RGMII_RXC" "0,1"
|
|
group.long 0x23000++0x03
|
|
line.long 0x00 "ENET1_RGMII_TXC,ENET1_RGMII_TXC"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_GPIO0_IO00,1: CONN_EQOS_RCLK50M_OUT,2: ADMA_LCDIF_D00,3: CONN_EQOS_RGMII_TXC,4: CONN_EQOS_RCLK50M_IN,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x23040++0x03
|
|
line.long 0x00 "ENET1_RGMII_TXD2,ENET1_RGMII_TXD2"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_LCDIF_D01,3: CONN_EQOS_RGMII_TXD2,4: LSIO_GPIO0_IO01,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x23080++0x03
|
|
line.long 0x00 "ENET1_RGMII_TX_CTL,ENET1_RGMII_TX_CTL"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_LCDIF_D02,3: CONN_EQOS_RGMII_TX_CTL,4: LSIO_GPIO0_IO02,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x230C0++0x03
|
|
line.long 0x00 "ENET1_RGMII_TXD3,ENET1_RGMII_TXD3"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_LCDIF_D03,3: CONN_EQOS_RGMII_TXD3,4: LSIO_GPIO0_IO03,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x23100++0x03
|
|
line.long 0x00 "ENET1_RGMII_RXC,ENET1_RGMII_RXC"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_LCDIF_D04,3: CONN_EQOS_RGMII_RXC,4: LSIO_GPIO0_IO04,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x23140++0x03
|
|
line.long 0x00 "ENET1_RGMII_RXD3,ENET1_RGMII_RXD3"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_LCDIF_D05,3: CONN_EQOS_RGMII_RXD3,4: LSIO_GPIO0_IO05,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x23180++0x03
|
|
line.long 0x00 "ENET1_RGMII_RXD2,ENET1_RGMII_RXD2"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_LCDIF_D06,3: CONN_EQOS_RGMII_RXD2,4: LSIO_GPIO0_IO06,5: LSIO_GPIO6_IO00,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x231C0++0x03
|
|
line.long 0x00 "ENET1_RGMII_RXD1,ENET1_RGMII_RXD1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_LCDIF_D07,3: CONN_EQOS_RGMII_RXD1,4: LSIO_GPIO0_IO07,5: LSIO_GPIO6_IO01,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x23200++0x03
|
|
line.long 0x00 "ENET1_RGMII_TXD0,ENET1_RGMII_TXD0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_LCDIF_D08,3: CONN_EQOS_RGMII_TXD0,4: LSIO_GPIO0_IO08,5: LSIO_GPIO6_IO02,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x23240++0x03
|
|
line.long 0x00 "ENET1_RGMII_TXD1,ENET1_RGMII_TXD1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_LCDIF_D09,3: CONN_EQOS_RGMII_TXD1,4: LSIO_GPIO0_IO09,5: LSIO_GPIO6_IO03,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x23280++0x03
|
|
line.long 0x00 "ENET1_RGMII_RXD0,ENET1_RGMII_RXD0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPDIF0_RX,1: ADMA_MQS_R,2: ADMA_LCDIF_D10,3: CONN_EQOS_RGMII_RXD0,4: LSIO_GPIO0_IO10,5: LSIO_GPIO6_IO04,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x232C0++0x03
|
|
line.long 0x00 "ENET1_RGMII_RX_CTL,ENET1_RGMII_RX_CTL"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPDIF0_TX,1: ADMA_MQS_L,2: ADMA_LCDIF_D11,3: CONN_EQOS_RGMII_RX_CTL,4: LSIO_GPIO0_IO11,5: LSIO_GPIO6_IO05,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x23300++0x03
|
|
line.long 0x00 "ENET1_REFCLK_125M_25M,ENET1_REFCLK_125M_25M"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPDIF0_EXT_CLK,?,2: ADMA_LCDIF_D12,3: CONN_EQOS_REFCLK_125M_25M,4: LSIO_GPIO0_IO12,5: LSIO_GPIO6_IO06,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x23340++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB,IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
rgroup.long 0x23400++0x03
|
|
line.long 0x00 "iomuxd_group_1_3,na"
|
|
bitfld.long 0x00 12. "ENET1_REFCLK_125M_25M,wakeup from ENET1_REFCLK_125M_25M" "0,1"
|
|
bitfld.long 0x00 11. "ENET1_RGMII_RX_CTL,wakeup from ENET1_RGMII_RX_CTL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "ENET1_RGMII_RXD0,wakeup from ENET1_RGMII_RXD0" "0,1"
|
|
bitfld.long 0x00 9. "ENET1_RGMII_TXD1,wakeup from ENET1_RGMII_TXD1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "ENET1_RGMII_TXD0,wakeup from ENET1_RGMII_TXD0" "0,1"
|
|
bitfld.long 0x00 7. "ENET1_RGMII_RXD1,wakeup from ENET1_RGMII_RXD1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "ENET1_RGMII_RXD2,wakeup from ENET1_RGMII_RXD2" "0,1"
|
|
bitfld.long 0x00 5. "ENET1_RGMII_RXD3,wakeup from ENET1_RGMII_RXD3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ENET1_RGMII_RXC,wakeup from ENET1_RGMII_RXC" "0,1"
|
|
bitfld.long 0x00 3. "ENET1_RGMII_TXD3,wakeup from ENET1_RGMII_TXD3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ENET1_RGMII_TX_CTL,wakeup from ENET1_RGMII_TX_CTL" "0,1"
|
|
bitfld.long 0x00 1. "ENET1_RGMII_TXD2,wakeup from ENET1_RGMII_TXD2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ENET1_RGMII_TXC,wakeup from ENET1_RGMII_TXC" "0,1"
|
|
group.long 0x40000++0x03
|
|
line.long 0x00 "SPI3_SCK,SPI3_SCK"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPI3_SCK,?,2: ADMA_LCDIF_D13,?,4: LSIO_GPIO0_IO13,5: ADMA_LCDIF_D00,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x40040++0x03
|
|
line.long 0x00 "SPI3_SDO,SPI3_SDO"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPI3_SDO,?,2: ADMA_LCDIF_D14,?,4: LSIO_GPIO0_IO14,5: ADMA_LCDIF_D01,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x40080++0x03
|
|
line.long 0x00 "SPI3_SDI,SPI3_SDI"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPI3_SDI,?,2: ADMA_LCDIF_D15,?,4: LSIO_GPIO0_IO15,5: ADMA_LCDIF_D02,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x400C0++0x03
|
|
line.long 0x00 "SPI3_CS0,SPI3_CS0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPI3_CS0,1: ADMA_ACM_MCLK_OUT1,2: ADMA_LCDIF_HSYNC,?,4: LSIO_GPIO0_IO16,5: ADMA_LCDIF_CS,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x40100++0x03
|
|
line.long 0x00 "SPI3_CS1,SPI3_CS1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPI3_CS1,1: ADMA_I2C3_SCL,2: ADMA_LCDIF_RESET,3: ADMA_SPI2_CS0,4: ADMA_LCDIF_D16,5: ADMA_LCDIF_RD_E,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x40140++0x03
|
|
line.long 0x00 "MCLK_IN1,MCLK_IN1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_ACM_MCLK_IN1,1: ADMA_I2C3_SDA,2: ADMA_LCDIF_EN,3: ADMA_SPI2_SCK,4: ADMA_LCDIF_D17,5: ADMA_LCDIF_D03,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x40180++0x03
|
|
line.long 0x00 "MCLK_IN0,MCLK_IN0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_ACM_MCLK_IN0,?,2: ADMA_LCDIF_VSYNC,3: ADMA_SPI2_SDI,4: LSIO_GPIO0_IO19,5: ADMA_LCDIF_RS,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x401C0++0x03
|
|
line.long 0x00 "MCLK_OUT0,MCLK_OUT0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_ACM_MCLK_OUT0,?,2: ADMA_LCDIF_CLK,3: ADMA_SPI2_SDO,4: LSIO_GPIO0_IO20,5: ADMA_LCDIF_WR_RWN,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x40200++0x03
|
|
line.long 0x00 "UART1_TX,UART1_TX"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_UART1_TX,1: LSIO_PWM0_OUT,2: LSIO_GPT0_CAPTURE,?,4: LSIO_GPIO0_IO21,5: ADMA_LCDIF_D04,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x40240++0x03
|
|
line.long 0x00 "UART1_RX,UART1_RX"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_UART1_RX,1: LSIO_PWM1_OUT,2: LSIO_GPT0_COMPARE,3: LSIO_GPT1_CLK,4: LSIO_GPIO0_IO22,5: ADMA_LCDIF_D05,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x40280++0x03
|
|
line.long 0x00 "UART1_RTS_B,UART1_RTS_B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_UART1_RTS_B,1: LSIO_PWM2_OUT,2: ADMA_LCDIF_D16,3: LSIO_GPT1_CAPTURE,4: LSIO_GPT0_CLK,5: ADMA_LCDIF_D06,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x402C0++0x03
|
|
line.long 0x00 "UART1_CTS_B,UART1_CTS_B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_UART1_CTS_B,1: LSIO_PWM3_OUT,2: ADMA_LCDIF_D17,3: LSIO_GPT1_COMPARE,4: LSIO_GPIO0_IO24,5: ADMA_LCDIF_D07,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x40300++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK,IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
group.long 0x40340++0x03
|
|
line.long 0x00 "SPI0_SCK,SPI0_SCK"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPI0_SCK,1: ADMA_SAI0_TXC,2: M40_I2C0_SCL,3: M40_GPIO0_IO00,4: LSIO_GPIO1_IO04,5: ADMA_LCDIF_D08,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x40380++0x03
|
|
line.long 0x00 "SPI0_SDI,SPI0_SDI"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPI0_SDI,1: ADMA_SAI0_TXD,2: M40_TPM0_CH0,3: M40_GPIO0_IO02,4: LSIO_GPIO1_IO05,5: ADMA_LCDIF_D09,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x403C0++0x03
|
|
line.long 0x00 "SPI0_SDO,SPI0_SDO"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPI0_SDO,1: ADMA_SAI0_TXFS,2: M40_I2C0_SDA,3: M40_GPIO0_IO01,4: LSIO_GPIO1_IO06,5: ADMA_LCDIF_D10,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
rgroup.long 0x40400++0x03
|
|
line.long 0x00 "iomuxd_group_2_0,na"
|
|
bitfld.long 0x00 15. "SPI0_SDO,wakeup from SPI0_SDO" "0,1"
|
|
bitfld.long 0x00 14. "SPI0_SDI,wakeup from SPI0_SDI" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "SPI0_SCK,wakeup from SPI0_SCK" "0,1"
|
|
bitfld.long 0x00 11. "UART1_CTS_B,wakeup from UART1_CTS_B" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "UART1_RTS_B,wakeup from UART1_RTS_B" "0,1"
|
|
bitfld.long 0x00 9. "UART1_RX,wakeup from UART1_RX" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "UART1_TX,wakeup from UART1_TX" "0,1"
|
|
bitfld.long 0x00 7. "MCLK_OUT0,wakeup from MCLK_OUT0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "MCLK_IN0,wakeup from MCLK_IN0" "0,1"
|
|
bitfld.long 0x00 5. "MCLK_IN1,wakeup from MCLK_IN1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SPI3_CS1,wakeup from SPI3_CS1" "0,1"
|
|
bitfld.long 0x00 3. "SPI3_CS0,wakeup from SPI3_CS0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SPI3_SDI,wakeup from SPI3_SDI" "0,1"
|
|
bitfld.long 0x00 1. "SPI3_SDO,wakeup from SPI3_SDO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SPI3_SCK,wakeup from SPI3_SCK" "0,1"
|
|
group.long 0x41000++0x03
|
|
line.long 0x00 "SPI0_CS1,SPI0_CS1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPI0_CS1,1: ADMA_SAI0_RXC,2: ADMA_SAI1_TXD,3: ADMA_LCD_PWM0_OUT,4: LSIO_GPIO1_IO07,5: ADMA_LCDIF_D11,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x41040++0x03
|
|
line.long 0x00 "SPI0_CS0,SPI0_CS0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_SPI0_CS0,1: ADMA_SAI0_RXD,2: M40_TPM0_CH1,3: M40_GPIO0_IO03,4: LSIO_GPIO1_IO08,5: ADMA_LCDIF_D12,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x41080++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT,IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
group.long 0x410C0++0x03
|
|
line.long 0x00 "ADC_IN1,ADC_IN1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_ADC_IN1,1: M40_I2C0_SDA,2: M40_GPIO0_IO01,3: ADMA_I2C0_SDA,4: LSIO_GPIO1_IO09,5: ADMA_LCDIF_D13,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x41100++0x03
|
|
line.long 0x00 "ADC_IN0,ADC_IN0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_ADC_IN0,1: M40_I2C0_SCL,2: M40_GPIO0_IO00,3: ADMA_I2C0_SCL,4: LSIO_GPIO1_IO10,5: ADMA_LCDIF_D14,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x41140++0x03
|
|
line.long 0x00 "ADC_IN3,ADC_IN3"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_ADC_IN3,1: M40_UART0_TX,2: M40_GPIO0_IO03,3: ADMA_ACM_MCLK_OUT0,4: LSIO_GPIO1_IO11,5: ADMA_LCDIF_D15,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x41180++0x03
|
|
line.long 0x00 "ADC_IN2,ADC_IN2"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_ADC_IN2,1: M40_UART0_RX,2: M40_GPIO0_IO02,3: ADMA_ACM_MCLK_IN0,4: LSIO_GPIO1_IO12,5: ADMA_LCDIF_D16,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x411C0++0x03
|
|
line.long 0x00 "ADC_IN5,ADC_IN5"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_ADC_IN5,1: M40_TPM0_CH1,2: M40_GPIO0_IO05,3: ADMA_LCDIF_LCDBUSY,4: LSIO_GPIO1_IO13,5: ADMA_LCDIF_D17,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x41200++0x03
|
|
line.long 0x00 "ADC_IN4,ADC_IN4"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_ADC_IN4,1: M40_TPM0_CH0,2: M40_GPIO0_IO04,3: ADMA_LCDIF_LCDRESET,4: LSIO_GPIO1_IO14,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x41240++0x03
|
|
line.long 0x00 "FLEXCAN0_RX,FLEXCAN0_RX"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_FLEXCAN0_RX,1: ADMA_SAI2_RXC,2: ADMA_UART0_RTS_B,3: ADMA_SAI1_TXC,4: LSIO_GPIO1_IO15,5: LSIO_GPIO6_IO08,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x41280++0x03
|
|
line.long 0x00 "FLEXCAN0_TX,FLEXCAN0_TX"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_FLEXCAN0_TX,1: ADMA_SAI2_RXD,2: ADMA_UART0_CTS_B,3: ADMA_SAI1_TXFS,4: LSIO_GPIO1_IO16,5: LSIO_GPIO6_IO09,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x412C0++0x03
|
|
line.long 0x00 "FLEXCAN1_RX,FLEXCAN1_RX"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_FLEXCAN1_RX,1: ADMA_SAI2_RXFS,2: ADMA_FTM_CH2,3: ADMA_SAI1_TXD,4: LSIO_GPIO1_IO17,5: LSIO_GPIO6_IO10,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x41300++0x03
|
|
line.long 0x00 "FLEXCAN1_TX,FLEXCAN1_TX"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_FLEXCAN1_TX,1: ADMA_SAI3_RXC,2: ADMA_DMA0_REQ_IN0,3: ADMA_SAI1_RXD,4: LSIO_GPIO1_IO18,5: LSIO_GPIO6_IO11,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x41340++0x03
|
|
line.long 0x00 "FLEXCAN2_RX,FLEXCAN2_RX"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_FLEXCAN2_RX,1: ADMA_SAI3_RXD,2: ADMA_UART3_RX,3: ADMA_SAI1_RXFS,4: LSIO_GPIO1_IO19,5: LSIO_GPIO6_IO12,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x41380++0x03
|
|
line.long 0x00 "FLEXCAN2_TX,FLEXCAN2_TX"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_FLEXCAN2_TX,1: ADMA_SAI3_RXFS,2: ADMA_UART3_TX,3: ADMA_SAI1_RXC,4: LSIO_GPIO1_IO20,5: LSIO_GPIO6_IO13,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x413C0++0x03
|
|
line.long 0x00 "UART0_RX,UART0_RX"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_UART0_RX,1: ADMA_MQS_R,2: ADMA_FLEXCAN0_RX,3: SCU_UART0_RX,4: LSIO_GPIO1_IO21,5: LSIO_GPIO6_IO14,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
rgroup.long 0x41400++0x03
|
|
line.long 0x00 "iomuxd_group_2_1,na"
|
|
bitfld.long 0x00 15. "UART0_RX,wakeup from UART0_RX" "0,1"
|
|
bitfld.long 0x00 14. "FLEXCAN2_TX,wakeup from FLEXCAN2_TX" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLEXCAN2_RX,wakeup from FLEXCAN2_RX" "0,1"
|
|
bitfld.long 0x00 12. "FLEXCAN1_TX,wakeup from FLEXCAN1_TX" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLEXCAN1_RX,wakeup from FLEXCAN1_RX" "0,1"
|
|
bitfld.long 0x00 10. "FLEXCAN0_TX,wakeup from FLEXCAN0_TX" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLEXCAN0_RX,wakeup from FLEXCAN0_RX" "0,1"
|
|
bitfld.long 0x00 8. "ADC_IN4,wakeup from ADC_IN4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "ADC_IN5,wakeup from ADC_IN5" "0,1"
|
|
bitfld.long 0x00 6. "ADC_IN2,wakeup from ADC_IN2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "ADC_IN3,wakeup from ADC_IN3" "0,1"
|
|
bitfld.long 0x00 4. "ADC_IN0,wakeup from ADC_IN0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ADC_IN1,wakeup from ADC_IN1" "0,1"
|
|
bitfld.long 0x00 1. "SPI0_CS0,wakeup from SPI0_CS0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "SPI0_CS1,wakeup from SPI0_CS1" "0,1"
|
|
group.long 0x42000++0x03
|
|
line.long 0x00 "UART0_TX,UART0_TX"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_UART0_TX,1: ADMA_MQS_L,2: ADMA_FLEXCAN0_TX,3: SCU_UART0_TX,4: LSIO_GPIO1_IO22,5: LSIO_GPIO6_IO15,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x42040++0x03
|
|
line.long 0x00 "UART2_TX,UART2_TX"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_UART2_TX,1: ADMA_FTM_CH1,2: ADMA_FLEXCAN1_TX,?,4: LSIO_GPIO1_IO23,5: LSIO_GPIO6_IO16,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x42080++0x03
|
|
line.long 0x00 "UART2_RX,UART2_RX"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: ADMA_UART2_RX,1: ADMA_FTM_CH0,2: ADMA_FLEXCAN1_RX,?,4: LSIO_GPIO1_IO24,5: LSIO_GPIO6_IO17,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x420C0++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH,IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
group.long 0x42100++0x03
|
|
line.long 0x00 "JTAG_TRST_B,JTAG_TRST_B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: SCU_JTAG_TRST_B,1: SCU_WDOG0_WDOG_OUT,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x42140++0x03
|
|
line.long 0x00 "PMIC_I2C_SCL,PMIC_I2C_SCL"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: SCU_PMIC_I2C_SCL,1: SCU_GPIO0_IOXX_PMIC_A35_ON,?,?,4: LSIO_GPIO2_IO01,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x42180++0x03
|
|
line.long 0x00 "PMIC_I2C_SDA,PMIC_I2C_SDA"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: SCU_PMIC_I2C_SDA,1: SCU_GPIO0_IOXX_PMIC_GPU_ON,?,?,4: LSIO_GPIO2_IO02,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x421C0++0x03
|
|
line.long 0x00 "PMIC_INT_B,PMIC_INT_B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: SCU_DSC_PMIC_INT_B,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x42200++0x03
|
|
line.long 0x00 "SCU_GPIO0_00,SCU_GPIO0_00"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: SCU_GPIO0_IO00,1: SCU_UART0_RX,2: M40_UART0_RX,3: ADMA_UART3_RX,4: LSIO_GPIO2_IO03,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x42240++0x03
|
|
line.long 0x00 "SCU_GPIO0_01,SCU_GPIO0_01"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: SCU_GPIO0_IO01,1: SCU_UART0_TX,2: M40_UART0_TX,3: ADMA_UART3_TX,4: SCU_WDOG0_WDOG_OUT,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x42280++0x03
|
|
line.long 0x00 "SCU_PMIC_STANDBY,SCU_PMIC_STANDBY"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: SCU_DSC_PMIC_STANDBY,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x422C0++0x03
|
|
line.long 0x00 "SCU_BOOT_MODE1,SCU_BOOT_MODE1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: SCU_DSC_BOOT_MODE1,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x42300++0x03
|
|
line.long 0x00 "SCU_BOOT_MODE0,SCU_BOOT_MODE0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: SCU_DSC_BOOT_MODE0,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
group.long 0x42340++0x03
|
|
line.long 0x00 "SCU_BOOT_MODE2,SCU_BOOT_MODE2"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: SCU_DSC_BOOT_MODE2,1: SCU_DSC_RTC_CLOCK_OUTPUT_32K,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: bus-keeper,1: pull-up,2: pull-down,3: no pull"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "DSE,Drive" "0: drive 1mA,1: drive 2mA,2: drive 4mA,3: drive 6mA,4: drive 8mA,5: drive 10mA,6: drive 12mA,7: High_Speed"
|
|
rgroup.long 0x42400++0x03
|
|
line.long 0x00 "iomuxd_group_2_2,na"
|
|
bitfld.long 0x00 13. "SCU_BOOT_MODE2,wakeup from SCU_BOOT_MODE2" "0,1"
|
|
bitfld.long 0x00 12. "SCU_BOOT_MODE0,wakeup from SCU_BOOT_MODE0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "SCU_BOOT_MODE1,wakeup from SCU_BOOT_MODE1" "0,1"
|
|
bitfld.long 0x00 10. "SCU_PMIC_STANDBY,wakeup from SCU_PMIC_STANDBY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SCU_GPIO0_01,wakeup from SCU_GPIO0_01" "0,1"
|
|
bitfld.long 0x00 8. "SCU_GPIO0_00,wakeup from SCU_GPIO0_00" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "PMIC_INT_B,wakeup from PMIC_INT_B" "0,1"
|
|
bitfld.long 0x00 6. "PMIC_I2C_SDA,wakeup from PMIC_I2C_SDA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PMIC_I2C_SCL,wakeup from PMIC_I2C_SCL" "0,1"
|
|
bitfld.long 0x00 4. "JTAG_TRST_B,wakeup from JTAG_TRST_B" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UART2_RX,wakeup from UART2_RX" "0,1"
|
|
bitfld.long 0x00 1. "UART2_TX,wakeup from UART2_TX" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UART0_TX,wakeup from UART0_TX" "0,1"
|
|
group.long 0x60000++0x03
|
|
line.long 0x00 "SNVS_TAMPER_DIG_OUT1,SNVS_TAMPER_DIG_OUT1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,?,?,4: LSIO_GPIO2_IO05_IN,5: LSIO_GPIO6_IO19_IN,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x60040++0x03
|
|
line.long 0x00 "SNVS_TAMPER_DIG_OUT2,SNVS_TAMPER_DIG_OUT2"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,?,?,4: LSIO_GPIO2_IO06_IN,5: LSIO_GPIO6_IO20_IN,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x60080++0x03
|
|
line.long 0x00 "SNVS_TAMPER_DIG_OUT3,SNVS_TAMPER_DIG_OUT3"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_SAI2_RXC,?,4: LSIO_GPIO2_IO07_IN,5: LSIO_GPIO6_IO21_IN,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x600C0++0x03
|
|
line.long 0x00 "SNVS_TAMPER_DIG_OUT4,SNVS_TAMPER_DIG_OUT4"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_SAI2_RXD,?,4: LSIO_GPIO2_IO08_IN,5: LSIO_GPIO6_IO22_IN,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x60100++0x03
|
|
line.long 0x00 "SNVS_TAMPER_DIG_IN0,SNVS_TAMPER_DIG_IN0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_SAI2_RXFS,?,4: LSIO_GPIO2_IO09_IN,5: LSIO_GPIO6_IO23_IN,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x60140++0x03
|
|
line.long 0x00 "SNVS_TAMPER_DIG_IN1,SNVS_TAMPER_DIG_IN1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_SAI3_RXC,?,4: LSIO_GPIO2_IO10_IN,5: LSIO_GPIO6_IO24_IN,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x60180++0x03
|
|
line.long 0x00 "SNVS_TAMPER_DIG_IN2,SNVS_TAMPER_DIG_IN2"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_SAI3_RXD,?,4: LSIO_GPIO2_IO11_IN,5: LSIO_GPIO6_IO25_IN,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x601C0++0x03
|
|
line.long 0x00 "SNVS_TAMPER_DIG_IN3,SNVS_TAMPER_DIG_IN3"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_SAI3_RXFS,?,4: LSIO_GPIO2_IO12_IN,5: LSIO_GPIO6_IO26_IN,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x60200++0x03
|
|
line.long 0x00 "SPI1_SCK,SPI1_SCK"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_I2C2_SDA,3: ADMA_SPI1_SCK,4: LSIO_GPIO3_IO00,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x60240++0x03
|
|
line.long 0x00 "SPI1_SDO,SPI1_SDO"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_I2C2_SCL,3: ADMA_SPI1_SDO,4: LSIO_GPIO3_IO01,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x60280++0x03
|
|
line.long 0x00 "SPI1_SDI,SPI1_SDI"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_I2C3_SCL,3: ADMA_SPI1_SDI,4: LSIO_GPIO3_IO02,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x602C0++0x03
|
|
line.long 0x00 "SPI1_CS0,SPI1_CS0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "?,?,2: ADMA_I2C3_SDA,3: ADMA_SPI1_CS0,4: LSIO_GPIO3_IO03,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x60300++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD,IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
rgroup.long 0x60400++0x03
|
|
line.long 0x00 "iomuxd_group_3_0,na"
|
|
bitfld.long 0x00 11. "SPI1_CS0,wakeup from SPI1_CS0" "0,1"
|
|
bitfld.long 0x00 10. "SPI1_SDI,wakeup from SPI1_SDI" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "SPI1_SDO,wakeup from SPI1_SDO" "0,1"
|
|
bitfld.long 0x00 8. "SPI1_SCK,wakeup from SPI1_SCK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "SNVS_TAMPER_DIG_IN3,wakeup from SNVS_TAMPER_DIG_IN3" "0,1"
|
|
bitfld.long 0x00 6. "SNVS_TAMPER_DIG_IN2,wakeup from SNVS_TAMPER_DIG_IN2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "SNVS_TAMPER_DIG_IN1,wakeup from SNVS_TAMPER_DIG_IN1" "0,1"
|
|
bitfld.long 0x00 4. "SNVS_TAMPER_DIG_IN0,wakeup from SNVS_TAMPER_DIG_IN0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SNVS_TAMPER_DIG_OUT4,wakeup from SNVS_TAMPER_DIG_OUT4" "0,1"
|
|
bitfld.long 0x00 2. "SNVS_TAMPER_DIG_OUT3,wakeup from SNVS_TAMPER_DIG_OUT3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "SNVS_TAMPER_DIG_OUT2,wakeup from SNVS_TAMPER_DIG_OUT2" "0,1"
|
|
bitfld.long 0x00 0. "SNVS_TAMPER_DIG_OUT1,wakeup from SNVS_TAMPER_DIG_OUT1" "0,1"
|
|
group.long 0x61000++0x03
|
|
line.long 0x00 "QSPI0A_DATA1,QSPI0A_DATA1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0A_DATA1,?,?,?,4: LSIO_GPIO3_IO10,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x61040++0x03
|
|
line.long 0x00 "QSPI0A_DATA0,QSPI0A_DATA0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0A_DATA0,?,?,?,4: LSIO_GPIO3_IO09,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x61080++0x03
|
|
line.long 0x00 "QSPI0A_DATA3,QSPI0A_DATA3"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0A_DATA3,?,?,?,4: LSIO_GPIO3_IO12,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x610C0++0x03
|
|
line.long 0x00 "QSPI0A_DATA2,QSPI0A_DATA2"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0A_DATA2,?,?,?,4: LSIO_GPIO3_IO11,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x61100++0x03
|
|
line.long 0x00 "QSPI0A_SS0_B,QSPI0A_SS0_B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0A_SS0_B,?,?,?,4: LSIO_GPIO3_IO14,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x61140++0x03
|
|
line.long 0x00 "QSPI0A_DQS,QSPI0A_DQS"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0A_DQS,?,?,?,4: LSIO_GPIO3_IO13,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x61180++0x03
|
|
line.long 0x00 "QSPI0A_SCLK,QSPI0A_SCLK"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0A_SCLK,?,?,?,4: LSIO_GPIO3_IO16,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x611C0++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A,IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
group.long 0x61200++0x03
|
|
line.long 0x00 "QSPI0B_SCLK,QSPI0B_SCLK"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0B_SCLK,?,?,?,4: LSIO_GPIO3_IO17,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x61240++0x03
|
|
line.long 0x00 "QSPI0B_DQS,QSPI0B_DQS"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0B_DQS,?,?,?,4: LSIO_GPIO3_IO22,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x61280++0x03
|
|
line.long 0x00 "QSPI0B_DATA1,QSPI0B_DATA1"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0B_DATA1,?,?,?,4: LSIO_GPIO3_IO19,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x612C0++0x03
|
|
line.long 0x00 "QSPI0B_DATA0,QSPI0B_DATA0"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0B_DATA0,?,?,?,4: LSIO_GPIO3_IO18,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x61300++0x03
|
|
line.long 0x00 "QSPI0B_DATA3,QSPI0B_DATA3"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0B_DATA3,?,?,?,4: LSIO_GPIO3_IO21,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x61340++0x03
|
|
line.long 0x00 "QSPI0B_DATA2,QSPI0B_DATA2"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0B_DATA2,?,?,?,4: LSIO_GPIO3_IO20,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x61380++0x03
|
|
line.long 0x00 "QSPI0B_SS0_B,QSPI0B_SS0_B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27.--29. "mux_mode,mux_mode" "0: LSIO_QSPI0B_SS0_B,?,?,?,4: LSIO_GPIO3_IO23,5: LSIO_QSPI0A_SS1_B,?..."
|
|
bitfld.long 0x00 25.--26. "sw_config,output and input configuration" "0: DEFAULT,1: OPEN_DRAIN,2: OPEN_DRAIN_INPUT,3: INOUT"
|
|
newline
|
|
bitfld.long 0x00 23.--24. "lp_config,lower power configuration" "0: PASS,1: EARLY_ISO,2: LATE_ISO,3: LATCH"
|
|
bitfld.long 0x00 22. "WAKEUP_MASK,wakeup mask" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "WAKEUP_CTRL,wakeup control" "0: OFF,1: RESAMPLE,?,?,4: LOW,5: FALL,6: RISE,7: HIGH"
|
|
bitfld.long 0x00 5.--6. "PULL,Pull Down Pull Up" "0: Prohibited,1: pull-up,2: pull-down,3: pull disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "PDRV,Drive" "0: high drive strength,1: low drive strength"
|
|
group.long 0x613C0++0x03
|
|
line.long 0x00 "IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B,IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B"
|
|
bitfld.long 0x00 31. "update_mux_mode,update lock for mux control" "0,1"
|
|
bitfld.long 0x00 30. "update_pad_ctl,update lock for pad control" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 23.--24. "SLEEP,SLEEP" "0: Normal mode,1: SLEEP mode is controlled by EARLY_ISO,2: SLEEP mode is controlled by LATE_ISO,3: Force into sleep mode"
|
|
rbitfld.long 0x00 15.--18. "READ_NASRC,READ_NASRC" "0: READ_ONLY,?..."
|
|
newline
|
|
rbitfld.long 0x00 14. "COMPOK,COMPOK" "0: compensation cell in another mode than Normal..,1: compensation cell in Normal mode and tracking.."
|
|
bitfld.long 0x00 13. "SELECT_NASRC,SELECT_NASRC" "0: NASRCP value,1: NASRCN value"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "RASRCN,RASRCN" "?,?,?,?,?,?,?,?,?,?,10: RASRCN_0b1010,?..."
|
|
bitfld.long 0x00 5.--8. "RASRCP,RASRCP" "?,?,?,?,?,5: RASRCP_0b0101,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FASTFRZ_EN,FASTFRZ_EN" "0: FASTFRZ signal is gated to 0,1: FASTFRZ signal is driven by output of subsystem"
|
|
bitfld.long 0x00 0.--2. "COMP,COMP" "0: Normal mode,1: Freeze mode,2: Fixed code mode,?,4: High impedance mode,?,6: Read mode,?..."
|
|
rgroup.long 0x61400++0x03
|
|
line.long 0x00 "iomuxd_group_3_1,na"
|
|
bitfld.long 0x00 14. "QSPI0B_SS0_B,wakeup from QSPI0B_SS0_B" "0,1"
|
|
bitfld.long 0x00 13. "QSPI0B_DATA2,wakeup from QSPI0B_DATA2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "QSPI0B_DATA3,wakeup from QSPI0B_DATA3" "0,1"
|
|
bitfld.long 0x00 11. "QSPI0B_DATA0,wakeup from QSPI0B_DATA0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "QSPI0B_DATA1,wakeup from QSPI0B_DATA1" "0,1"
|
|
bitfld.long 0x00 9. "QSPI0B_DQS,wakeup from QSPI0B_DQS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "QSPI0B_SCLK,wakeup from QSPI0B_SCLK" "0,1"
|
|
bitfld.long 0x00 6. "QSPI0A_SCLK,wakeup from QSPI0A_SCLK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "QSPI0A_DQS,wakeup from QSPI0A_DQS" "0,1"
|
|
bitfld.long 0x00 4. "QSPI0A_SS0_B,wakeup from QSPI0A_SS0_B" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "QSPI0A_DATA2,wakeup from QSPI0A_DATA2" "0,1"
|
|
bitfld.long 0x00 2. "QSPI0A_DATA3,wakeup from QSPI0A_DATA3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "QSPI0A_DATA0,wakeup from QSPI0A_DATA0" "0,1"
|
|
bitfld.long 0x00 0. "QSPI0A_DATA1,wakeup from QSPI0A_DATA1" "0,1"
|
|
tree.end
|
|
tree "LCDIF (LCD Interface)"
|
|
base ad:0x5A180000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,LCDIF General Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,This bit must be set to zero to enable normal operation of the LCDIF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,This bit must be set to zero for normal operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "YCBCR422_INPUT,Zero implies input data is in RGB color space" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "READ_WRITEB,By default LCDIF is in the write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "WAIT_FOR_VSYNC_EDGE,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "DATA_SHIFT_DIR,Use this bit to determine the direction of shift of transmit data" "0: Data to be transmitted is shifted LEFT by..,1: Data to be transmitted is shifted RIGHT by.."
|
|
newline
|
|
bitfld.long 0x00 21.--25. "SHIFT_NUM_BITS,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 20. "DVI_MODE,Set this bit to 1 to get into the ITU-R BT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "BYPASS_COUNT,When this bit is 0 it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "VSYNC_MODE,Setting this bit to 1 will make the LCDIF hardware go into VSYNC mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DOTCLK_MODE,Set this bit to 1 to make the hardware go into the DOTCLK mode i" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DATA_SELECT,Command Mode polarity bit" "0: Command Mode,1: Data Mode"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "INPUT_DATA_SWIZZLE,This field specifies how to swap the bytes fetched by the bus master interface" "0: No byte swapping.(Little endian),1: Big Endian swap (swap bytes 0 3 and 1 2),2: Swap half-words,3: Swap bytes within each half-word"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "CSC_DATA_SWIZZLE,This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "0: No byte swapping.(Little endian),1: Big Endian swap (swap bytes 0 3 and 1 2),2: Swap half-words,3: Swap bytes within each half-word"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "LCD_DATABUS_WIDTH,LCD Data bus transfer width" "0: 16-bit data bus mode,1: 8-bit data bus mode,2: 18-bit data bus mode,3: 24-bit data bus mode"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "WORD_LENGTH,Input data format" "0: Input data is 16 bits per pixel,1: Input data is 8 bits wide,2: Input data is 18 bits per pixel,3: Input data is 24 bits per pixel"
|
|
newline
|
|
bitfld.long 0x00 7. "RGB_TO_YCBCR422_CSC,Set this bit to 1 to enable conversion from RGB to YCbCr colorspace" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "MASTER,Set this bit to make the LCDIF act as a bus master" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DATA_FORMAT_16_BIT,When this bit is 1 and WORD_LENGTH = 0 it implies that the 16-bit data is in ARGB555 format" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DATA_FORMAT_18_BIT,Used only when WORD_LENGTH = 2 i.e" "0: Data input to the block is in 18 bpp format..,1: Data input to the block is in 18 bpp format.."
|
|
newline
|
|
bitfld.long 0x00 1. "DATA_FORMAT_24_BIT,Used only when WORD_LENGTH = 3 i" "0: Data input to the block is in 24 bpp format..,1: Data input to the block is actually RGB 18.."
|
|
newline
|
|
bitfld.long 0x00 0. "RUN,When this bit is set by software the LCDIF will begin transferring data between the SoC and the display" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL_SET,LCDIF General Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,This bit must be set to zero to enable normal operation of the LCDIF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,This bit must be set to zero for normal operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "YCBCR422_INPUT,Zero implies input data is in RGB color space" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "READ_WRITEB,By default LCDIF is in the write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "WAIT_FOR_VSYNC_EDGE,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "DATA_SHIFT_DIR,Use this bit to determine the direction of shift of transmit data" "0: Data to be transmitted is shifted LEFT by..,1: Data to be transmitted is shifted RIGHT by.."
|
|
newline
|
|
bitfld.long 0x00 21.--25. "SHIFT_NUM_BITS,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 20. "DVI_MODE,Set this bit to 1 to get into the ITU-R BT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "BYPASS_COUNT,When this bit is 0 it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "VSYNC_MODE,Setting this bit to 1 will make the LCDIF hardware go into VSYNC mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DOTCLK_MODE,Set this bit to 1 to make the hardware go into the DOTCLK mode i" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DATA_SELECT,Command Mode polarity bit" "0: Command Mode,1: Data Mode"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "INPUT_DATA_SWIZZLE,This field specifies how to swap the bytes fetched by the bus master interface" "0: No byte swapping.(Little endian),1: Big Endian swap (swap bytes 0 3 and 1 2),2: Swap half-words,3: Swap bytes within each half-word"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "CSC_DATA_SWIZZLE,This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "0: No byte swapping.(Little endian),1: Big Endian swap (swap bytes 0 3 and 1 2),2: Swap half-words,3: Swap bytes within each half-word"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "LCD_DATABUS_WIDTH,LCD Data bus transfer width" "0: 16-bit data bus mode,1: 8-bit data bus mode,2: 18-bit data bus mode,3: 24-bit data bus mode"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "WORD_LENGTH,Input data format" "0: Input data is 16 bits per pixel,1: Input data is 8 bits wide,2: Input data is 18 bits per pixel,3: Input data is 24 bits per pixel"
|
|
newline
|
|
bitfld.long 0x00 7. "RGB_TO_YCBCR422_CSC,Set this bit to 1 to enable conversion from RGB to YCbCr colorspace" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "MASTER,Set this bit to make the LCDIF act as a bus master" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DATA_FORMAT_16_BIT,When this bit is 1 and WORD_LENGTH = 0 it implies that the 16-bit data is in ARGB555 format" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DATA_FORMAT_18_BIT,Used only when WORD_LENGTH = 2 i.e" "0: Data input to the block is in 18 bpp format..,1: Data input to the block is in 18 bpp format.."
|
|
newline
|
|
bitfld.long 0x00 1. "DATA_FORMAT_24_BIT,Used only when WORD_LENGTH = 3 i" "0: Data input to the block is in 24 bpp format..,1: Data input to the block is actually RGB 18.."
|
|
newline
|
|
bitfld.long 0x00 0. "RUN,When this bit is set by software the LCDIF will begin transferring data between the SoC and the display" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL_CLR,LCDIF General Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,This bit must be set to zero to enable normal operation of the LCDIF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,This bit must be set to zero for normal operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "YCBCR422_INPUT,Zero implies input data is in RGB color space" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "READ_WRITEB,By default LCDIF is in the write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "WAIT_FOR_VSYNC_EDGE,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "DATA_SHIFT_DIR,Use this bit to determine the direction of shift of transmit data" "0: Data to be transmitted is shifted LEFT by..,1: Data to be transmitted is shifted RIGHT by.."
|
|
newline
|
|
bitfld.long 0x00 21.--25. "SHIFT_NUM_BITS,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 20. "DVI_MODE,Set this bit to 1 to get into the ITU-R BT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "BYPASS_COUNT,When this bit is 0 it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "VSYNC_MODE,Setting this bit to 1 will make the LCDIF hardware go into VSYNC mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DOTCLK_MODE,Set this bit to 1 to make the hardware go into the DOTCLK mode i" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DATA_SELECT,Command Mode polarity bit" "0: Command Mode,1: Data Mode"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "INPUT_DATA_SWIZZLE,This field specifies how to swap the bytes fetched by the bus master interface" "0: No byte swapping.(Little endian),1: Big Endian swap (swap bytes 0 3 and 1 2),2: Swap half-words,3: Swap bytes within each half-word"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "CSC_DATA_SWIZZLE,This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "0: No byte swapping.(Little endian),1: Big Endian swap (swap bytes 0 3 and 1 2),2: Swap half-words,3: Swap bytes within each half-word"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "LCD_DATABUS_WIDTH,LCD Data bus transfer width" "0: 16-bit data bus mode,1: 8-bit data bus mode,2: 18-bit data bus mode,3: 24-bit data bus mode"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "WORD_LENGTH,Input data format" "0: Input data is 16 bits per pixel,1: Input data is 8 bits wide,2: Input data is 18 bits per pixel,3: Input data is 24 bits per pixel"
|
|
newline
|
|
bitfld.long 0x00 7. "RGB_TO_YCBCR422_CSC,Set this bit to 1 to enable conversion from RGB to YCbCr colorspace" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "MASTER,Set this bit to make the LCDIF act as a bus master" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DATA_FORMAT_16_BIT,When this bit is 1 and WORD_LENGTH = 0 it implies that the 16-bit data is in ARGB555 format" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DATA_FORMAT_18_BIT,Used only when WORD_LENGTH = 2 i.e" "0: Data input to the block is in 18 bpp format..,1: Data input to the block is in 18 bpp format.."
|
|
newline
|
|
bitfld.long 0x00 1. "DATA_FORMAT_24_BIT,Used only when WORD_LENGTH = 3 i" "0: Data input to the block is in 24 bpp format..,1: Data input to the block is actually RGB 18.."
|
|
newline
|
|
bitfld.long 0x00 0. "RUN,When this bit is set by software the LCDIF will begin transferring data between the SoC and the display" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CTRL_TOG,LCDIF General Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,This bit must be set to zero to enable normal operation of the LCDIF" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,This bit must be set to zero for normal operation" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "YCBCR422_INPUT,Zero implies input data is in RGB color space" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "READ_WRITEB,By default LCDIF is in the write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "WAIT_FOR_VSYNC_EDGE,Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "DATA_SHIFT_DIR,Use this bit to determine the direction of shift of transmit data" "0: Data to be transmitted is shifted LEFT by..,1: Data to be transmitted is shifted RIGHT by.."
|
|
newline
|
|
bitfld.long 0x00 21.--25. "SHIFT_NUM_BITS,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 20. "DVI_MODE,Set this bit to 1 to get into the ITU-R BT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "BYPASS_COUNT,When this bit is 0 it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "VSYNC_MODE,Setting this bit to 1 will make the LCDIF hardware go into VSYNC mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "DOTCLK_MODE,Set this bit to 1 to make the hardware go into the DOTCLK mode i" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "DATA_SELECT,Command Mode polarity bit" "0: Command Mode,1: Data Mode"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "INPUT_DATA_SWIZZLE,This field specifies how to swap the bytes fetched by the bus master interface" "0: No byte swapping.(Little endian),1: Big Endian swap (swap bytes 0 3 and 1 2),2: Swap half-words,3: Swap bytes within each half-word"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "CSC_DATA_SWIZZLE,This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus" "0: No byte swapping.(Little endian),1: Big Endian swap (swap bytes 0 3 and 1 2),2: Swap half-words,3: Swap bytes within each half-word"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "LCD_DATABUS_WIDTH,LCD Data bus transfer width" "0: 16-bit data bus mode,1: 8-bit data bus mode,2: 18-bit data bus mode,3: 24-bit data bus mode"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "WORD_LENGTH,Input data format" "0: Input data is 16 bits per pixel,1: Input data is 8 bits wide,2: Input data is 18 bits per pixel,3: Input data is 24 bits per pixel"
|
|
newline
|
|
bitfld.long 0x00 7. "RGB_TO_YCBCR422_CSC,Set this bit to 1 to enable conversion from RGB to YCbCr colorspace" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "MASTER,Set this bit to make the LCDIF act as a bus master" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "DATA_FORMAT_16_BIT,When this bit is 1 and WORD_LENGTH = 0 it implies that the 16-bit data is in ARGB555 format" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DATA_FORMAT_18_BIT,Used only when WORD_LENGTH = 2 i.e" "0: Data input to the block is in 18 bpp format..,1: Data input to the block is in 18 bpp format.."
|
|
newline
|
|
bitfld.long 0x00 1. "DATA_FORMAT_24_BIT,Used only when WORD_LENGTH = 3 i" "0: Data input to the block is in 24 bpp format..,1: Data input to the block is actually RGB 18.."
|
|
newline
|
|
bitfld.long 0x00 0. "RUN,When this bit is set by software the LCDIF will begin transferring data between the SoC and the display" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTRL1,LCDIF General Control1 Register"
|
|
bitfld.long 0x00 27. "COMBINE_MPU_WR_STRB,If this bit is not set the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "BM_ERROR_IRQ_EN,This bit is set to enable bus master error interrupt in the LCDIF master mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "BM_ERROR_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 24. "RECOVER_ON_UNDERFLOW,Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "INTERLACE_FIELDS,Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "START_INTERLACE_FROM_SECOND_FIELD,The default is to grab the odd lines first and then the even lines" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "FIFO_CLEAR,Set this bit to clear all the data in the latency FIFO (LFIFO) TXFIFO and the RXFIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "IRQ_ON_ALTERNATE_FIELDS,If this bit is set the LCDIF block will assert the cur_frame_done interrupt only on alternate fields otherwise it will issue the interrupt on both odd and even field" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "BYTE_PACKING_FORMAT,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15. "OVERFLOW_IRQ_EN,This bit is set to enable an overflow interrupt in the TXFIFO in the write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "UNDERFLOW_IRQ_EN,This bit is set to enable an underflow interrupt in the TXFIFO in the write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CUR_FRAME_DONE_IRQ_EN,This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "VSYNC_EDGE_IRQ_EN,This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes or the beginning of every field in DVI mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "OVERFLOW_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 10. "UNDERFLOW_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 9. "CUR_FRAME_DONE_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 8. "VSYNC_EDGE_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 2. "BUSY_ENABLE,This bit enables the use of the interface's busy signal input" "0: The busy signal from the LCD controller will..,1: Enable the use of the busy signal from the.."
|
|
newline
|
|
bitfld.long 0x00 1. "MODE86,This bit is used to select between the 8080 and 6800 series of microprocessor modes" "0: Pins LCD_WR_RWn and LCD_RD_E function as..,1: Pins LCD_WR_RWn and LCD_RD_E function as.."
|
|
newline
|
|
bitfld.long 0x00 0. "RESET,Reset bit for the external LCD controller" "0: LCD_RESET output signal is low,1: LCD_RESET output signal is high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTRL1_SET,LCDIF General Control1 Register"
|
|
bitfld.long 0x00 27. "COMBINE_MPU_WR_STRB,If this bit is not set the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "BM_ERROR_IRQ_EN,This bit is set to enable bus master error interrupt in the LCDIF master mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "BM_ERROR_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 24. "RECOVER_ON_UNDERFLOW,Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "INTERLACE_FIELDS,Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "START_INTERLACE_FROM_SECOND_FIELD,The default is to grab the odd lines first and then the even lines" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "FIFO_CLEAR,Set this bit to clear all the data in the latency FIFO (LFIFO) TXFIFO and the RXFIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "IRQ_ON_ALTERNATE_FIELDS,If this bit is set the LCDIF block will assert the cur_frame_done interrupt only on alternate fields otherwise it will issue the interrupt on both odd and even field" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "BYTE_PACKING_FORMAT,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15. "OVERFLOW_IRQ_EN,This bit is set to enable an overflow interrupt in the TXFIFO in the write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "UNDERFLOW_IRQ_EN,This bit is set to enable an underflow interrupt in the TXFIFO in the write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CUR_FRAME_DONE_IRQ_EN,This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "VSYNC_EDGE_IRQ_EN,This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes or the beginning of every field in DVI mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "OVERFLOW_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 10. "UNDERFLOW_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 9. "CUR_FRAME_DONE_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 8. "VSYNC_EDGE_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 2. "BUSY_ENABLE,This bit enables the use of the interface's busy signal input" "0: The busy signal from the LCD controller will..,1: Enable the use of the busy signal from the.."
|
|
newline
|
|
bitfld.long 0x00 1. "MODE86,This bit is used to select between the 8080 and 6800 series of microprocessor modes" "0: Pins LCD_WR_RWn and LCD_RD_E function as..,1: Pins LCD_WR_RWn and LCD_RD_E function as.."
|
|
newline
|
|
bitfld.long 0x00 0. "RESET,Reset bit for the external LCD controller" "0: LCD_RESET output signal is low,1: LCD_RESET output signal is high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL1_CLR,LCDIF General Control1 Register"
|
|
bitfld.long 0x00 27. "COMBINE_MPU_WR_STRB,If this bit is not set the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "BM_ERROR_IRQ_EN,This bit is set to enable bus master error interrupt in the LCDIF master mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "BM_ERROR_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 24. "RECOVER_ON_UNDERFLOW,Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "INTERLACE_FIELDS,Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "START_INTERLACE_FROM_SECOND_FIELD,The default is to grab the odd lines first and then the even lines" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "FIFO_CLEAR,Set this bit to clear all the data in the latency FIFO (LFIFO) TXFIFO and the RXFIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "IRQ_ON_ALTERNATE_FIELDS,If this bit is set the LCDIF block will assert the cur_frame_done interrupt only on alternate fields otherwise it will issue the interrupt on both odd and even field" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "BYTE_PACKING_FORMAT,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15. "OVERFLOW_IRQ_EN,This bit is set to enable an overflow interrupt in the TXFIFO in the write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "UNDERFLOW_IRQ_EN,This bit is set to enable an underflow interrupt in the TXFIFO in the write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CUR_FRAME_DONE_IRQ_EN,This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "VSYNC_EDGE_IRQ_EN,This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes or the beginning of every field in DVI mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "OVERFLOW_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 10. "UNDERFLOW_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 9. "CUR_FRAME_DONE_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 8. "VSYNC_EDGE_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 2. "BUSY_ENABLE,This bit enables the use of the interface's busy signal input" "0: The busy signal from the LCD controller will..,1: Enable the use of the busy signal from the.."
|
|
newline
|
|
bitfld.long 0x00 1. "MODE86,This bit is used to select between the 8080 and 6800 series of microprocessor modes" "0: Pins LCD_WR_RWn and LCD_RD_E function as..,1: Pins LCD_WR_RWn and LCD_RD_E function as.."
|
|
newline
|
|
bitfld.long 0x00 0. "RESET,Reset bit for the external LCD controller" "0: LCD_RESET output signal is low,1: LCD_RESET output signal is high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CTRL1_TOG,LCDIF General Control1 Register"
|
|
bitfld.long 0x00 27. "COMBINE_MPU_WR_STRB,If this bit is not set the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the LCD_RD_E pin in the 6800 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "BM_ERROR_IRQ_EN,This bit is set to enable bus master error interrupt in the LCDIF master mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "BM_ERROR_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 24. "RECOVER_ON_UNDERFLOW,Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "INTERLACE_FIELDS,Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "START_INTERLACE_FROM_SECOND_FIELD,The default is to grab the odd lines first and then the even lines" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "FIFO_CLEAR,Set this bit to clear all the data in the latency FIFO (LFIFO) TXFIFO and the RXFIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "IRQ_ON_ALTERNATE_FIELDS,If this bit is set the LCDIF block will assert the cur_frame_done interrupt only on alternate fields otherwise it will issue the interrupt on both odd and even field" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "BYTE_PACKING_FORMAT,This bitfield is used to show which data bytes in a 32-bit word are valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 15. "OVERFLOW_IRQ_EN,This bit is set to enable an overflow interrupt in the TXFIFO in the write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "UNDERFLOW_IRQ_EN,This bit is set to enable an underflow interrupt in the TXFIFO in the write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "CUR_FRAME_DONE_IRQ_EN,This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "VSYNC_EDGE_IRQ_EN,This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes or the beginning of every field in DVI mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "OVERFLOW_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 10. "UNDERFLOW_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 9. "CUR_FRAME_DONE_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 8. "VSYNC_EDGE_IRQ,This bit is set to indicate that an interrupt is requested by the LCDIF block" "0: No Interrupt Request Pending,1: Interrupt Request Pending"
|
|
newline
|
|
bitfld.long 0x00 2. "BUSY_ENABLE,This bit enables the use of the interface's busy signal input" "0: The busy signal from the LCD controller will..,1: Enable the use of the busy signal from the.."
|
|
newline
|
|
bitfld.long 0x00 1. "MODE86,This bit is used to select between the 8080 and 6800 series of microprocessor modes" "0: Pins LCD_WR_RWn and LCD_RD_E function as..,1: Pins LCD_WR_RWn and LCD_RD_E function as.."
|
|
newline
|
|
bitfld.long 0x00 0. "RESET,Reset bit for the external LCD controller" "0: LCD_RESET output signal is low,1: LCD_RESET output signal is high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CTRL2,LCDIF General Control2 Register"
|
|
bitfld.long 0x00 21.--23. "OUTSTANDING_REQS,This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master" "0: REQ_1,1: REQ_2,2: REQ_4,3: REQ_8,4: REQ_16,?..."
|
|
newline
|
|
bitfld.long 0x00 20. "BURST_LEN_8,By default when the LCDIF is in the bus master mode it will issue AXI bursts of length 16 (except when in packed 24 bpp mode it will issue bursts of length 15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "ODD_LINE_PATTERN,This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1 3 5" "0: RGB,1: RBG,2: GBR,3: GRB,4: BRG,5: BGR,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "EVEN_LINE_PATTERN,This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2 4 6" "0: RGB,1: RBG,2: GBR,3: GRB,4: BRG,5: BGR,?..."
|
|
newline
|
|
bitfld.long 0x00 10. "READ_PACK_DIR,The default value of 0 indicates data is stored in the little endian format" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "READ_MODE_OUTPUT_IN_RGB_FORMAT,Setting this bit will enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "READ_MODE_6_BIT_INPUT,Setting this bit to 1 indicates to LCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits the input data is actually only 6 bits wide and exists on D5-D0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "READ_MODE_NUM_PACKED_SUBWORDS,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "INITIAL_DUMMY_READ,The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CTRL2_SET,LCDIF General Control2 Register"
|
|
bitfld.long 0x00 21.--23. "OUTSTANDING_REQS,This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master" "0: REQ_1,1: REQ_2,2: REQ_4,3: REQ_8,4: REQ_16,?..."
|
|
newline
|
|
bitfld.long 0x00 20. "BURST_LEN_8,By default when the LCDIF is in the bus master mode it will issue AXI bursts of length 16 (except when in packed 24 bpp mode it will issue bursts of length 15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "ODD_LINE_PATTERN,This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1 3 5" "0: RGB,1: RBG,2: GBR,3: GRB,4: BRG,5: BGR,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "EVEN_LINE_PATTERN,This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2 4 6" "0: RGB,1: RBG,2: GBR,3: GRB,4: BRG,5: BGR,?..."
|
|
newline
|
|
bitfld.long 0x00 10. "READ_PACK_DIR,The default value of 0 indicates data is stored in the little endian format" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "READ_MODE_OUTPUT_IN_RGB_FORMAT,Setting this bit will enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "READ_MODE_6_BIT_INPUT,Setting this bit to 1 indicates to LCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits the input data is actually only 6 bits wide and exists on D5-D0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "READ_MODE_NUM_PACKED_SUBWORDS,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "INITIAL_DUMMY_READ,The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CTRL2_CLR,LCDIF General Control2 Register"
|
|
bitfld.long 0x00 21.--23. "OUTSTANDING_REQS,This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master" "0: REQ_1,1: REQ_2,2: REQ_4,3: REQ_8,4: REQ_16,?..."
|
|
newline
|
|
bitfld.long 0x00 20. "BURST_LEN_8,By default when the LCDIF is in the bus master mode it will issue AXI bursts of length 16 (except when in packed 24 bpp mode it will issue bursts of length 15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "ODD_LINE_PATTERN,This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1 3 5" "0: RGB,1: RBG,2: GBR,3: GRB,4: BRG,5: BGR,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "EVEN_LINE_PATTERN,This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2 4 6" "0: RGB,1: RBG,2: GBR,3: GRB,4: BRG,5: BGR,?..."
|
|
newline
|
|
bitfld.long 0x00 10. "READ_PACK_DIR,The default value of 0 indicates data is stored in the little endian format" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "READ_MODE_OUTPUT_IN_RGB_FORMAT,Setting this bit will enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "READ_MODE_6_BIT_INPUT,Setting this bit to 1 indicates to LCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits the input data is actually only 6 bits wide and exists on D5-D0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "READ_MODE_NUM_PACKED_SUBWORDS,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "INITIAL_DUMMY_READ,The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CTRL2_TOG,LCDIF General Control2 Register"
|
|
bitfld.long 0x00 21.--23. "OUTSTANDING_REQS,This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master" "0: REQ_1,1: REQ_2,2: REQ_4,3: REQ_8,4: REQ_16,?..."
|
|
newline
|
|
bitfld.long 0x00 20. "BURST_LEN_8,By default when the LCDIF is in the bus master mode it will issue AXI bursts of length 16 (except when in packed 24 bpp mode it will issue bursts of length 15)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "ODD_LINE_PATTERN,This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1 3 5" "0: RGB,1: RBG,2: GBR,3: GRB,4: BRG,5: BGR,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "EVEN_LINE_PATTERN,This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2 4 6" "0: RGB,1: RBG,2: GBR,3: GRB,4: BRG,5: BGR,?..."
|
|
newline
|
|
bitfld.long 0x00 10. "READ_PACK_DIR,The default value of 0 indicates data is stored in the little endian format" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "READ_MODE_OUTPUT_IN_RGB_FORMAT,Setting this bit will enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "READ_MODE_6_BIT_INPUT,Setting this bit to 1 indicates to LCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits the input data is actually only 6 bits wide and exists on D5-D0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "READ_MODE_NUM_PACKED_SUBWORDS,Indicates the number of valid 8/16/18/24-bit subwords that will be packed into the 32-bit word in read mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 1.--3. "INITIAL_DUMMY_READ,The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TRANSFER_COUNT,LCDIF Horizontal and Vertical Valid Data Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "V_COUNT,Number of horizontal lines per frame which contain valid data"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "H_COUNT,Total valid data (pixels) in each horizontal line"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CUR_BUF,LCD Interface Current Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Address of the current frame being transmitted by LCDIF"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "NEXT_BUF,LCD Interface Next Buffer Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Address of the next frame that will be transmitted by LCDIF"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TIMING,LCD Interface Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CMD_HOLD,Number of DISPLAY CLOCK (pix_clk) cycles that the LCD_RS signal is active after LCD_CS is deasserted"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "CMD_SETUP,Number of DISPLAY CLOCK (pix_clk) cycles that the LCD_RS signal is active before LCD_CS is asserted"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_HOLD,Data bus hold time in DISPLAY CLOCK (pix_clk) cycles"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_SETUP,Data bus setup time in DISPLAY CLOCK (pix_clk) cycles"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "VDCTRL0,LCDIF VSYNC Mode and Dotclk Mode Control Register0"
|
|
bitfld.long 0x00 29. "VSYNC_OEB,0 means the VSYNC signal is an output 1 means it is an input" "0: The VSYNC pin is in the output mode and the..,1: The VSYNC pin is in the input mode and the.."
|
|
newline
|
|
bitfld.long 0x00 28. "ENABLE_PRESENT,Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode thereby making it the true RGB interface along with the remaining three signals VSYNC HSYNC and DOTCLK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "VSYNC_POL,Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "HSYNC_POL,Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DOTCLK_POL,Default is data launched at negative edge of DOTCLK and captured at positive edge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "ENABLE_POL,Default 0 active low during valid data transfer on each horizontal line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "VSYNC_PERIOD_UNIT,Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "VSYNC_PULSE_WIDTH_UNIT,Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "HALF_LINE,Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "HALF_LINE_MODE,When this bit is 0 the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "VSYNC_PULSE_WIDTH,Number of units for which VSYNC signal is active"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "VDCTRL0_SET,LCDIF VSYNC Mode and Dotclk Mode Control Register0"
|
|
bitfld.long 0x00 29. "VSYNC_OEB,0 means the VSYNC signal is an output 1 means it is an input" "0: The VSYNC pin is in the output mode and the..,1: The VSYNC pin is in the input mode and the.."
|
|
newline
|
|
bitfld.long 0x00 28. "ENABLE_PRESENT,Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode thereby making it the true RGB interface along with the remaining three signals VSYNC HSYNC and DOTCLK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "VSYNC_POL,Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "HSYNC_POL,Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DOTCLK_POL,Default is data launched at negative edge of DOTCLK and captured at positive edge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "ENABLE_POL,Default 0 active low during valid data transfer on each horizontal line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "VSYNC_PERIOD_UNIT,Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "VSYNC_PULSE_WIDTH_UNIT,Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "HALF_LINE,Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "HALF_LINE_MODE,When this bit is 0 the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "VSYNC_PULSE_WIDTH,Number of units for which VSYNC signal is active"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "VDCTRL0_CLR,LCDIF VSYNC Mode and Dotclk Mode Control Register0"
|
|
bitfld.long 0x00 29. "VSYNC_OEB,0 means the VSYNC signal is an output 1 means it is an input" "0: The VSYNC pin is in the output mode and the..,1: The VSYNC pin is in the input mode and the.."
|
|
newline
|
|
bitfld.long 0x00 28. "ENABLE_PRESENT,Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode thereby making it the true RGB interface along with the remaining three signals VSYNC HSYNC and DOTCLK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "VSYNC_POL,Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "HSYNC_POL,Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DOTCLK_POL,Default is data launched at negative edge of DOTCLK and captured at positive edge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "ENABLE_POL,Default 0 active low during valid data transfer on each horizontal line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "VSYNC_PERIOD_UNIT,Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "VSYNC_PULSE_WIDTH_UNIT,Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "HALF_LINE,Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "HALF_LINE_MODE,When this bit is 0 the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "VSYNC_PULSE_WIDTH,Number of units for which VSYNC signal is active"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "VDCTRL0_TOG,LCDIF VSYNC Mode and Dotclk Mode Control Register0"
|
|
bitfld.long 0x00 29. "VSYNC_OEB,0 means the VSYNC signal is an output 1 means it is an input" "0: The VSYNC pin is in the output mode and the..,1: The VSYNC pin is in the input mode and the.."
|
|
newline
|
|
bitfld.long 0x00 28. "ENABLE_PRESENT,Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode thereby making it the true RGB interface along with the remaining three signals VSYNC HSYNC and DOTCLK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "VSYNC_POL,Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "HSYNC_POL,Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "DOTCLK_POL,Default is data launched at negative edge of DOTCLK and captured at positive edge" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "ENABLE_POL,Default 0 active low during valid data transfer on each horizontal line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "VSYNC_PERIOD_UNIT,Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "VSYNC_PULSE_WIDTH_UNIT,Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "HALF_LINE,Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "HALF_LINE_MODE,When this bit is 0 the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "VSYNC_PULSE_WIDTH,Number of units for which VSYNC signal is active"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "VDCTRL1,LCDIF VSYNC Mode and Dotclk Mode Control Register1"
|
|
hexmask.long 0x00 0.--31. 1. "VSYNC_PERIOD,Total number of units between two positive or two negative edges of the VSYNC signal"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "VDCTRL2,LCDIF VSYNC Mode and Dotclk Mode Control Register2"
|
|
hexmask.long.word 0x00 18.--31. 1. "HSYNC_PULSE_WIDTH,Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "HSYNC_PERIOD,Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "VDCTRL3,LCDIF VSYNC Mode and Dotclk Mode Control Register3"
|
|
bitfld.long 0x00 29. "MUX_SYNC_SIGNALS,When this bit is set the LCDIF block will internally mux HSYNC with LCD_D14 DOTCLK with LCD_D13 and ENABLE with LCD_D12 otherwise these signals will go out on separate pins" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "VSYNC_ONLY,This bit must be set to 1 in the VSYNC mode of operation and 0 in the DOTCLK mode of operation" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. "HORIZONTAL_WAIT_CNT,In the DOTCLK mode wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "VERTICAL_WAIT_CNT,In the VSYNC interface mode wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "VDCTRL4,LCDIF VSYNC Mode and Dotclk Mode Control Register4"
|
|
bitfld.long 0x00 29.--31. "DOTCLK_DLY_SEL,This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 18. "SYNC_SIGNALS_ON,Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data.." "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "DOTCLK_H_VALID_DATA_CNT,Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DVICTRL0,Digital Video Interface Control0 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. "H_ACTIVE_CNT,Number of active video samples to be transmitted"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "H_BLANKING_CNT,Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DVICTRL1,Digital Video Interface Control1 Register"
|
|
hexmask.long.word 0x00 20.--29. 1. "F1_START_LINE,Vertical line number from which Field 1 begins"
|
|
newline
|
|
hexmask.long.word 0x00 10.--19. 1. "F1_END_LINE,Vertical line number at which Field1 ends"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "F2_START_LINE,Vertical line number from which Field 2 begins"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DVICTRL2,Digital Video Interface Control2 Register"
|
|
hexmask.long.word 0x00 20.--29. 1. "F2_END_LINE,Vertical line number at which Field 2 ends"
|
|
newline
|
|
hexmask.long.word 0x00 10.--19. 1. "V1_BLANK_START_LINE,Vertical line number towards the end of Field1 where first Vertical Blanking interval starts"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "V1_BLANK_END_LINE,Vertical line number in the beginning part of Field2 where first Vertical Blanking interval ends"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DVICTRL3,Digital Video Interface Control3 Register"
|
|
hexmask.long.word 0x00 20.--29. 1. "V2_BLANK_START_LINE,Vertical line number towards the end of Field2 where second Vertical Blanking interval starts"
|
|
newline
|
|
hexmask.long.word 0x00 10.--19. 1. "V2_BLANK_END_LINE,Vertical line number in the beginning part of Field1 where second Vertical Blanking interval ends"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "V_LINES_CNT,Total number of vertical lines per frame (generally 525 or 625)"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DVICTRL4,Digital Video Interface Control4 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Y_FILL_VALUE,Value of Y component of filler data"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "CB_FILL_VALUE,Value of CB component of filler data"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CR_FILL_VALUE,Value of CR component of filler data"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "H_FILL_CNT,Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CSC_COEFF0,RGB to YCbCr 4:2:2 CSC Coefficient0 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "C0,Two's complement red multiplier coefficient for Y"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CSC_SUBSAMPLE_FILTER,This register describes the filtering and subsampling scheme to be performed on the chroma components in order to convert from YCbCr 4:4:4 to YCbCr 4:2:2 space" "0: No filtering simply keep every chroma value..,?,2: Chroma samples numbered 2n and 2n+1 are..,3: Chroma samples numbered 2n-1 2n and 2n+1 are.."
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CSC_COEFF1,RGB to YCbCr 4:2:2 CSC Coefficient1 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "C2,Two's complement blue multiplier coefficient for Y"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "C1,Two's complement green multiplier coefficient for Y"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CSC_COEFF2,RGB to YCbCr 4:2:2 CSC Coefficent2 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "C4,Two's complement green multiplier coefficient for Cb"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "C3,Two's complement red multiplier coefficient for Cb"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CSC_COEFF3,RGB to YCbCr 4:2:2 CSC Coefficient3 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "C6,Two's complement red multiplier coefficient for Cr"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "C5,Two's complement blue multiplier coefficient for Cb"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CSC_COEFF4,RGB to YCbCr 4:2:2 CSC Coefficient4 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "C8,Two's complement blue multiplier coefficient for Cr"
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "C7,Two's complement green multiplier coefficient for Cr"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "CSC_OFFSET,RGB to YCbCr 4:2:2 CSC Offset Register"
|
|
hexmask.long.word 0x00 16.--24. 1. "CBCR_OFFSET,Two's complement offset for the Cb and Cr components"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "Y_OFFSET,Two's complement offset for the Y component"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CSC_LIMIT,RGB to YCbCr 4:2:2 CSC Limit Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CBCR_MIN,Lower limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "CBCR_MAX,Upper limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Y_MIN,Lower limit of Y after RGB to 4:2:2 YCbCr conversion"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "Y_MAX,Upper limit of Y after RGB to 4:2:2 YCbCr conversion"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DATA,LCD Interface Data Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_THREE,Byte 3 (most significant byte) of data written to LCDIF"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_TWO,Byte 2 of data written to LCDIF"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_ONE,Byte 1 of data written to LCDIF"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_ZERO,Byte 0 (least significant byte) of data written to LCDIF"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "BM_ERROR_STAT,Bus Master Error Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Virtual address at which bus master error occurred"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CRC_STAT,CRC Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "CRC_VALUE,Calculated CRC value"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "STAT,LCD Interface Status Register"
|
|
bitfld.long 0x00 31. "PRESENT," "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "LFIFO_FULL,Read only view of the signals that indicates LCD LFIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "LFIFO_EMPTY,Read only view of the signals that indicates LCD LFIFO is empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "TXFIFO_FULL,Read only view of the signals that indicates LCD TXFIFO is full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "TXFIFO_EMPTY,Read only view of the signals that indicates LCD TXFIFO is empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "BUSY,Read only view of the input busy signal from the external LCD controller" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "DVI_CURRENT_FIELD,Read only view of the current field being transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "LFIFO_COUNT,Read only view of the current count in Latency buffer (LFIFO)"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "THRES,LCDIF Threshold Register"
|
|
hexmask.long.word 0x00 16.--24. 1. "FASTCLOCK,This value should be set to a value of pixels from 0 to 511"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. "PANIC,This value should be set to a value of pixels from 0 to 511"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "AS_CTRL,LCDIF AS Buffer Control Register"
|
|
bitfld.long 0x00 31. "CSI_VSYNC_ENABLE,When this bit is set by software the LCDIF work as sync mode with CSI input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CSI_VSYNC_POL,Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "CSI_VSYNC_MODE,this bit is set by software to decide which vsync generate mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "CSI_SYNC_ON_IRQ_EN,This bit is set to enable an interrupt when LCDIF lock with CSI vsync input" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "CSI_SYNC_ON_IRQ,this bit is set by software to decide which vsync generate mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 24.--26. "RVDS1,Reserved always set to zero" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. "PS_DISABLE,When this bit is set by software the LCDIF will disable PS buffer data" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "INPUT_DATA_SWIZZLE,This field specifies how to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 20. "ALPHA_INVERT,Setting this bit to logic 0 will not alter the alpha value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "ROP,Indicates a raster operation to perform when enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "ALPHA,Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in REG_AS_CTRL[ALPHA_CTRL]"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "FORMAT,Indicates the input buffer format for AS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "ENABLE_COLORKEY,Indicates that colorkey functionality is enabled for this alpha surface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "ALPHA_CTRL,Determines how the alpha value is constructed for this alpha surface" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "AS_ENABLE,When this bit is set by software the LCDIF will start fetching AS buffer data in bus master mode and combine it with another buffer" "0,1"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "AS_BUF,Alpha Surface Buffer Pointer"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Address pointer for the alpha surface 0 buffer"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "AS_NEXT_BUF,When the LCDIF is behaving as a master this address points to the address of the next frame of data that will be sent out via the LCDIF"
|
|
hexmask.long 0x00 0.--31. 1. "ADDR,Address of the next frame that will be transmitted by LCDIF"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "AS_CLRKEYLOW,LCDIF Overlay Color Key Low"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RSVD1,Reserved always set to zero"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "PIXEL,Low range of RGB color key applied to AS buffer"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "AS_CLRKEYHIGH,LCDIF Overlay Color Key High"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RSVD1,Reserved always set to zero"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "PIXEL,High range of RGB color key applied to AS buffer"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "SYNC_DELAY,LCD working insync mode with CSI for VSYNC delay"
|
|
hexmask.long.word 0x00 16.--31. 1. "V_COUNT_DELAY,LCDIF VSYNC delayed counter for CSI_VSYNC"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "H_COUNT_DELAY,LCDIF VSYNC delayed counter for CSI_VSYNC"
|
|
tree.end
|
|
tree "LPCG_GPIO_CLK"
|
|
base ad:0x5F100000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_GPIO_CLK_0,na"
|
|
rbitfld.long 0x00 19. "gpio_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "gpio_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpio_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_ACM_REGS"
|
|
base ad:0x59C60000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_acm_regs_0,na"
|
|
rbitfld.long 0x00 19. "acm_regs_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "acm_regs_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "acm_regs_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_ADC0"
|
|
base ad:0x5AC80000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_adc0_0,na"
|
|
rbitfld.long 0x00 19. "anamix_ipg_clk_adc0_STOP_AND_anamix_ipg_clk_s_adc0_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "anamix_ipg_clk_adc0_SWEN_AND_anamix_ipg_clk_s_adc0_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "anamix_ipg_clk_adc0_HWEN_AND_anamix_ipg_clk_s_adc0_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "anamix_adc_clk_adc0_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "anamix_adc_clk_adc0_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "anamix_adc_clk_adc0_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_APB"
|
|
base ad:0x5C0F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_apb_0,na"
|
|
rbitfld.long 0x00 3. "ddr_ctl_pclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 1. "ddr_ctl_pclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "ddr_ctl_pclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "LPCG_lpcg_apb_4,na"
|
|
rbitfld.long 0x00 3. "ddr_phy_pclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 1. "ddr_phy_pclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "ddr_phy_pclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_ASRC0"
|
|
base ad:0x59400000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_asrc0_0,na"
|
|
rbitfld.long 0x00 19. "asrc0_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "asrc0_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "asrc0_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_AUD_PLL_DIV_CLK"
|
|
tree "ADMA__LPCG_ACM_AUD_PLL_DIV_CLK0"
|
|
base ad:0x59D20000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_aud_pll_div_clk0_0,na"
|
|
rbitfld.long 0x00 3. "acm_aud_pll_div_clk0_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "acm_aud_pll_div_clk0_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "acm_aud_pll_div_clk0_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_ACM_AUD_PLL_DIV_CLK1"
|
|
base ad:0x59D30000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_aud_pll_div_clk1_0,na"
|
|
rbitfld.long 0x00 3. "acm_aud_pll_div_clk1_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "acm_aud_pll_div_clk1_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "acm_aud_pll_div_clk1_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LPCG_LPCG_AUD_REC_CLK"
|
|
tree "ADMA__LPCG_ACM_AUD_REC_CLK0"
|
|
base ad:0x59D00000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_aud_rec_clk0_0,na"
|
|
rbitfld.long 0x00 3. "acm_aud_rec_clk0_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "acm_aud_rec_clk0_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "acm_aud_rec_clk0_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_ACM_AUD_REC_CLK1"
|
|
base ad:0x59D10000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_aud_rec_clk1_0,na"
|
|
rbitfld.long 0x00 3. "acm_aud_rec_clk1_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "acm_aud_rec_clk1_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "acm_aud_rec_clk1_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LPCG_LPCG_CAN"
|
|
tree "ADMA__LPCG_CAN0_IPG_CLK"
|
|
base ad:0x5ACD0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_can0_0,na"
|
|
rbitfld.long 0x00 23. "can0_ipg_clk_chi_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "can0_ipg_clk_chi_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 20. "can0_ipg_clk_chi_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "can0_ipg_clk_STOP_AND_can0_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "can0_ipg_clk_SWEN_AND_can0_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "can0_ipg_clk_HWEN_AND_can0_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "can0_ipg_clk_pe_nogate_STOP_AND_can0_ipg_clk_pe_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "can0_ipg_clk_pe_nogate_SWEN_AND_can0_ipg_clk_pe_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "can0_ipg_clk_pe_nogate_HWEN_AND_can0_ipg_clk_pe_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_CAN1_IPG_CLK"
|
|
base ad:0x5ACE0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_can1_0,na"
|
|
rbitfld.long 0x00 23. "can1_ipg_clk_chi_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "can1_ipg_clk_chi_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 20. "can1_ipg_clk_chi_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "can1_ipg_clk_STOP_AND_can1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "can1_ipg_clk_SWEN_AND_can1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "can1_ipg_clk_HWEN_AND_can1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "can1_ipg_clk_pe_nogate_STOP_AND_can1_ipg_clk_pe_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "can1_ipg_clk_pe_nogate_SWEN_AND_can1_ipg_clk_pe_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "can1_ipg_clk_pe_nogate_HWEN_AND_can1_ipg_clk_pe_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_CAN2_IPG_CLK"
|
|
base ad:0x5ACF0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_can2_0,na"
|
|
rbitfld.long 0x00 23. "can2_ipg_clk_chi_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "can2_ipg_clk_chi_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 20. "can2_ipg_clk_chi_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "can2_ipg_clk_STOP_AND_can2_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "can2_ipg_clk_SWEN_AND_can2_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "can2_ipg_clk_HWEN_AND_can2_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "can2_ipg_clk_pe_nogate_STOP_AND_can2_ipg_clk_pe_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "can2_ipg_clk_pe_nogate_SWEN_AND_can2_ipg_clk_pe_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "can2_ipg_clk_pe_nogate_HWEN_AND_can2_ipg_clk_pe_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LPCG_LPCG_DDRC"
|
|
base ad:0x5C0D0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_ddrc_0,na"
|
|
rbitfld.long 0x00 3. "ddr_ctl_core_ddrc_core_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ddr_ctl_core_ddrc_core_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "ddr_ctl_core_ddrc_core_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_EDMA"
|
|
tree "ADMA__LPCG_EDMA0_HCLK"
|
|
base ad:0x595F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_edma0_0,na"
|
|
rbitfld.long 0x00 19. "edma0_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "edma0_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "edma0_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "edma0_hclk_STOP_AND_edma0_ipd_gasket_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "edma0_hclk_SWEN_AND_edma0_ipd_gasket_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "edma0_hclk_HWEN_AND_edma0_ipd_gasket_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_EDMA2_HCLK"
|
|
base ad:0x5A5F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_edma2_0,na"
|
|
rbitfld.long 0x00 19. "edma2_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "edma2_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "edma2_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "edma2_hclk_STOP_AND_edma2_ipd_gasket_ipg_clk_STOP_AND_ipd_sync_0_hclk_STOP," "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "edma2_hclk_SWEN_AND_edma2_ipd_gasket_ipg_clk_SWEN_AND_ipd_sync_0_hclk_SWEN," "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "edma2_hclk_HWEN_AND_edma2_ipd_gasket_ipg_clk_HWEN_AND_ipd_sync_0_hclk_HWEN,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_EDMA3_HCLK"
|
|
base ad:0x5ADF0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_edma3_0,na"
|
|
rbitfld.long 0x00 19. "edma3_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "edma3_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "edma3_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "edma3_hclk_STOP_AND_edma3_ipd_gasket_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "edma3_hclk_SWEN_AND_edma3_ipd_gasket_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "edma3_hclk_HWEN_AND_edma3_ipd_gasket_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LPCG_LPCG_FTM"
|
|
tree "ADMA__LPCG_FTM0_IPG_CLK"
|
|
base ad:0x5ACA0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_ftm0_0,na"
|
|
rbitfld.long 0x00 19. "ftm0_ipg_clk_STOP_AND_ftm0_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "ftm0_ipg_clk_SWEN_AND_ftm0_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "ftm0_ipg_clk_HWEN_AND_ftm0_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "ftm0_ipp_ind_extclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ftm0_ipp_ind_extclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "ftm0_ipp_ind_extclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_FTM1_IPG_CLK"
|
|
base ad:0x5ACB0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_ftm1_0,na"
|
|
rbitfld.long 0x00 19. "ftm1_ipg_clk_STOP_AND_ftm1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "ftm1_ipg_clk_SWEN_AND_ftm1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "ftm1_ipg_clk_HWEN_AND_ftm1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "ftm1_ipp_ind_extclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ftm1_ipp_ind_extclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "ftm1_ipp_ind_extclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LPCG_LPCG_GPT"
|
|
tree "ADMA__LPCG_GPT0_IPG_CLK_24M"
|
|
base ad:0x594B0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_gpt0_0,na"
|
|
rbitfld.long 0x00 19. "gpt0_ipg_clk_STOP_AND_gpt0_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "gpt0_ipg_clk_SWEN_AND_gpt0_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpt0_ipg_clk_HWEN_AND_gpt0_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "gpt0_ipp_ind_clkin_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "gpt0_ipp_ind_clkin_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "gpt0_ipp_ind_clkin_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_GPT1_IPG_CLK_24M"
|
|
base ad:0x594C0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_gpt1_0,na"
|
|
rbitfld.long 0x00 19. "gpt1_ipg_clk_STOP_AND_gpt1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "gpt1_ipg_clk_SWEN_AND_gpt1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpt1_ipg_clk_HWEN_AND_gpt1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "gpt1_ipp_ind_clkin_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "gpt1_ipp_ind_clkin_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "gpt1_ipp_ind_clkin_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_GPT2_IPG_CLK_24M"
|
|
base ad:0x594D0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_gpt2_0,na"
|
|
rbitfld.long 0x00 19. "gpt2_ipg_clk_STOP_AND_gpt2_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "gpt2_ipg_clk_SWEN_AND_gpt2_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpt2_ipg_clk_HWEN_AND_gpt2_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "gpt2_ipp_ind_clkin_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "gpt2_ipp_ind_clkin_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "gpt2_ipp_ind_clkin_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_GPT3_IPG_CLK_24M"
|
|
base ad:0x594E0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_gpt3_0,na"
|
|
rbitfld.long 0x00 19. "gpt3_ipg_clk_STOP_AND_gpt3_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "gpt3_ipg_clk_SWEN_AND_gpt3_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpt3_ipg_clk_HWEN_AND_gpt3_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "gpt3_ipp_ind_clkin_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "gpt3_ipp_ind_clkin_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "gpt3_ipp_ind_clkin_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LPCG_LPCG_I2C"
|
|
tree "ADMA__LPCG_I2C0_IPG_CLK"
|
|
base ad:0x5AC00000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_i2c0_0,na"
|
|
rbitfld.long 0x00 19. "i2c0_ipg_clk_STOP_AND_i2c0_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "i2c0_ipg_clk_SWEN_AND_i2c0_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "i2c0_ipg_clk_HWEN_AND_i2c0_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "i2c0_lpi2c_clk_STOP_AND_i2c0_lpi2c_div_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "i2c0_lpi2c_clk_SWEN_AND_i2c0_lpi2c_div_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "i2c0_lpi2c_clk_HWEN_AND_i2c0_lpi2c_div_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_I2C1_IPG_CLK"
|
|
base ad:0x5AC10000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_i2c1_0,na"
|
|
rbitfld.long 0x00 19. "i2c1_ipg_clk_STOP_AND_i2c1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "i2c1_ipg_clk_SWEN_AND_i2c1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "i2c1_ipg_clk_HWEN_AND_i2c1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "i2c1_lpi2c_clk_STOP_AND_i2c1_lpi2c_div_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "i2c1_lpi2c_clk_SWEN_AND_i2c1_lpi2c_div_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "i2c1_lpi2c_clk_HWEN_AND_i2c1_lpi2c_div_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_I2C2_IPG_CLK"
|
|
base ad:0x5AC20000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_i2c2_0,na"
|
|
rbitfld.long 0x00 19. "i2c2_ipg_clk_STOP_AND_i2c2_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "i2c2_ipg_clk_SWEN_AND_i2c2_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "i2c2_ipg_clk_HWEN_AND_i2c2_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "i2c2_lpi2c_clk_STOP_AND_i2c2_lpi2c_div_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "i2c2_lpi2c_clk_SWEN_AND_i2c2_lpi2c_div_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "i2c2_lpi2c_clk_HWEN_AND_i2c2_lpi2c_div_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_I2C3_IPG_CLK"
|
|
base ad:0x5AC30000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_i2c3_0,na"
|
|
rbitfld.long 0x00 19. "i2c3_ipg_clk_STOP_AND_i2c3_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "i2c3_ipg_clk_SWEN_AND_i2c3_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "i2c3_ipg_clk_HWEN_AND_i2c3_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "i2c3_lpi2c_clk_STOP_AND_i2c3_lpi2c_div_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "i2c3_lpi2c_clk_SWEN_AND_i2c3_lpi2c_div_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "i2c3_lpi2c_clk_HWEN_AND_i2c3_lpi2c_div_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LPCG_LPCG_IRQ"
|
|
base ad:0x510F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_irq_0,na"
|
|
rbitfld.long 0x00 23. "gic_clk_STOP_AND_gic_axi_cnt_clk_STOP_AND_gic_axi_pause_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "gic_clk_SWEN_AND_gic_axi_cnt_clk_SWEN_AND_gic_axi_pause_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "gic_clk_HWEN_AND_gic_axi_cnt_clk_HWEN_AND_gic_axi_pause_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "irqstr_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "irqstr_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "irqstr_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "adb_s0_aclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "adb_s0_aclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "adb_s0_aclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "adb_m0_aclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "adb_m0_aclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "adb_m0_aclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_LCDIF"
|
|
base ad:0x5A580000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_lcdif_0,na"
|
|
rbitfld.long 0x00 19. "lcdif_apb_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "lcdif_apb_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "lcdif_apb_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "lcdif_pix_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "lcdif_pix_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "lcdif_pix_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_MCLKOUT"
|
|
tree "ADMA__LPCG_MCLKOUT0"
|
|
base ad:0x59D50000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_mclkout0_0,na"
|
|
rbitfld.long 0x00 3. "mclkout0_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 1. "mclkout0_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "mclkout0_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_MCLKOUT1"
|
|
base ad:0x59D60000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_mclkout1_0,na"
|
|
rbitfld.long 0x00 3. "mclkout1_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 1. "mclkout1_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "mclkout1_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LPCG_LPCG_MQS_REGS"
|
|
base ad:0x59C50000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_mqs_regs_0,na"
|
|
rbitfld.long 0x00 19. "mqs_regs_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mqs_regs_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mqs_regs_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mqs_hmclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mqs_hmclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mqs_hmclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_PUB"
|
|
base ad:0x5C080000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_pub_0,na"
|
|
rbitfld.long 0x00 3. "ddr_phy_pub_ctl_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 1. "ddr_phy_pub_ctl_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "ddr_phy_pub_ctl_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_PWM"
|
|
base ad:0x5A590000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_pwm_0,na"
|
|
rbitfld.long 0x00 19. "pwm_ipg_clk_STOP_AND_pwm_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "pwm_ipg_clk_SWEN_AND_pwm_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "pwm_ipg_clk_HWEN_AND_pwm_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "pwm_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "pwm_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "pwm_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_SAI"
|
|
tree "ADMA__LPCG_SAI0_IPG_CLK"
|
|
base ad:0x59440000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_sai0_0,na"
|
|
rbitfld.long 0x00 19. "sai0_ipg_clk_STOP_AND_sai0_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "sai0_ipg_clk_SWEN_AND_sai0_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "sai0_ipg_clk_HWEN_AND_sai0_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "sai0_ipg_clk_sai_mclk_1_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "sai0_ipg_clk_sai_mclk_1_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "sai0_ipg_clk_sai_mclk_1_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_SAI1_IPG_CLK"
|
|
base ad:0x59450000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_sai1_0,na"
|
|
rbitfld.long 0x00 19. "sai1_ipg_clk_STOP_AND_sai1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "sai1_ipg_clk_SWEN_AND_sai1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "sai1_ipg_clk_HWEN_AND_sai1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "sai1_ipg_clk_sai_mclk_1_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "sai1_ipg_clk_sai_mclk_1_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "sai1_ipg_clk_sai_mclk_1_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_SAI2_IPG_CLK"
|
|
base ad:0x59460000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_sai2_0,na"
|
|
rbitfld.long 0x00 19. "sai2_ipg_clk_STOP_AND_sai2_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "sai2_ipg_clk_SWEN_AND_sai2_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "sai2_ipg_clk_HWEN_AND_sai2_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "sai2_ipg_clk_sai_mclk_1_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "sai2_ipg_clk_sai_mclk_1_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "sai2_ipg_clk_sai_mclk_1_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_SAI3_IPG_CLK"
|
|
base ad:0x59470000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_sai3_0,na"
|
|
rbitfld.long 0x00 19. "sai3_ipg_clk_STOP_AND_sai3_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "sai3_ipg_clk_SWEN_AND_sai3_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "sai3_ipg_clk_HWEN_AND_sai3_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "sai3_ipg_clk_sai_mclk_1_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "sai3_ipg_clk_sai_mclk_1_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "sai3_ipg_clk_sai_mclk_1_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LPCG_LPCG_SBR"
|
|
base ad:0x5C0B0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_sbr_0,na"
|
|
rbitfld.long 0x00 3. "ddr_ctl_sbr_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 1. "ddr_ctl_sbr_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "ddr_ctl_sbr_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_SPDIF0"
|
|
base ad:0x59420000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_spdif0_0,na"
|
|
rbitfld.long 0x00 19. "spdif0_ipg_clk_s_STOP_AND_spdif0_gclkw_t0_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "spdif0_ipg_clk_s_SWEN_AND_spdif0_gclkw_t0_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "spdif0_ipg_clk_s_HWEN_AND_spdif0_gclkw_t0_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "spdif0_tx_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "spdif0_tx_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "spdif0_tx_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_SPI"
|
|
tree "ADMA__LPCG_SPI0_IPG_CLK"
|
|
base ad:0x5A400000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_spi0_0,na"
|
|
rbitfld.long 0x00 19. "spi0_ipg_clk_STOP_AND_spi0_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "spi0_ipg_clk_SWEN_AND_spi0_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "spi0_ipg_clk_HWEN_AND_spi0_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "spi0_lpspi_clk_STOP_AND_spi0_lpspi_div_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "spi0_lpspi_clk_SWEN_AND_spi0_lpspi_div_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "spi0_lpspi_clk_HWEN_AND_spi0_lpspi_div_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_SPI1_IPG_CLK"
|
|
base ad:0x5A410000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_spi1_0,na"
|
|
rbitfld.long 0x00 19. "spi1_ipg_clk_STOP_AND_spi1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "spi1_ipg_clk_SWEN_AND_spi1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "spi1_ipg_clk_HWEN_AND_spi1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "spi1_lpspi_clk_STOP_AND_spi1_lpspi_div_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "spi1_lpspi_clk_SWEN_AND_spi1_lpspi_div_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "spi1_lpspi_clk_HWEN_AND_spi1_lpspi_div_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_SPI2_IPG_CLK"
|
|
base ad:0x5A420000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_spi2_0,na"
|
|
rbitfld.long 0x00 19. "spi2_ipg_clk_STOP_AND_spi2_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "spi2_ipg_clk_SWEN_AND_spi2_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "spi2_ipg_clk_HWEN_AND_spi2_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "spi2_lpspi_clk_STOP_AND_spi2_lpspi_div_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "spi2_lpspi_clk_SWEN_AND_spi2_lpspi_div_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "spi2_lpspi_clk_HWEN_AND_spi2_lpspi_div_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_SPI3_IPG_CLK"
|
|
base ad:0x5A430000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_spi3_0,na"
|
|
rbitfld.long 0x00 19. "spi3_ipg_clk_STOP_AND_spi3_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "spi3_ipg_clk_SWEN_AND_spi3_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "spi3_ipg_clk_HWEN_AND_spi3_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "spi3_lpspi_clk_STOP_AND_spi3_lpspi_div_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "spi3_lpspi_clk_SWEN_AND_spi3_lpspi_div_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "spi3_lpspi_clk_HWEN_AND_spi3_lpspi_div_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LPCG_LPCG_SSI"
|
|
base ad:0x5C0C0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_ssi_0,na"
|
|
rbitfld.long 0x00 3. "ssi_port0_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 1. "ssi_port0_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "ssi_port0_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPCG_UART"
|
|
tree "ADMA__LPCG_UART0_IPG_CLK"
|
|
base ad:0x5A460000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_uart0_0,na"
|
|
rbitfld.long 0x00 19. "uart0_ipg_clk_STOP_AND_uart0_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "uart0_ipg_clk_SWEN_AND_uart0_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "uart0_ipg_clk_HWEN_AND_uart0_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "uart0_lpuart_baud_clk_STOP_AND_uart0_lpuart_baud_gated_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "uart0_lpuart_baud_clk_SWEN_AND_uart0_lpuart_baud_gated_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "uart0_lpuart_baud_clk_HWEN_AND_uart0_lpuart_baud_gated_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_UART1_IPG_CLK"
|
|
base ad:0x5A470000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_uart1_0,na"
|
|
rbitfld.long 0x00 19. "uart1_ipg_clk_STOP_AND_uart1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "uart1_ipg_clk_SWEN_AND_uart1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "uart1_ipg_clk_HWEN_AND_uart1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "uart1_lpuart_baud_clk_STOP_AND_uart1_lpuart_baud_gated_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "uart1_lpuart_baud_clk_SWEN_AND_uart1_lpuart_baud_gated_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "uart1_lpuart_baud_clk_HWEN_AND_uart1_lpuart_baud_gated_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_UART2_IPG_CLK"
|
|
base ad:0x5A480000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_uart2_0,na"
|
|
rbitfld.long 0x00 19. "uart2_ipg_clk_STOP_AND_uart2_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "uart2_ipg_clk_SWEN_AND_uart2_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "uart2_ipg_clk_HWEN_AND_uart2_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "uart2_lpuart_baud_clk_STOP_AND_uart2_lpuart_baud_gated_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "uart2_lpuart_baud_clk_SWEN_AND_uart2_lpuart_baud_gated_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "uart2_lpuart_baud_clk_HWEN_AND_uart2_lpuart_baud_gated_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "ADMA__LPCG_UART3_IPG_CLK"
|
|
base ad:0x5A490000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_lpcg_uart3_0,na"
|
|
rbitfld.long 0x00 19. "uart3_ipg_clk_STOP_AND_uart3_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "uart3_ipg_clk_SWEN_AND_uart3_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "uart3_ipg_clk_HWEN_AND_uart3_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "uart3_lpuart_baud_clk_STOP_AND_uart3_lpuart_baud_gated_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "uart3_lpuart_baud_clk_SWEN_AND_uart3_lpuart_baud_gated_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "uart3_lpuart_baud_clk_HWEN_AND_uart3_lpuart_baud_gated_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LPCG_LPI2C"
|
|
base ad:0x33630000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_LPI2C_0,na"
|
|
rbitfld.long 0x00 7. "lpi2c1_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "lpi2c1_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "lpi2c1_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "lpi2c1_lpi2c_clk_HWEN_AND_lpi2c1_lpi2c_div_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPIT"
|
|
base ad:0x33610000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_LPIT_0,na"
|
|
rbitfld.long 0x00 7. "lpit1_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "lpit1_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "lpit1_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "lpit1_ipg_per_clk_HWEN_AND_lpit1_ipg_ungated_per_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_LPUART"
|
|
base ad:0x33620000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_LPUART_0,na"
|
|
rbitfld.long 0x00 7. "lpuart1_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "lpuart1_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "lpuart1_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "lpuart1_lpuart_baud_clk_HWEN_AND_lpuart1_lpuart_baud_gated_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_MISC_CRR5"
|
|
base ad:0x5F0F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MISC_CRR5_0,na"
|
|
rbitfld.long 0x00 19. "hsio_misc_regs_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "hsio_misc_regs_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "hsio_misc_regs_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_MMCAU_HCLK"
|
|
base ad:0x335F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MMCAU_HCLK_0,na"
|
|
rbitfld.long 0x00 3. "cm4_mmcau_hclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 1. "cm4_mmcau_hclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "cm4_mmcau_hclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_PCIEX1"
|
|
base ad:0x5F060000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_PCIEX1_0,na"
|
|
rbitfld.long 0x00 27. "pcie_clk_rst_dbi_axi_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "pcie_clk_rst_dbi_axi_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 24. "pcie_clk_rst_dbi_axi_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "pcie_clk_rst_slv_axi_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "pcie_clk_rst_slv_axi_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "pcie_clk_rst_slv_axi_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "pcie_clk_rst_mstr_axi_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "pcie_clk_rst_mstr_axi_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "pcie_clk_rst_mstr_axi_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_PCIEX1_CRR3"
|
|
base ad:0x5F0D0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_PCIEX1_CRR3_0,na"
|
|
rbitfld.long 0x00 19. "hsio_pciex1_regs_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "hsio_pciex1_regs_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "hsio_pciex1_regs_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_PHYX1"
|
|
base ad:0x5F090000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_PHYX1_0,na"
|
|
rbitfld.long 0x00 19. "pcs_phy_x1_apb_pclk_0_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "pcs_phy_x1_apb_pclk_0_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "pcs_phy_x1_apb_pclk_0_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_PHYX1_CRR1"
|
|
base ad:0x5F0B0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_PHYX1_CRR1_0,na"
|
|
rbitfld.long 0x00 19. "hsio_phyx1_regs_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "hsio_phyx1_regs_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "hsio_phyx1_regs_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_SSI"
|
|
base ad:0x5F070000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_SSI_0,na"
|
|
rbitfld.long 0x00 3. "ssi_pclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 1. "ssi_pclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "ssi_pclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_TCMC_HCLK"
|
|
base ad:0x335E0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_TCMC_HCLK_0,na"
|
|
rbitfld.long 0x00 3. "cm4_tcmc_hclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 1. "cm4_tcmc_hclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "cm4_tcmc_hclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPCG_TPM"
|
|
base ad:0x33600000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_TPM_0,na"
|
|
rbitfld.long 0x00 7. "tpm1_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 5. "tpm1_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "tpm1_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "tpm1_lptpm_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "tpm1_lptpm_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "tpm1_lptpm_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LPI2C"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x5A800000 ad:0x5A810000 ad:0x5A820000 ad:0x5A830000)
|
|
tree "ADMA__LPI2C$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 8.--11. "MRXFIFO,Master Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MTXFIFO,Master Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: NO_EFFECT,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: NO_EFFECT,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Master is disabled in debug mode,1: Master is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Master is enabled in Doze mode,1: Master is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Master Enable" "0: Master logic is disabled,1: Master logic is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MSR,Master Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "MBF,Master Busy Flag" "0: I2C Master is idle,1: I2C Master is busy"
|
|
newline
|
|
eventfld.long 0x00 14. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
eventfld.long 0x00 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout has not occurred or is disabled,1: Pin low timeout has occurred"
|
|
newline
|
|
eventfld.long 0x00 12. "FEF,FIFO Error Flag" "0: No error,1: Master sending or receiving data without a.."
|
|
eventfld.long 0x00 11. "ALF,Arbitration Lost Flag" "0: Master has not lost arbitration,1: Master has lost arbitration"
|
|
newline
|
|
eventfld.long 0x00 10. "NDF,NACK Detect Flag" "0: Unexpected NACK was not detected,1: Unexpected NACK was detected"
|
|
eventfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Master has not generated a STOP condition,1: Master has generated a STOP condition"
|
|
newline
|
|
eventfld.long 0x00 8. "EPF,End Packet Flag" "0: Master has not generated a STOP or Repeated..,1: Master has generated a STOP or Repeated START.."
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data is not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 14. "DMIE,Data Match Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 12. "FEIE,FIFO Error Interrupt Enable" "0: ENABLED,1: DISABLED"
|
|
bitfld.long 0x00 11. "ALIE,Arbitration Lost Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 10. "NDIE,NACK Detect Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 8. "EPIE,End Packet Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO,1: Received data is discarded unless the the.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: ACTIVE_LOW,1: ACTIVE_HIGH"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request input is disabled,1: Host request input is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. "PINCFG,Pin Configuration" "0: 2-pin open drain mode,1: 2-pin output only mode (ultra-fast mode),2: 2-pin push-pull mode,3: 4-pin push-pull mode,4: 2-pin open drain mode with separate LPI2C slave,5: 2-pin output only mode (ultra-fast mode) with..,6: 2-pin push-pull mode with separate LPI2C slave,7: 4-pin push-pull mode (inverted outputs)"
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: Match is enabled (1st data word equals MATCH0..,3: Match is enabled (any data word equals MATCH0..,4: Match is enabled (1st data word equals MATCH0..,5: Match is enabled (any data word equals MATCH0..,6: Match is enabled (1st data word AND MATCH1..,7: Match is enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 10. "TIMECFG,Timeout Configuration" "0: Pin Low Timeout Flag will set if SCL is low..,1: Pin Low Timeout Flag will set if either SCL.."
|
|
bitfld.long 0x00 9. "IGNACK,IGNACK" "0: LPI2C Master will receive ACK and NACK normally,1: LPI2C Master will treat a received NACK as if.."
|
|
newline
|
|
bitfld.long 0x00 8. "AUTOSTOP,Automatic STOP Generation" "0: No effect,1: STOP condition is automatically generated.."
|
|
bitfld.long 0x00 0.--2. "PRESCALE,Prescaler" "0: DIVIDE_BY_1,1: DIVIDE_BY_2,2: DIVIDE_BY_4,3: DIVIDE_BY_8,4: DIVIDE_BY_16,5: DIVIDE_BY_32,6: DIVIDE_BY_64,7: DIVIDE_BY_128"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BUSIDLE,Bus Idle Timeout"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x00 8.--19. 1. "PINLOW,Pin Low Timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MATCH1,Match 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MATCH0,Match 0 Value"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x8 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "MCCR$1,Master Clock Configuration Register $1"
|
|
bitfld.long 0x00 24.--29. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "SETHOLD,Setup Hold Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CLKHI,Clock High Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "CLKLO,Clock Low Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
bitfld.long 0x00 16.--19. "RXWATER,Receive FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "TXWATER,Transmit FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
bitfld.long 0x00 16.--20. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
wgroup.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. "CMD,Command Data" "0: TRANSMIT_DATA_7_THROUGH_0,1: RECEIVE_DATA_7_THROUGH_0_PLUS_ONE,2: GENERATE_STOP_CONDITION,3: RECEIVE_AND_DISCARD_DATA_7_THROUGH_0_PLUS_ONE,4: Generate (repeated) START and transmit..,5: Generate (repeated) START and transmit..,6: Generate (repeated) START and transmit..,7: Generate (repeated) START and transmit.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "MRDR,Master Receive Data Register"
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: Receive FIFO is not empty,1: Receive FIFO is empty"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: NO_EFFECT,1: Receive Data Register is now empty"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: NO_EFFECT,1: Transmit Data Register is now empty"
|
|
newline
|
|
bitfld.long 0x00 5. "FILTDZ,Filter Doze Enable" "0: Filter remains enabled in Doze mode,1: Filter is disabled in Doze mode"
|
|
bitfld.long 0x00 4. "FILTEN,Filter Enable" "0: Disable digital filter and output delay..,1: Enable digital filter and output delay.."
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Slave mode logic is not reset,1: Slave mode logic is reset"
|
|
bitfld.long 0x00 0. "SEN,Slave Enable" "0: I2C Slave mode is disabled,1: I2C Slave mode is enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "SBF,Slave Busy Flag" "0: I2C Slave is idle,1: I2C Slave is busy"
|
|
newline
|
|
rbitfld.long 0x00 15. "SARF,SMBus Alert Response Flag" "0: SMBus Alert Response is disabled or not..,1: SMBus Alert Response is enabled and detected"
|
|
rbitfld.long 0x00 14. "GCF,General Call Flag" "0: Slave has not detected the General Call..,1: Slave has detected the General Call Address"
|
|
newline
|
|
rbitfld.long 0x00 13. "AM1F,Address Match 1 Flag" "0: Have not received an ADDR1 or ADDR0/ADDR1..,1: Have received an ADDR1 or ADDR0/ADDR1 range.."
|
|
rbitfld.long 0x00 12. "AM0F,Address Match 0 Flag" "0: Have not received an ADDR0 matching address,1: Have received an ADDR0 matching address"
|
|
newline
|
|
eventfld.long 0x00 11. "FEF,FIFO Error Flag" "0: FIFO underflow or overflow was not detected,1: FIFO underflow or overflow was detected"
|
|
eventfld.long 0x00 10. "BEF,Bit Error Flag" "0: Slave has not detected a bit error,1: Slave has detected a bit error"
|
|
newline
|
|
eventfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Slave has not detected a STOP condition,1: Slave has detected a STOP condition"
|
|
eventfld.long 0x00 8. "RSF,Repeated Start Flag" "0: Slave has not detected a Repeated START..,1: Slave has detected a Repeated START condition"
|
|
newline
|
|
rbitfld.long 0x00 3. "TAF,Transmit ACK Flag" "0: Transmit ACK/NACK is not required,1: Transmit ACK/NACK is required"
|
|
rbitfld.long 0x00 2. "AVF,Address Valid Flag" "0: Address Status Register is not valid,1: Address Status Register is valid"
|
|
newline
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive data is not ready,1: Receive data is ready"
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 14. "GCIE,General Call Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 13. "AM1F,Address Match 1 Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 12. "AM0IE,Address Match 0 Interrupt Enable" "0: ENABLED,1: DISABLED"
|
|
newline
|
|
bitfld.long 0x00 11. "FEIE,FIFO Error Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 10. "BEIE,Bit Error Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 8. "RSIE,Repeated Start Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 3. "TAIE,Transmit ACK Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 2. "AVIE,Address Valid Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x00 9. "SDDE,Stop Detect DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
bitfld.long 0x00 8. "RSDE,Repeated Start DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "AVDE,Address Valid DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or Address match 1..,3: Address match 0 (10-bit) or Address match 1..,4: Address match 0 (7-bit) or Address match 1..,5: Address match 0 (10-bit) or Address match 1..,6: From Address match 0 (7-bit) to Address match..,7: From Address match 0 (10-bit) to Address.."
|
|
bitfld.long 0x00 13. "HSMEN,High Speed Mode Enable" "0: Disables detection of HS-mode master code,1: Enables detection of HS-mode master code"
|
|
newline
|
|
bitfld.long 0x00 12. "IGNACK,Ignore NACK" "0: Slave will end transfer when NACK is detected,1: Slave will not end transfer when NACK detected"
|
|
bitfld.long 0x00 11. "RXCFG,Receive Data Configuration" "0: Reading the Receive Data register will return..,1: Reading the Receive Data register when the.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXCFG,Transmit Flag Configuration" "0: Transmit Data Flag will only assert during a..,1: Transmit Data Flag will assert whenever the.."
|
|
bitfld.long 0x00 9. "SAEN,SMBus Alert Enable" "0: Disables match on SMBus Alert,1: Enables match on SMBus Alert"
|
|
newline
|
|
bitfld.long 0x00 8. "GCEN,General Call Enable" "0: General Call address is disabled,1: General Call address is enabled"
|
|
bitfld.long 0x00 3. "ACKSTALL,ACK SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXDSTALL,TX Data SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
bitfld.long 0x00 1. "RXSTALL,RX SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADRSTALL,Address SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "CLKHOLD,Clock Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 1. "ADDR1,Address 1 Value"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR0,Address 0 Value"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. "ANV,Address Not Valid" "0: Received Address (RADDR) is valid,1: Received Address (RADDR) is not valid"
|
|
hexmask.long.word 0x00 0.--10. 1. "RADDR,Received Address"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. "TXNACK,Transmit NACK" "0: Write a Transmit ACK for each received word,1: Write a Transmit NACK for each received word"
|
|
wgroup.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "SRDR,Slave Receive Data Register"
|
|
bitfld.long 0x00 15. "SOF,Start Of Frame" "0: Indicates this is not the first data word..,1: Indicates this is the first data word since a.."
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: The Receive Data Register is not empty,1: The Receive Data Register is empty"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
tree.end
|
|
repeat.end
|
|
tree "CM4__LPI2C"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x41230000
|
|
else
|
|
base ad:0x37230000
|
|
endif
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 8.--11. "MRXFIFO,Master Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MTXFIFO,Master Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: NO_EFFECT,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: NO_EFFECT,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Master is disabled in debug mode,1: Master is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Master is enabled in Doze mode,1: Master is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Master Enable" "0: Master logic is disabled,1: Master logic is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MSR,Master Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "MBF,Master Busy Flag" "0: I2C Master is idle,1: I2C Master is busy"
|
|
newline
|
|
eventfld.long 0x00 14. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
eventfld.long 0x00 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout has not occurred or is disabled,1: Pin low timeout has occurred"
|
|
newline
|
|
eventfld.long 0x00 12. "FEF,FIFO Error Flag" "0: No error,1: Master sending or receiving data without a.."
|
|
eventfld.long 0x00 11. "ALF,Arbitration Lost Flag" "0: Master has not lost arbitration,1: Master has lost arbitration"
|
|
newline
|
|
eventfld.long 0x00 10. "NDF,NACK Detect Flag" "0: Unexpected NACK was not detected,1: Unexpected NACK was detected"
|
|
eventfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Master has not generated a STOP condition,1: Master has generated a STOP condition"
|
|
newline
|
|
eventfld.long 0x00 8. "EPF,End Packet Flag" "0: Master has not generated a STOP or Repeated..,1: Master has generated a STOP or Repeated START.."
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data is not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 14. "DMIE,Data Match Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 12. "FEIE,FIFO Error Interrupt Enable" "0: ENABLED,1: DISABLED"
|
|
bitfld.long 0x00 11. "ALIE,Arbitration Lost Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 10. "NDIE,NACK Detect Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 8. "EPIE,End Packet Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO,1: Received data is discarded unless the the.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: ACTIVE_LOW,1: ACTIVE_HIGH"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request input is disabled,1: Host request input is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. "PINCFG,Pin Configuration" "0: 2-pin open drain mode,1: 2-pin output only mode (ultra-fast mode),2: 2-pin push-pull mode,3: 4-pin push-pull mode,4: 2-pin open drain mode with separate LPI2C slave,5: 2-pin output only mode (ultra-fast mode) with..,6: 2-pin push-pull mode with separate LPI2C slave,7: 4-pin push-pull mode (inverted outputs)"
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: Match is enabled (1st data word equals MATCH0..,3: Match is enabled (any data word equals MATCH0..,4: Match is enabled (1st data word equals MATCH0..,5: Match is enabled (any data word equals MATCH0..,6: Match is enabled (1st data word AND MATCH1..,7: Match is enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 10. "TIMECFG,Timeout Configuration" "0: Pin Low Timeout Flag will set if SCL is low..,1: Pin Low Timeout Flag will set if either SCL.."
|
|
bitfld.long 0x00 9. "IGNACK,IGNACK" "0: LPI2C Master will receive ACK and NACK normally,1: LPI2C Master will treat a received NACK as if.."
|
|
newline
|
|
bitfld.long 0x00 8. "AUTOSTOP,Automatic STOP Generation" "0: No effect,1: STOP condition is automatically generated.."
|
|
bitfld.long 0x00 0.--2. "PRESCALE,Prescaler" "0: DIVIDE_BY_1,1: DIVIDE_BY_2,2: DIVIDE_BY_4,3: DIVIDE_BY_8,4: DIVIDE_BY_16,5: DIVIDE_BY_32,6: DIVIDE_BY_64,7: DIVIDE_BY_128"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BUSIDLE,Bus Idle Timeout"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x00 8.--19. 1. "PINLOW,Pin Low Timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MATCH1,Match 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MATCH0,Match 0 Value"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x8 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "MCCR$1,Master Clock Configuration Register $1"
|
|
bitfld.long 0x00 24.--29. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "SETHOLD,Setup Hold Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CLKHI,Clock High Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "CLKLO,Clock Low Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. "CMD,Command Data" "0: TRANSMIT_DATA_7_THROUGH_0,1: RECEIVE_DATA_7_THROUGH_0_PLUS_ONE,2: GENERATE_STOP_CONDITION,3: RECEIVE_AND_DISCARD_DATA_7_THROUGH_0_PLUS_ONE,4: Generate (repeated) START and transmit..,5: Generate (repeated) START and transmit..,6: Generate (repeated) START and transmit..,7: Generate (repeated) START and transmit.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "MRDR,Master Receive Data Register"
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: Receive FIFO is not empty,1: Receive FIFO is empty"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: NO_EFFECT,1: Receive Data Register is now empty"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: NO_EFFECT,1: Transmit Data Register is now empty"
|
|
newline
|
|
bitfld.long 0x00 5. "FILTDZ,Filter Doze Enable" "0: Filter remains enabled in Doze mode,1: Filter is disabled in Doze mode"
|
|
bitfld.long 0x00 4. "FILTEN,Filter Enable" "0: Disable digital filter and output delay..,1: Enable digital filter and output delay.."
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Slave mode logic is not reset,1: Slave mode logic is reset"
|
|
bitfld.long 0x00 0. "SEN,Slave Enable" "0: I2C Slave mode is disabled,1: I2C Slave mode is enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "SBF,Slave Busy Flag" "0: I2C Slave is idle,1: I2C Slave is busy"
|
|
newline
|
|
rbitfld.long 0x00 15. "SARF,SMBus Alert Response Flag" "0: SMBus Alert Response is disabled or not..,1: SMBus Alert Response is enabled and detected"
|
|
rbitfld.long 0x00 14. "GCF,General Call Flag" "0: Slave has not detected the General Call..,1: Slave has detected the General Call Address"
|
|
newline
|
|
rbitfld.long 0x00 13. "AM1F,Address Match 1 Flag" "0: Have not received an ADDR1 or ADDR0/ADDR1..,1: Have received an ADDR1 or ADDR0/ADDR1 range.."
|
|
rbitfld.long 0x00 12. "AM0F,Address Match 0 Flag" "0: Have not received an ADDR0 matching address,1: Have received an ADDR0 matching address"
|
|
newline
|
|
eventfld.long 0x00 11. "FEF,FIFO Error Flag" "0: FIFO underflow or overflow was not detected,1: FIFO underflow or overflow was detected"
|
|
eventfld.long 0x00 10. "BEF,Bit Error Flag" "0: Slave has not detected a bit error,1: Slave has detected a bit error"
|
|
newline
|
|
eventfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Slave has not detected a STOP condition,1: Slave has detected a STOP condition"
|
|
eventfld.long 0x00 8. "RSF,Repeated Start Flag" "0: Slave has not detected a Repeated START..,1: Slave has detected a Repeated START condition"
|
|
newline
|
|
rbitfld.long 0x00 3. "TAF,Transmit ACK Flag" "0: Transmit ACK/NACK is not required,1: Transmit ACK/NACK is required"
|
|
rbitfld.long 0x00 2. "AVF,Address Valid Flag" "0: Address Status Register is not valid,1: Address Status Register is valid"
|
|
newline
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive data is not ready,1: Receive data is ready"
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 14. "GCIE,General Call Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 13. "AM1F,Address Match 1 Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 12. "AM0IE,Address Match 0 Interrupt Enable" "0: ENABLED,1: DISABLED"
|
|
newline
|
|
bitfld.long 0x00 11. "FEIE,FIFO Error Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 10. "BEIE,Bit Error Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 8. "RSIE,Repeated Start Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 3. "TAIE,Transmit ACK Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 2. "AVIE,Address Valid Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x00 2. "AVDE,Address Valid DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or Address match 1..,3: Address match 0 (10-bit) or Address match 1..,4: Address match 0 (7-bit) or Address match 1..,5: Address match 0 (10-bit) or Address match 1..,6: From Address match 0 (7-bit) to Address match..,7: From Address match 0 (10-bit) to Address.."
|
|
bitfld.long 0x00 13. "HSMEN,High Speed Mode Enable" "0: Disables detection of HS-mode master code,1: Enables detection of HS-mode master code"
|
|
newline
|
|
bitfld.long 0x00 12. "IGNACK,Ignore NACK" "0: Slave will end transfer when NACK is detected,1: Slave will not end transfer when NACK detected"
|
|
bitfld.long 0x00 11. "RXCFG,Receive Data Configuration" "0: Reading the Receive Data register will return..,1: Reading the Receive Data register when the.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXCFG,Transmit Flag Configuration" "0: Transmit Data Flag will only assert during a..,1: Transmit Data Flag will assert whenever the.."
|
|
bitfld.long 0x00 9. "SAEN,SMBus Alert Enable" "0: Disables match on SMBus Alert,1: Enables match on SMBus Alert"
|
|
newline
|
|
bitfld.long 0x00 8. "GCEN,General Call Enable" "0: General Call address is disabled,1: General Call address is enabled"
|
|
bitfld.long 0x00 3. "ACKSTALL,ACK SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXDSTALL,TX Data SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
bitfld.long 0x00 1. "RXSTALL,RX SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADRSTALL,Address SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "CLKHOLD,Clock Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 1. "ADDR1,Address 1 Value"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR0,Address 0 Value"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. "ANV,Address Not Valid" "0: Received Address (RADDR) is valid,1: Received Address (RADDR) is not valid"
|
|
hexmask.long.word 0x00 0.--10. 1. "RADDR,Received Address"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. "TXNACK,Transmit NACK" "0: Write a Transmit ACK for each received word,1: Write a Transmit NACK for each received word"
|
|
wgroup.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "SRDR,Slave Receive Data Register"
|
|
bitfld.long 0x00 15. "SOF,Start Of Frame" "0: Indicates this is not the first data word..,1: Indicates this is the first data word since a.."
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: The Receive Data Register is not empty,1: The Receive Data Register is empty"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
tree.end
|
|
tree "SCU__LPI2C"
|
|
base ad:0x33230000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 8.--11. "MRXFIFO,Master Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MTXFIFO,Master Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: NO_EFFECT,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: NO_EFFECT,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Master is disabled in debug mode,1: Master is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Master is enabled in Doze mode,1: Master is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Master Enable" "0: Master logic is disabled,1: Master logic is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MSR,Master Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "MBF,Master Busy Flag" "0: I2C Master is idle,1: I2C Master is busy"
|
|
newline
|
|
eventfld.long 0x00 14. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
eventfld.long 0x00 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout has not occurred or is disabled,1: Pin low timeout has occurred"
|
|
newline
|
|
eventfld.long 0x00 12. "FEF,FIFO Error Flag" "0: No error,1: Master sending or receiving data without a.."
|
|
eventfld.long 0x00 11. "ALF,Arbitration Lost Flag" "0: Master has not lost arbitration,1: Master has lost arbitration"
|
|
newline
|
|
eventfld.long 0x00 10. "NDF,NACK Detect Flag" "0: Unexpected NACK was not detected,1: Unexpected NACK was detected"
|
|
eventfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Master has not generated a STOP condition,1: Master has generated a STOP condition"
|
|
newline
|
|
eventfld.long 0x00 8. "EPF,End Packet Flag" "0: Master has not generated a STOP or Repeated..,1: Master has generated a STOP or Repeated START.."
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data is not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 14. "DMIE,Data Match Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 12. "FEIE,FIFO Error Interrupt Enable" "0: ENABLED,1: DISABLED"
|
|
bitfld.long 0x00 11. "ALIE,Arbitration Lost Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 10. "NDIE,NACK Detect Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 8. "EPIE,End Packet Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO,1: Received data is discarded unless the the.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: ACTIVE_LOW,1: ACTIVE_HIGH"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request input is disabled,1: Host request input is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. "PINCFG,Pin Configuration" "0: 2-pin open drain mode,1: 2-pin output only mode (ultra-fast mode),2: 2-pin push-pull mode,3: 4-pin push-pull mode,4: 2-pin open drain mode with separate LPI2C slave,5: 2-pin output only mode (ultra-fast mode) with..,6: 2-pin push-pull mode with separate LPI2C slave,7: 4-pin push-pull mode (inverted outputs)"
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: Match is enabled (1st data word equals MATCH0..,3: Match is enabled (any data word equals MATCH0..,4: Match is enabled (1st data word equals MATCH0..,5: Match is enabled (any data word equals MATCH0..,6: Match is enabled (1st data word AND MATCH1..,7: Match is enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 10. "TIMECFG,Timeout Configuration" "0: Pin Low Timeout Flag will set if SCL is low..,1: Pin Low Timeout Flag will set if either SCL.."
|
|
bitfld.long 0x00 9. "IGNACK,IGNACK" "0: LPI2C Master will receive ACK and NACK normally,1: LPI2C Master will treat a received NACK as if.."
|
|
newline
|
|
bitfld.long 0x00 8. "AUTOSTOP,Automatic STOP Generation" "0: No effect,1: STOP condition is automatically generated.."
|
|
bitfld.long 0x00 0.--2. "PRESCALE,Prescaler" "0: DIVIDE_BY_1,1: DIVIDE_BY_2,2: DIVIDE_BY_4,3: DIVIDE_BY_8,4: DIVIDE_BY_16,5: DIVIDE_BY_32,6: DIVIDE_BY_64,7: DIVIDE_BY_128"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BUSIDLE,Bus Idle Timeout"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x00 8.--19. 1. "PINLOW,Pin Low Timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MATCH1,Match 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MATCH0,Match 0 Value"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x8 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "MCCR$1,Master Clock Configuration Register $1"
|
|
bitfld.long 0x00 24.--29. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "SETHOLD,Setup Hold Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CLKHI,Clock High Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "CLKLO,Clock Low Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. "CMD,Command Data" "0: TRANSMIT_DATA_7_THROUGH_0,1: RECEIVE_DATA_7_THROUGH_0_PLUS_ONE,2: GENERATE_STOP_CONDITION,3: RECEIVE_AND_DISCARD_DATA_7_THROUGH_0_PLUS_ONE,4: Generate (repeated) START and transmit..,5: Generate (repeated) START and transmit..,6: Generate (repeated) START and transmit..,7: Generate (repeated) START and transmit.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "MRDR,Master Receive Data Register"
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: Receive FIFO is not empty,1: Receive FIFO is empty"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: NO_EFFECT,1: Receive Data Register is now empty"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: NO_EFFECT,1: Transmit Data Register is now empty"
|
|
newline
|
|
bitfld.long 0x00 5. "FILTDZ,Filter Doze Enable" "0: Filter remains enabled in Doze mode,1: Filter is disabled in Doze mode"
|
|
bitfld.long 0x00 4. "FILTEN,Filter Enable" "0: Disable digital filter and output delay..,1: Enable digital filter and output delay.."
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Slave mode logic is not reset,1: Slave mode logic is reset"
|
|
bitfld.long 0x00 0. "SEN,Slave Enable" "0: I2C Slave mode is disabled,1: I2C Slave mode is enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "SBF,Slave Busy Flag" "0: I2C Slave is idle,1: I2C Slave is busy"
|
|
newline
|
|
rbitfld.long 0x00 15. "SARF,SMBus Alert Response Flag" "0: SMBus Alert Response is disabled or not..,1: SMBus Alert Response is enabled and detected"
|
|
rbitfld.long 0x00 14. "GCF,General Call Flag" "0: Slave has not detected the General Call..,1: Slave has detected the General Call Address"
|
|
newline
|
|
rbitfld.long 0x00 13. "AM1F,Address Match 1 Flag" "0: Have not received an ADDR1 or ADDR0/ADDR1..,1: Have received an ADDR1 or ADDR0/ADDR1 range.."
|
|
rbitfld.long 0x00 12. "AM0F,Address Match 0 Flag" "0: Have not received an ADDR0 matching address,1: Have received an ADDR0 matching address"
|
|
newline
|
|
eventfld.long 0x00 11. "FEF,FIFO Error Flag" "0: FIFO underflow or overflow was not detected,1: FIFO underflow or overflow was detected"
|
|
eventfld.long 0x00 10. "BEF,Bit Error Flag" "0: Slave has not detected a bit error,1: Slave has detected a bit error"
|
|
newline
|
|
eventfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Slave has not detected a STOP condition,1: Slave has detected a STOP condition"
|
|
eventfld.long 0x00 8. "RSF,Repeated Start Flag" "0: Slave has not detected a Repeated START..,1: Slave has detected a Repeated START condition"
|
|
newline
|
|
rbitfld.long 0x00 3. "TAF,Transmit ACK Flag" "0: Transmit ACK/NACK is not required,1: Transmit ACK/NACK is required"
|
|
rbitfld.long 0x00 2. "AVF,Address Valid Flag" "0: Address Status Register is not valid,1: Address Status Register is valid"
|
|
newline
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive data is not ready,1: Receive data is ready"
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 14. "GCIE,General Call Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 13. "AM1F,Address Match 1 Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 12. "AM0IE,Address Match 0 Interrupt Enable" "0: ENABLED,1: DISABLED"
|
|
newline
|
|
bitfld.long 0x00 11. "FEIE,FIFO Error Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 10. "BEIE,Bit Error Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 8. "RSIE,Repeated Start Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 3. "TAIE,Transmit ACK Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 2. "AVIE,Address Valid Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x00 2. "AVDE,Address Valid DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or Address match 1..,3: Address match 0 (10-bit) or Address match 1..,4: Address match 0 (7-bit) or Address match 1..,5: Address match 0 (10-bit) or Address match 1..,6: From Address match 0 (7-bit) to Address match..,7: From Address match 0 (10-bit) to Address.."
|
|
bitfld.long 0x00 13. "HSMEN,High Speed Mode Enable" "0: Disables detection of HS-mode master code,1: Enables detection of HS-mode master code"
|
|
newline
|
|
bitfld.long 0x00 12. "IGNACK,Ignore NACK" "0: Slave will end transfer when NACK is detected,1: Slave will not end transfer when NACK detected"
|
|
bitfld.long 0x00 11. "RXCFG,Receive Data Configuration" "0: Reading the Receive Data register will return..,1: Reading the Receive Data register when the.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXCFG,Transmit Flag Configuration" "0: Transmit Data Flag will only assert during a..,1: Transmit Data Flag will assert whenever the.."
|
|
bitfld.long 0x00 9. "SAEN,SMBus Alert Enable" "0: Disables match on SMBus Alert,1: Enables match on SMBus Alert"
|
|
newline
|
|
bitfld.long 0x00 8. "GCEN,General Call Enable" "0: General Call address is disabled,1: General Call address is enabled"
|
|
bitfld.long 0x00 3. "ACKSTALL,ACK SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXDSTALL,TX Data SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
bitfld.long 0x00 1. "RXSTALL,RX SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADRSTALL,Address SCL Stall" "0: Clock stretching is disabled,1: Clock stretching is enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "CLKHOLD,Clock Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 1. "ADDR1,Address 1 Value"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR0,Address 0 Value"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. "ANV,Address Not Valid" "0: Received Address (RADDR) is valid,1: Received Address (RADDR) is not valid"
|
|
hexmask.long.word 0x00 0.--10. 1. "RADDR,Received Address"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. "TXNACK,Transmit NACK" "0: Write a Transmit ACK for each received word,1: Write a Transmit NACK for each received word"
|
|
wgroup.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "SRDR,Slave Receive Data Register"
|
|
bitfld.long 0x00 15. "SOF,Start Of Frame" "0: Indicates this is not the first data word..,1: Indicates this is the first data word since a.."
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: The Receive Data Register is not empty,1: The Receive Data Register is empty"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
tree.end
|
|
tree.end
|
|
tree "LPSPI"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x5A000000 ad:0x5A010000 ad:0x5A020000 ad:0x5A030000)
|
|
tree "ADMA__LPSPI$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Module Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: NO_EFFECT,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: NO_EFFECT,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: LPSPI module is disabled in debug mode,1: LPSPI module is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze Mode Enable" "0: LPSPI module is enabled in Doze mode,1: LPSPI module is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
bitfld.long 0x00 0. "MEN,Module Enable" "0: Module is disabled,1: Module is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy"
|
|
eventfld.long 0x00 13. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
newline
|
|
eventfld.long 0x00 12. "REF,Receive Error Flag" "0: Receive FIFO has not overflowed,1: Receive FIFO has overflowed"
|
|
eventfld.long 0x00 11. "TEF,Transmit Error Flag" "0: Transmit FIFO underrun has not occurred,1: Transmit FIFO underrun has occurred"
|
|
newline
|
|
eventfld.long 0x00 10. "TCF,Transfer Complete Flag" "0: All transfers have not completed,1: All transfers have completed"
|
|
eventfld.long 0x00 9. "FCF,Frame Complete Flag" "0: Frame transfer has not completed,1: Frame transfer has completed"
|
|
newline
|
|
eventfld.long 0x00 8. "WCF,Word Complete Flag" "0: Transfer of a received word has not yet..,1: Transfer of a received word has completed"
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "DMIE,Data Match Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 12. "REIE,Receive Error Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 11. "TEIE,Transmit Error Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 10. "TCIE,Transfer Complete Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 9. "FCIE,Frame Complete Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 8. "WCIE,Word Complete Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DER,DMA Enable Register"
|
|
bitfld.long 0x00 9. "FCDE,Frame Complete DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the Data.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are configured for chip select..,1: PCS[3:2] are configured for half-duplex 4-bit.."
|
|
bitfld.long 0x00 26. "OUTCFG,Output Configuration" "0: Output data retains last value when chip..,1: Output data is tristated when chip select is.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data and SOUT is used..,1: SIN is used for both input and output data..,2: SOUT is used for both input and output data..,3: SOUT is used for input data and SIN is used.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: 010b - Match is enabled if 1st data word..,3: 011b - Match is enabled if any data word..,4: 100b - Match is enabled if 1st data word..,5: 101b - Match is enabled if any data word..,6: 110b - Match is enabled if (1st data word AND..,7: 111b - Match is enabled if (any data word AND.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PCSPOL,Peripheral Chip Select Polarity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. "NOSTALL,No Stall" "0: Transfers will stall when the transmit FIFO..,1: Transfers will not stall allowing transmit.."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTOPCS,Automatic PCS" "0: Automatic PCS generation is disabled,1: Automatic PCS generation is enabled"
|
|
bitfld.long 0x00 1. "SAMPLE,Sample Point" "0: Input data is sampled on SCK edge,1: Input data is sampled on delayed SCK edge"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER,Master Mode" "0: SLAVE_MODE,1: MASTER_MODE"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH0,Match 0 Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMR1,Data Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH1,Match 1 Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCKPCS,SCK-to-PCS Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSSCK,PCS-to-SCK Delay"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DBT,Delay Between Transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCKDIV,SCK Divider"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,The FIFO Control register contains the RXWATER and TXWATER control fields"
|
|
bitfld.long 0x00 16.--21. "RXWATER,Receive FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "TXWATER,Transmit FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "RXCOUNT,Receive FIFO Count"
|
|
hexmask.long.byte 0x00 0.--6. 1. "TXCOUNT,Transmit FIFO Count"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
|
|
bitfld.long 0x00 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
|
|
newline
|
|
bitfld.long 0x00 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
bitfld.long 0x00 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using LPSPI_PCS[0],1: Transfer using LPSPI_PCS[1],2: Transfer using LPSPI_PCS[2],3: Transfer using LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
|
|
bitfld.long 0x00 22. "BYSW,Byte Swap" "0: Byte swap is disabled,1: Byte swap is enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CONT,Continuous Transfer" "0: Continuous transfer is disabled,1: Continuous transfer is enabled"
|
|
bitfld.long 0x00 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked"
|
|
bitfld.long 0x00 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "WIDTH,Transfer Width" "0: 1 bit transfer,1: 2 bit transfer,2: 4 bit transfer,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. "FRAMESZ,Frame Size"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. "RXEMPTY,RX FIFO Empty" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
bitfld.long 0x00 0. "SOF,Start Of Frame" "0: Subsequent data word received after LPSPI_PCS..,1: First data word received after LPSPI_PCS.."
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Receive Data"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LPTPM (TPM)"
|
|
tree "CM4__TPM"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x41200000
|
|
else
|
|
base ad:0x37200000
|
|
endif
|
|
sif cpuis("IMX8D?L-CM4")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WIDTH,Counter Width"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRIG,Trigger Count"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHAN,Channel Count"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,TPM Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC,Status and Control"
|
|
bitfld.long 0x00 8. "DMA,DMA Enable" "0: Disables DMA transfers,1: Enables DMA transfers"
|
|
eventfld.long 0x00 7. "TOF,Timer Overflow Flag" "0: TPM counter has not overflowed,1: TPM counter has overflowed"
|
|
newline
|
|
bitfld.long 0x00 6. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
|
|
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: TPM counter operates in up counting mode,1: TPM counter operates in up-down counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CMOD,Clock Mode Selection" "0: TPM counter is disabled,1: TPM counter increments on every TPM counter..,2: TPM counter increments on rising edge of..,3: TPM counter increments on rising edge of the.."
|
|
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Counter value"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MOD,Modulo"
|
|
hexmask.long 0x00 0.--31. 1. "MOD,Modulo value"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "STATUS,Capture and Compare Status"
|
|
eventfld.long 0x00 8. "TOF,Timer Overflow Flag" "0: TPM counter has not overflowed,1: TPM counter has overflowed"
|
|
eventfld.long 0x00 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
eventfld.long 0x00 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
eventfld.long 0x00 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
eventfld.long 0x00 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
eventfld.long 0x00 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
eventfld.long 0x00 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "COMBINE,Combine Channel Register"
|
|
bitfld.long 0x00 17. "COMSWAP2,Combine Channels 4 and 5 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 16. "COMBINE2,Combine Channels 4 and 5" "0: Channels 4 and 5 are independent,1: Channels 4 and 5 are combined"
|
|
newline
|
|
bitfld.long 0x00 9. "COMSWAP1,Combine Channels 2 and 3 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 8. "COMBINE1,Combine Channels 2 and 3" "0: Channels 2 and 3 are independent,1: Channels 2 and 3 are combined"
|
|
newline
|
|
bitfld.long 0x00 1. "COMSWAP0,Combine Channel 0 and 1 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 0. "COMBINE0,Combine Channels 0 and 1" "0: Channels 0 and 1 are independent,1: Channels 0 and 1 are combined"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRIG,Channel Trigger"
|
|
bitfld.long 0x00 5. "TRIG5,Channel 5 Trigger" "0: No effect,1: Configures trigger input 1 to be used by.."
|
|
bitfld.long 0x00 4. "TRIG4,Channel 4 Trigger" "0: No effect,1: Configures trigger input 0 to be used by.."
|
|
newline
|
|
bitfld.long 0x00 3. "TRIG3,Channel 3 Trigger" "0: No effect,1: Configures trigger input 1 to be used by.."
|
|
bitfld.long 0x00 2. "TRIG2,Channel 2 Trigger" "0: No effect,1: Configures trigger input 0 to be used by.."
|
|
newline
|
|
bitfld.long 0x00 1. "TRIG1,Channel 1 Trigger" "0: No effect,1: Configures trigger input 1 to be used by.."
|
|
bitfld.long 0x00 0. "TRIG0,Channel 0 Trigger" "0: No effect,1: Configures trigger input 0 to be used by.."
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "POL,Channel Polarity"
|
|
bitfld.long 0x00 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,Filter Control"
|
|
bitfld.long 0x00 20.--23. "CH5FVAL,Channel 5 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "CH4FVAL,Channel 4 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "CH3FVAL,Channel 3 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "CH2FVAL,Channel 2 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CH1FVAL,Channel 1 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CH0FVAL,Channel 0 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "QDCTRL,Quadrature Decoder Control and Status"
|
|
bitfld.long 0x00 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase encoding mode,1: Count and direction encoding mode"
|
|
rbitfld.long 0x00 2. "QUADIR,Counter Direction in Quadrature Decode Mode" "0: Counter direction is decreasing (counter..,1: Counter direction is increasing (counter.."
|
|
newline
|
|
rbitfld.long 0x00 1. "TOFDIR,TOFDIR" "0: TOF bit was set on the bottom of counting,1: TOF bit was set on the top of counting"
|
|
bitfld.long 0x00 0. "QUADEN,QUADEN" "0: Quadrature decoder mode is disabled,1: Quadrature decoder mode is enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. "TRGSEL,Trigger Select" "?,1: Channel 0 pin input capture,2: Channel 1 pin input capture,3: Channel 0 or Channel 1 pin input capture,4: Channel 2 pin input capture,5: Channel 0 or Channel 2 pin input capture,6: Channel 1 or Channel 2 pin input capture,7: Channel 0 or Channel 1 or Channel 2 pin input..,8: Channel 3 pin input capture,9: Channel 0 or Channel 3 pin input capture,10: Channel 1 or Channel 3 pin input capture,11: Channel 0 or Channel 1 or Channel 3 pin..,12: Channel 2 or Channel 3 pin input capture,13: Channel 0 or Channel 2 or Channel 3 pin..,14: Channel 1 or Channel 2 or Channel 3 pin..,15: Channel 0 or Channel 1 or Channel 2 or.."
|
|
bitfld.long 0x00 23. "TRGSRC,Trigger Source" "0: Trigger source selected by TRGSEL is external,1: Trigger source selected by TRGSEL is internal.."
|
|
newline
|
|
bitfld.long 0x00 22. "TRGPOL,Trigger Polarity" "0: Trigger is active high,1: Trigger is active low"
|
|
bitfld.long 0x00 19. "CPOT,Counter Pause On Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CROT,Counter Reload On Trigger" "0: Counter is not reloaded due to a rising edge..,1: Counter is reloaded when a rising edge is.."
|
|
bitfld.long 0x00 17. "CSOO,Counter Stop On Overflow" "0: TPM counter continues incrementing or..,1: TPM counter stops incrementing or.."
|
|
newline
|
|
bitfld.long 0x00 16. "CSOT,Counter Start on Trigger" "0: TPM counter starts to increment immediately..,1: TPM counter only starts to increment when it.."
|
|
bitfld.long 0x00 9. "GTBEEN,Global time base enable" "0: All channels use the internally generated TPM..,1: All channels use an externally generated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GTBSYNC,Global Time Base Synchronization" "0: Global timebase synchronization disabled,1: Global timebase synchronization enabled"
|
|
bitfld.long 0x00 6.--7. "DBGMODE,Debug Mode" "0: TPM counter is paused and does not increment..,?,?,3: TPM counter continues in debug mode"
|
|
newline
|
|
bitfld.long 0x00 5. "DOZEEN,Doze Enable" "0: Internal TPM counter continues in Doze mode,1: Internal TPM counter is paused and does not.."
|
|
endif
|
|
repeat 6. (increment 0 1)(increment 0 0x8)
|
|
tree "CHANNEL[$1]"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "CSC,Channel (n) Status and Control"
|
|
eventfld.long 0x00 7. "CHF,Channel Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 6. "CHIE,Channel Interrupt Enable" "0: Disable channel interrupts,1: Enable channel interrupts"
|
|
newline
|
|
bitfld.long 0x00 5. "MSB,Channel Mode Select" "0,1"
|
|
bitfld.long 0x00 4. "MSA,Channel Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ELSB,Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 2. "ELSA,Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "CV,Channel (n) Value"
|
|
hexmask.long 0x00 0.--31. 1. "VAL,Channel Value"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SCU__TPM"
|
|
base ad:0x33200000
|
|
sif cpuis("IMX8D?L-CM4")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WIDTH,Counter Width"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRIG,Trigger Count"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHAN,Channel Count"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,TPM Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC,Status and Control"
|
|
bitfld.long 0x00 8. "DMA,DMA Enable" "0: Disables DMA transfers,1: Enables DMA transfers"
|
|
eventfld.long 0x00 7. "TOF,Timer Overflow Flag" "0: TPM counter has not overflowed,1: TPM counter has overflowed"
|
|
newline
|
|
bitfld.long 0x00 6. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
|
|
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: TPM counter operates in up counting mode,1: TPM counter operates in up-down counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CMOD,Clock Mode Selection" "0: TPM counter is disabled,1: TPM counter increments on every TPM counter..,2: TPM counter increments on rising edge of..,3: TPM counter increments on rising edge of the.."
|
|
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Counter value"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MOD,Modulo"
|
|
hexmask.long 0x00 0.--31. 1. "MOD,Modulo value"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "STATUS,Capture and Compare Status"
|
|
eventfld.long 0x00 8. "TOF,Timer Overflow Flag" "0: TPM counter has not overflowed,1: TPM counter has overflowed"
|
|
eventfld.long 0x00 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
eventfld.long 0x00 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
eventfld.long 0x00 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
eventfld.long 0x00 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
eventfld.long 0x00 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
eventfld.long 0x00 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "COMBINE,Combine Channel Register"
|
|
bitfld.long 0x00 17. "COMSWAP2,Combine Channels 4 and 5 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 16. "COMBINE2,Combine Channels 4 and 5" "0: Channels 4 and 5 are independent,1: Channels 4 and 5 are combined"
|
|
newline
|
|
bitfld.long 0x00 9. "COMSWAP1,Combine Channels 2 and 3 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 8. "COMBINE1,Combine Channels 2 and 3" "0: Channels 2 and 3 are independent,1: Channels 2 and 3 are combined"
|
|
newline
|
|
bitfld.long 0x00 1. "COMSWAP0,Combine Channel 0 and 1 Swap" "0: Even channel is used for input capture and..,1: Odd channel is used for input capture and 1st.."
|
|
bitfld.long 0x00 0. "COMBINE0,Combine Channels 0 and 1" "0: Channels 0 and 1 are independent,1: Channels 0 and 1 are combined"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRIG,Channel Trigger"
|
|
bitfld.long 0x00 5. "TRIG5,Channel 5 Trigger" "0: No effect,1: Configures trigger input 1 to be used by.."
|
|
bitfld.long 0x00 4. "TRIG4,Channel 4 Trigger" "0: No effect,1: Configures trigger input 0 to be used by.."
|
|
newline
|
|
bitfld.long 0x00 3. "TRIG3,Channel 3 Trigger" "0: No effect,1: Configures trigger input 1 to be used by.."
|
|
bitfld.long 0x00 2. "TRIG2,Channel 2 Trigger" "0: No effect,1: Configures trigger input 0 to be used by.."
|
|
newline
|
|
bitfld.long 0x00 1. "TRIG1,Channel 1 Trigger" "0: No effect,1: Configures trigger input 1 to be used by.."
|
|
bitfld.long 0x00 0. "TRIG0,Channel 0 Trigger" "0: No effect,1: Configures trigger input 0 to be used by.."
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "POL,Channel Polarity"
|
|
bitfld.long 0x00 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
newline
|
|
bitfld.long 0x00 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
bitfld.long 0x00 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "FILTER,Filter Control"
|
|
bitfld.long 0x00 20.--23. "CH5FVAL,Channel 5 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "CH4FVAL,Channel 4 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "CH3FVAL,Channel 3 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "CH2FVAL,Channel 2 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CH1FVAL,Channel 1 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "CH0FVAL,Channel 0 Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "QDCTRL,Quadrature Decoder Control and Status"
|
|
bitfld.long 0x00 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase encoding mode,1: Count and direction encoding mode"
|
|
rbitfld.long 0x00 2. "QUADIR,Counter Direction in Quadrature Decode Mode" "0: Counter direction is decreasing (counter..,1: Counter direction is increasing (counter.."
|
|
newline
|
|
rbitfld.long 0x00 1. "TOFDIR,TOFDIR" "0: TOF bit was set on the bottom of counting,1: TOF bit was set on the top of counting"
|
|
bitfld.long 0x00 0. "QUADEN,QUADEN" "0: Quadrature decoder mode is disabled,1: Quadrature decoder mode is enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CONF,Configuration"
|
|
bitfld.long 0x00 24.--27. "TRGSEL,Trigger Select" "?,1: Channel 0 pin input capture,2: Channel 1 pin input capture,3: Channel 0 or Channel 1 pin input capture,4: Channel 2 pin input capture,5: Channel 0 or Channel 2 pin input capture,6: Channel 1 or Channel 2 pin input capture,7: Channel 0 or Channel 1 or Channel 2 pin input..,8: Channel 3 pin input capture,9: Channel 0 or Channel 3 pin input capture,10: Channel 1 or Channel 3 pin input capture,11: Channel 0 or Channel 1 or Channel 3 pin..,12: Channel 2 or Channel 3 pin input capture,13: Channel 0 or Channel 2 or Channel 3 pin..,14: Channel 1 or Channel 2 or Channel 3 pin..,15: Channel 0 or Channel 1 or Channel 2 or.."
|
|
bitfld.long 0x00 23. "TRGSRC,Trigger Source" "0: Trigger source selected by TRGSEL is external,1: Trigger source selected by TRGSEL is internal.."
|
|
newline
|
|
bitfld.long 0x00 22. "TRGPOL,Trigger Polarity" "0: Trigger is active high,1: Trigger is active low"
|
|
bitfld.long 0x00 19. "CPOT,Counter Pause On Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "CROT,Counter Reload On Trigger" "0: Counter is not reloaded due to a rising edge..,1: Counter is reloaded when a rising edge is.."
|
|
bitfld.long 0x00 17. "CSOO,Counter Stop On Overflow" "0: TPM counter continues incrementing or..,1: TPM counter stops incrementing or.."
|
|
newline
|
|
bitfld.long 0x00 16. "CSOT,Counter Start on Trigger" "0: TPM counter starts to increment immediately..,1: TPM counter only starts to increment when it.."
|
|
bitfld.long 0x00 9. "GTBEEN,Global time base enable" "0: All channels use the internally generated TPM..,1: All channels use an externally generated.."
|
|
newline
|
|
bitfld.long 0x00 8. "GTBSYNC,Global Time Base Synchronization" "0: Global timebase synchronization disabled,1: Global timebase synchronization enabled"
|
|
bitfld.long 0x00 6.--7. "DBGMODE,Debug Mode" "0: TPM counter is paused and does not increment..,?,?,3: TPM counter continues in debug mode"
|
|
newline
|
|
bitfld.long 0x00 5. "DOZEEN,Doze Enable" "0: Internal TPM counter continues in Doze mode,1: Internal TPM counter is paused and does not.."
|
|
endif
|
|
repeat 6. (increment 0 1)(increment 0 0x8)
|
|
tree "CHANNEL[$1]"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
group.long ($2+0x20)++0x03
|
|
line.long 0x00 "CSC,Channel (n) Status and Control"
|
|
eventfld.long 0x00 7. "CHF,Channel Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 6. "CHIE,Channel Interrupt Enable" "0: Disable channel interrupts,1: Enable channel interrupts"
|
|
newline
|
|
bitfld.long 0x00 5. "MSB,Channel Mode Select" "0,1"
|
|
bitfld.long 0x00 4. "MSA,Channel Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ELSB,Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 2. "ELSA,Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "CV,Channel (n) Value"
|
|
hexmask.long 0x00 0.--31. 1. "VAL,Channel Value"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "LPUART"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x5A060000 ad:0x5A070000 ad:0x5A080000 ad:0x5A090000)
|
|
tree "ADMA__LPUART$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RX pin input,2: Input trigger is used instead of CTS_B pin..,3: Input trigger is used to modulate the TX pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 7-bit to 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0: Writing 0 to this field results in an..,?,?,3: Oversampling ratio of 4 requires BOTHEDGE to..,4: Oversampling ratio of 5 requires BOTHEDGE to..,5: Oversampling ratio of 6 requires BOTHEDGE to..,6: Oversampling ratio of 7 requires BOTHEDGE to..,7: Oversampling ratio of 8,8: Oversampling ratio of 9,9: Oversampling ratio of 10,10: Oversampling ratio of 11,11: Oversampling ratio of 12,12: Oversampling ratio of 13,13: Oversampling ratio of 14,14: Oversampling ratio of 15,15: Oversampling ratio of 16,16: Oversampling ratio of 17,17: Oversampling ratio of 18,18: Oversampling ratio of 19,19: Oversampling ratio of 20,20: Oversampling ratio of 21,21: Oversampling ratio of 22,22: Oversampling ratio of 23,23: Oversampling ratio of 24,24: Oversampling ratio of 25,25: Oversampling ratio of 26,26: Oversampling ratio of 27,27: Oversampling ratio of 28,28: Oversampling ratio of 29,29: Oversampling ratio of 30,30: Oversampling ratio of 31,31: Oversampling ratio of 32"
|
|
newline
|
|
bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RIDMAE,Receiver Idle DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,3: Enables RWU on Data Match and Match On/Off.."
|
|
newline
|
|
bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
newline
|
|
bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from STAT[LBKDIF] flag..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from STAT[RXEDGIF] are..,1: Hardware interrupt is requested when.."
|
|
newline
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
eventfld.long 0x00 30. "RXEDGIF,RX Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
newline
|
|
bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
|
|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
|
|
bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
|
|
newline
|
|
bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: LIN break detect is disabled normal break..,1: LIN break detect is enabled"
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (RX input not idle)"
|
|
newline
|
|
rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
|
|
rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
|
|
eventfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
|
|
newline
|
|
eventfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
|
|
eventfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
|
|
newline
|
|
eventfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
eventfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
|
|
newline
|
|
eventfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
|
|
eventfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
|
|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TXDIR,TX Pin Direction in Single-Wire Mode" "0: TX pin is an input in single-wire mode,1: TX pin is an output in single-wire mode"
|
|
bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
|
|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
|
|
newline
|
|
bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
|
|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
|
|
newline
|
|
bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
|
|
bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
|
|
newline
|
|
bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
|
|
bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
|
|
newline
|
|
bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
|
|
bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
|
|
bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
|
|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "M7,7-Bit Mode Select" "0: Receiver and transmitter use 8-bit to 10-bit..,1: Receiver and transmitter use 7-bit data.."
|
|
bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
|
|
newline
|
|
bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RX and TX use separate pins,1: Loop mode or single-wire mode where.."
|
|
bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the TX pin is.."
|
|
bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
|
|
newline
|
|
bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
|
|
bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
|
|
bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DATA,LPUART Data Register"
|
|
rbitfld.long 0x00 15. "NOISY,NOISY" "0: The dataword was received without noise,1: The data was received with noise"
|
|
rbitfld.long 0x00 14. "PARITYE,PARITYE" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
|
|
newline
|
|
bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
|
|
rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
|
|
newline
|
|
rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
|
|
bitfld.long 0x00 9. "R9T9,R9T9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "R8T8,R8T8" "0,1"
|
|
bitfld.long 0x00 7. "R7T7,R7T7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "R6T6,R6T6" "0,1"
|
|
bitfld.long 0x00 5. "R5T5,R5T5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "R4T4,R4T4" "0,1"
|
|
bitfld.long 0x00 3. "R3T3,R3T3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "R2T2,R2T2" "0,1"
|
|
bitfld.long 0x00 1. "R1T1,R1T1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "R0T0,R0T0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODIR,LPUART Modem IrDA Register"
|
|
bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
|
|
bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "RTSWATER,Receive RTS Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the CTS_B pin,1: CTS input is the inverted Receiver Match result"
|
|
newline
|
|
bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,1: RTS is deasserted if the receiver data.."
|
|
newline
|
|
bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
|
|
bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
eventfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
eventfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
|
|
bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
|
|
newline
|
|
bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO/Buffer depth = 1 dataword,1: Transmit FIFO/Buffer depth = 4 datawords,2: Transmit FIFO/Buffer depth = 8 datawords,3: Transmit FIFO/Buffer depth = 16 datawords,4: Transmit FIFO/Buffer depth = 32 datawords,5: Transmit FIFO/Buffer depth = 64 datawords,6: Transmit FIFO/Buffer depth = 128 datawords,7: Transmit FIFO/Buffer depth = 256 datawords"
|
|
bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO/Buffer depth = 1 dataword,1: Receive FIFO/Buffer depth = 4 datawords,2: Receive FIFO/Buffer depth = 8 datawords,3: Receive FIFO/Buffer depth = 16 datawords,4: Receive FIFO/Buffer depth = 32 datawords,5: Receive FIFO/Buffer depth = 64 datawords,6: Receive FIFO/Buffer depth = 128 datawords,7: Receive FIFO/Buffer depth = 256 datawords"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. "RXCOUNT,Receive Counter"
|
|
bitfld.long 0x00 16.--21. "RXWATER,Receive Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "TXCOUNT,Transmit Counter"
|
|
bitfld.long 0x00 0.--5. "TXWATER,Transmit Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
repeat.end
|
|
tree "CM4__LPUART"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x41220000
|
|
else
|
|
base ad:0x37220000
|
|
endif
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RX pin input,2: Input trigger is used instead of CTS_B pin..,3: Input trigger is used to modulate the TX pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 7-bit to 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0: Writing 0 to this field results in an..,?,?,3: Oversampling ratio of 4 requires BOTHEDGE to..,4: Oversampling ratio of 5 requires BOTHEDGE to..,5: Oversampling ratio of 6 requires BOTHEDGE to..,6: Oversampling ratio of 7 requires BOTHEDGE to..,7: Oversampling ratio of 8,8: Oversampling ratio of 9,9: Oversampling ratio of 10,10: Oversampling ratio of 11,11: Oversampling ratio of 12,12: Oversampling ratio of 13,13: Oversampling ratio of 14,14: Oversampling ratio of 15,15: Oversampling ratio of 16,16: Oversampling ratio of 17,17: Oversampling ratio of 18,18: Oversampling ratio of 19,19: Oversampling ratio of 20,20: Oversampling ratio of 21,21: Oversampling ratio of 22,22: Oversampling ratio of 23,23: Oversampling ratio of 24,24: Oversampling ratio of 25,25: Oversampling ratio of 26,26: Oversampling ratio of 27,27: Oversampling ratio of 28,28: Oversampling ratio of 29,29: Oversampling ratio of 30,30: Oversampling ratio of 31,31: Oversampling ratio of 32"
|
|
newline
|
|
bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RIDMAE,Receiver Idle DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,3: Enables RWU on Data Match and Match On/Off.."
|
|
newline
|
|
bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
newline
|
|
bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from STAT[LBKDIF] flag..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from STAT[RXEDGIF] are..,1: Hardware interrupt is requested when.."
|
|
newline
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
eventfld.long 0x00 30. "RXEDGIF,RX Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
newline
|
|
bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
|
|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
|
|
bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
|
|
newline
|
|
bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: LIN break detect is disabled normal break..,1: LIN break detect is enabled"
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (RX input not idle)"
|
|
newline
|
|
rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
|
|
rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
|
|
eventfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
|
|
newline
|
|
eventfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
|
|
eventfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
|
|
newline
|
|
eventfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
eventfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
|
|
newline
|
|
eventfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
|
|
eventfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
|
|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TXDIR,TX Pin Direction in Single-Wire Mode" "0: TX pin is an input in single-wire mode,1: TX pin is an output in single-wire mode"
|
|
bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
|
|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
|
|
newline
|
|
bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
|
|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
|
|
newline
|
|
bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
|
|
bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
|
|
newline
|
|
bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
|
|
bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
|
|
newline
|
|
bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
|
|
bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
|
|
bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
|
|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "M7,7-Bit Mode Select" "0: Receiver and transmitter use 8-bit to 10-bit..,1: Receiver and transmitter use 7-bit data.."
|
|
bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
|
|
newline
|
|
bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RX and TX use separate pins,1: Loop mode or single-wire mode where.."
|
|
bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the TX pin is.."
|
|
bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
|
|
newline
|
|
bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
|
|
bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
|
|
bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DATA,LPUART Data Register"
|
|
rbitfld.long 0x00 15. "NOISY,NOISY" "0: The dataword was received without noise,1: The data was received with noise"
|
|
rbitfld.long 0x00 14. "PARITYE,PARITYE" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
|
|
newline
|
|
bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
|
|
rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
|
|
newline
|
|
rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
|
|
bitfld.long 0x00 9. "R9T9,R9T9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "R8T8,R8T8" "0,1"
|
|
bitfld.long 0x00 7. "R7T7,R7T7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "R6T6,R6T6" "0,1"
|
|
bitfld.long 0x00 5. "R5T5,R5T5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "R4T4,R4T4" "0,1"
|
|
bitfld.long 0x00 3. "R3T3,R3T3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "R2T2,R2T2" "0,1"
|
|
bitfld.long 0x00 1. "R1T1,R1T1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "R0T0,R0T0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODIR,LPUART Modem IrDA Register"
|
|
bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
|
|
bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "RTSWATER,Receive RTS Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the CTS_B pin,1: CTS input is the inverted Receiver Match result"
|
|
newline
|
|
bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,1: RTS is deasserted if the receiver data.."
|
|
newline
|
|
bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
|
|
bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
eventfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
eventfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
|
|
bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
|
|
newline
|
|
bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO/Buffer depth = 1 dataword,1: Transmit FIFO/Buffer depth = 4 datawords,2: Transmit FIFO/Buffer depth = 8 datawords,3: Transmit FIFO/Buffer depth = 16 datawords,4: Transmit FIFO/Buffer depth = 32 datawords,5: Transmit FIFO/Buffer depth = 64 datawords,6: Transmit FIFO/Buffer depth = 128 datawords,7: Transmit FIFO/Buffer depth = 256 datawords"
|
|
bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO/Buffer depth = 1 dataword,1: Receive FIFO/Buffer depth = 4 datawords,2: Receive FIFO/Buffer depth = 8 datawords,3: Receive FIFO/Buffer depth = 16 datawords,4: Receive FIFO/Buffer depth = 32 datawords,5: Receive FIFO/Buffer depth = 64 datawords,6: Receive FIFO/Buffer depth = 128 datawords,7: Receive FIFO/Buffer depth = 256 datawords"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
rbitfld.long 0x00 24.--29. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--20. "RXWATER,Receive Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 8.--13. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--4. "TXWATER,Transmit Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "SCU__LPUART"
|
|
base ad:0x33220000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RX pin input,2: Input trigger is used instead of CTS_B pin..,3: Input trigger is used to modulate the TX pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 7-bit to 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0: Writing 0 to this field results in an..,?,?,3: Oversampling ratio of 4 requires BOTHEDGE to..,4: Oversampling ratio of 5 requires BOTHEDGE to..,5: Oversampling ratio of 6 requires BOTHEDGE to..,6: Oversampling ratio of 7 requires BOTHEDGE to..,7: Oversampling ratio of 8,8: Oversampling ratio of 9,9: Oversampling ratio of 10,10: Oversampling ratio of 11,11: Oversampling ratio of 12,12: Oversampling ratio of 13,13: Oversampling ratio of 14,14: Oversampling ratio of 15,15: Oversampling ratio of 16,16: Oversampling ratio of 17,17: Oversampling ratio of 18,18: Oversampling ratio of 19,19: Oversampling ratio of 20,20: Oversampling ratio of 21,21: Oversampling ratio of 22,22: Oversampling ratio of 23,23: Oversampling ratio of 24,24: Oversampling ratio of 25,25: Oversampling ratio of 26,26: Oversampling ratio of 27,27: Oversampling ratio of 28,28: Oversampling ratio of 29,29: Oversampling ratio of 30,30: Oversampling ratio of 31,31: Oversampling ratio of 32"
|
|
newline
|
|
bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RIDMAE,Receiver Idle DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,3: Enables RWU on Data Match and Match On/Off.."
|
|
newline
|
|
bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
newline
|
|
bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from STAT[LBKDIF] flag..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from STAT[RXEDGIF] are..,1: Hardware interrupt is requested when.."
|
|
newline
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
eventfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
eventfld.long 0x00 30. "RXEDGIF,RX Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
newline
|
|
bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
|
|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
|
|
bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
|
|
newline
|
|
bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: LIN break detect is disabled normal break..,1: LIN break detect is enabled"
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (RX input not idle)"
|
|
newline
|
|
rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
|
|
rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
|
|
eventfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
|
|
newline
|
|
eventfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
|
|
eventfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
|
|
newline
|
|
eventfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
eventfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
|
|
newline
|
|
eventfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
|
|
eventfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
|
|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TXDIR,TX Pin Direction in Single-Wire Mode" "0: TX pin is an input in single-wire mode,1: TX pin is an output in single-wire mode"
|
|
bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
|
|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
|
|
newline
|
|
bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
|
|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
|
|
newline
|
|
bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
|
|
bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
|
|
newline
|
|
bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
|
|
bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
|
|
newline
|
|
bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
|
|
bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
|
|
bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
|
|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "M7,7-Bit Mode Select" "0: Receiver and transmitter use 8-bit to 10-bit..,1: Receiver and transmitter use 7-bit data.."
|
|
bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
|
|
newline
|
|
bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RX and TX use separate pins,1: Loop mode or single-wire mode where.."
|
|
bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the TX pin is.."
|
|
bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
|
|
newline
|
|
bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
|
|
bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
|
|
bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DATA,LPUART Data Register"
|
|
rbitfld.long 0x00 15. "NOISY,NOISY" "0: The dataword was received without noise,1: The data was received with noise"
|
|
rbitfld.long 0x00 14. "PARITYE,PARITYE" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
|
|
newline
|
|
bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
|
|
rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
|
|
newline
|
|
rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
|
|
bitfld.long 0x00 9. "R9T9,R9T9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "R8T8,R8T8" "0,1"
|
|
bitfld.long 0x00 7. "R7T7,R7T7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "R6T6,R6T6" "0,1"
|
|
bitfld.long 0x00 5. "R5T5,R5T5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "R4T4,R4T4" "0,1"
|
|
bitfld.long 0x00 3. "R3T3,R3T3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "R2T2,R2T2" "0,1"
|
|
bitfld.long 0x00 1. "R1T1,R1T1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "R0T0,R0T0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODIR,LPUART Modem IrDA Register"
|
|
bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
|
|
bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "RTSWATER,Receive RTS Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the CTS_B pin,1: CTS input is the inverted Receiver Match result"
|
|
newline
|
|
bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,1: RTS is deasserted if the receiver data.."
|
|
newline
|
|
bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
|
|
bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
eventfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
eventfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
|
|
bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
|
|
newline
|
|
bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO/Buffer depth = 1 dataword,1: Transmit FIFO/Buffer depth = 4 datawords,2: Transmit FIFO/Buffer depth = 8 datawords,3: Transmit FIFO/Buffer depth = 16 datawords,4: Transmit FIFO/Buffer depth = 32 datawords,5: Transmit FIFO/Buffer depth = 64 datawords,6: Transmit FIFO/Buffer depth = 128 datawords,7: Transmit FIFO/Buffer depth = 256 datawords"
|
|
bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO/Buffer depth = 1 dataword,1: Receive FIFO/Buffer depth = 4 datawords,2: Receive FIFO/Buffer depth = 8 datawords,3: Receive FIFO/Buffer depth = 16 datawords,4: Receive FIFO/Buffer depth = 32 datawords,5: Receive FIFO/Buffer depth = 64 datawords,6: Receive FIFO/Buffer depth = 128 datawords,7: Receive FIFO/Buffer depth = 256 datawords"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
rbitfld.long 0x00 24.--29. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--20. "RXWATER,Receive Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.long 0x00 8.--13. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--4. "TXWATER,Transmit Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree.end
|
|
tree "LSIO_LPCG_GPIO"
|
|
tree "LSIO__LPCG_GPIO0"
|
|
base ad:0x5D480000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_GPIO0_0,na"
|
|
rbitfld.long 0x00 19. "gpio0_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "gpio0_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpio0_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_GPIO1"
|
|
base ad:0x5D490000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_GPIO1_0,na"
|
|
rbitfld.long 0x00 19. "gpio1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "gpio1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpio1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_GPIO2"
|
|
base ad:0x5D4A0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_GPIO2_0,na"
|
|
rbitfld.long 0x00 19. "gpio2_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "gpio2_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpio2_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_GPIO3"
|
|
base ad:0x5D4B0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_GPIO3_0,na"
|
|
rbitfld.long 0x00 19. "gpio3_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "gpio3_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpio3_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_GPIO4"
|
|
base ad:0x5D4C0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_GPIO4_0,na"
|
|
rbitfld.long 0x00 19. "gpio4_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "gpio4_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpio4_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_GPIO5"
|
|
base ad:0x5D4D0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_GPIO5_0,na"
|
|
rbitfld.long 0x00 19. "gpio5_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "gpio5_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpio5_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_GPIO6"
|
|
base ad:0x5D4E0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_GPIO6_0,na"
|
|
rbitfld.long 0x00 19. "gpio6_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "gpio6_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpio6_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_GPIO7"
|
|
base ad:0x5D4F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_GPIO7_0,na"
|
|
rbitfld.long 0x00 19. "gpio7_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "gpio7_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpio7_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LSIO_LPCG_GPT"
|
|
tree "LSIO__LPCG_GPT0"
|
|
base ad:0x5D540000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_GPT0_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_gpt0_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_gpt0_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_gpt0_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_gpt0_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_gpt0_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_gpt0_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "gpt0_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "gpt0_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpt0_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper0_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper0_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper0_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "gpt0_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "gpt0_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "gpt0_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "gpt0_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "gpt0_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "gpt0_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_GPT1"
|
|
base ad:0x5D550000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_GPT1_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_gpt1_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_gpt1_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_gpt1_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_gpt1_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_gpt1_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_gpt1_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "gpt1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "gpt1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpt1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper1_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper1_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper1_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "gpt1_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "gpt1_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "gpt1_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "gpt1_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "gpt1_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "gpt1_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_GPT2"
|
|
base ad:0x5D560000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_GPT2_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_gpt2_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_gpt2_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_gpt2_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_gpt2_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_gpt2_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_gpt2_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "gpt2_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "gpt2_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpt2_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper2_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper2_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper2_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "gpt2_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "gpt2_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "gpt2_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "gpt2_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "gpt2_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "gpt2_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_GPT3"
|
|
base ad:0x5D570000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_GPT3_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_gpt3_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_gpt3_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_gpt3_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_gpt3_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_gpt3_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_gpt3_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "gpt3_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "gpt3_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpt3_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper3_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper3_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper3_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "gpt3_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "gpt3_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "gpt3_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "gpt3_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "gpt3_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "gpt3_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_GPT4"
|
|
base ad:0x5D580000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_GPT4_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_gpt4_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_gpt4_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_gpt4_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_gpt4_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_gpt4_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_gpt4_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "gpt4_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "gpt4_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "gpt4_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper4_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper4_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper4_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "gpt4_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "gpt4_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "gpt4_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "gpt4_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "gpt4_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "gpt4_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LSIO_LPCG_KPP"
|
|
base ad:0x5D5A0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_KPP_0,na"
|
|
rbitfld.long 0x00 19. "kpp_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "kpp_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "kpp_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "ccm_ckil_sync_wrapper13_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ccm_ckil_sync_wrapper13_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 0. "ccm_ckil_sync_wrapper13_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU10_DSP"
|
|
base ad:0x5D6E0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU10_DSP_0,na"
|
|
rbitfld.long 0x00 19. "mu10_ipg_clk_s_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu10_ipg_clk_s_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu10_ipg_clk_s_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu10_ipg_clk_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu10_ipg_clk_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu10_ipg_clk_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU10_MCU"
|
|
base ad:0x5D650000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU10_MCU_0,na"
|
|
rbitfld.long 0x00 19. "mu10_ipg_clk_s_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu10_ipg_clk_s_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu10_ipg_clk_s_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu10_ipg_clk_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu10_ipg_clk_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu10_ipg_clk_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU11_DSP"
|
|
base ad:0x5D6F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU11_DSP_0,na"
|
|
rbitfld.long 0x00 19. "mu11_ipg_clk_s_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu11_ipg_clk_s_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu11_ipg_clk_s_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu11_ipg_clk_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu11_ipg_clk_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu11_ipg_clk_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU11_MCU"
|
|
base ad:0x5D660000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU11_MCU_0,na"
|
|
rbitfld.long 0x00 19. "mu11_ipg_clk_s_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu11_ipg_clk_s_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu11_ipg_clk_s_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu11_ipg_clk_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu11_ipg_clk_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu11_ipg_clk_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU12_DSP"
|
|
base ad:0x5D700000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU12_DSP_0,na"
|
|
rbitfld.long 0x00 19. "mu12_ipg_clk_s_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu12_ipg_clk_s_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu12_ipg_clk_s_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu12_ipg_clk_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu12_ipg_clk_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu12_ipg_clk_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU12_MCU"
|
|
base ad:0x5D670000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU12_MCU_0,na"
|
|
rbitfld.long 0x00 19. "mu12_ipg_clk_s_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu12_ipg_clk_s_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu12_ipg_clk_s_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu12_ipg_clk_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu12_ipg_clk_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu12_ipg_clk_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU13_DSP"
|
|
base ad:0x5D710000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU13_DSP_0,na"
|
|
rbitfld.long 0x00 19. "mu13_ipg_clk_s_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu13_ipg_clk_s_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu13_ipg_clk_s_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu13_ipg_clk_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu13_ipg_clk_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu13_ipg_clk_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU13_MCU"
|
|
base ad:0x5D680000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU13_MCU_0,na"
|
|
rbitfld.long 0x00 19. "mu13_ipg_clk_s_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu13_ipg_clk_s_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu13_ipg_clk_s_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu13_ipg_clk_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu13_ipg_clk_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu13_ipg_clk_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU5_DSP"
|
|
base ad:0x5D690000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU5_DSP_0,na"
|
|
rbitfld.long 0x00 19. "mu5_ipg_clk_s_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu5_ipg_clk_s_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu5_ipg_clk_s_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu5_ipg_clk_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu5_ipg_clk_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu5_ipg_clk_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU5_MCU"
|
|
base ad:0x5D600000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU5_MCU_0,na"
|
|
rbitfld.long 0x00 19. "mu5_ipg_clk_s_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu5_ipg_clk_s_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu5_ipg_clk_s_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu5_ipg_clk_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu5_ipg_clk_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu5_ipg_clk_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU6_DSP"
|
|
base ad:0x5D6A0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU6_DSP_0,na"
|
|
rbitfld.long 0x00 19. "mu6_ipg_clk_s_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu6_ipg_clk_s_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu6_ipg_clk_s_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu6_ipg_clk_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu6_ipg_clk_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu6_ipg_clk_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU6_MCU"
|
|
base ad:0x5D610000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU6_MCU_0,na"
|
|
rbitfld.long 0x00 19. "mu6_ipg_clk_s_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu6_ipg_clk_s_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu6_ipg_clk_s_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu6_ipg_clk_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu6_ipg_clk_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu6_ipg_clk_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU7_DSP"
|
|
base ad:0x5D6B0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU7_DSP_0,na"
|
|
rbitfld.long 0x00 19. "mu7_ipg_clk_s_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu7_ipg_clk_s_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu7_ipg_clk_s_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu7_ipg_clk_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu7_ipg_clk_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu7_ipg_clk_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU7_MCU"
|
|
base ad:0x5D620000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU7_MCU_0,na"
|
|
rbitfld.long 0x00 19. "mu7_ipg_clk_s_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu7_ipg_clk_s_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu7_ipg_clk_s_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu7_ipg_clk_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu7_ipg_clk_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu7_ipg_clk_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU8_DSP"
|
|
base ad:0x5D6C0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU8_DSP_0,na"
|
|
rbitfld.long 0x00 19. "mu8_ipg_clk_s_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu8_ipg_clk_s_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu8_ipg_clk_s_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu8_ipg_clk_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu8_ipg_clk_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu8_ipg_clk_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU8_MCU"
|
|
base ad:0x5D630000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU8_MCU_0,na"
|
|
rbitfld.long 0x00 19. "mu8_ipg_clk_s_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu8_ipg_clk_s_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu8_ipg_clk_s_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu8_ipg_clk_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu8_ipg_clk_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu8_ipg_clk_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU9_DSP"
|
|
base ad:0x5D6D0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU9_DSP_0,na"
|
|
rbitfld.long 0x00 19. "mu9_ipg_clk_s_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu9_ipg_clk_s_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu9_ipg_clk_s_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu9_ipg_clk_dsp_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu9_ipg_clk_dsp_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu9_ipg_clk_dsp_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_MU9_MCU"
|
|
base ad:0x5D640000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_MU9_MCU_0,na"
|
|
rbitfld.long 0x00 19. "mu9_ipg_clk_s_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "mu9_ipg_clk_s_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "mu9_ipg_clk_s_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "mu9_ipg_clk_mcu_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "mu9_ipg_clk_mcu_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "mu9_ipg_clk_mcu_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_OCRAM"
|
|
base ad:0x5D590000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_OCRAM_0,na"
|
|
rbitfld.long 0x00 7. "ocram_mem_wrapper_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 5. "ocram_mem_wrapper_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "ocram_mem_wrapper_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "ocram_ctrl_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ocram_ctrl_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "ocram_ctrl_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO_LPCG_PWM"
|
|
tree "LSIO__LPCG_PWM0"
|
|
base ad:0x5D400000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_PWM0_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_pwm0_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_pwm0_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_pwm0_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_pwm0_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_pwm0_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_pwm0_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "pwm0_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "pwm0_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "pwm0_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper5_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper5_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper5_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "pwm0_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "pwm0_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "pwm0_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "pwm0_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "pwm0_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "pwm0_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_PWM1"
|
|
base ad:0x5D410000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_PWM1_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_pwm1_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_pwm1_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_pwm1_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_pwm1_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_pwm1_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_pwm1_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "pwm1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "pwm1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "pwm1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper6_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper6_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper6_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "pwm1_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "pwm1_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "pwm1_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "pwm1_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "pwm1_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "pwm1_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_PWM2"
|
|
base ad:0x5D420000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_PWM2_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_pwm2_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_pwm2_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_pwm2_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_pwm2_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_pwm2_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_pwm2_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "pwm2_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "pwm2_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "pwm2_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper7_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper7_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper7_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "pwm2_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "pwm2_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "pwm2_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "pwm2_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "pwm2_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "pwm2_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_PWM3"
|
|
base ad:0x5D430000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_PWM3_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_pwm3_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_pwm3_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_pwm3_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_pwm3_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_pwm3_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_pwm3_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "pwm3_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "pwm3_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "pwm3_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper8_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper8_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper8_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "pwm3_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "pwm3_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "pwm3_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "pwm3_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "pwm3_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "pwm3_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_PWM4"
|
|
base ad:0x5D440000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_PWM4_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_pwm4_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_pwm4_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_pwm4_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_pwm4_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_pwm4_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_pwm4_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "pwm4_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "pwm4_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "pwm4_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper9_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper9_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper9_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "pwm4_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "pwm4_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "pwm4_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "pwm4_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "pwm4_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "pwm4_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_PWM5"
|
|
base ad:0x5D450000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_PWM5_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_pwm5_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_pwm5_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_pwm5_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_pwm5_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_pwm5_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_pwm5_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "pwm5_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "pwm5_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "pwm5_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper10_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper10_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper10_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "pwm5_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "pwm5_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "pwm5_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "pwm5_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "pwm5_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "pwm5_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_PWM6"
|
|
base ad:0x5D460000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_PWM6_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_pwm6_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_pwm6_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_pwm6_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_pwm6_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_pwm6_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_pwm6_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "pwm6_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "pwm6_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "pwm6_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper11_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper11_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper11_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "pwm6_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "pwm6_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "pwm6_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "pwm6_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "pwm6_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "pwm6_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_PWM7"
|
|
base ad:0x5D470000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_IPS_SYNC_PWM7_0,na"
|
|
rbitfld.long 0x00 27. "ips_sync_pwm7_ipg_master_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "ips_sync_pwm7_ipg_master_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "ips_sync_pwm7_ipg_master_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 23. "ips_sync_pwm7_ipg_slave_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "ips_sync_pwm7_ipg_slave_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 20. "ips_sync_pwm7_ipg_slave_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "pwm7_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "pwm7_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 16. "pwm7_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 11. "ccm_ckil_sync_wrapper12_clk_in_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ccm_ckil_sync_wrapper12_clk_in_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 8. "ccm_ckil_sync_wrapper12_clk_in_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 7. "pwm7_ipg_clk_highfreq_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "pwm7_ipg_clk_highfreq_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 4. "pwm7_ipg_clk_highfreq_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 3. "pwm7_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "pwm7_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 0. "pwm7_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "LSIO_LPCG_QSPI"
|
|
tree "LSIO__LPCG_QSPI0"
|
|
base ad:0x5D520000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_QSPI0_0,na"
|
|
rbitfld.long 0x00 27. "qspi0_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 25. "qspi0_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "qspi0_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 23. "qspi0_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "qspi0_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 20. "qspi0_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "qspi0_hclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "qspi0_hclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "qspi0_hclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "qspi0_ipg_clk_sfck_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "qspi0_ipg_clk_sfck_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "qspi0_ipg_clk_sfck_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree "LSIO__LPCG_QSPI1"
|
|
base ad:0x5D530000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LPCG_QSPI1_0,na"
|
|
rbitfld.long 0x00 27. "qspi1_ipg_clk_s_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 25. "qspi1_ipg_clk_s_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
bitfld.long 0x00 24. "qspi1_ipg_clk_s_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 23. "qspi1_ipg_clk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "qspi1_ipg_clk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 20. "qspi1_ipg_clk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
newline
|
|
rbitfld.long 0x00 19. "qspi1_hclk_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
bitfld.long 0x00 17. "qspi1_hclk_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
newline
|
|
rbitfld.long 0x00 16. "qspi1_hclk_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
rbitfld.long 0x00 3. "qspi1_ipg_clk_sfck_STOP,show clock root status 1 means clock stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "qspi1_ipg_clk_sfck_SWEN,Software Enable" "0: Disable SW clock regardless of HWEN,1: Enable SW clock gating"
|
|
rbitfld.long 0x00 0. "qspi1_ipg_clk_sfck_HWEN,Hardware Enable" "0: Ignore all HW signal (if swen!=0 it&apos s..,1: Enable HW automatic gating"
|
|
tree.end
|
|
tree.end
|
|
tree "MUA (Messaging Unit Processor A-side)"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x37440000 ad:0x37450000 ad:0x37460000 ad:0x37470000) (list ad:0x41440000 ad:0x41450000 ad:0x41460000 ad:0x41470000)
|
|
tree "CM4__MU0_A$1"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base $3
|
|
else
|
|
base $2
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
repeat.end
|
|
tree "CM4__MU1_A"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x41480000
|
|
else
|
|
base ad:0x37480000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU0_A"
|
|
base ad:0x5D1B0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU1_A"
|
|
base ad:0x5D1C0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU2_A"
|
|
base ad:0x5D1D0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU3_A"
|
|
base ad:0x5D1E0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU4_A"
|
|
base ad:0x5D1F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU5_A"
|
|
base ad:0x5D200000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU6_A"
|
|
base ad:0x5D210000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU7_A"
|
|
base ad:0x5D220000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU8_A"
|
|
base ad:0x5D230000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU9_A"
|
|
base ad:0x5D240000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU10_A"
|
|
base ad:0x5D250000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU11_A"
|
|
base ad:0x5D260000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU12_A"
|
|
base ad:0x5D270000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree "LSIO__MU13_A"
|
|
base ad:0x5D280000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x33440000 ad:0x33450000 ad:0x33460000 ad:0x33470000)
|
|
tree "SCU__MU0_A$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
repeat.end
|
|
tree "SCU__MU1_A"
|
|
base ad:0x33480000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATR0,Processor A Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ATR0,ATR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATR1,Processor A Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ATR1,ATR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATR2,Processor A Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ATR2,ATR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATR3,Processor A Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ATR3,ATR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ARR0,Processor A Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ARR0,ARR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ARR1,Processor A Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "ARR1,ARR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ARR2,Processor A Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "ARR2,ARR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ARR3,Processor A Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "ARR3,ARR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ASR,Processor A Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor A general purpose interrupt n is..,1: Processor A general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: ARRn register is not full (default),1: ARRn register has received data from BTRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: ATRn register is not empty,1: ATRn register is empty (default),?..."
|
|
bitfld.long 0x00 9. "BRDIP,BRDIP" "0: The Processor A general purpose interrupt 3..,1: The Processor B-side is out of reset"
|
|
newline
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor A..,1: Processor A initiated flags update processing"
|
|
bitfld.long 0x00 7. "BRS,BRS" "0: The Processor B-side of the MU is not in reset,1: The Processor B-side of the MU is in reset"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor A-side event is not pending..,1: The Processor A-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: BAFn bit in BCR register is written 0 (default),1: BAFn bit in BCR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ACR,Processor A Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor A General Interrupt n,1: Enables Processor A General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor A Receive Interrupt n,1: Enables Processor A Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor A Transmit Interrupt n,1: Enables Processor A Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor A General Interrupt n is not..,1: Processor A General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 6. "BRDIE,BRDIE" "0: Disables the Processor A General Purpose..,1: Enables Processor A General Purpose Interrupt.."
|
|
bitfld.long 0x00 5. "MUR,MUR" "0: N/A,1: Asserts the Processor A MU reset"
|
|
newline
|
|
bitfld.long 0x00 4. "BHR,BHR" "0: De-assert Hardware reset to the Processor B,1: Assert Hardware reset to the Processor B"
|
|
bitfld.long 0x00 0.--2. "ABFn,ABFn" "0: N/A,1: Asserts the Processor A MU reset,?..."
|
|
tree.end
|
|
tree.end
|
|
tree "MUB (Messaging Unit Processor B-side)"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x37430000 ad:0x37430080 ad:0x37430100 ad:0x37430180) (list ad:0x41430000 ad:0x41430080 ad:0x41430100 ad:0x41430180)
|
|
tree "CM4__MU0_B$1"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base $3
|
|
else
|
|
base $2
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BTR0,Processor B Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BTR0,BTR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BTR1,Processor B Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BTR1,BTR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "BTR2,Processor B Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BTR2,BTR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BTR3,Processor B Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BTR3,BTR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BRR0,Processor B Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BRR0,BRR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "BRR1,Processor B Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BRR1,BRR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BRR2,Processor B Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BRR2,BRR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "BRR3,Processor B Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BRR3,BRR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BSR,Processor B Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor B general purpose interrupt n is..,1: Processor B general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: BRRn register is not full (default),1: BRRn register has received data from ATRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: BTRn register is not empty,1: BTRn register is empty (default),?..."
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor B..,1: Processor B initiated flags update processing"
|
|
newline
|
|
bitfld.long 0x00 7. "ARS,ARS" "0: The Processor A or the Processor A-side of..,1: The Processor A or the Processor A-side of.."
|
|
bitfld.long 0x00 5.--6. "APM,APM" "0: The System is in Run Mode,1: The System is in WAIT Mode,?,3: The System is in STOP Mode"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor B-side event is not pending..,1: The Processor B-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: ABFn bit in ACR register is written 0 (default),1: ABFn bit in ACR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR,Processor B Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor B General Interrupt n,1: Enables Processor B General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor B Receive Interrupt n,1: Enables Processor B Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor B Transmit Interrupt n,1: Enables Processor B Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor B General Interrupt n is not..,1: Processor B General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "HRM,HRM" "0: BHR bit in ACR is not masked enables the..,1: BHR bit in ACR is masked disables the.."
|
|
bitfld.long 0x00 0.--2. "BAFn,BAFn" "0: Clears the Fn bit in the ASR register,1: Sets the Fn bit in the ASR register,?..."
|
|
tree.end
|
|
repeat.end
|
|
tree "LSIO__MU5_B"
|
|
base ad:0x5D290000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BTR0,Processor B Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BTR0,BTR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BTR1,Processor B Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BTR1,BTR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "BTR2,Processor B Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BTR2,BTR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BTR3,Processor B Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BTR3,BTR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BRR0,Processor B Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BRR0,BRR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "BRR1,Processor B Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BRR1,BRR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BRR2,Processor B Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BRR2,BRR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "BRR3,Processor B Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BRR3,BRR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BSR,Processor B Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor B general purpose interrupt n is..,1: Processor B general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: BRRn register is not full (default),1: BRRn register has received data from ATRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: BTRn register is not empty,1: BTRn register is empty (default),?..."
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor B..,1: Processor B initiated flags update processing"
|
|
newline
|
|
bitfld.long 0x00 7. "ARS,ARS" "0: The Processor A or the Processor A-side of..,1: The Processor A or the Processor A-side of.."
|
|
bitfld.long 0x00 5.--6. "APM,APM" "0: The System is in Run Mode,1: The System is in WAIT Mode,?,3: The System is in STOP Mode"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor B-side event is not pending..,1: The Processor B-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: ABFn bit in ACR register is written 0 (default),1: ABFn bit in ACR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR,Processor B Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor B General Interrupt n,1: Enables Processor B General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor B Receive Interrupt n,1: Enables Processor B Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor B Transmit Interrupt n,1: Enables Processor B Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor B General Interrupt n is not..,1: Processor B General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "HRM,HRM" "0: BHR bit in ACR is not masked enables the..,1: BHR bit in ACR is masked disables the.."
|
|
bitfld.long 0x00 0.--2. "BAFn,BAFn" "0: Clears the Fn bit in the ASR register,1: Sets the Fn bit in the ASR register,?..."
|
|
tree.end
|
|
tree "LSIO__MU6_B"
|
|
base ad:0x5D2A0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BTR0,Processor B Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BTR0,BTR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BTR1,Processor B Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BTR1,BTR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "BTR2,Processor B Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BTR2,BTR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BTR3,Processor B Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BTR3,BTR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BRR0,Processor B Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BRR0,BRR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "BRR1,Processor B Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BRR1,BRR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BRR2,Processor B Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BRR2,BRR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "BRR3,Processor B Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BRR3,BRR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BSR,Processor B Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor B general purpose interrupt n is..,1: Processor B general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: BRRn register is not full (default),1: BRRn register has received data from ATRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: BTRn register is not empty,1: BTRn register is empty (default),?..."
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor B..,1: Processor B initiated flags update processing"
|
|
newline
|
|
bitfld.long 0x00 7. "ARS,ARS" "0: The Processor A or the Processor A-side of..,1: The Processor A or the Processor A-side of.."
|
|
bitfld.long 0x00 5.--6. "APM,APM" "0: The System is in Run Mode,1: The System is in WAIT Mode,?,3: The System is in STOP Mode"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor B-side event is not pending..,1: The Processor B-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: ABFn bit in ACR register is written 0 (default),1: ABFn bit in ACR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR,Processor B Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor B General Interrupt n,1: Enables Processor B General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor B Receive Interrupt n,1: Enables Processor B Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor B Transmit Interrupt n,1: Enables Processor B Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor B General Interrupt n is not..,1: Processor B General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "HRM,HRM" "0: BHR bit in ACR is not masked enables the..,1: BHR bit in ACR is masked disables the.."
|
|
bitfld.long 0x00 0.--2. "BAFn,BAFn" "0: Clears the Fn bit in the ASR register,1: Sets the Fn bit in the ASR register,?..."
|
|
tree.end
|
|
tree "LSIO__MU7_B"
|
|
base ad:0x5D2B0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BTR0,Processor B Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BTR0,BTR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BTR1,Processor B Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BTR1,BTR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "BTR2,Processor B Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BTR2,BTR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BTR3,Processor B Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BTR3,BTR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BRR0,Processor B Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BRR0,BRR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "BRR1,Processor B Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BRR1,BRR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BRR2,Processor B Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BRR2,BRR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "BRR3,Processor B Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BRR3,BRR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BSR,Processor B Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor B general purpose interrupt n is..,1: Processor B general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: BRRn register is not full (default),1: BRRn register has received data from ATRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: BTRn register is not empty,1: BTRn register is empty (default),?..."
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor B..,1: Processor B initiated flags update processing"
|
|
newline
|
|
bitfld.long 0x00 7. "ARS,ARS" "0: The Processor A or the Processor A-side of..,1: The Processor A or the Processor A-side of.."
|
|
bitfld.long 0x00 5.--6. "APM,APM" "0: The System is in Run Mode,1: The System is in WAIT Mode,?,3: The System is in STOP Mode"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor B-side event is not pending..,1: The Processor B-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: ABFn bit in ACR register is written 0 (default),1: ABFn bit in ACR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR,Processor B Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor B General Interrupt n,1: Enables Processor B General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor B Receive Interrupt n,1: Enables Processor B Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor B Transmit Interrupt n,1: Enables Processor B Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor B General Interrupt n is not..,1: Processor B General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "HRM,HRM" "0: BHR bit in ACR is not masked enables the..,1: BHR bit in ACR is masked disables the.."
|
|
bitfld.long 0x00 0.--2. "BAFn,BAFn" "0: Clears the Fn bit in the ASR register,1: Sets the Fn bit in the ASR register,?..."
|
|
tree.end
|
|
tree "LSIO__MU8_B"
|
|
base ad:0x5D2C0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BTR0,Processor B Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BTR0,BTR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BTR1,Processor B Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BTR1,BTR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "BTR2,Processor B Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BTR2,BTR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BTR3,Processor B Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BTR3,BTR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BRR0,Processor B Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BRR0,BRR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "BRR1,Processor B Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BRR1,BRR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BRR2,Processor B Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BRR2,BRR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "BRR3,Processor B Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BRR3,BRR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BSR,Processor B Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor B general purpose interrupt n is..,1: Processor B general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: BRRn register is not full (default),1: BRRn register has received data from ATRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: BTRn register is not empty,1: BTRn register is empty (default),?..."
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor B..,1: Processor B initiated flags update processing"
|
|
newline
|
|
bitfld.long 0x00 7. "ARS,ARS" "0: The Processor A or the Processor A-side of..,1: The Processor A or the Processor A-side of.."
|
|
bitfld.long 0x00 5.--6. "APM,APM" "0: The System is in Run Mode,1: The System is in WAIT Mode,?,3: The System is in STOP Mode"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor B-side event is not pending..,1: The Processor B-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: ABFn bit in ACR register is written 0 (default),1: ABFn bit in ACR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR,Processor B Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor B General Interrupt n,1: Enables Processor B General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor B Receive Interrupt n,1: Enables Processor B Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor B Transmit Interrupt n,1: Enables Processor B Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor B General Interrupt n is not..,1: Processor B General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "HRM,HRM" "0: BHR bit in ACR is not masked enables the..,1: BHR bit in ACR is masked disables the.."
|
|
bitfld.long 0x00 0.--2. "BAFn,BAFn" "0: Clears the Fn bit in the ASR register,1: Sets the Fn bit in the ASR register,?..."
|
|
tree.end
|
|
tree "LSIO__MU9_B"
|
|
base ad:0x5D2D0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BTR0,Processor B Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BTR0,BTR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BTR1,Processor B Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BTR1,BTR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "BTR2,Processor B Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BTR2,BTR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BTR3,Processor B Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BTR3,BTR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BRR0,Processor B Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BRR0,BRR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "BRR1,Processor B Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BRR1,BRR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BRR2,Processor B Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BRR2,BRR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "BRR3,Processor B Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BRR3,BRR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BSR,Processor B Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor B general purpose interrupt n is..,1: Processor B general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: BRRn register is not full (default),1: BRRn register has received data from ATRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: BTRn register is not empty,1: BTRn register is empty (default),?..."
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor B..,1: Processor B initiated flags update processing"
|
|
newline
|
|
bitfld.long 0x00 7. "ARS,ARS" "0: The Processor A or the Processor A-side of..,1: The Processor A or the Processor A-side of.."
|
|
bitfld.long 0x00 5.--6. "APM,APM" "0: The System is in Run Mode,1: The System is in WAIT Mode,?,3: The System is in STOP Mode"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor B-side event is not pending..,1: The Processor B-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: ABFn bit in ACR register is written 0 (default),1: ABFn bit in ACR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR,Processor B Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor B General Interrupt n,1: Enables Processor B General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor B Receive Interrupt n,1: Enables Processor B Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor B Transmit Interrupt n,1: Enables Processor B Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor B General Interrupt n is not..,1: Processor B General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "HRM,HRM" "0: BHR bit in ACR is not masked enables the..,1: BHR bit in ACR is masked disables the.."
|
|
bitfld.long 0x00 0.--2. "BAFn,BAFn" "0: Clears the Fn bit in the ASR register,1: Sets the Fn bit in the ASR register,?..."
|
|
tree.end
|
|
tree "LSIO__MU10_B"
|
|
base ad:0x5D2E0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BTR0,Processor B Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BTR0,BTR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BTR1,Processor B Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BTR1,BTR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "BTR2,Processor B Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BTR2,BTR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BTR3,Processor B Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BTR3,BTR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BRR0,Processor B Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BRR0,BRR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "BRR1,Processor B Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BRR1,BRR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BRR2,Processor B Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BRR2,BRR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "BRR3,Processor B Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BRR3,BRR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BSR,Processor B Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor B general purpose interrupt n is..,1: Processor B general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: BRRn register is not full (default),1: BRRn register has received data from ATRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: BTRn register is not empty,1: BTRn register is empty (default),?..."
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor B..,1: Processor B initiated flags update processing"
|
|
newline
|
|
bitfld.long 0x00 7. "ARS,ARS" "0: The Processor A or the Processor A-side of..,1: The Processor A or the Processor A-side of.."
|
|
bitfld.long 0x00 5.--6. "APM,APM" "0: The System is in Run Mode,1: The System is in WAIT Mode,?,3: The System is in STOP Mode"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor B-side event is not pending..,1: The Processor B-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: ABFn bit in ACR register is written 0 (default),1: ABFn bit in ACR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR,Processor B Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor B General Interrupt n,1: Enables Processor B General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor B Receive Interrupt n,1: Enables Processor B Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor B Transmit Interrupt n,1: Enables Processor B Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor B General Interrupt n is not..,1: Processor B General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "HRM,HRM" "0: BHR bit in ACR is not masked enables the..,1: BHR bit in ACR is masked disables the.."
|
|
bitfld.long 0x00 0.--2. "BAFn,BAFn" "0: Clears the Fn bit in the ASR register,1: Sets the Fn bit in the ASR register,?..."
|
|
tree.end
|
|
tree "LSIO__MU11_B"
|
|
base ad:0x5D2F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BTR0,Processor B Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BTR0,BTR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BTR1,Processor B Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BTR1,BTR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "BTR2,Processor B Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BTR2,BTR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BTR3,Processor B Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BTR3,BTR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BRR0,Processor B Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BRR0,BRR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "BRR1,Processor B Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BRR1,BRR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BRR2,Processor B Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BRR2,BRR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "BRR3,Processor B Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BRR3,BRR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BSR,Processor B Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor B general purpose interrupt n is..,1: Processor B general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: BRRn register is not full (default),1: BRRn register has received data from ATRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: BTRn register is not empty,1: BTRn register is empty (default),?..."
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor B..,1: Processor B initiated flags update processing"
|
|
newline
|
|
bitfld.long 0x00 7. "ARS,ARS" "0: The Processor A or the Processor A-side of..,1: The Processor A or the Processor A-side of.."
|
|
bitfld.long 0x00 5.--6. "APM,APM" "0: The System is in Run Mode,1: The System is in WAIT Mode,?,3: The System is in STOP Mode"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor B-side event is not pending..,1: The Processor B-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: ABFn bit in ACR register is written 0 (default),1: ABFn bit in ACR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR,Processor B Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor B General Interrupt n,1: Enables Processor B General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor B Receive Interrupt n,1: Enables Processor B Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor B Transmit Interrupt n,1: Enables Processor B Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor B General Interrupt n is not..,1: Processor B General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "HRM,HRM" "0: BHR bit in ACR is not masked enables the..,1: BHR bit in ACR is masked disables the.."
|
|
bitfld.long 0x00 0.--2. "BAFn,BAFn" "0: Clears the Fn bit in the ASR register,1: Sets the Fn bit in the ASR register,?..."
|
|
tree.end
|
|
tree "LSIO__MU12_B"
|
|
base ad:0x5D300000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BTR0,Processor B Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BTR0,BTR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BTR1,Processor B Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BTR1,BTR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "BTR2,Processor B Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BTR2,BTR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BTR3,Processor B Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BTR3,BTR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BRR0,Processor B Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BRR0,BRR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "BRR1,Processor B Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BRR1,BRR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BRR2,Processor B Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BRR2,BRR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "BRR3,Processor B Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BRR3,BRR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BSR,Processor B Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor B general purpose interrupt n is..,1: Processor B general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: BRRn register is not full (default),1: BRRn register has received data from ATRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: BTRn register is not empty,1: BTRn register is empty (default),?..."
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor B..,1: Processor B initiated flags update processing"
|
|
newline
|
|
bitfld.long 0x00 7. "ARS,ARS" "0: The Processor A or the Processor A-side of..,1: The Processor A or the Processor A-side of.."
|
|
bitfld.long 0x00 5.--6. "APM,APM" "0: The System is in Run Mode,1: The System is in WAIT Mode,?,3: The System is in STOP Mode"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor B-side event is not pending..,1: The Processor B-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: ABFn bit in ACR register is written 0 (default),1: ABFn bit in ACR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR,Processor B Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor B General Interrupt n,1: Enables Processor B General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor B Receive Interrupt n,1: Enables Processor B Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor B Transmit Interrupt n,1: Enables Processor B Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor B General Interrupt n is not..,1: Processor B General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "HRM,HRM" "0: BHR bit in ACR is not masked enables the..,1: BHR bit in ACR is masked disables the.."
|
|
bitfld.long 0x00 0.--2. "BAFn,BAFn" "0: Clears the Fn bit in the ASR register,1: Sets the Fn bit in the ASR register,?..."
|
|
tree.end
|
|
tree "LSIO__MU13_B"
|
|
base ad:0x5D310000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BTR0,Processor B Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BTR0,BTR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BTR1,Processor B Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BTR1,BTR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "BTR2,Processor B Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BTR2,BTR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BTR3,Processor B Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BTR3,BTR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BRR0,Processor B Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BRR0,BRR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "BRR1,Processor B Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BRR1,BRR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BRR2,Processor B Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BRR2,BRR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "BRR3,Processor B Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BRR3,BRR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BSR,Processor B Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor B general purpose interrupt n is..,1: Processor B general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: BRRn register is not full (default),1: BRRn register has received data from ATRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: BTRn register is not empty,1: BTRn register is empty (default),?..."
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor B..,1: Processor B initiated flags update processing"
|
|
newline
|
|
bitfld.long 0x00 7. "ARS,ARS" "0: The Processor A or the Processor A-side of..,1: The Processor A or the Processor A-side of.."
|
|
bitfld.long 0x00 5.--6. "APM,APM" "0: The System is in Run Mode,1: The System is in WAIT Mode,?,3: The System is in STOP Mode"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor B-side event is not pending..,1: The Processor B-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: ABFn bit in ACR register is written 0 (default),1: ABFn bit in ACR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR,Processor B Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor B General Interrupt n,1: Enables Processor B General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor B Receive Interrupt n,1: Enables Processor B Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor B Transmit Interrupt n,1: Enables Processor B Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor B General Interrupt n is not..,1: Processor B General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "HRM,HRM" "0: BHR bit in ACR is not masked enables the..,1: BHR bit in ACR is masked disables the.."
|
|
bitfld.long 0x00 0.--2. "BAFn,BAFn" "0: Clears the Fn bit in the ASR register,1: Sets the Fn bit in the ASR register,?..."
|
|
tree.end
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x33430000 ad:0x33430080 ad:0x33430100 ad:0x33430180)
|
|
tree "SCU__MU0_B$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BTR0,Processor B Transmit Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BTR0,BTR0"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BTR1,Processor B Transmit Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BTR1,BTR1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "BTR2,Processor B Transmit Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BTR2,BTR2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BTR3,Processor B Transmit Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BTR3,BTR3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "BRR0,Processor B Receive Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "BRR0,BRR0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "BRR1,Processor B Receive Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "BRR1,BRR1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "BRR2,Processor B Receive Register 2"
|
|
hexmask.long 0x00 0.--31. 1. "BRR2,BRR2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "BRR3,Processor B Receive Register 3"
|
|
hexmask.long 0x00 0.--31. 1. "BRR3,BRR3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BSR,Processor B Status Register"
|
|
bitfld.long 0x00 28.--31. "GIPn,GIPn" "0: Processor B general purpose interrupt n is..,1: Processor B general purpose interrupt n is..,?..."
|
|
bitfld.long 0x00 24.--27. "RFn,RFn" "0: BRRn register is not full (default),1: BRRn register has received data from ATRn..,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TEn,TEn" "0: BTRn register is not empty,1: BTRn register is empty (default),?..."
|
|
bitfld.long 0x00 8. "FUP,FUP" "0: No flags updated initiated by the Processor B..,1: Processor B initiated flags update processing"
|
|
newline
|
|
bitfld.long 0x00 7. "ARS,ARS" "0: The Processor A or the Processor A-side of..,1: The Processor A or the Processor A-side of.."
|
|
bitfld.long 0x00 5.--6. "APM,APM" "0: The System is in Run Mode,1: The System is in WAIT Mode,?,3: The System is in STOP Mode"
|
|
newline
|
|
bitfld.long 0x00 4. "EP,EP" "0: The Processor B-side event is not pending..,1: The Processor B-side event is pending"
|
|
bitfld.long 0x00 0.--2. "Fn,Fn" "0: ABFn bit in ACR register is written 0 (default),1: ABFn bit in ACR register is written 1,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BCR,Processor B Control Register"
|
|
bitfld.long 0x00 28.--31. "GIEn,GIEn" "0: Disables Processor B General Interrupt n,1: Enables Processor B General Interrupt n,?..."
|
|
bitfld.long 0x00 24.--27. "RIEn,RIEn" "0: Disables Processor B Receive Interrupt n,1: Enables Processor B Receive Interrupt n,?..."
|
|
newline
|
|
bitfld.long 0x00 20.--23. "TIEn,TIEn" "0: Disables Processor B Transmit Interrupt n,1: Enables Processor B Transmit Interrupt n,?..."
|
|
bitfld.long 0x00 16.--19. "GIRn,GIRn" "0: Processor B General Interrupt n is not..,1: Processor B General Interrupt n is requested..,?..."
|
|
newline
|
|
bitfld.long 0x00 4. "HRM,HRM" "0: BHR bit in ACR is not masked enables the..,1: BHR bit in ACR is masked disables the.."
|
|
bitfld.long 0x00 0.--2. "BAFn,BAFn" "0: Clears the Fn bit in the ASR register,1: Sets the Fn bit in the ASR register,?..."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PHY_PMAPCS_TOP (PCIE_PHY)"
|
|
base ad:0x5F1A0000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "reg00,Control register 0"
|
|
bitfld.byte 0x00 7. "auto_shift,auto_shift" "0,1"
|
|
bitfld.byte 0x00 6. "force_rx_detect,force_rx_detect" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4.--5. "cdr_reference,cdr_reference" "0,1,2,3"
|
|
bitfld.byte 0x00 2. "cdr_pll_delta,cdr_pll_delta" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "signal_detect_threshold,signal_detect_threshold" "0,1"
|
|
bitfld.byte 0x00 0. "Tx_select_rx_feedback,Tx_select_rx_feedback" "0,1"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "reg01,Clock count for error counter decrement"
|
|
hexmask.byte 0x00 0.--7. 1. "errcnt_dec,errcnt_dec"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "reg02,Error counter threshold - Rx idle detect max latency"
|
|
bitfld.byte 0x00 4.--7. "rxidle_max,rxidle_max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "errcnt_thr,errcnt_thr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "reg03,Rx Impedance ratio"
|
|
hexmask.byte 0x00 0.--7. 1. "rx_imped_ratio,rx_imped_ratio"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "reg04,TxPLL F setting and PCLK ratio"
|
|
bitfld.byte 0x00 4.--5. "tx_div_mode0,tx_div_mode0" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. "TxF,TxF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "reg05,Tx PLL M and N Settings"
|
|
bitfld.byte 0x00 7. "cnt250ns_max_bit8,cnt250ns_max_bit8" "0,1"
|
|
bitfld.byte 0x00 5.--6. "TxM,TxM" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x00 0.--4. "TxN,TxN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "reg06,RxPLL F setting and PCLK ratio"
|
|
bitfld.byte 0x00 4.--5. "rx_div_mode0,rx_div_mode0" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. "RxF,RxF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "reg07,Rx PLL M and N Settings"
|
|
bitfld.byte 0x00 5.--6. "RxM,RxM" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. "RxN,RxN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "reg08,250ns timer base count"
|
|
hexmask.byte 0x00 0.--7. 1. "cnt250ns_max,cnt250ns_max"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "reg09,Tx Impedance Ratio"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_imped_ratio,tx_imped_ratio"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "reg10,Tx Post-Cursor Ratio"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_pst_ratio,tx_pst_ratio"
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "reg11,Tx Pre-Cursor ratio"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_pre_ratio,tx_pre_ratio"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "reg12,End of calibration counter"
|
|
hexmask.byte 0x00 0.--7. 1. "endcalib_max,endcalib_max"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "reg13,Calibration stability Counter"
|
|
bitfld.byte 0x00 5.--7. "calib_settle_max,calib_settle_max" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--4. "calib_stable_max,calib_stable_max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x0E++0x00
|
|
line.byte 0x00 "reg14,Power Down Feature"
|
|
bitfld.byte 0x00 6.--7. "rxidle_msb,rxidle_msb" "0,1,2,3"
|
|
bitfld.byte 0x00 5. "Force_Signal,Force_Signal" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "Force_Idle,Force_Idle" "0,1"
|
|
bitfld.byte 0x00 3. "NO_FCMP,NO_FCMP" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "PMFF_ALL,PMFF_ALL" "0,1"
|
|
bitfld.byte 0x00 1. "CDR_ERR,CDR_ERR" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "CDR_P1,CDR_P1" "0,1"
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "reg15,Rx Offset Counter"
|
|
bitfld.byte 0x00 5.--7. "rxoff_settle_max,rxoff_settle_max" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--4. "rxoff_stable_max,rxoff_stable_max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "reg16,TxPLL F setting and PCLK ratio in PCIe 5Gbps speed"
|
|
bitfld.byte 0x00 4.--5. "tx_div_mode1,tx_div_mode1" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. "TxF,TxF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "reg17,Tx PLL M and N Settings in PCIe 5Gbps speed"
|
|
bitfld.byte 0x00 5.--6. "TxM,TxM" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. "TxN,TxN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "reg18,CDRPLL F setting and PCLK ratio in PCIe 5Gbps speed"
|
|
bitfld.byte 0x00 4.--5. "rx_div_mode1,rx_div_mode1" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. "RxF,RxF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "reg19,CDRPLL M and N Settings in PCIe 5Gbps speed"
|
|
bitfld.byte 0x00 5.--6. "RxM,RxM" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. "RxN,RxN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "reg20,Tx Post-cursor ratio with TxDeemp=0 Full Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_pst_ratio_deemp0_full,tx_pst_ratio_deemp0_full"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "reg21,Tx Pre-cursor ratio with TxDeemp=0 Full Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_pre_ratio_deemp0_full,tx_pre_ratio_deemp0_full"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "reg22,Tx Post-cursor ratio with TxDeemp=1 Full Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_pst_ratio_deemp1_full,tx_pst_ratio_deemp1_full"
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "reg23,Tx Pre-cursor ratio with TxDeemp=1 Full Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_pre_ratio_deemp1_full,tx_pre_ratio_deemp1_full"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "reg24,Tx Amplitude ratio TxMargin=0 full swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin0_full,tx_amp_ratio_margin0_full"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "reg25,Tx Amplitude ratio TxMargin=1 full swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin1_full,tx_amp_ratio_margin1_full"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "reg26,Tx Amplitude ratio TxMargin=2 full swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin2_full,tx_amp_ratio_margin2_full"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "reg27,Tx Amplitude ratio TxMargin=3 full swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin3_full,tx_amp_ratio_margin3_full"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "reg28,Tx Amplitude ratio TxMargin=4 full swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin4_full,tx_amp_ratio_margin4_full"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "reg29,Tx Amplitude ratio TxMargin=5 full swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin5_full,tx_amp_ratio_margin5_full"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "reg30,Tx Amplitude ratio TxMargin=6 full swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin6_full,tx_amp_ratio_margin6_full"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "reg31,Tx Amplitude ratio TxMargin=7 full swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin7_full,tx_amp_ratio_margin7_full"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "reg32,auxiliary clock for 1us base time"
|
|
hexmask.byte 0x00 0.--7. 1. "auxclk1us_max,auxclk1us_max"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "reg33,CDRPLLL frequency comparator counter"
|
|
hexmask.byte 0x00 0.--7. 1. "cdrpll_cmp_max,cdrpll_cmp_max"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "reg34,CDRPLLL frequency comparator maximum difference"
|
|
hexmask.byte 0x00 0.--7. 1. "cdr_cnt_max,cdr_cnt_max"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "reg35,EI4 mode register"
|
|
bitfld.byte 0x00 7. "EI4,EI4" "0,1"
|
|
bitfld.byte 0x00 2. "rstcdr_idl,rstcdr_idl" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "rstcdr_frq,rstcdr_frq" "0,1"
|
|
bitfld.byte 0x00 0. "rstcdr_err,rstcdr_err" "0,1"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "reg36,Tx Post-Cursor ratio with TxDeemp=0 half Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_pst_ratio_deemp0_half,tx_pst_ratio_deemp0_half"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "reg37,Tx Pre-Cursor ratio with TxDeemp=0 half Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_pre_ratio_deemp0_half,tx_pre_ratio_deemp0_half"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "reg38,Tx Post-Cursor ratio with TxDeemp=1 half Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_pst_ratio_deemp1_half,tx_pst_ratio_deemp1_half"
|
|
group.byte 0x27++0x00
|
|
line.byte 0x00 "reg39,Tx Pre-Cursor ratio TxDeemp=1 half Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_pre_ratio_deemp1_half,tx_pre_ratio_deemp1_half"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "reg40,Tx Amplitude ratio TxMargin=0 half Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin0_half,tx_amp_ratio_margin0_half"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "reg41,Tx Amplitude ratio TxMargin=1 half Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin1_half,tx_amp_ratio_margin1_half"
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "reg42,Tx Amplitude ratio TxMargin=2 half Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin2_half,tx_amp_ratio_margin2_half"
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "reg43,Tx Amplitude ratio TxMargin=3 half Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin3_half,tx_amp_ratio_margin3_half"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "reg44,Tx Amplitude ratio TxMargin=4 half Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin4_half,tx_amp_ratio_margin4_half"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "reg45,Tx Amplitude ratio TxMargin=5 half Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin5_half,tx_amp_ratio_margin5_half"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "reg46,Tx Amplitude ratio TxMargin=6 half Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin6_half,tx_amp_ratio_margin6_half"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "reg47,Tx Amplitude ratio TxMargin=7 half Swing"
|
|
hexmask.byte 0x00 0.--7. 1. "tx_amp_ratio_margin7_half,tx_amp_ratio_margin7_half"
|
|
rgroup.byte 0x30++0x00
|
|
line.byte 0x00 "reg48,PMA status"
|
|
bitfld.byte 0x00 7. "pma_rdy,pma_rdy" "0,1"
|
|
bitfld.byte 0x00 5. "arxctle_err,arxctle_err" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "asch_err,asch_err" "0,1"
|
|
bitfld.byte 0x00 3. "arxes_err,arxes_err" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "arxdm_err,arxdm_err" "0,1"
|
|
bitfld.byte 0x00 1. "arxdp_err,arxdp_err" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "arxt_err,arxt_err" "0,1"
|
|
rgroup.byte 0x31++0x00
|
|
line.byte 0x00 "reg49,Tx Sweep center"
|
|
bitfld.byte 0x00 7. "tx_val,tx_val" "0,1"
|
|
hexmask.byte 0x00 0.--6. 1. "tx_sweep_center_result,tx_sweep_center_result"
|
|
rgroup.byte 0x32++0x00
|
|
line.byte 0x00 "reg50,Rx Sweep center"
|
|
bitfld.byte 0x00 7. "rx_val,rx_val" "0,1"
|
|
hexmask.byte 0x00 0.--6. 1. "rx_sweep_center_result,rx_sweep_center_result"
|
|
rgroup.byte 0x34++0x00
|
|
line.byte 0x00 "reg52,Receiver Shift Loader parameter 0"
|
|
hexmask.byte 0x00 0.--6. 1. "atxdrr_sel0,atxdrr_sel0"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "reg53,EOMx Update Cnt Value"
|
|
hexmask.byte 0x00 0.--6. 1. "eomx_update_cnt_value,eomx_update_cnt_value"
|
|
rgroup.byte 0x36++0x00
|
|
line.byte 0x00 "reg54,transmitter P shift Loader parameter 0-0"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdrp_dyn_1,atxdrp_dyn_1"
|
|
rgroup.byte 0x37++0x00
|
|
line.byte 0x00 "reg55,transmitter P shift Loader parameter 0-1"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdrp_dyn_2,atxdrp_dyn_2"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "reg56,transmitter P shift Loader parameter 0-2"
|
|
bitfld.byte 0x00 5.--7. "eom_done_cnt_value_a,eom_done_cnt_value_a" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 0.--4. "atxdrp_dyn_3,atxdrp_dyn_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x39++0x00
|
|
line.byte 0x00 "reg57,transmitter A shift Loader parameter 0-0"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdra_dyn_1,atxdra_dyn_1"
|
|
rgroup.byte 0x3A++0x00
|
|
line.byte 0x00 "reg58,transmitter A shift Loader parameter 0-1"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdra_dyn_2,atxdra_dyn_2"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "reg59,transmitter A shift Loader parameter 0-2"
|
|
bitfld.byte 0x00 5.--7. "eom_done_cnt_value_b,eom_done_cnt_value_b" "0,1,2,3,4,5,6,7"
|
|
rbitfld.byte 0x00 0.--4. "atxdra_dyn_3,atxdra_dyn_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "reg60,transmitter T shift Loader parameter 0-0"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdrt_dyn_1,atxdrt_dyn_1"
|
|
rgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "reg61,transmitter T shift Loader parameter 0-1"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdrt_dyn_2,atxdrt_dyn_2"
|
|
rgroup.byte 0x3E++0x00
|
|
line.byte 0x00 "reg62,transmitter T shift Loader parameter 0-2"
|
|
bitfld.byte 0x00 0.--4. "atxdrt_dyn_3,atxdrt_dyn_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x3F++0x00
|
|
line.byte 0x00 "reg63,transmitter P shift Loader parameter 1-0"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdrp_ei1_1,atxdrp_ei1_1"
|
|
rgroup.byte 0x40++0x00
|
|
line.byte 0x00 "reg64,transmitter P shift Loader parameter 1-1"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdrp_ei1_2,atxdrp_ei1_2"
|
|
rgroup.byte 0x41++0x00
|
|
line.byte 0x00 "reg65,transmitter P shift Loader parameter 1-2"
|
|
bitfld.byte 0x00 0.--4. "atxdrp_ei1_3,atxdrp_ei1_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x42++0x00
|
|
line.byte 0x00 "reg66,transmitter A shift Loader parameter 1-0"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdra_ei1_1,atxdra_ei1_1"
|
|
rgroup.byte 0x43++0x00
|
|
line.byte 0x00 "reg67,transmitter A shift Loader parameter 1-1"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdra_ei1_2,atxdra_ei1_2"
|
|
rgroup.byte 0x44++0x00
|
|
line.byte 0x00 "reg68,transmitter A shift Loader parameter 1-2"
|
|
bitfld.byte 0x00 0.--4. "atxdra_ei1_3,atxdra_ei1_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x45++0x00
|
|
line.byte 0x00 "reg69,transmitter T shift Loader parameter 1-0"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdrt_ei1_1,atxdrt_ei1_1"
|
|
rgroup.byte 0x46++0x00
|
|
line.byte 0x00 "reg70,transmitter T shift Loader parameter 1-1"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdrt_ei1_2,atxdrt_ei1_2"
|
|
rgroup.byte 0x47++0x00
|
|
line.byte 0x00 "reg71,transmitter T shift Loader parameter 1-2"
|
|
bitfld.byte 0x00 0.--4. "atxdrt_ei1_3,atxdrt_ei1_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x48++0x00
|
|
line.byte 0x00 "reg72,transmitter P shift Loader parameter 2-0"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdrp_ei2_1,atxdrp_ei2_1"
|
|
rgroup.byte 0x49++0x00
|
|
line.byte 0x00 "reg73,transmitter P shift Loader parameter 2-1"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdrp_ei2_2,atxdrp_ei2_2"
|
|
rgroup.byte 0x4A++0x00
|
|
line.byte 0x00 "reg74,transmitter P shift Loader parameter 2-2"
|
|
bitfld.byte 0x00 0.--4. "atxdrp_ei2_3,atxdrp_ei2_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x4B++0x00
|
|
line.byte 0x00 "reg75,transmitter A shift Loader parameter 2-0"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdra_ei2_1,atxdra_ei2_1"
|
|
rgroup.byte 0x4C++0x00
|
|
line.byte 0x00 "reg76,transmitter A shift Loader parameter 2-1"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdra_ei2_2,atxdra_ei2_2"
|
|
rgroup.byte 0x4D++0x00
|
|
line.byte 0x00 "reg77,transmitter A shift Loader parameter 2-2"
|
|
bitfld.byte 0x00 0.--4. "atxdra_ei2_3,atxdra_ei2_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "reg78,transmitter T shift Loader parameter 2-0"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdrt_ei2_1,atxdrt_ei2_1"
|
|
rgroup.byte 0x4F++0x00
|
|
line.byte 0x00 "reg79,transmitter T shift Loader parameter 2-1"
|
|
hexmask.byte 0x00 0.--7. 1. "atxdrt_ei2_2,atxdrt_ei2_2"
|
|
rgroup.byte 0x50++0x00
|
|
line.byte 0x00 "reg80,transmitter T shift Loader parameter 2-2"
|
|
bitfld.byte 0x00 0.--4. "atxdrt_ei2_3,atxdrt_ei2_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "reg81,override calibration register"
|
|
bitfld.byte 0x00 7. "over_ctle,over_ctle" "0,1"
|
|
bitfld.byte 0x00 6. "over_rxes,over_rxes" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "over_rxdm,over_rxdm" "0,1"
|
|
bitfld.byte 0x00 4. "over_sch,over_sch" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "over_rxt,over_rxt" "0,1"
|
|
bitfld.byte 0x00 2. "over_rxdp,over_rxdp" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "over_rx,over_rx" "0,1"
|
|
bitfld.byte 0x00 0. "over_tx,over_tx" "0,1"
|
|
group.byte 0x52++0x00
|
|
line.byte 0x00 "reg82,Force Receiver Shift Loader parameter 0"
|
|
hexmask.byte 0x00 0.--7. 1. "force_atxdrr_1,force_atxdrr_1"
|
|
group.byte 0x53++0x00
|
|
line.byte 0x00 "reg83,Force Receiver Shift Loader parameter 1"
|
|
hexmask.byte 0x00 0.--7. 1. "force_atxdrr_2,force_atxdrr_2"
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "reg84,Force Receiver Shift Loader parameter 2"
|
|
bitfld.byte 0x00 0.--4. "force_atxdrr_3,force_atxdrr_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x55++0x00
|
|
line.byte 0x00 "reg85,Force transmitter P shift Loader parameter 0"
|
|
hexmask.byte 0x00 0.--7. 1. "force_atxdrp_1,force_atxdrp_1"
|
|
rgroup.byte 0x56++0x00
|
|
line.byte 0x00 "reg86,Force transmitter P shift Loader parameter 1"
|
|
hexmask.byte 0x00 0.--7. 1. "force_atxdrp_2,force_atxdrp_2"
|
|
rgroup.byte 0x57++0x00
|
|
line.byte 0x00 "reg87,Force transmitter P shift Loader parameter 2"
|
|
bitfld.byte 0x00 0.--4. "force_atxdrp_3,force_atxdrp_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x58++0x00
|
|
line.byte 0x00 "reg88,Force transmitter A shift Loader parameter 0"
|
|
hexmask.byte 0x00 0.--7. 1. "force_atxdra_1,force_atxdra_1"
|
|
rgroup.byte 0x59++0x00
|
|
line.byte 0x00 "reg89,Force transmitter A shift Loader parameter 1"
|
|
hexmask.byte 0x00 0.--7. 1. "force_atxdra_2,force_atxdra_2"
|
|
rgroup.byte 0x5A++0x00
|
|
line.byte 0x00 "reg90,Force transmitter A shift Loader parameter 2"
|
|
bitfld.byte 0x00 0.--4. "force_atxdra_3,force_atxdra_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x5B++0x00
|
|
line.byte 0x00 "reg91,Force transmitter T shift Loader parameter 0"
|
|
hexmask.byte 0x00 0.--7. 1. "force_atxdrt_1,force_atxdrt_1"
|
|
rgroup.byte 0x5C++0x00
|
|
line.byte 0x00 "reg92,Force transmitter T shift Loader parameter 1"
|
|
hexmask.byte 0x00 0.--7. 1. "force_atxdrt_2,force_atxdrt_2"
|
|
rgroup.byte 0x5D++0x00
|
|
line.byte 0x00 "reg93,Force transmitter T shift Loader parameter 2"
|
|
bitfld.byte 0x00 0.--4. "force_atxdrt_3,force_atxdrt_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x5E++0x00
|
|
line.byte 0x00 "reg94,RxDP offset calibration result"
|
|
bitfld.byte 0x00 6.--7. "calib_err,calib_err" "0,1,2,3"
|
|
bitfld.byte 0x00 5. "arxdpdir,arxdpdir" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--4. "arxdpnull,arxdpnull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x5F++0x00
|
|
line.byte 0x00 "reg95,RxT offset calibration result"
|
|
bitfld.byte 0x00 6.--7. "calib_err,calib_err" "0,1,2,3"
|
|
bitfld.byte 0x00 5. "arxtdir,arxtdir" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--4. "arxtnull,arxtnull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x60++0x00
|
|
line.byte 0x00 "reg96,Schmitt trigger calibration result"
|
|
bitfld.byte 0x00 6.--7. "asch_err,asch_err" "0,1,2,3"
|
|
bitfld.byte 0x00 4. "aschdir,aschdir" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "aschnull,aschnull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x61++0x00
|
|
line.byte 0x00 "reg97,Force RxDP offset calibration result"
|
|
bitfld.byte 0x00 5. "f_arxdpdir,f_arxdpdir" "0,1"
|
|
bitfld.byte 0x00 0.--4. "f_arxdpnull,f_arxdpnull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x62++0x00
|
|
line.byte 0x00 "reg98,Force RxT offset calibration result"
|
|
bitfld.byte 0x00 5. "f_arxtdir,f_arxtdir" "0,1"
|
|
bitfld.byte 0x00 0.--4. "f_arxtnull,f_arxtnull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x63++0x00
|
|
line.byte 0x00 "reg99,Force Schmitt trigger calibration result"
|
|
bitfld.byte 0x00 5. "f_aschcal,f_aschcal" "0,1"
|
|
bitfld.byte 0x00 4. "f_aschdir,f_aschdir" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "f_aschnull,f_aschnull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x64++0x00
|
|
line.byte 0x00 "reg100,PRBS Control register"
|
|
bitfld.byte 0x00 6. "prbs_chk,prbs_chk" "0,1"
|
|
bitfld.byte 0x00 4.--5. "actag_reg,actag_reg" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x00 2.--3. "prbs_typ,prbs_typ" "0,1,2,3"
|
|
bitfld.byte 0x00 1. "lpbk_en,lpbk_en" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "prbs_gen,prbs_gen" "0,1"
|
|
rgroup.byte 0x65++0x00
|
|
line.byte 0x00 "reg101,PRBS error counter register"
|
|
hexmask.byte 0x00 0.--7. 1. "prbs_errcnt,prbs_errcnt"
|
|
group.byte 0x66++0x00
|
|
line.byte 0x00 "reg102,PHY reset override register"
|
|
bitfld.byte 0x00 7. "rxhf_clkdn,rxhf_clkdn" "0,1"
|
|
bitfld.byte 0x00 6. "txhf_clkdn,txhf_clkdn" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "rxpllrst,rxpllrst" "0,1"
|
|
bitfld.byte 0x00 4. "txpllrst,txpllrst" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "rxpll_init,rxpll_init" "0,1"
|
|
bitfld.byte 0x00 2. "txpll_init,txpll_init" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "rx_hiz,rx_hiz" "0,1"
|
|
bitfld.byte 0x00 0. "tx_hiz,tx_hiz" "0,1"
|
|
group.byte 0x67++0x00
|
|
line.byte 0x00 "reg103,PHY power override register"
|
|
bitfld.byte 0x00 0. "rx_pwrdn,rx_pwrdn" "0,1"
|
|
group.byte 0x68++0x00
|
|
line.byte 0x00 "reg104,Custom Pattern Byte 0"
|
|
hexmask.byte 0x00 0.--7. 1. "custom_pattern_1,custom_pattern_1"
|
|
group.byte 0x69++0x00
|
|
line.byte 0x00 "reg105,Custom Pattern Byte 1"
|
|
hexmask.byte 0x00 0.--7. 1. "custom_pattern_2,custom_pattern_2"
|
|
group.byte 0x6A++0x00
|
|
line.byte 0x00 "reg106,Custom Pattern Byte 2"
|
|
hexmask.byte 0x00 0.--7. 1. "custom_pattern_3,custom_pattern_3"
|
|
group.byte 0x6B++0x00
|
|
line.byte 0x00 "reg107,Custom Pattern Byte 3"
|
|
hexmask.byte 0x00 0.--7. 1. "custom_pattern_4,custom_pattern_4"
|
|
group.byte 0x6C++0x00
|
|
line.byte 0x00 "reg108,Custom Pattern Byte 4"
|
|
hexmask.byte 0x00 0.--7. 1. "custom_pattern_5,custom_pattern_5"
|
|
group.byte 0x6D++0x00
|
|
line.byte 0x00 "reg109,Custom Pattern Byte 5"
|
|
hexmask.byte 0x00 0.--7. 1. "custom_pattern_6,custom_pattern_6"
|
|
group.byte 0x6E++0x00
|
|
line.byte 0x00 "reg110,Custom Pattern Byte 6"
|
|
hexmask.byte 0x00 0.--7. 1. "custom_pattern_7,custom_pattern_7"
|
|
group.byte 0x6F++0x00
|
|
line.byte 0x00 "reg111,Custom Pattern Byte 7"
|
|
hexmask.byte 0x00 0.--7. 1. "custom_pattern_8,custom_pattern_8"
|
|
group.byte 0x70++0x00
|
|
line.byte 0x00 "reg112,Custom Pattern Byte 8"
|
|
hexmask.byte 0x00 0.--7. 1. "custom_pattern_9,custom_pattern_9"
|
|
group.byte 0x71++0x00
|
|
line.byte 0x00 "reg113,Custom Pattern Byte 9"
|
|
hexmask.byte 0x00 0.--7. 1. "custom_pattern_10,custom_pattern_10"
|
|
group.byte 0x72++0x00
|
|
line.byte 0x00 "reg114,custom pattern control"
|
|
bitfld.byte 0x00 6. "cust_auto,cust_auto" "0,1"
|
|
bitfld.byte 0x00 5. "cust_skip,cust_skip" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "cust_chk,cust_chk" "0,1"
|
|
bitfld.byte 0x00 1.--3. "cust_typ,cust_typ" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x00 0. "cust_sel,cust_sel" "0,1"
|
|
group.byte 0x73++0x00
|
|
line.byte 0x00 "reg115,Custom pattern status register"
|
|
bitfld.byte 0x00 5.--7. "cust_state,cust_state" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. "cust_sync,cust_sync" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "cust_error,cust_error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x74++0x00
|
|
line.byte 0x00 "reg116,PCS Loopback Control"
|
|
bitfld.byte 0x00 6. "rx_polinv,rx_polinv" "0,1"
|
|
bitfld.byte 0x00 5. "tx_polinv,tx_polinv" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "eff_lpbk,eff_lpbk" "0,1"
|
|
rbitfld.byte 0x00 3. "meso_sync,meso_sync" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "meso_lpbk,meso_lpbk" "0,1"
|
|
bitfld.byte 0x00 1. "par_lpbk,par_lpbk" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "plesio_lpbk,plesio_lpbk" "0,1"
|
|
group.byte 0x75++0x00
|
|
line.byte 0x00 "reg117,Gen1 Transmit PLL Current charge Pump"
|
|
bitfld.byte 0x00 0.--2. "atxicp_rate0,atxicp_rate0" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x76++0x00
|
|
line.byte 0x00 "reg118,Gen1 Receive PLL Current charge Pump"
|
|
bitfld.byte 0x00 4.--6. "arxcdricp_rate0,arxcdricp_rate0" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--2. "arxicp_rate0,arxicp_rate0" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x77++0x00
|
|
line.byte 0x00 "reg119,Gen2 Transmit PLL Current charge Pump"
|
|
bitfld.byte 0x00 0.--2. "atxicp_rate1,atxicp_rate1" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x78++0x00
|
|
line.byte 0x00 "reg120,Gen2 Receive PLL Current charge Pump"
|
|
bitfld.byte 0x00 4.--6. "arxcdricp_rate1,arxcdricp_rate1" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--2. "arxicp_rate1,arxicp_rate1" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x79++0x00
|
|
line.byte 0x00 "reg121,CDR PLL manual control"
|
|
bitfld.byte 0x00 2. "fine_grain,fine_grain" "0,1"
|
|
bitfld.byte 0x00 1. "coarse_grain,coarse_grain" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "freq_lock,freq_lock" "0,1"
|
|
group.byte 0x7A++0x00
|
|
line.byte 0x00 "reg122,Gen3 Transmit PLL Current charge Pump"
|
|
bitfld.byte 0x00 4.--7. "ctlebias,ctlebias" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--2. "atxicp_rate2,atxicp_rate2" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x7B++0x00
|
|
line.byte 0x00 "reg123,Gen3 Receive PLL Current charge Pump"
|
|
bitfld.byte 0x00 4.--6. "arxcdricp_rate2,arxcdricp_rate2" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--2. "arxicp_rate2,arxicp_rate2" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x7C++0x00
|
|
line.byte 0x00 "reg124,CTLE gian override and bypass control"
|
|
bitfld.byte 0x00 5. "es_pwrdn,es_pwrdn" "0,1"
|
|
bitfld.byte 0x00 4. "dfe_pwrdn,dfe_pwrdn" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "ovr_hint3db,ovr_hint3db" "0,1"
|
|
bitfld.byte 0x00 1. "ovr_gain3db,ovr_gain3db" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "ctlebypass,ctlebypass" "0,1"
|
|
group.byte 0x7D++0x00
|
|
line.byte 0x00 "reg125,PMA RsvCtl"
|
|
hexmask.byte 0x00 0.--7. 1. "arxrsvctl,arxrsvctl"
|
|
rgroup.byte 0x7E++0x00
|
|
line.byte 0x00 "reg126,PMA RsvSts"
|
|
bitfld.byte 0x00 4.--6. "pcie2_mode,pcie2_mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--3. "arxrsvsts,arxrsvsts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0x7F++0x00
|
|
line.byte 0x00 "reg127,PMA test_out"
|
|
bitfld.byte 0x00 7. "aschmittout,aschmittout" "0,1"
|
|
bitfld.byte 0x00 6. "afarendrxabsent,afarendrxabsent" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "arxclkstatble,arxclkstatble" "0,1"
|
|
bitfld.byte 0x00 4. "atxclkstable,atxclkstable" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "acdrdiagout,acdrdiagout" "0,1"
|
|
bitfld.byte 0x00 2. "atrandet,atrandet" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "acdrpllrst,acdrpllrst" "0,1"
|
|
bitfld.byte 0x00 0. "atxpllrst,atxpllrst" "0,1"
|
|
wgroup.byte 0x80++0x00
|
|
line.byte 0x00 "reg128,Update settings command register"
|
|
hexmask.byte 0x00 0.--7. 1. "update_settings,update_settings"
|
|
rgroup.byte 0x84++0x00
|
|
line.byte 0x00 "reg132,RxDM offset calibration result"
|
|
bitfld.byte 0x00 6.--7. "calib_err,calib_err" "0,1,2,3"
|
|
bitfld.byte 0x00 5. "arxdmdir,arxdmdir" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--4. "arxdmnull,arxdmnull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x85++0x00
|
|
line.byte 0x00 "reg133,RxEs offset calibration result"
|
|
bitfld.byte 0x00 6.--7. "calib_err,calib_err" "0,1,2,3"
|
|
bitfld.byte 0x00 5. "arxesdir,arxesdir" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--4. "arxesnull,arxesnull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x86++0x00
|
|
line.byte 0x00 "reg134,Force RxDM offset calibration result"
|
|
bitfld.byte 0x00 5. "f_arxdmdir,f_arxdmdir" "0,1"
|
|
bitfld.byte 0x00 0.--4. "f_arxdmnull,f_arxdmnull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x87++0x00
|
|
line.byte 0x00 "reg135,Force RxEs offset calibration result"
|
|
bitfld.byte 0x00 5. "f_arxesdir,f_arxesdir" "0,1"
|
|
bitfld.byte 0x00 0.--4. "f_arxesnull,f_arxesnull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "reg136,RSA/CTLE calibration override control"
|
|
bitfld.byte 0x00 6. "arxeom_pwrdn,arxeom_pwrdn" "0,1"
|
|
bitfld.byte 0x00 5. "arxdmpwrdn,arxdmpwrdn" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "arxdppwrdn,arxdppwrdn" "0,1"
|
|
bitfld.byte 0x00 2. "arxovr_out,arxovr_out" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "arxsel_out,arxsel_out" "0,1"
|
|
bitfld.byte 0x00 0. "arxcal_out,arxcal_out" "0,1"
|
|
rgroup.byte 0x89++0x00
|
|
line.byte 0x00 "reg137,RSA output signals"
|
|
bitfld.byte 0x00 4. "asch_out,asch_out" "0,1"
|
|
bitfld.byte 0x00 3. "arxt_out,arxt_out" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "arxes_out,arxes_out" "0,1"
|
|
bitfld.byte 0x00 1. "arxdm_out,arxdm_out" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "arxdp_out,arxdp_out" "0,1"
|
|
group.byte 0x8A++0x00
|
|
line.byte 0x00 "reg138,DFE Bias control"
|
|
bitfld.byte 0x00 0.--3. "dfe_bias,dfe_bias" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x8B++0x00
|
|
line.byte 0x00 "reg139,RSA ctat and ptat control"
|
|
bitfld.byte 0x00 4.--7. "arxrsaptat,arxrsaptat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "arxrsactat,arxrsactat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "reg140,Force CTLE offset calibration settings"
|
|
bitfld.byte 0x00 5. "f_arxctledir,f_arxctledir" "0,1"
|
|
bitfld.byte 0x00 0.--4. "f_arxctlenull,f_arxctlenull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.byte 0x8D++0x00
|
|
line.byte 0x00 "reg141,CTLE offset calibration result"
|
|
bitfld.byte 0x00 6.--7. "arxctle_err,arxctle_err" "0,1,2,3"
|
|
bitfld.byte 0x00 4. "arxctledir,arxctledir" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "arxctlenull,arxctlenull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x90++0x00
|
|
line.byte 0x00 "reg144,Error Scale 1"
|
|
bitfld.byte 0x00 4.--7. "RL2,RL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "RL1,RL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x91++0x00
|
|
line.byte 0x00 "reg145,Error Scale 2"
|
|
bitfld.byte 0x00 0.--3. "RL3,RL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x92++0x00
|
|
line.byte 0x00 "reg146,L1 Low power PLL lock time"
|
|
bitfld.byte 0x00 3.--7. "i1_exit_pll_lock_time,i1_exit_pll_lock_time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.byte 0x00 0.--2. "i1_enter_pll_reset_time,i1_enter_pll_reset_time" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x93++0x00
|
|
line.byte 0x00 "reg147,Aux Idle Max"
|
|
hexmask.byte 0x00 0.--7. 1. "auxidl_max,auxidl_max"
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "reg148,Elastic buffer Gen1/2"
|
|
bitfld.byte 0x00 0.--5. "almost_empty_10b,almost_empty_10b" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "reg149,Elastic buffer Gen1/2"
|
|
bitfld.byte 0x00 0.--5. "mid_valu_10b,mid_valu_10b" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x96++0x00
|
|
line.byte 0x00 "reg150,Elastic buffer Gen1/2"
|
|
bitfld.byte 0x00 0.--5. "almost_full_10b,almost_full_10b" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "reg151,Elastic buffer Gen1/2 20b: almost empty threshold"
|
|
bitfld.byte 0x00 0.--5. "almost_empty_20b,almost_empty_20b" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "reg152,Elastic buffer Gen1/2 20b: middle value threshold"
|
|
bitfld.byte 0x00 0.--5. "mid_valu_20b,mid_valu_20b" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x99++0x00
|
|
line.byte 0x00 "reg153,Elastic buffer Gen1/2 20b: almost full threshold"
|
|
bitfld.byte 0x00 0.--5. "almost_full_20b,almost_full_20b" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x9A++0x00
|
|
line.byte 0x00 "reg154,Elastic buffer Gen3: almost empty threshold"
|
|
bitfld.byte 0x00 0.--5. "almost_empty_gen3,almost_empty_gen3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x9B++0x00
|
|
line.byte 0x00 "reg155,Elastic buffer Gen3: middle value threshold"
|
|
bitfld.byte 0x00 0.--5. "mid_value_gen3,mid_value_gen3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x9C++0x00
|
|
line.byte 0x00 "reg156,Elastic buffer Gen3: almost full threshold"
|
|
bitfld.byte 0x00 0.--5. "almost_full_gen3,almost_full_gen3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x9E++0x00
|
|
line.byte 0x00 "reg158,RxEOM offset calibration result"
|
|
bitfld.byte 0x00 6.--7. "calib_err,calib_err" "0,1,2,3"
|
|
bitfld.byte 0x00 5. "arxeomdir,arxeomdir" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--4. "arxeomnull,arxeomnull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x9F++0x00
|
|
line.byte 0x00 "reg159,Force RxEOM offset calibration settings"
|
|
bitfld.byte 0x00 5. "f_arxceomdir,f_arxceomdir" "0,1"
|
|
bitfld.byte 0x00 0.--4. "f_arxeomnull,f_arxeomnull" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "reg160,EOM X and Direction Control"
|
|
bitfld.byte 0x00 7. "EOM1Dir,EOM1Dir" "0,1"
|
|
bitfld.byte 0x00 6. "EOM0Dir,EOM0Dir" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--5. "EOMx,EOMx" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0xA1++0x00
|
|
line.byte 0x00 "reg161,EOM Y control"
|
|
hexmask.byte 0x00 0.--7. 1. "EOMy,EOMy"
|
|
group.byte 0xA2++0x00
|
|
line.byte 0x00 "reg162,EOM Time MSB Control"
|
|
hexmask.byte 0x00 0.--7. 1. "EOM_time_1,EOM_time_1"
|
|
group.byte 0xA3++0x00
|
|
line.byte 0x00 "reg163,EOM Time LSB Control"
|
|
hexmask.byte 0x00 0.--7. 1. "EOM_time_2,EOM_time_2"
|
|
group.byte 0xA4++0x00
|
|
line.byte 0x00 "reg164,EOM Execution control"
|
|
bitfld.byte 0x00 6.--7. "EOMMode,EOMMode" "0,1,2,3"
|
|
bitfld.byte 0x00 5. "EOMRdSel,EOMRdSel" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 4. "EOMDivDis,EOMDivDis" "0,1"
|
|
bitfld.byte 0x00 3. "EOMCtrl0_Low,EOMCtrl0_Low" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "EOMStart,EOMStart" "0,1"
|
|
group.byte 0xA5++0x00
|
|
line.byte 0x00 "reg165,EOM Result 0"
|
|
hexmask.byte 0x00 0.--7. 1. "EOMRslt_1,EOMRslt_1"
|
|
group.byte 0xA6++0x00
|
|
line.byte 0x00 "reg166,EOM Result 1"
|
|
hexmask.byte 0x00 0.--7. 1. "EOMRslt_2,EOMRslt_2"
|
|
group.byte 0xA7++0x00
|
|
line.byte 0x00 "reg167,EOM Result 2"
|
|
hexmask.byte 0x00 0.--7. 1. "EOMRslt_3,EOMRslt_3"
|
|
group.byte 0xAF++0x00
|
|
line.byte 0x00 "reg175,Max RSA Calibration Wait Count"
|
|
hexmask.byte 0x00 0.--7. 1. "max_calib_RSA_wait_cnt,max_calib_RSA_wait_cnt"
|
|
group.byte 0xB0++0x00
|
|
line.byte 0x00 "reg176,Tx PLL F settings and PCLK ratio"
|
|
bitfld.byte 0x00 4.--5. "tx_div_mode2,tx_div_mode2" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. "TxF,TxF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xB1++0x00
|
|
line.byte 0x00 "reg177,Tx PLL M and N settings"
|
|
bitfld.byte 0x00 5.--6. "TxM,TxM" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. "TxN,TxN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0xB2++0x00
|
|
line.byte 0x00 "reg178,CDR PLL F settings and PCLK ratio"
|
|
bitfld.byte 0x00 4.--5. "rx_div_mode2,rx_div_mode2" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. "RxF,RxF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xB3++0x00
|
|
line.byte 0x00 "reg179,CDR PLL M and N settings"
|
|
bitfld.byte 0x00 5.--6. "RxM,RxM" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. "RxN,RxN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0xB4++0x00
|
|
line.byte 0x00 "reg180,Rx Equalization low frequency LF"
|
|
bitfld.byte 0x00 0.--5. "LF,LF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0xB5++0x00
|
|
line.byte 0x00 "reg181,A2 Gain during CTLE calibration"
|
|
bitfld.byte 0x00 6. "dB3_calib,3dB_calib" "0,1"
|
|
bitfld.byte 0x00 0.--5. "A2Gain_calib,A2Gain_calib" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0xB6++0x00
|
|
line.byte 0x00 "reg182,activity detector timeout 0 in Gen3"
|
|
hexmask.byte 0x00 0.--7. 1. "rxidle_max2_1,rxidle_max2_1"
|
|
group.byte 0xB7++0x00
|
|
line.byte 0x00 "reg183,activity detector timeout 1 in Gen3"
|
|
hexmask.byte 0x00 0.--7. 1. "rxidle_max2_2,rxidle_max2_2"
|
|
group.byte 0xB8++0x00
|
|
line.byte 0x00 "reg184,preset0 post-cursor and pre-cursor settings"
|
|
bitfld.byte 0x00 4.--7. "preset0_postcursor,preset0_postcursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "preset0_precursor,preset0_precursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xB9++0x00
|
|
line.byte 0x00 "reg185,preset1 post-cursor and pre-cursor settings"
|
|
bitfld.byte 0x00 4.--7. "preset1_postcursor,preset1_postcursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "preset1_precursor,preset1_precursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xBA++0x00
|
|
line.byte 0x00 "reg186,preset2 post-cursor and pre-cursor settings"
|
|
bitfld.byte 0x00 4.--7. "preset2_postcursor,preset2_postcursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "preset2_precursor,preset2_precursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xBB++0x00
|
|
line.byte 0x00 "reg187,preset3 post-cursor and pre-cursor settings"
|
|
bitfld.byte 0x00 4.--7. "preset3_postcursor,preset3_postcursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "preset3_precursor,preset3_precursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xBC++0x00
|
|
line.byte 0x00 "reg188,preset4 post-cursor and pre-cursor settings"
|
|
bitfld.byte 0x00 4.--7. "preset4_postcursor,preset4_postcursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "preset4_precursor,preset4_precursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xBD++0x00
|
|
line.byte 0x00 "reg189,preset5 post-cursor and pre-cursor settings"
|
|
bitfld.byte 0x00 4.--7. "preset5_postcursor,preset5_postcursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "preset5_precursor,preset5_precursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xBE++0x00
|
|
line.byte 0x00 "reg190,preset6 post-cursor and pre-cursor settings"
|
|
bitfld.byte 0x00 4.--7. "preset6_postcursor,preset6_postcursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "preset6_precursor,preset6_precursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xBF++0x00
|
|
line.byte 0x00 "reg191,preset7 post-cursor and pre-cursor settings"
|
|
bitfld.byte 0x00 4.--7. "preset7_postcursor,preset7_postcursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "preset7_precursor,preset7_precursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "reg192,preset8 post-cursor and pre-cursor settings"
|
|
bitfld.byte 0x00 4.--7. "preset8_postcursor,preset8_postcursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "preset8_precursor,preset8_precursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xC1++0x00
|
|
line.byte 0x00 "reg193,preset9 post-cursor and pre-cursor settings"
|
|
bitfld.byte 0x00 4.--7. "preset9_postcursor,preset9_postcursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "preset9_precursor,preset9_precursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xC2++0x00
|
|
line.byte 0x00 "reg194,preset10 post-cursor and pre-cursor settings"
|
|
bitfld.byte 0x00 4.--7. "preset10_postcursor,preset10_postcursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. "preset10_precursor,preset10_precursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xC3++0x00
|
|
line.byte 0x00 "reg195,Rx Equlaization init preset count"
|
|
bitfld.byte 0x00 0.--3. "preset_count_ini,preset_count_ini" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "reg196,CDR PLL coarse grain phase-lock timer before Rx Equalization"
|
|
hexmask.byte 0x00 0.--7. 1. "cdrpll_pre_rxeq_coarse_timer,cdrpll_pre_rxeq_coarse_timer"
|
|
group.byte 0xC5++0x00
|
|
line.byte 0x00 "reg197,CDR PLL coarse grain phase-lock timer after Rx Equalization"
|
|
hexmask.byte 0x00 0.--7. 1. "cdrpll_pst_rxeq_coarse_timer,cdrpll_pst_rxeq_coarse_timer"
|
|
group.byte 0xC6++0x00
|
|
line.byte 0x00 "reg198,CDR PLL fine grain phase-lock timer before Rx Equalization"
|
|
hexmask.byte 0x00 0.--7. 1. "cdrpll_pre_rxeq_fine_timer,cdrpll_pre_rxeq_fine_timer"
|
|
group.byte 0xC7++0x00
|
|
line.byte 0x00 "reg199,CDR PLL fine grain phase-lock timer after Rx Equalization"
|
|
hexmask.byte 0x00 0.--7. 1. "cdrpll_pst_rxeq_fine_timer,cdrpll_pst_rxeq_fine_timer"
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "reg200,Rx Preset Hint 0 mapping to A0 A2 Gain and CTLEgain3db"
|
|
bitfld.byte 0x00 6. "Hint0_3db,Hint0_3db" "0,1"
|
|
bitfld.byte 0x00 3.--5. "Hint0_A0Gain,Hint0_A0Gain" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "Hint0_A2Gain,Hint0_A2Gain" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xC9++0x00
|
|
line.byte 0x00 "reg201,Rx Preset Hint 1 mapping to A0 A2 Gain and CTLEgain3db"
|
|
bitfld.byte 0x00 6. "Hint1_3db,Hint1_3db" "0,1"
|
|
bitfld.byte 0x00 3.--5. "Hint1_A0Gain,Hint1_A0Gain" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "Hint1_A2Gain,Hint1_A2Gain" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xCA++0x00
|
|
line.byte 0x00 "reg202,Rx Preset Hint 2 mapping to A0 A2 Gain and CTLEgain3db"
|
|
bitfld.byte 0x00 6. "Hint2_3db,Hint2_3db" "0,1"
|
|
bitfld.byte 0x00 3.--5. "Hint2_A0Gain,Hint2_A0Gain" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "Hint2_A2Gain,Hint2_A2Gain" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xCB++0x00
|
|
line.byte 0x00 "reg203,Rx Preset Hint 3 mapping to A0 A2 Gain and CTLEgain3db"
|
|
bitfld.byte 0x00 6. "Hint3_3db,Hint3_3db" "0,1"
|
|
bitfld.byte 0x00 3.--5. "Hint3_A0Gain,Hint3_A0Gain" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "Hint3_A2Gain,Hint3_A2Gain" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "reg204,Rx Preset Hint 4 mapping to A0 A2 Gain and CTLEgain3db"
|
|
bitfld.byte 0x00 6. "Hint4_3db,Hint4_3db" "0,1"
|
|
bitfld.byte 0x00 3.--5. "Hint4_A0Gain,Hint4_A0Gain" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "Hint4_A2Gain,Hint4_A2Gain" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xCD++0x00
|
|
line.byte 0x00 "reg205,Rx Preset Hint 5 mapping to A0 A2 Gain and CTLEgain3db"
|
|
bitfld.byte 0x00 6. "Hint5_3db,Hint5_3db" "0,1"
|
|
bitfld.byte 0x00 3.--5. "Hint5_A0Gain,Hint5_A0Gain" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "Hint5_A2Gain,Hint5_A2Gain" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xCE++0x00
|
|
line.byte 0x00 "reg206,Rx Preset Hint 6 mapping to A0 A2 Gain and CTLEgain3db"
|
|
bitfld.byte 0x00 6. "Hint6_3db,Hint6_3db" "0,1"
|
|
bitfld.byte 0x00 3.--5. "Hint6_A0Gain,Hint6_A0Gain" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "Hint6_A2Gain,Hint6_A2Gain" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xCF++0x00
|
|
line.byte 0x00 "reg207,Rx Preset Hint 7 mapping to A0 A2 Gain and CTLEgain3db"
|
|
bitfld.byte 0x00 6. "Hint7_3db,Hint7_3db" "0,1"
|
|
bitfld.byte 0x00 3.--5. "Hint7_A0Gain,Hint7_A0Gain" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x00 0.--2. "Hint7_A2Gain,Hint7_A2Gain" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "reg208,Pre-Equalization A2 and A1 Gain"
|
|
bitfld.byte 0x00 3.--5. "pre_a1coef,pre_a1coef" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--2. "pre_a2coef,pre_a2coef" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xD1++0x00
|
|
line.byte 0x00 "reg209,Pre-Equalization A0 Gain and iteration count"
|
|
bitfld.byte 0x00 7. "gen3_ena,gen3_ena" "0,1"
|
|
bitfld.byte 0x00 6. "gen12_ena,gen12_ena" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3.--5. "pre_itercnt,pre_itercnt" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--2. "pre_a0coef,pre_a0coef" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xD2++0x00
|
|
line.byte 0x00 "reg210,Post-Equalization A2 and A1 Gain"
|
|
bitfld.byte 0x00 3.--5. "post_a1coef,post_a1coef" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--2. "post_a2coef,post_a2coef" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xD3++0x00
|
|
line.byte 0x00 "reg211,Post-Equalization A0 Gain and iteration count"
|
|
bitfld.byte 0x00 7. "gen3_ena,gen3_ena" "0,1"
|
|
bitfld.byte 0x00 6. "gen12_ena,gen12_ena" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3.--5. "post_itercnt,post_itercnt" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--2. "post_a0coef,post_a0coef" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "reg212,Equalization Training A2 and A1 Gain"
|
|
bitfld.byte 0x00 3.--5. "trng_a1coef,trng_a1coef" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--2. "trng_a2coef,trng_a2coef" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "reg213,Equalization Training A0 Gain and iteration count"
|
|
bitfld.byte 0x00 7. "gen3_ena,gen3_ena" "0,1"
|
|
bitfld.byte 0x00 6. "gen12_ena,gen12_ena" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3.--5. "trng_itercnt,trng_itercnt" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--2. "trng_a0coef,trng_a0coef" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xD6++0x00
|
|
line.byte 0x00 "reg214,Rx Equalization discard timer"
|
|
bitfld.byte 0x00 4.--6. "a_chngd_max,a_chngd_max" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--2. "ctle_settle,ctle_settle" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "reg215,FOM control register 0"
|
|
bitfld.byte 0x00 7. "fom_hires,fom_hires" "0,1"
|
|
bitfld.byte 0x00 4.--6. "pre_fom_avg,pre_fom_avg" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "fom_thr,fom_thr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "reg216,FOM control register 1"
|
|
bitfld.byte 0x00 7. "pre_fom,pre_fom" "0,1"
|
|
bitfld.byte 0x00 6. "cur_fom,cur_fom" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3.--5. "cur_fom_avg,cur_fom_avg" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--2. "fom_itercnt,fom_itercnt" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xD9++0x00
|
|
line.byte 0x00 "reg217,Adaptive equalization enable register"
|
|
bitfld.byte 0x00 7. "byp_avg,byp_avg" "0,1"
|
|
bitfld.byte 0x00 4.--6. "rxeq_algo,rxeq_algo" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x00 3. "mode_bff,mode_bff" "0,1"
|
|
bitfld.byte 0x00 0.--2. "rxeq_enable,rxeq_enable" "0,1,2,3,4,5,6,7"
|
|
group.byte 0xDA++0x00
|
|
line.byte 0x00 "reg218,Adaptive equalization alert register"
|
|
bitfld.byte 0x00 5.--7. "alert_enable,alert_enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--4. "max_var,max_var" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0xDB++0x00
|
|
line.byte 0x00 "reg219,Maximum number of evaluation"
|
|
hexmask.byte 0x00 0.--7. 1. "rxeq_eval_max,rxeq_eval_max"
|
|
group.byte 0xDC++0x00
|
|
line.byte 0x00 "reg220,Force Direction result"
|
|
bitfld.byte 0x00 0.--5. "force_dir_rslt,force_dir_rslt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0xDD++0x00
|
|
line.byte 0x00 "reg221,Force FOM result"
|
|
hexmask.byte 0x00 0.--7. 1. "force_fom_rslt,force_fom_rslt"
|
|
group.byte 0xDE++0x00
|
|
line.byte 0x00 "reg222,maximum number of evaluation in pre-training"
|
|
hexmask.byte 0x00 0.--7. 1. "pre_rxeq_timer,pre_rxeq_timer"
|
|
rgroup.byte 0xDF++0x00
|
|
line.byte 0x00 "reg223,maximum number of evaluation in training"
|
|
hexmask.byte 0x00 0.--7. 1. "trng_rxeq_timer,trng_rxeq_timer"
|
|
rgroup.byte 0xE0++0x00
|
|
line.byte 0x00 "reg224,Direction result"
|
|
bitfld.byte 0x00 0.--5. "dir_rslt,dir_rslt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0xE1++0x00
|
|
line.byte 0x00 "reg225,FOM result"
|
|
hexmask.byte 0x00 0.--7. 1. "fom_rslt,fom_rslt"
|
|
rgroup.byte 0xE2++0x00
|
|
line.byte 0x00 "reg226,Rx Equalization current state"
|
|
bitfld.byte 0x00 0.--3. "rxeq_fsm,rxeq_fsm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0xE3++0x00
|
|
line.byte 0x00 "reg227,Rx Equalization current number of evaluation"
|
|
bitfld.byte 0x00 7. "eval_seen,eval_seen" "0,1"
|
|
hexmask.byte 0x00 0.--6. 1. "eval_count,eval_count"
|
|
rgroup.byte 0xE4++0x00
|
|
line.byte 0x00 "reg228,Rx Equalization A0 Gain"
|
|
bitfld.byte 0x00 0.--5. "A0Gain,A0Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0xE5++0x00
|
|
line.byte 0x00 "reg229,Rx Equalization A1 Gain"
|
|
bitfld.byte 0x00 0.--5. "A1Gain,A1Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0xE6++0x00
|
|
line.byte 0x00 "reg230,Rx Equalization A2 Gain"
|
|
bitfld.byte 0x00 0.--5. "A2Gain,A2Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0xE7++0x00
|
|
line.byte 0x00 "reg231,Best FOM Found Rx Equalization A0 Gain"
|
|
bitfld.byte 0x00 0.--5. "BFF_a0Gain,BFF_a0Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0xE8++0x00
|
|
line.byte 0x00 "reg232,FOM result a0dir=0 / a1dir=0"
|
|
hexmask.byte 0x00 0.--7. 1. "fom_rslt00,fom_rslt00"
|
|
rgroup.byte 0xE9++0x00
|
|
line.byte 0x00 "reg233,FOM result a0dir=1 / a1dir=0"
|
|
hexmask.byte 0x00 0.--7. 1. "fom_rslt01,fom_rslt01"
|
|
rgroup.byte 0xEA++0x00
|
|
line.byte 0x00 "reg234,FOM result a0dir=0 / a1dir=1"
|
|
hexmask.byte 0x00 0.--7. 1. "fom_rslt10,fom_rslt10"
|
|
rgroup.byte 0xEB++0x00
|
|
line.byte 0x00 "reg235,FOM result a0dir=1 / a1dir=1"
|
|
hexmask.byte 0x00 0.--7. 1. "fom_rslt11,fom_rslt11"
|
|
rgroup.byte 0xEC++0x00
|
|
line.byte 0x00 "reg236,Best FOM Found Rx Equalization A1 Gain"
|
|
bitfld.byte 0x00 0.--5. "BFF_a1Gain,BFF_a1Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0xED++0x00
|
|
line.byte 0x00 "reg237,Best FOM Found Rx Equalization A2 Gain"
|
|
bitfld.byte 0x00 0.--5. "BFF_a2Gain,BFF_a2Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0xEE++0x00
|
|
line.byte 0x00 "reg238,MAC signal snooping"
|
|
bitfld.byte 0x00 1.--3. "presethint,presethint" "0,1,2,3,4,5,6,7"
|
|
rgroup.byte 0xEF++0x00
|
|
line.byte 0x00 "reg239,MAC event status"
|
|
bitfld.byte 0x00 5. "invalreq,invalreq" "0,1"
|
|
bitfld.byte 0x00 4. "gen3_entry,gen3_entry" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "gen2_entry,gen2_entry" "0,1"
|
|
bitfld.byte 0x00 2. "gen1_entry,gen1_entry" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "rxeq_start,rxeq_start" "0,1"
|
|
bitfld.byte 0x00 0. "rxeq_stop,rxeq_stop" "0,1"
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "reg240,Force A0 Gain"
|
|
bitfld.byte 0x00 7. "A0_force,A0_force" "0,1"
|
|
bitfld.byte 0x00 6. "A0_freeze,A0_freeze" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--5. "A0_init,A0_init" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0xF1++0x00
|
|
line.byte 0x00 "reg241,Force A1 Gain"
|
|
bitfld.byte 0x00 7. "A1_force,A1_force" "0,1"
|
|
bitfld.byte 0x00 6. "A1_freeze,A1_freeze" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--5. "A1_init,A1_init" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0xF2++0x00
|
|
line.byte 0x00 "reg242,Force A2 Gain"
|
|
bitfld.byte 0x00 7. "A2_force,A2_force" "0,1"
|
|
bitfld.byte 0x00 6. "A2_freeze,A2_freeze" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--5. "A2_init,A2_init" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0xF3++0x00
|
|
line.byte 0x00 "reg243,Rx Equalization Training override"
|
|
bitfld.byte 0x00 7. "rxeq_manual,rxeq_manual" "0,1"
|
|
bitfld.byte 0x00 6. "ovr_cdr,ovr_cdr" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "ovr_dir,ovr_dir" "0,1"
|
|
bitfld.byte 0x00 4. "ovr_fom,ovr_fom" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "rxeq_state,rxeq_state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "reg244,FOM compare register"
|
|
hexmask.byte 0x00 0.--7. 1. "FOM_compare,FOM_compare"
|
|
rgroup.byte 0xF5++0x00
|
|
line.byte 0x00 "reg245,FOM compare result"
|
|
bitfld.byte 0x00 0. "FOM_pass,FOM_pass" "0,1"
|
|
group.byte 0xF6++0x00
|
|
line.byte 0x00 "reg246,Rx Equalization a0dir/a1dir override and alternate direction modes"
|
|
bitfld.byte 0x00 5. "mix_dir,mix_dir" "0,1"
|
|
bitfld.byte 0x00 4. "dsp_dir,dsp_dir" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. "adir_ovr,adir_ovr" "0,1"
|
|
bitfld.byte 0x00 1. "a1dir_val,a1dir_val" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0. "a0dir_val,a0dir_val" "0,1"
|
|
rgroup.byte 0xF7++0x00
|
|
line.byte 0x00 "reg247,Rx Equalization farthest gathered samples"
|
|
bitfld.byte 0x00 7. "old14,old14" "0,1"
|
|
bitfld.byte 0x00 6. "old13,old13" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "old12,old12" "0,1"
|
|
bitfld.byte 0x00 4. "old11,old11" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "new4,new4" "0,1"
|
|
bitfld.byte 0x00 2. "new3,new3" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "new2,new2" "0,1"
|
|
bitfld.byte 0x00 0. "new1,new1" "0,1"
|
|
rgroup.byte 0xF8++0x00
|
|
line.byte 0x00 "reg248,Rx Equalization gathered samples"
|
|
bitfld.byte 0x00 7. "err19,err19" "0,1"
|
|
bitfld.byte 0x00 6. "err18,err18" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "new0,new0" "0,1"
|
|
bitfld.byte 0x00 4. "old19,old19" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "old18,old18" "0,1"
|
|
bitfld.byte 0x00 2. "old17,old17" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "old16,old16" "0,1"
|
|
bitfld.byte 0x00 0. "old15,old15" "0,1"
|
|
group.byte 0xF9++0x00
|
|
line.byte 0x00 "reg249,DSP direction LUT Post_cursor Sign 0"
|
|
hexmask.byte 0x00 0.--7. 1. "dspdir_pstsgn0,dspdir_pstsgn0"
|
|
group.byte 0xFA++0x00
|
|
line.byte 0x00 "reg250,DSP direction LUT Post_cursor Sign 1"
|
|
hexmask.byte 0x00 0.--7. 1. "dspdir_pstsgn1,dspdir_pstsgn1"
|
|
group.byte 0xFB++0x00
|
|
line.byte 0x00 "reg251,DSP direction LUT Post-cursor Ampliture 0"
|
|
hexmask.byte 0x00 0.--7. 1. "dspdir_pstval0,dspdir_pstval0"
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "reg252,DSP direction LUT Post-cursor Ampliture 1"
|
|
hexmask.byte 0x00 0.--7. 1. "dspdir_pstval1,dspdir_pstval1"
|
|
group.byte 0xFD++0x00
|
|
line.byte 0x00 "reg253,DSP direction LUT Pre-cursor Sign"
|
|
hexmask.byte 0x00 0.--7. 1. "dspdir_presgn,dspdir_presgn"
|
|
group.byte 0xFE++0x00
|
|
line.byte 0x00 "reg254,DSP direction LUT Pre-cursor Amplitude"
|
|
hexmask.byte 0x00 0.--7. 1. "dspdir_preval,dspdir_preval"
|
|
group.byte 0xFF++0x00
|
|
line.byte 0x00 "reg255,Timer Gain1 and DSP direction timer"
|
|
bitfld.byte 0x00 6.--7. "dir_pre_gain,dir_pre_gain" "0,1,2,3"
|
|
bitfld.byte 0x00 4.--5. "dir_pst_gain,dir_pst_gain" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "gain_timer1,gain_timer1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "PWM (Pulse-Width Modulator)"
|
|
tree "ADMA__PWM"
|
|
base ad:0x5A190000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 26.--27. "FWM,FWM" "0: FIFO empty flag is set when there are more..,1: FIFO empty flag is set when there are more..,2: FIFO empty flag is set when there are more..,3: FIFO empty flag is set when there are more.."
|
|
bitfld.long 0x00 25. "STOPEN,STOPEN" "0: Inactive in stop mode,1: Active in stop mode"
|
|
newline
|
|
bitfld.long 0x00 24. "DOZEN,DOZEN" "0: Inactive in doze mode,1: Active in doze mode"
|
|
bitfld.long 0x00 23. "WAITEN,WAITEN" "0: Inactive in wait mode,1: Active in wait mode"
|
|
newline
|
|
bitfld.long 0x00 22. "DBGEN,DBGEN" "0: Inactive in debug mode,1: Active in debug mode"
|
|
bitfld.long 0x00 21. "BCTR,BCTR" "0: byte ordering remains the same,1: byte ordering is reversed"
|
|
newline
|
|
bitfld.long 0x00 20. "HCTR,HCTR" "0: Half word swapping does not take place,1: Half words from write data bus are swapped"
|
|
bitfld.long 0x00 18.--19. "POUTC,POUTC" "0: Output pin is set at rollover and cleared at..,1: Output pin is cleared at rollover and set at..,2: PWM output is disconnected,3: PWM output is disconnected"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "CLKSRC,CLKSRC" "0: Clock is off,1: CLKSRC_1,2: ipg_clk_highfreq,3: ipg_clk_32k"
|
|
hexmask.long.word 0x00 4.--15. 1. "PRESCALER,PRESCALER"
|
|
newline
|
|
bitfld.long 0x00 3. "SWR,SWR" "0: PWM is out of reset,1: PWM is undergoing reset"
|
|
bitfld.long 0x00 1.--2. "REPEAT,REPEAT" "0: Use each sample once,1: Use each sample twice,2: Use each sample four times,3: Use each sample eight times"
|
|
newline
|
|
bitfld.long 0x00 0. "EN,EN" "0: PWM disabled,1: PWM enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWMSR,PWM Status Register"
|
|
eventfld.long 0x00 6. "FWE,FWE" "0: FIFO write error not occurred,1: FIFO write error occurred"
|
|
eventfld.long 0x00 5. "CMP,CMP" "0: Compare event not occurred,1: Compare event occurred"
|
|
newline
|
|
eventfld.long 0x00 4. "ROV,ROV" "0: Roll-over event not occurred,1: Roll-over event occurred"
|
|
eventfld.long 0x00 3. "FE,FE" "0: Data level is above water mark,1: When the data level falls below the mark set.."
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "FIFOAV,FIFOAV" "0: No data available,1: 1 word of data in FIFO,2: 2 words of data in FIFO,3: 3 words of data in FIFO,4: 4 words of data in FIFO,5: FIFOAV_5,6: FIFOAV_6,7: FIFOAV_7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PWMIR,PWM Interrupt Register"
|
|
bitfld.long 0x00 2. "CIE,CIE" "0: Compare Interrupt not enabled,1: Compare Interrupt enabled"
|
|
bitfld.long 0x00 1. "RIE,RIE" "0: Roll-over interrupt not enabled,1: Roll-over Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FIE,FIE" "0: FIFO Empty interrupt disabled,1: FIFO Empty interrupt enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "SAMPLE,SAMPLE"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PWMPR,PWM Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PERIOD"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PWMCNR,PWM Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,COUNT"
|
|
tree.end
|
|
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7.) (list ad:0x5D000000 ad:0x5D010000 ad:0x5D020000 ad:0x5D030000 ad:0x5D040000 ad:0x5D050000 ad:0x5D060000 ad:0x5D070000)
|
|
tree "LSIO__PWM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 26.--27. "FWM,FWM" "0: FIFO empty flag is set when there are more..,1: FIFO empty flag is set when there are more..,2: FIFO empty flag is set when there are more..,3: FIFO empty flag is set when there are more.."
|
|
bitfld.long 0x00 25. "STOPEN,STOPEN" "0: Inactive in stop mode,1: Active in stop mode"
|
|
newline
|
|
bitfld.long 0x00 24. "DOZEN,DOZEN" "0: Inactive in doze mode,1: Active in doze mode"
|
|
bitfld.long 0x00 23. "WAITEN,WAITEN" "0: Inactive in wait mode,1: Active in wait mode"
|
|
newline
|
|
bitfld.long 0x00 22. "DBGEN,DBGEN" "0: Inactive in debug mode,1: Active in debug mode"
|
|
bitfld.long 0x00 21. "BCTR,BCTR" "0: byte ordering remains the same,1: byte ordering is reversed"
|
|
newline
|
|
bitfld.long 0x00 20. "HCTR,HCTR" "0: Half word swapping does not take place,1: Half words from write data bus are swapped"
|
|
bitfld.long 0x00 18.--19. "POUTC,POUTC" "0: Output pin is set at rollover and cleared at..,1: Output pin is cleared at rollover and set at..,2: PWM output is disconnected,3: PWM output is disconnected"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "CLKSRC,CLKSRC" "0: Clock is off,1: CLKSRC_1,2: ipg_clk_highfreq,3: ipg_clk_32k"
|
|
hexmask.long.word 0x00 4.--15. 1. "PRESCALER,PRESCALER"
|
|
newline
|
|
bitfld.long 0x00 3. "SWR,SWR" "0: PWM is out of reset,1: PWM is undergoing reset"
|
|
bitfld.long 0x00 1.--2. "REPEAT,REPEAT" "0: Use each sample once,1: Use each sample twice,2: Use each sample four times,3: Use each sample eight times"
|
|
newline
|
|
bitfld.long 0x00 0. "EN,EN" "0: PWM disabled,1: PWM enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWMSR,PWM Status Register"
|
|
eventfld.long 0x00 6. "FWE,FWE" "0: FIFO write error not occurred,1: FIFO write error occurred"
|
|
eventfld.long 0x00 5. "CMP,CMP" "0: Compare event not occurred,1: Compare event occurred"
|
|
newline
|
|
eventfld.long 0x00 4. "ROV,ROV" "0: Roll-over event not occurred,1: Roll-over event occurred"
|
|
eventfld.long 0x00 3. "FE,FE" "0: Data level is above water mark,1: When the data level falls below the mark set.."
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "FIFOAV,FIFOAV" "0: No data available,1: 1 word of data in FIFO,2: 2 words of data in FIFO,3: 3 words of data in FIFO,4: 4 words of data in FIFO,5: FIFOAV_5,6: FIFOAV_6,7: FIFOAV_7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PWMIR,PWM Interrupt Register"
|
|
bitfld.long 0x00 2. "CIE,CIE" "0: Compare Interrupt not enabled,1: Compare Interrupt enabled"
|
|
bitfld.long 0x00 1. "RIE,RIE" "0: Roll-over interrupt not enabled,1: Roll-over Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "FIE,FIE" "0: FIFO Empty interrupt disabled,1: FIFO Empty interrupt enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "SAMPLE,SAMPLE"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PWMPR,PWM Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PERIOD"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PWMCNR,PWM Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,COUNT"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "RGPIO2P (GPIO)"
|
|
tree "CM4__RGPIO"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x410F0000
|
|
else
|
|
base ad:0x370F0000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
tree.end
|
|
tree "SCU__RGPIO"
|
|
base ad:0x330F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR,Port Data Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDO,Port Data Output"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSOR,Port Set Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTSO,Port Set Output"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCOR,Port Clear Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTCO,Port Clear Output"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
hexmask.long 0x00 0.--31. 1. "PTTO,Port Toggle Output"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDI,Port Data Input"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDD,Port Data Direction"
|
|
tree.end
|
|
tree.end
|
|
tree "SAI (I2S)"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x59040000 ad:0x59050000 ad:0x59060000 ad:0x59070000)
|
|
tree "ADMA__SAI$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TCSR,SAI Transmit Control Register"
|
|
bitfld.long 0x00 31. "TE,Transmitter Enable" "0: Transmitter is disabled,1: Transmitter is enabled or transmitter has.."
|
|
bitfld.long 0x00 30. "STOPE,Stop Enable" "0: Transmitter disabled in Stop mode,1: Transmitter enabled in Stop mode"
|
|
newline
|
|
bitfld.long 0x00 29. "DBGE,Debug Enable" "0: Transmitter is disabled in Debug mode after..,1: Transmitter is enabled in Debug mode"
|
|
bitfld.long 0x00 28. "BCE,Bit Clock Enable" "0: Transmit bit clock is disabled,1: Transmit bit clock is enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "FR,FIFO Reset" "0: No effect,1: FIFO reset"
|
|
bitfld.long 0x00 24. "SR,Software Reset" "0: No effect,1: Software reset"
|
|
newline
|
|
eventfld.long 0x00 20. "WSF,Word Start Flag" "0: Start of word not detected,1: Start of word detected"
|
|
eventfld.long 0x00 19. "SEF,Sync Error Flag" "0: Sync error not detected,1: Frame sync error detected"
|
|
newline
|
|
eventfld.long 0x00 18. "FEF,FIFO Error Flag" "0: Transmit underrun not detected,1: Transmit underrun detected"
|
|
rbitfld.long 0x00 17. "FWF,FIFO Warning Flag" "0: No enabled transmit FIFO is empty,1: Enabled transmit FIFO is empty"
|
|
newline
|
|
rbitfld.long 0x00 16. "FRF,FIFO Request Flag" "0: Transmit FIFO watermark has not been reached,1: Transmit FIFO watermark has been reached"
|
|
bitfld.long 0x00 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
bitfld.long 0x00 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
bitfld.long 0x00 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "FWDE,FIFO Warning DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
bitfld.long 0x00 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TCR1,SAI Transmit Configuration 1 Register"
|
|
bitfld.long 0x00 0.--5. "TFW,Transmit FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with receiver,2: Synchronous with another SAI transmitter,3: Synchronous with another SAI receiver"
|
|
bitfld.long 0x00 29. "BCS,Bit Clock Swap" "0: Use the normal bit clock source,1: Swap the bit clock source"
|
|
newline
|
|
bitfld.long 0x00 28. "BCI,Bit Clock Input" "0: No effect,1: Internal logic is clocked as if bit clock was.."
|
|
bitfld.long 0x00 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected,1: Master Clock (MCLK) 1 option selected,2: Master Clock (MCLK) 2 option selected,3: Master Clock (MCLK) 3 option selected"
|
|
newline
|
|
bitfld.long 0x00 25. "BCP,Bit Clock Polarity" "0: Bit clock is active high with drive outputs..,1: Bit clock is active low with drive outputs on.."
|
|
bitfld.long 0x00 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode,1: Bit clock is generated internally in Master.."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV,Bit Clock Divide"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TCR3,SAI Transmit Configuration 3 Register"
|
|
bitfld.long 0x00 16. "TCE,Transmit Channel Enable" "0,1"
|
|
bitfld.long 0x00 0.--4. "WDFL,Word Flag Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TCR4,SAI Transmit Configuration 4 Register"
|
|
bitfld.long 0x00 28. "FCONT,FIFO Continue on Error" "0: On FIFO error the SAI will continue from the..,1: On FIFO error the SAI will continue from the.."
|
|
bitfld.long 0x00 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled,?,2: 8-bit FIFO packing is enabled,3: 16-bit FIFO packing is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "FRSZ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. "SYWD,Sync Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 4. "MF,MSB First" "0: LSB is transmitted first,1: MSB is transmitted first"
|
|
bitfld.long 0x00 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first.."
|
|
newline
|
|
bitfld.long 0x00 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously,1: Internal frame sync is generated when the.."
|
|
bitfld.long 0x00 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high,1: Frame sync is active low"
|
|
newline
|
|
bitfld.long 0x00 0. "FSD,Frame Sync Direction" "0: Frame sync is generated externally in Slave..,1: Frame sync is generated internally in Master.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TCR5,SAI Transmit Configuration 5 Register"
|
|
bitfld.long 0x00 24.--28. "WNW,Word N Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "W0W,Word 0 Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "FBT,First Bit Shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TDR0,SAI Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "TDR,Transmit Data Register"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TFR0,SAI Transmit FIFO Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "WFP,Write FIFO Pointer"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RFP,Read FIFO Pointer"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TMR,SAI Transmit Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. "TWM,Transmit Word Mask"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RCSR,SAI Receive Control Register"
|
|
bitfld.long 0x00 31. "RE,Receiver Enable" "0: Receiver is disabled,1: Receiver is enabled or receiver has been.."
|
|
bitfld.long 0x00 30. "STOPE,Stop Enable" "0: Receiver disabled in Stop mode,1: Receiver enabled in Stop mode"
|
|
newline
|
|
bitfld.long 0x00 29. "DBGE,Debug Enable" "0: Receiver is disabled in Debug mode after..,1: Receiver is enabled in Debug mode"
|
|
bitfld.long 0x00 28. "BCE,Bit Clock Enable" "0: Receive bit clock is disabled,1: Receive bit clock is enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "FR,FIFO Reset" "0: No effect,1: FIFO reset"
|
|
bitfld.long 0x00 24. "SR,Software Reset" "0: No effect,1: Software reset"
|
|
newline
|
|
eventfld.long 0x00 20. "WSF,Word Start Flag" "0: Start of word not detected,1: Start of word detected"
|
|
eventfld.long 0x00 19. "SEF,Sync Error Flag" "0: Sync error not detected,1: Frame sync error detected"
|
|
newline
|
|
eventfld.long 0x00 18. "FEF,FIFO Error Flag" "0: Receive overflow not detected,1: Receive overflow detected"
|
|
rbitfld.long 0x00 17. "FWF,FIFO Warning Flag" "0: No enabled receive FIFO is full,1: Enabled receive FIFO is full"
|
|
newline
|
|
rbitfld.long 0x00 16. "FRF,FIFO Request Flag" "0: Receive FIFO watermark not reached,1: Receive FIFO watermark has been reached"
|
|
bitfld.long 0x00 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
bitfld.long 0x00 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
bitfld.long 0x00 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. "FWDE,FIFO Warning DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
bitfld.long 0x00 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RCR1,SAI Receive Configuration 1 Register"
|
|
bitfld.long 0x00 0.--5. "RFW,Receive FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RCR2,SAI Receive Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with transmitter,2: Synchronous with another SAI receiver,3: Synchronous with another SAI transmitter"
|
|
bitfld.long 0x00 29. "BCS,Bit Clock Swap" "0: Use the normal bit clock source,1: Swap the bit clock source"
|
|
newline
|
|
bitfld.long 0x00 28. "BCI,Bit Clock Input" "0: No effect,1: Internal logic is clocked as if bit clock was.."
|
|
bitfld.long 0x00 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected,1: Master Clock (MCLK) 1 option selected,2: Master Clock (MCLK) 2 option selected,3: Master Clock (MCLK) 3 option selected"
|
|
newline
|
|
bitfld.long 0x00 25. "BCP,Bit Clock Polarity" "0: Bit Clock is active high with drive outputs..,1: Bit Clock is active low with drive outputs on.."
|
|
bitfld.long 0x00 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode,1: Bit clock is generated internally in Master.."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV,Bit Clock Divide"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "RCR3,SAI Receive Configuration 3 Register"
|
|
bitfld.long 0x00 16. "RCE,Receive Channel Enable" "0,1"
|
|
bitfld.long 0x00 0.--4. "WDFL,Word Flag Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "RCR4,SAI Receive Configuration 4 Register"
|
|
bitfld.long 0x00 28. "FCONT,FIFO Continue on Error" "0: On FIFO error the SAI will continue from the..,1: On FIFO error the SAI will continue from the.."
|
|
bitfld.long 0x00 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled,?,2: 8-bit FIFO packing is enabled,3: 16-bit FIFO packing is enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "FRSZ,Frame Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. "SYWD,Sync Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 4. "MF,MSB First" "0: LSB is received first,1: MSB is received first"
|
|
bitfld.long 0x00 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first.."
|
|
newline
|
|
bitfld.long 0x00 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously,1: Internal frame sync is generated when the.."
|
|
bitfld.long 0x00 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high,1: Frame sync is active low"
|
|
newline
|
|
bitfld.long 0x00 0. "FSD,Frame Sync Direction" "0: Frame Sync is generated externally in Slave..,1: Frame Sync is generated internally in Master.."
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "RCR5,SAI Receive Configuration 5 Register"
|
|
bitfld.long 0x00 24.--28. "WNW,Word N Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "W0W,Word 0 Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "FBT,First Bit Shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "RDR0,SAI Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "RDR,Receive Data Register"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "RFR0,SAI Receive FIFO Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "WFP,Write FIFO Pointer"
|
|
hexmask.long.byte 0x00 0.--6. 1. "RFP,Read FIFO Pointer"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RMR,SAI Receive Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. "RWM,Receive Word Mask"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SEMA42_IPS (SEMA42)"
|
|
tree "CM4__SEMA42"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x411B0000
|
|
else
|
|
base ad:0x371B0000
|
|
endif
|
|
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x00)++0x00
|
|
line.byte 0x00 "GATE$1,Gate Register"
|
|
bitfld.byte 0x00 0.--3. "GTFSM,Gate finite state machine" "0: The gate is unlocked (free),1: Domain 0 locked the gate,2: Domain 1 locked the gate,3: Domain 2 locked the gate,4: Domain 3 locked the gate,5: Domain 4 locked the gate,6: Domain 5 locked the gate,7: Domain 6 locked the gate,8: Domain 7 locked the gate,9: Domain 8 locked the gate,10: Domain 9 locked the gate,11: Domain 10 locked the gate,12: Domain 11 locked the gate,13: Domain 12 locked the gate,14: Domain 13 locked the gate,15: Domain 14 locked the gate"
|
|
repeat.end
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "RSTGT_R,Reset Gate"
|
|
bitfld.word 0x00 14.--15. "ROZ,ROZ" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. "RSTGSM,Reset gate finite state machine" "0: Idle waiting for the first data pattern,1: Waiting for the second data pattern,2: The 2-write sequence has completed,?..."
|
|
newline
|
|
bitfld.word 0x00 8.--11. "RSTGMS,Reset gate domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word.byte 0x00 0.--7. 1. "RSTGTN,Reset gate number"
|
|
wgroup.word 0x42++0x01
|
|
line.word 0x00 "RSTGT_W,Reset Gate"
|
|
hexmask.word.byte 0x00 8.--15. 1. "RSTGDP,Reset gate data pattern"
|
|
hexmask.word.byte 0x00 0.--7. 1. "RSTGTN,Reset gate number"
|
|
tree.end
|
|
tree "SCU__SEMA42"
|
|
base ad:0x331B0000
|
|
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x00)++0x00
|
|
line.byte 0x00 "GATE$1,Gate Register"
|
|
bitfld.byte 0x00 0.--3. "GTFSM,Gate finite state machine" "0: The gate is unlocked (free),1: Domain 0 locked the gate,2: Domain 1 locked the gate,3: Domain 2 locked the gate,4: Domain 3 locked the gate,5: Domain 4 locked the gate,6: Domain 5 locked the gate,7: Domain 6 locked the gate,8: Domain 7 locked the gate,9: Domain 8 locked the gate,10: Domain 9 locked the gate,11: Domain 10 locked the gate,12: Domain 11 locked the gate,13: Domain 12 locked the gate,14: Domain 13 locked the gate,15: Domain 14 locked the gate"
|
|
repeat.end
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "RSTGT_R,Reset Gate"
|
|
bitfld.word 0x00 14.--15. "ROZ,ROZ" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. "RSTGSM,Reset gate finite state machine" "0: Idle waiting for the first data pattern,1: Waiting for the second data pattern,2: The 2-write sequence has completed,?..."
|
|
newline
|
|
bitfld.word 0x00 8.--11. "RSTGMS,Reset gate domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word.byte 0x00 0.--7. 1. "RSTGTN,Reset gate number"
|
|
wgroup.word 0x42++0x01
|
|
line.word 0x00 "RSTGT_W,Reset Gate"
|
|
hexmask.word.byte 0x00 8.--15. 1. "RSTGDP,Reset gate data pattern"
|
|
hexmask.word.byte 0x00 0.--7. 1. "RSTGTN,Reset gate number"
|
|
tree.end
|
|
tree.end
|
|
tree "SPDIF (Sony/Philips Digital Interface)"
|
|
base ad:0x59020000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCR,SPDIF Configuration Register"
|
|
bitfld.long 0x00 23. "RxFIFO_Ctrl,RxFIFO_Ctrl" "0: Normal operation,1: Always read zero from Rx data register"
|
|
bitfld.long 0x00 22. "RxFIFO_Off_On,RxFIFO_Off_On" "0: SPDIF Rx FIFO is on,1: SPDIF Rx FIFO is off"
|
|
newline
|
|
bitfld.long 0x00 21. "RxFIFO_Rst,RxFIFO_Rst" "0: Normal operation,1: Reset register to 1 sample remaining"
|
|
bitfld.long 0x00 19.--20. "RxFIFOFull_Sel,RxFIFOFull_Sel" "0: Full interrupt if at least 1 sample in Rx..,1: Full interrupt if at least 4 sample in Rx..,2: Full interrupt if at least 8 sample in Rx..,3: Full interrupt if at least 16 sample in Rx.."
|
|
newline
|
|
bitfld.long 0x00 18. "RxAutoSync,RxAutoSync" "0: Rx FIFO auto sync off,1: RxFIFO auto sync on"
|
|
bitfld.long 0x00 17. "TxAutoSync,TxAutoSync" "0: Tx FIFO auto sync off,1: Tx FIFO auto sync on"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "TxFIFOEmpty_Sel,TxFIFOEmpty_Sel" "0: Empty interrupt if 0 sample in Tx left and..,1: Empty interrupt if at most 4 sample in Tx..,2: Empty interrupt if at most 8 sample in Tx..,3: Empty interrupt if at most 12 sample in Tx.."
|
|
bitfld.long 0x00 13. "LOW_POWER,LOW_POWER" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "soft_reset,soft_reset" "0,1"
|
|
bitfld.long 0x00 10.--11. "TxFIFO_Ctrl,TxFIFO_Ctrl" "0: Send out digital zero on SPDIF Tx,1: Tx Normal operation,2: Reset to 1 sample remaining,?..."
|
|
newline
|
|
bitfld.long 0x00 9. "DMA_Rx_En,DMA_Rx_En" "0,1"
|
|
bitfld.long 0x00 8. "DMA_TX_En,DMA_TX_En" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "InputSrcSel,InputSrcSel" "0: spdif_in,1: none_sel,2: none_sel,3: none_sel"
|
|
bitfld.long 0x00 5. "ValCtrl,ValCtrl" "0: Outgoing Validity always set,1: Outgoing Validity always clear"
|
|
newline
|
|
bitfld.long 0x00 2.--4. "TxSel,TxSel" "0: Off and output 0,1: Feed-through SPDIFIN,?,?,?,5: Tx Normal operation,?..."
|
|
bitfld.long 0x00 0.--1. "USrc_Sel,USrc_Sel" "0: No embedded U channel,1: U channel from SPDIF receive block (CD mode),?,3: U channel from on chip transmitter"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SRCD,CDText Control Register"
|
|
bitfld.long 0x00 1. "USyncMode,USyncMode" "0: Non-CD data,1: CD user channel subcode"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SRPC,PhaseConfig Register"
|
|
bitfld.long 0x00 7.--10. "ClkSrc_Sel,ClkSrc_Sel" "0: if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K..,1: if (DPLL Locked) SPDIF_RxClk else tx_clk..,?,3: if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK,?,5: REF_CLK_32K (XTALOSC),6: tx_clk (SPDIF0_CLK_ROOT),?,8: clksrc_0b1000,?..."
|
|
rbitfld.long 0x00 6. "LOCK,LOCK" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--5. "GainSel,GainSel" "0: gainsel_0b000,1: gainsel_0b001,2: gainsel_0b010,3: gainsel_0b011,4: gainsel_0b100,5: gainsel_0b101,6: gainsel_0b110,?..."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SIE,InterruptEn Register"
|
|
bitfld.long 0x00 20. "Lock,Lock" "0,1"
|
|
bitfld.long 0x00 19. "TxUnOv,TxUnOv" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TxResyn,TxResyn" "0,1"
|
|
bitfld.long 0x00 17. "CNew,CNew" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ValNoGood,ValNoGood" "0,1"
|
|
bitfld.long 0x00 15. "SymErr,SymErr" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "BitErr,BitErr" "0,1"
|
|
bitfld.long 0x00 10. "URxFul,URxFul" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "URxOv,URxOv" "0,1"
|
|
bitfld.long 0x00 8. "QRxFul,QRxFul" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "QRxOv,QRxOv" "0,1"
|
|
bitfld.long 0x00 6. "UQSync,UQSync" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "UQErr,UQErr" "0,1"
|
|
bitfld.long 0x00 4. "RxFIFOUnOv,RxFIFOUnOv" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RxFIFOResyn,RxFIFOResyn" "0,1"
|
|
bitfld.long 0x00 2. "LockLoss,LockLoss" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TxEm,TxEm" "0,1"
|
|
bitfld.long 0x00 0. "RxFIFOFul,RxFIFOFul" "0,1"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SIC,InterruptClear Register"
|
|
bitfld.long 0x00 20. "Lock,Lock" "0,1"
|
|
bitfld.long 0x00 19. "TxUnOv,TxUnOv" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TxResyn,TxResyn" "0,1"
|
|
bitfld.long 0x00 17. "CNew,CNew" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ValNoGood,ValNoGood" "0,1"
|
|
bitfld.long 0x00 15. "SymErr,SymErr" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "BitErr,BitErr" "0,1"
|
|
bitfld.long 0x00 9. "URxOv,URxOv" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "QRxOv,QRxOv" "0,1"
|
|
bitfld.long 0x00 6. "UQSync,UQSync" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "UQErr,UQErr" "0,1"
|
|
bitfld.long 0x00 4. "RxFIFOUnOv,RxFIFOUnOv" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RxFIFOResyn,RxFIFOResyn" "0,1"
|
|
bitfld.long 0x00 2. "LockLoss,LockLoss" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SIS,InterruptStat Register"
|
|
bitfld.long 0x00 20. "Lock,Lock" "0,1"
|
|
bitfld.long 0x00 19. "TxUnOv,TxUnOv" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "TxResyn,TxResyn" "0,1"
|
|
bitfld.long 0x00 17. "CNew,CNew" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "ValNoGood,ValNoGood" "0,1"
|
|
bitfld.long 0x00 15. "SymErr,SymErr" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "BitErr,BitErr" "0,1"
|
|
bitfld.long 0x00 10. "URxFul,URxFul" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "URxOv,URxOv" "0,1"
|
|
bitfld.long 0x00 8. "QRxFul,QRxFul" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "QRxOv,QRxOv" "0,1"
|
|
bitfld.long 0x00 6. "UQSync,UQSync" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "UQErr,UQErr" "0,1"
|
|
bitfld.long 0x00 4. "RxFIFOUnOv,RxFIFOUnOv" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "RxFIFOResyn,RxFIFOResyn" "0,1"
|
|
bitfld.long 0x00 2. "LockLoss,LockLoss" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TxEm,TxEm" "0,1"
|
|
bitfld.long 0x00 0. "RxFIFOFul,RxFIFOFul" "0,1"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SRL,SPDIFRxLeft Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RxDataLeft,RxDataLeft"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SRR,SPDIFRxRight Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RxDataRight,RxDataRight"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SRCSH,SPDIFRxCChannel_h Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RxCChannel_h,RxCChannel_h"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SRCSL,SPDIFRxCChannel_l Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RxCChannel_l,RxCChannel_l"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SRU,UchannelRx Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RxUChannel,RxUChannel"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SRQ,QchannelRx Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RxQChannel,RxQChannel"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "STL,SPDIFTxLeft Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TxDataLeft,TxDataLeft"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "STR,SPDIFTxRight Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TxDataRight,TxDataRight"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "STCSCH,SPDIFTxCChannelCons_h Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TxCChannelCons_h,TxCChannelCons_h"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "STCSCL,SPDIFTxCChannelCons_l Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TxCChannelCons_l,TxCChannelCons_l"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SRFM,FreqMeas Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "FreqMeas,FreqMeas"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "STC,SPDIFTxClk Register"
|
|
hexmask.long.word 0x00 11.--19. 1. "SYSCLK_DF,SYSCLK_DF"
|
|
bitfld.long 0x00 8.--10. "TxClk_Source,TxClk_Source" "0: REF_CLK_32K input (XTALOSC 32 kHz clock),1: tx_clk input (from SPDIF0_CLK_ROOT. See clock..,?,3: SPDIF_EXT_CLK from pads,?,5: ipg_clk input (frequency divided),?..."
|
|
newline
|
|
bitfld.long 0x00 7. "tx_all_clk_en,tx_all_clk_en" "0: disable transfer clock,1: enable transfer clock"
|
|
hexmask.long.byte 0x00 0.--6. 1. "TxClk_DF,TxClk_DF"
|
|
tree.end
|
|
tree "SPP_DMA3 (DMA MP)"
|
|
repeat 2. (list 0. 2.) (list ad:0x591F0000 ad:0x5A1F0000)
|
|
tree "ADMA__EDMA$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MP_CSR,Management Page Control"
|
|
rbitfld.long 0x00 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel"
|
|
rbitfld.long 0x00 24.--28. "ACTIVE_ID,Active Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 9. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer"
|
|
bitfld.long 0x00 8. "ECX,Cancel Transfer With Error" "0: Normal operation,1: Cancel the remaining data transfer"
|
|
newline
|
|
bitfld.long 0x00 7. "GMRC,Global Master ID Replication Control" "0: Master ID replication disabled for all channels,1: Master ID replication available and.."
|
|
bitfld.long 0x00 6. "GCLC,Global Channel Linking Control" "0: Channel linking disabled for all channels,1: Channel linking available and controlled by.."
|
|
newline
|
|
bitfld.long 0x00 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels"
|
|
bitfld.long 0x00 4. "HAE,Halt After Error" "0: Normal operation,1: Any error causes the HALT field to be set to 1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Round-robin channel arbitration disabled,1: Round-robin channel arbitration enabled"
|
|
bitfld.long 0x00 1. "EDBG,Enable Debug" "0: Debug mode disabled,1: Debug mode is enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MP_ES,Management Page Error Status"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: No ERR fields are set to 1,1: At least one ERR field is set to 1 indicating.."
|
|
bitfld.long 0x00 24.--28. "ERRCHN,Error Channel Number or Canceled Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8. "ECX,Transfer Canceled" "0: No canceled transfers,1: Last recorded entry was a canceled transfer.."
|
|
bitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
bitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
bitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
bitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
bitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was NBYTES equal to.."
|
|
newline
|
|
bitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
bitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was a bus error on a source"
|
|
newline
|
|
bitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was a bus error on a.."
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "MP_INT,Management Page Interrupt Request Status"
|
|
hexmask.long 0x00 0.--31. 1. "INT,Interrupt Request Status"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "MP_HRS,Management Page Hardware Request Status"
|
|
hexmask.long 0x00 0.--31. 1. "HRS,Hardware Request Status"
|
|
repeat 32. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "CH_GRPRI[$1],Channel Arbitration Group $1"
|
|
bitfld.long 0x00 0.--4. "GRPRI,Arbitration Group For Channel n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree "ADMA__EDMA3"
|
|
base ad:0x5A9F0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MP_CSR,Management Page Control"
|
|
rbitfld.long 0x00 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel"
|
|
rbitfld.long 0x00 24.--27. "ACTIVE_ID,Active Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 9. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer"
|
|
bitfld.long 0x00 8. "ECX,Cancel Transfer With Error" "0: Normal operation,1: Cancel the remaining data transfer"
|
|
newline
|
|
bitfld.long 0x00 7. "GMRC,Global Master ID Replication Control" "0: Master ID replication disabled for all channels,1: Master ID replication available and.."
|
|
bitfld.long 0x00 6. "GCLC,Global Channel Linking Control" "0: Channel linking disabled for all channels,1: Channel linking available and controlled by.."
|
|
newline
|
|
bitfld.long 0x00 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels"
|
|
bitfld.long 0x00 4. "HAE,Halt After Error" "0: Normal operation,1: Any error causes the HALT field to be set to 1"
|
|
newline
|
|
bitfld.long 0x00 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Round-robin channel arbitration disabled,1: Round-robin channel arbitration enabled"
|
|
bitfld.long 0x00 1. "EDBG,Enable Debug" "0: Debug mode disabled,1: Debug mode is enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MP_ES,Management Page Error Status"
|
|
bitfld.long 0x00 31. "VLD,Valid" "0: No ERR fields are set to 1,1: At least one ERR field is set to 1 indicating.."
|
|
bitfld.long 0x00 24.--27. "ERRCHN,Error Channel Number or Canceled Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8. "ECX,Transfer Canceled" "0: No canceled transfers,1: Last recorded entry was a canceled transfer.."
|
|
bitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
bitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
bitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
bitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
bitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was NBYTES equal to.."
|
|
newline
|
|
bitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
bitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was a bus error on a source"
|
|
newline
|
|
bitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was a bus error on a.."
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "MP_INT,Management Page Interrupt Request Status"
|
|
hexmask.long.word 0x00 0.--15. 1. "INT,Interrupt Request Status"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "MP_HRS,Management Page Hardware Request Status"
|
|
hexmask.long 0x00 0.--31. 1. "HRS,Hardware Request Status"
|
|
repeat 16. (increment 0 1) (increment 0 0x04)
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "CH_GRPRI[$1],Channel Arbitration Group $1"
|
|
bitfld.long 0x00 0.--4. "GRPRI,Arbitration Group For Channel n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "SPP_DMA3_TCD (DMA TCD)"
|
|
tree "ADMA__EDMA0_TCD"
|
|
base ad:0x59200000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CH0_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CH0_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CH0_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CH0_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x26++0x01
|
|
line.word 0x00 "TCD0_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TCD0_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TCD0_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCD0_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x10000++0x03
|
|
line.long 0x00 "CH1_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x10004++0x03
|
|
line.long 0x00 "CH1_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x10008++0x03
|
|
line.long 0x00 "CH1_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1000C++0x03
|
|
line.long 0x00 "CH1_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10010++0x03
|
|
line.long 0x00 "CH1_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10020++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10024++0x01
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x10026++0x01
|
|
line.word 0x00 "TCD1_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x10028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1002C++0x03
|
|
line.long 0x00 "TCD1_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x10030++0x03
|
|
line.long 0x00 "TCD1_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10034++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10038++0x03
|
|
line.long 0x00 "TCD1_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1003C++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1003E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1003E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x20000++0x03
|
|
line.long 0x00 "CH2_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x20004++0x03
|
|
line.long 0x00 "CH2_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x20008++0x03
|
|
line.long 0x00 "CH2_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x2000C++0x03
|
|
line.long 0x00 "CH2_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20010++0x03
|
|
line.long 0x00 "CH2_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20020++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x20024++0x01
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x20026++0x01
|
|
line.word 0x00 "TCD2_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20028++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x20028++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x2002C++0x03
|
|
line.long 0x00 "TCD2_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x20030++0x03
|
|
line.long 0x00 "TCD2_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x20034++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x20036++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x20036++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x20038++0x03
|
|
line.long 0x00 "TCD2_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x2003C++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x2003E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x2003E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x30000++0x03
|
|
line.long 0x00 "CH3_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x30004++0x03
|
|
line.long 0x00 "CH3_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x30008++0x03
|
|
line.long 0x00 "CH3_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x3000C++0x03
|
|
line.long 0x00 "CH3_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x30010++0x03
|
|
line.long 0x00 "CH3_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x30020++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x30024++0x01
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x30026++0x01
|
|
line.word 0x00 "TCD3_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x30028++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x30028++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x3002C++0x03
|
|
line.long 0x00 "TCD3_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x30030++0x03
|
|
line.long 0x00 "TCD3_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x30034++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x30036++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x30036++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x30038++0x03
|
|
line.long 0x00 "TCD3_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x3003C++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x3003E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x3003E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x40000++0x03
|
|
line.long 0x00 "CH4_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x40004++0x03
|
|
line.long 0x00 "CH4_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x40008++0x03
|
|
line.long 0x00 "CH4_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x4000C++0x03
|
|
line.long 0x00 "CH4_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x40010++0x03
|
|
line.long 0x00 "CH4_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40020++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x40024++0x01
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x40026++0x01
|
|
line.word 0x00 "TCD4_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40028++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x40028++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x4002C++0x03
|
|
line.long 0x00 "TCD4_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x40030++0x03
|
|
line.long 0x00 "TCD4_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x40034++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x40036++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x40036++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x40038++0x03
|
|
line.long 0x00 "TCD4_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x4003C++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x4003E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x4003E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x50000++0x03
|
|
line.long 0x00 "CH5_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x50004++0x03
|
|
line.long 0x00 "CH5_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x50008++0x03
|
|
line.long 0x00 "CH5_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x5000C++0x03
|
|
line.long 0x00 "CH5_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x50010++0x03
|
|
line.long 0x00 "CH5_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50020++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x50024++0x01
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x50026++0x01
|
|
line.word 0x00 "TCD5_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50028++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x50028++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x5002C++0x03
|
|
line.long 0x00 "TCD5_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x50030++0x03
|
|
line.long 0x00 "TCD5_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x50034++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x50036++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x50036++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x50038++0x03
|
|
line.long 0x00 "TCD5_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x5003C++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x5003E++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x5003E++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x60000++0x03
|
|
line.long 0x00 "CH6_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x60004++0x03
|
|
line.long 0x00 "CH6_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x60008++0x03
|
|
line.long 0x00 "CH6_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x6000C++0x03
|
|
line.long 0x00 "CH6_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x60010++0x03
|
|
line.long 0x00 "CH6_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60020++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x60024++0x01
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x60026++0x01
|
|
line.word 0x00 "TCD6_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60028++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x60028++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x6002C++0x03
|
|
line.long 0x00 "TCD6_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x60030++0x03
|
|
line.long 0x00 "TCD6_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x60034++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x60036++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x60036++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x60038++0x03
|
|
line.long 0x00 "TCD6_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x6003C++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x6003E++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x6003E++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x70000++0x03
|
|
line.long 0x00 "CH7_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x70004++0x03
|
|
line.long 0x00 "CH7_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x70008++0x03
|
|
line.long 0x00 "CH7_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x7000C++0x03
|
|
line.long 0x00 "CH7_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x70010++0x03
|
|
line.long 0x00 "CH7_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x70020++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x70024++0x01
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x70026++0x01
|
|
line.word 0x00 "TCD7_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x70028++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x70028++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x7002C++0x03
|
|
line.long 0x00 "TCD7_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x70030++0x03
|
|
line.long 0x00 "TCD7_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x70034++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x70036++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x70036++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x70038++0x03
|
|
line.long 0x00 "TCD7_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x7003C++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x7003E++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x7003E++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x80000++0x03
|
|
line.long 0x00 "CH8_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x80004++0x03
|
|
line.long 0x00 "CH8_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x80008++0x03
|
|
line.long 0x00 "CH8_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x8000C++0x03
|
|
line.long 0x00 "CH8_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x80010++0x03
|
|
line.long 0x00 "CH8_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x80020++0x03
|
|
line.long 0x00 "TCD8_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x80024++0x01
|
|
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x80026++0x01
|
|
line.word 0x00 "TCD8_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x80028++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x80028++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x8002C++0x03
|
|
line.long 0x00 "TCD8_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x80030++0x03
|
|
line.long 0x00 "TCD8_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x80034++0x01
|
|
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x80036++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x80036++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x80038++0x03
|
|
line.long 0x00 "TCD8_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x8003C++0x01
|
|
line.word 0x00 "TCD8_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x8003E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x8003E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x90000++0x03
|
|
line.long 0x00 "CH9_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x90004++0x03
|
|
line.long 0x00 "CH9_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x90008++0x03
|
|
line.long 0x00 "CH9_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x9000C++0x03
|
|
line.long 0x00 "CH9_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x90010++0x03
|
|
line.long 0x00 "CH9_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90020++0x03
|
|
line.long 0x00 "TCD9_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x90024++0x01
|
|
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x90026++0x01
|
|
line.word 0x00 "TCD9_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90028++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x90028++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x9002C++0x03
|
|
line.long 0x00 "TCD9_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x90030++0x03
|
|
line.long 0x00 "TCD9_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x90034++0x01
|
|
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x90036++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x90036++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x90038++0x03
|
|
line.long 0x00 "TCD9_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x9003C++0x01
|
|
line.word 0x00 "TCD9_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x9003E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x9003E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xA0000++0x03
|
|
line.long 0x00 "CH10_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xA0004++0x03
|
|
line.long 0x00 "CH10_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xA0008++0x03
|
|
line.long 0x00 "CH10_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xA000C++0x03
|
|
line.long 0x00 "CH10_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA0010++0x03
|
|
line.long 0x00 "CH10_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0020++0x03
|
|
line.long 0x00 "TCD10_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xA0024++0x01
|
|
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xA0026++0x01
|
|
line.word 0x00 "TCD10_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0028++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xA0028++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xA002C++0x03
|
|
line.long 0x00 "TCD10_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xA0030++0x03
|
|
line.long 0x00 "TCD10_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xA0034++0x01
|
|
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xA0036++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xA0036++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xA0038++0x03
|
|
line.long 0x00 "TCD10_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xA003C++0x01
|
|
line.word 0x00 "TCD10_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xA003E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xA003E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xB0000++0x03
|
|
line.long 0x00 "CH11_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xB0004++0x03
|
|
line.long 0x00 "CH11_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xB0008++0x03
|
|
line.long 0x00 "CH11_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xB000C++0x03
|
|
line.long 0x00 "CH11_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB0010++0x03
|
|
line.long 0x00 "CH11_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xB0020++0x03
|
|
line.long 0x00 "TCD11_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xB0024++0x01
|
|
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xB0026++0x01
|
|
line.word 0x00 "TCD11_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xB0028++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xB0028++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xB002C++0x03
|
|
line.long 0x00 "TCD11_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xB0030++0x03
|
|
line.long 0x00 "TCD11_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xB0034++0x01
|
|
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xB0036++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xB0036++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xB0038++0x03
|
|
line.long 0x00 "TCD11_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xB003C++0x01
|
|
line.word 0x00 "TCD11_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xB003E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xB003E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xC0000++0x03
|
|
line.long 0x00 "CH12_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xC0004++0x03
|
|
line.long 0x00 "CH12_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xC0008++0x03
|
|
line.long 0x00 "CH12_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xC000C++0x03
|
|
line.long 0x00 "CH12_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC0010++0x03
|
|
line.long 0x00 "CH12_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0020++0x03
|
|
line.long 0x00 "TCD12_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xC0024++0x01
|
|
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xC0026++0x01
|
|
line.word 0x00 "TCD12_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0028++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xC0028++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xC002C++0x03
|
|
line.long 0x00 "TCD12_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xC0030++0x03
|
|
line.long 0x00 "TCD12_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xC0034++0x01
|
|
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xC0036++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xC0036++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xC0038++0x03
|
|
line.long 0x00 "TCD12_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xC003C++0x01
|
|
line.word 0x00 "TCD12_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xC003E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xC003E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xD0000++0x03
|
|
line.long 0x00 "CH13_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xD0004++0x03
|
|
line.long 0x00 "CH13_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xD0008++0x03
|
|
line.long 0x00 "CH13_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xD000C++0x03
|
|
line.long 0x00 "CH13_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xD0010++0x03
|
|
line.long 0x00 "CH13_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD0020++0x03
|
|
line.long 0x00 "TCD13_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xD0024++0x01
|
|
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xD0026++0x01
|
|
line.word 0x00 "TCD13_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD0028++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xD0028++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xD002C++0x03
|
|
line.long 0x00 "TCD13_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xD0030++0x03
|
|
line.long 0x00 "TCD13_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xD0034++0x01
|
|
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xD0036++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xD0036++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xD0038++0x03
|
|
line.long 0x00 "TCD13_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xD003C++0x01
|
|
line.word 0x00 "TCD13_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xD003E++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xD003E++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xE0000++0x03
|
|
line.long 0x00 "CH14_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xE0004++0x03
|
|
line.long 0x00 "CH14_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xE0008++0x03
|
|
line.long 0x00 "CH14_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xE000C++0x03
|
|
line.long 0x00 "CH14_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE0010++0x03
|
|
line.long 0x00 "CH14_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE0020++0x03
|
|
line.long 0x00 "TCD14_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xE0024++0x01
|
|
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xE0026++0x01
|
|
line.word 0x00 "TCD14_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE0028++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xE0028++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xE002C++0x03
|
|
line.long 0x00 "TCD14_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xE0030++0x03
|
|
line.long 0x00 "TCD14_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xE0034++0x01
|
|
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xE0036++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xE0036++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xE0038++0x03
|
|
line.long 0x00 "TCD14_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xE003C++0x01
|
|
line.word 0x00 "TCD14_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xE003E++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xE003E++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xF0000++0x03
|
|
line.long 0x00 "CH15_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xF0004++0x03
|
|
line.long 0x00 "CH15_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xF0008++0x03
|
|
line.long 0x00 "CH15_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xF000C++0x03
|
|
line.long 0x00 "CH15_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF0010++0x03
|
|
line.long 0x00 "CH15_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xF0020++0x03
|
|
line.long 0x00 "TCD15_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xF0024++0x01
|
|
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xF0026++0x01
|
|
line.word 0x00 "TCD15_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xF0028++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xF0028++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xF002C++0x03
|
|
line.long 0x00 "TCD15_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xF0030++0x03
|
|
line.long 0x00 "TCD15_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xF0034++0x01
|
|
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xF0036++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xF0036++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xF0038++0x03
|
|
line.long 0x00 "TCD15_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xF003C++0x01
|
|
line.word 0x00 "TCD15_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xF003E++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xF003E++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x100000++0x03
|
|
line.long 0x00 "CH16_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x100004++0x03
|
|
line.long 0x00 "CH16_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x100008++0x03
|
|
line.long 0x00 "CH16_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x10000C++0x03
|
|
line.long 0x00 "CH16_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x100010++0x03
|
|
line.long 0x00 "CH16_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x100020++0x03
|
|
line.long 0x00 "TCD16_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x100024++0x01
|
|
line.word 0x00 "TCD16_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x100026++0x01
|
|
line.word 0x00 "TCD16_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x100028++0x03
|
|
line.long 0x00 "TCD16_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x100028++0x03
|
|
line.long 0x00 "TCD16_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x10002C++0x03
|
|
line.long 0x00 "TCD16_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x100030++0x03
|
|
line.long 0x00 "TCD16_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x100034++0x01
|
|
line.word 0x00 "TCD16_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x100036++0x01
|
|
line.word 0x00 "TCD16_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x100036++0x01
|
|
line.word 0x00 "TCD16_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x100038++0x03
|
|
line.long 0x00 "TCD16_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x10003C++0x01
|
|
line.word 0x00 "TCD16_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x10003E++0x01
|
|
line.word 0x00 "TCD16_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10003E++0x01
|
|
line.word 0x00 "TCD16_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x110000++0x03
|
|
line.long 0x00 "CH17_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x110004++0x03
|
|
line.long 0x00 "CH17_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x110008++0x03
|
|
line.long 0x00 "CH17_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x11000C++0x03
|
|
line.long 0x00 "CH17_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x110010++0x03
|
|
line.long 0x00 "CH17_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x110020++0x03
|
|
line.long 0x00 "TCD17_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x110024++0x01
|
|
line.word 0x00 "TCD17_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x110026++0x01
|
|
line.word 0x00 "TCD17_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x110028++0x03
|
|
line.long 0x00 "TCD17_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x110028++0x03
|
|
line.long 0x00 "TCD17_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x11002C++0x03
|
|
line.long 0x00 "TCD17_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x110030++0x03
|
|
line.long 0x00 "TCD17_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x110034++0x01
|
|
line.word 0x00 "TCD17_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x110036++0x01
|
|
line.word 0x00 "TCD17_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x110036++0x01
|
|
line.word 0x00 "TCD17_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x110038++0x03
|
|
line.long 0x00 "TCD17_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x11003C++0x01
|
|
line.word 0x00 "TCD17_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x11003E++0x01
|
|
line.word 0x00 "TCD17_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x11003E++0x01
|
|
line.word 0x00 "TCD17_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x120000++0x03
|
|
line.long 0x00 "CH18_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x120004++0x03
|
|
line.long 0x00 "CH18_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x120008++0x03
|
|
line.long 0x00 "CH18_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x12000C++0x03
|
|
line.long 0x00 "CH18_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x120010++0x03
|
|
line.long 0x00 "CH18_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x120020++0x03
|
|
line.long 0x00 "TCD18_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x120024++0x01
|
|
line.word 0x00 "TCD18_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x120026++0x01
|
|
line.word 0x00 "TCD18_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x120028++0x03
|
|
line.long 0x00 "TCD18_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x120028++0x03
|
|
line.long 0x00 "TCD18_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x12002C++0x03
|
|
line.long 0x00 "TCD18_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x120030++0x03
|
|
line.long 0x00 "TCD18_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x120034++0x01
|
|
line.word 0x00 "TCD18_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x120036++0x01
|
|
line.word 0x00 "TCD18_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x120036++0x01
|
|
line.word 0x00 "TCD18_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x120038++0x03
|
|
line.long 0x00 "TCD18_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x12003C++0x01
|
|
line.word 0x00 "TCD18_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x12003E++0x01
|
|
line.word 0x00 "TCD18_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x12003E++0x01
|
|
line.word 0x00 "TCD18_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x130000++0x03
|
|
line.long 0x00 "CH19_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x130004++0x03
|
|
line.long 0x00 "CH19_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x130008++0x03
|
|
line.long 0x00 "CH19_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x13000C++0x03
|
|
line.long 0x00 "CH19_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x130010++0x03
|
|
line.long 0x00 "CH19_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x130020++0x03
|
|
line.long 0x00 "TCD19_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x130024++0x01
|
|
line.word 0x00 "TCD19_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x130026++0x01
|
|
line.word 0x00 "TCD19_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x130028++0x03
|
|
line.long 0x00 "TCD19_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x130028++0x03
|
|
line.long 0x00 "TCD19_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x13002C++0x03
|
|
line.long 0x00 "TCD19_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x130030++0x03
|
|
line.long 0x00 "TCD19_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x130034++0x01
|
|
line.word 0x00 "TCD19_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x130036++0x01
|
|
line.word 0x00 "TCD19_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x130036++0x01
|
|
line.word 0x00 "TCD19_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x130038++0x03
|
|
line.long 0x00 "TCD19_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x13003C++0x01
|
|
line.word 0x00 "TCD19_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x13003E++0x01
|
|
line.word 0x00 "TCD19_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x13003E++0x01
|
|
line.word 0x00 "TCD19_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x140000++0x03
|
|
line.long 0x00 "CH20_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x140004++0x03
|
|
line.long 0x00 "CH20_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x140008++0x03
|
|
line.long 0x00 "CH20_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x14000C++0x03
|
|
line.long 0x00 "CH20_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x140010++0x03
|
|
line.long 0x00 "CH20_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x140020++0x03
|
|
line.long 0x00 "TCD20_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x140024++0x01
|
|
line.word 0x00 "TCD20_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x140026++0x01
|
|
line.word 0x00 "TCD20_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x140028++0x03
|
|
line.long 0x00 "TCD20_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x140028++0x03
|
|
line.long 0x00 "TCD20_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x14002C++0x03
|
|
line.long 0x00 "TCD20_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x140030++0x03
|
|
line.long 0x00 "TCD20_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x140034++0x01
|
|
line.word 0x00 "TCD20_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x140036++0x01
|
|
line.word 0x00 "TCD20_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x140036++0x01
|
|
line.word 0x00 "TCD20_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x140038++0x03
|
|
line.long 0x00 "TCD20_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x14003C++0x01
|
|
line.word 0x00 "TCD20_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x14003E++0x01
|
|
line.word 0x00 "TCD20_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x14003E++0x01
|
|
line.word 0x00 "TCD20_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x150000++0x03
|
|
line.long 0x00 "CH21_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x150004++0x03
|
|
line.long 0x00 "CH21_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x150008++0x03
|
|
line.long 0x00 "CH21_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x15000C++0x03
|
|
line.long 0x00 "CH21_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x150010++0x03
|
|
line.long 0x00 "CH21_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x150020++0x03
|
|
line.long 0x00 "TCD21_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x150024++0x01
|
|
line.word 0x00 "TCD21_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x150026++0x01
|
|
line.word 0x00 "TCD21_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x150028++0x03
|
|
line.long 0x00 "TCD21_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x150028++0x03
|
|
line.long 0x00 "TCD21_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x15002C++0x03
|
|
line.long 0x00 "TCD21_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x150030++0x03
|
|
line.long 0x00 "TCD21_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x150034++0x01
|
|
line.word 0x00 "TCD21_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x150036++0x01
|
|
line.word 0x00 "TCD21_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x150036++0x01
|
|
line.word 0x00 "TCD21_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x150038++0x03
|
|
line.long 0x00 "TCD21_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x15003C++0x01
|
|
line.word 0x00 "TCD21_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x15003E++0x01
|
|
line.word 0x00 "TCD21_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x15003E++0x01
|
|
line.word 0x00 "TCD21_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x160000++0x03
|
|
line.long 0x00 "CH22_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x160004++0x03
|
|
line.long 0x00 "CH22_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x160008++0x03
|
|
line.long 0x00 "CH22_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x16000C++0x03
|
|
line.long 0x00 "CH22_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x160010++0x03
|
|
line.long 0x00 "CH22_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x160020++0x03
|
|
line.long 0x00 "TCD22_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x160024++0x01
|
|
line.word 0x00 "TCD22_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x160026++0x01
|
|
line.word 0x00 "TCD22_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x160028++0x03
|
|
line.long 0x00 "TCD22_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x160028++0x03
|
|
line.long 0x00 "TCD22_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x16002C++0x03
|
|
line.long 0x00 "TCD22_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x160030++0x03
|
|
line.long 0x00 "TCD22_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x160034++0x01
|
|
line.word 0x00 "TCD22_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x160036++0x01
|
|
line.word 0x00 "TCD22_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x160036++0x01
|
|
line.word 0x00 "TCD22_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x160038++0x03
|
|
line.long 0x00 "TCD22_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x16003C++0x01
|
|
line.word 0x00 "TCD22_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x16003E++0x01
|
|
line.word 0x00 "TCD22_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x16003E++0x01
|
|
line.word 0x00 "TCD22_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x170000++0x03
|
|
line.long 0x00 "CH23_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x170004++0x03
|
|
line.long 0x00 "CH23_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x170008++0x03
|
|
line.long 0x00 "CH23_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x17000C++0x03
|
|
line.long 0x00 "CH23_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x170010++0x03
|
|
line.long 0x00 "CH23_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x170020++0x03
|
|
line.long 0x00 "TCD23_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x170024++0x01
|
|
line.word 0x00 "TCD23_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x170026++0x01
|
|
line.word 0x00 "TCD23_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x170028++0x03
|
|
line.long 0x00 "TCD23_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x170028++0x03
|
|
line.long 0x00 "TCD23_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x17002C++0x03
|
|
line.long 0x00 "TCD23_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x170030++0x03
|
|
line.long 0x00 "TCD23_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x170034++0x01
|
|
line.word 0x00 "TCD23_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x170036++0x01
|
|
line.word 0x00 "TCD23_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x170036++0x01
|
|
line.word 0x00 "TCD23_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x170038++0x03
|
|
line.long 0x00 "TCD23_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x17003C++0x01
|
|
line.word 0x00 "TCD23_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x17003E++0x01
|
|
line.word 0x00 "TCD23_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x17003E++0x01
|
|
line.word 0x00 "TCD23_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x180000++0x03
|
|
line.long 0x00 "CH24_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x180004++0x03
|
|
line.long 0x00 "CH24_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x180008++0x03
|
|
line.long 0x00 "CH24_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x18000C++0x03
|
|
line.long 0x00 "CH24_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x180010++0x03
|
|
line.long 0x00 "CH24_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x180020++0x03
|
|
line.long 0x00 "TCD24_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x180024++0x01
|
|
line.word 0x00 "TCD24_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x180026++0x01
|
|
line.word 0x00 "TCD24_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x180028++0x03
|
|
line.long 0x00 "TCD24_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x180028++0x03
|
|
line.long 0x00 "TCD24_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x18002C++0x03
|
|
line.long 0x00 "TCD24_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x180030++0x03
|
|
line.long 0x00 "TCD24_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x180034++0x01
|
|
line.word 0x00 "TCD24_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x180036++0x01
|
|
line.word 0x00 "TCD24_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x180036++0x01
|
|
line.word 0x00 "TCD24_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x180038++0x03
|
|
line.long 0x00 "TCD24_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x18003C++0x01
|
|
line.word 0x00 "TCD24_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x18003E++0x01
|
|
line.word 0x00 "TCD24_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x18003E++0x01
|
|
line.word 0x00 "TCD24_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x190000++0x03
|
|
line.long 0x00 "CH25_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x190004++0x03
|
|
line.long 0x00 "CH25_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x190008++0x03
|
|
line.long 0x00 "CH25_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x19000C++0x03
|
|
line.long 0x00 "CH25_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x190010++0x03
|
|
line.long 0x00 "CH25_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x190020++0x03
|
|
line.long 0x00 "TCD25_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x190024++0x01
|
|
line.word 0x00 "TCD25_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x190026++0x01
|
|
line.word 0x00 "TCD25_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x190028++0x03
|
|
line.long 0x00 "TCD25_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x190028++0x03
|
|
line.long 0x00 "TCD25_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x19002C++0x03
|
|
line.long 0x00 "TCD25_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x190030++0x03
|
|
line.long 0x00 "TCD25_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x190034++0x01
|
|
line.word 0x00 "TCD25_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x190036++0x01
|
|
line.word 0x00 "TCD25_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x190036++0x01
|
|
line.word 0x00 "TCD25_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x190038++0x03
|
|
line.long 0x00 "TCD25_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x19003C++0x01
|
|
line.word 0x00 "TCD25_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x19003E++0x01
|
|
line.word 0x00 "TCD25_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x19003E++0x01
|
|
line.word 0x00 "TCD25_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1A0000++0x03
|
|
line.long 0x00 "CH26_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x1A0004++0x03
|
|
line.long 0x00 "CH26_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x1A0008++0x03
|
|
line.long 0x00 "CH26_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1A000C++0x03
|
|
line.long 0x00 "CH26_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1A0010++0x03
|
|
line.long 0x00 "CH26_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1A0020++0x03
|
|
line.long 0x00 "TCD26_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1A0024++0x01
|
|
line.word 0x00 "TCD26_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x1A0026++0x01
|
|
line.word 0x00 "TCD26_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1A0028++0x03
|
|
line.long 0x00 "TCD26_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1A0028++0x03
|
|
line.long 0x00 "TCD26_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1A002C++0x03
|
|
line.long 0x00 "TCD26_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x1A0030++0x03
|
|
line.long 0x00 "TCD26_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1A0034++0x01
|
|
line.word 0x00 "TCD26_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1A0036++0x01
|
|
line.word 0x00 "TCD26_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1A0036++0x01
|
|
line.word 0x00 "TCD26_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1A0038++0x03
|
|
line.long 0x00 "TCD26_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1A003C++0x01
|
|
line.word 0x00 "TCD26_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1A003E++0x01
|
|
line.word 0x00 "TCD26_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1A003E++0x01
|
|
line.word 0x00 "TCD26_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1B0000++0x03
|
|
line.long 0x00 "CH27_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x1B0004++0x03
|
|
line.long 0x00 "CH27_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x1B0008++0x03
|
|
line.long 0x00 "CH27_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1B000C++0x03
|
|
line.long 0x00 "CH27_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1B0010++0x03
|
|
line.long 0x00 "CH27_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1B0020++0x03
|
|
line.long 0x00 "TCD27_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1B0024++0x01
|
|
line.word 0x00 "TCD27_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x1B0026++0x01
|
|
line.word 0x00 "TCD27_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1B0028++0x03
|
|
line.long 0x00 "TCD27_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1B0028++0x03
|
|
line.long 0x00 "TCD27_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1B002C++0x03
|
|
line.long 0x00 "TCD27_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x1B0030++0x03
|
|
line.long 0x00 "TCD27_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1B0034++0x01
|
|
line.word 0x00 "TCD27_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1B0036++0x01
|
|
line.word 0x00 "TCD27_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1B0036++0x01
|
|
line.word 0x00 "TCD27_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1B0038++0x03
|
|
line.long 0x00 "TCD27_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1B003C++0x01
|
|
line.word 0x00 "TCD27_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1B003E++0x01
|
|
line.word 0x00 "TCD27_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1B003E++0x01
|
|
line.word 0x00 "TCD27_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1C0000++0x03
|
|
line.long 0x00 "CH28_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x1C0004++0x03
|
|
line.long 0x00 "CH28_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x1C0008++0x03
|
|
line.long 0x00 "CH28_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1C000C++0x03
|
|
line.long 0x00 "CH28_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1C0010++0x03
|
|
line.long 0x00 "CH28_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C0020++0x03
|
|
line.long 0x00 "TCD28_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1C0024++0x01
|
|
line.word 0x00 "TCD28_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x1C0026++0x01
|
|
line.word 0x00 "TCD28_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C0028++0x03
|
|
line.long 0x00 "TCD28_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1C0028++0x03
|
|
line.long 0x00 "TCD28_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1C002C++0x03
|
|
line.long 0x00 "TCD28_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x1C0030++0x03
|
|
line.long 0x00 "TCD28_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1C0034++0x01
|
|
line.word 0x00 "TCD28_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1C0036++0x01
|
|
line.word 0x00 "TCD28_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1C0036++0x01
|
|
line.word 0x00 "TCD28_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1C0038++0x03
|
|
line.long 0x00 "TCD28_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1C003C++0x01
|
|
line.word 0x00 "TCD28_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1C003E++0x01
|
|
line.word 0x00 "TCD28_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1C003E++0x01
|
|
line.word 0x00 "TCD28_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1D0000++0x03
|
|
line.long 0x00 "CH29_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x1D0004++0x03
|
|
line.long 0x00 "CH29_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x1D0008++0x03
|
|
line.long 0x00 "CH29_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1D000C++0x03
|
|
line.long 0x00 "CH29_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1D0010++0x03
|
|
line.long 0x00 "CH29_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1D0020++0x03
|
|
line.long 0x00 "TCD29_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1D0024++0x01
|
|
line.word 0x00 "TCD29_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x1D0026++0x01
|
|
line.word 0x00 "TCD29_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1D0028++0x03
|
|
line.long 0x00 "TCD29_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1D0028++0x03
|
|
line.long 0x00 "TCD29_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1D002C++0x03
|
|
line.long 0x00 "TCD29_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x1D0030++0x03
|
|
line.long 0x00 "TCD29_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1D0034++0x01
|
|
line.word 0x00 "TCD29_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1D0036++0x01
|
|
line.word 0x00 "TCD29_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1D0036++0x01
|
|
line.word 0x00 "TCD29_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1D0038++0x03
|
|
line.long 0x00 "TCD29_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1D003C++0x01
|
|
line.word 0x00 "TCD29_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1D003E++0x01
|
|
line.word 0x00 "TCD29_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1D003E++0x01
|
|
line.word 0x00 "TCD29_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1E0000++0x03
|
|
line.long 0x00 "CH30_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x1E0004++0x03
|
|
line.long 0x00 "CH30_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x1E0008++0x03
|
|
line.long 0x00 "CH30_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1E000C++0x03
|
|
line.long 0x00 "CH30_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1E0010++0x03
|
|
line.long 0x00 "CH30_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1E0020++0x03
|
|
line.long 0x00 "TCD30_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1E0024++0x01
|
|
line.word 0x00 "TCD30_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x1E0026++0x01
|
|
line.word 0x00 "TCD30_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1E0028++0x03
|
|
line.long 0x00 "TCD30_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1E0028++0x03
|
|
line.long 0x00 "TCD30_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1E002C++0x03
|
|
line.long 0x00 "TCD30_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x1E0030++0x03
|
|
line.long 0x00 "TCD30_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1E0034++0x01
|
|
line.word 0x00 "TCD30_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1E0036++0x01
|
|
line.word 0x00 "TCD30_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1E0036++0x01
|
|
line.word 0x00 "TCD30_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1E0038++0x03
|
|
line.long 0x00 "TCD30_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1E003C++0x01
|
|
line.word 0x00 "TCD30_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1E003E++0x01
|
|
line.word 0x00 "TCD30_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1E003E++0x01
|
|
line.word 0x00 "TCD30_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1F0000++0x03
|
|
line.long 0x00 "CH31_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x1F0004++0x03
|
|
line.long 0x00 "CH31_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x1F0008++0x03
|
|
line.long 0x00 "CH31_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1F000C++0x03
|
|
line.long 0x00 "CH31_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1F0010++0x03
|
|
line.long 0x00 "CH31_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1F0020++0x03
|
|
line.long 0x00 "TCD31_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1F0024++0x01
|
|
line.word 0x00 "TCD31_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x1F0026++0x01
|
|
line.word 0x00 "TCD31_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1F0028++0x03
|
|
line.long 0x00 "TCD31_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1F0028++0x03
|
|
line.long 0x00 "TCD31_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1F002C++0x03
|
|
line.long 0x00 "TCD31_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x1F0030++0x03
|
|
line.long 0x00 "TCD31_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1F0034++0x01
|
|
line.word 0x00 "TCD31_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1F0036++0x01
|
|
line.word 0x00 "TCD31_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1F0036++0x01
|
|
line.word 0x00 "TCD31_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1F0038++0x03
|
|
line.long 0x00 "TCD31_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1F003C++0x01
|
|
line.word 0x00 "TCD31_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1F003E++0x01
|
|
line.word 0x00 "TCD31_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1F003E++0x01
|
|
line.word 0x00 "TCD31_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
tree.end
|
|
tree "ADMA__EDMA2_TCD"
|
|
base ad:0x5A200000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CH0_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CH0_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CH0_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CH0_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x26++0x01
|
|
line.word 0x00 "TCD0_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TCD0_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TCD0_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCD0_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x10000++0x03
|
|
line.long 0x00 "CH1_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x10004++0x03
|
|
line.long 0x00 "CH1_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x10008++0x03
|
|
line.long 0x00 "CH1_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1000C++0x03
|
|
line.long 0x00 "CH1_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10010++0x03
|
|
line.long 0x00 "CH1_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10020++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10024++0x01
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x10026++0x01
|
|
line.word 0x00 "TCD1_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x10028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1002C++0x03
|
|
line.long 0x00 "TCD1_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x10030++0x03
|
|
line.long 0x00 "TCD1_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10034++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10038++0x03
|
|
line.long 0x00 "TCD1_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1003C++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1003E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1003E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x20000++0x03
|
|
line.long 0x00 "CH2_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x20004++0x03
|
|
line.long 0x00 "CH2_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x20008++0x03
|
|
line.long 0x00 "CH2_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x2000C++0x03
|
|
line.long 0x00 "CH2_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20010++0x03
|
|
line.long 0x00 "CH2_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20020++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x20024++0x01
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x20026++0x01
|
|
line.word 0x00 "TCD2_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20028++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x20028++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x2002C++0x03
|
|
line.long 0x00 "TCD2_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x20030++0x03
|
|
line.long 0x00 "TCD2_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x20034++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x20036++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x20036++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x20038++0x03
|
|
line.long 0x00 "TCD2_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x2003C++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x2003E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x2003E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x30000++0x03
|
|
line.long 0x00 "CH3_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x30004++0x03
|
|
line.long 0x00 "CH3_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x30008++0x03
|
|
line.long 0x00 "CH3_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x3000C++0x03
|
|
line.long 0x00 "CH3_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x30010++0x03
|
|
line.long 0x00 "CH3_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x30020++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x30024++0x01
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x30026++0x01
|
|
line.word 0x00 "TCD3_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x30028++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x30028++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x3002C++0x03
|
|
line.long 0x00 "TCD3_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x30030++0x03
|
|
line.long 0x00 "TCD3_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x30034++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x30036++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x30036++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x30038++0x03
|
|
line.long 0x00 "TCD3_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x3003C++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x3003E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x3003E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x40000++0x03
|
|
line.long 0x00 "CH4_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x40004++0x03
|
|
line.long 0x00 "CH4_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x40008++0x03
|
|
line.long 0x00 "CH4_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x4000C++0x03
|
|
line.long 0x00 "CH4_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x40010++0x03
|
|
line.long 0x00 "CH4_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40020++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x40024++0x01
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x40026++0x01
|
|
line.word 0x00 "TCD4_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40028++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x40028++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x4002C++0x03
|
|
line.long 0x00 "TCD4_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x40030++0x03
|
|
line.long 0x00 "TCD4_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x40034++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x40036++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x40036++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x40038++0x03
|
|
line.long 0x00 "TCD4_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x4003C++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x4003E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x4003E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x50000++0x03
|
|
line.long 0x00 "CH5_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x50004++0x03
|
|
line.long 0x00 "CH5_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x50008++0x03
|
|
line.long 0x00 "CH5_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x5000C++0x03
|
|
line.long 0x00 "CH5_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x50010++0x03
|
|
line.long 0x00 "CH5_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50020++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x50024++0x01
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x50026++0x01
|
|
line.word 0x00 "TCD5_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50028++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x50028++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x5002C++0x03
|
|
line.long 0x00 "TCD5_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x50030++0x03
|
|
line.long 0x00 "TCD5_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x50034++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x50036++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x50036++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x50038++0x03
|
|
line.long 0x00 "TCD5_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x5003C++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x5003E++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x5003E++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x60000++0x03
|
|
line.long 0x00 "CH6_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x60004++0x03
|
|
line.long 0x00 "CH6_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x60008++0x03
|
|
line.long 0x00 "CH6_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x6000C++0x03
|
|
line.long 0x00 "CH6_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x60010++0x03
|
|
line.long 0x00 "CH6_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60020++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x60024++0x01
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x60026++0x01
|
|
line.word 0x00 "TCD6_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60028++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x60028++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x6002C++0x03
|
|
line.long 0x00 "TCD6_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x60030++0x03
|
|
line.long 0x00 "TCD6_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x60034++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x60036++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x60036++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x60038++0x03
|
|
line.long 0x00 "TCD6_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x6003C++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x6003E++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x6003E++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x70000++0x03
|
|
line.long 0x00 "CH7_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x70004++0x03
|
|
line.long 0x00 "CH7_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x70008++0x03
|
|
line.long 0x00 "CH7_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x7000C++0x03
|
|
line.long 0x00 "CH7_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x70010++0x03
|
|
line.long 0x00 "CH7_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x70020++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x70024++0x01
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x70026++0x01
|
|
line.word 0x00 "TCD7_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x70028++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x70028++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x7002C++0x03
|
|
line.long 0x00 "TCD7_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x70030++0x03
|
|
line.long 0x00 "TCD7_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x70034++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x70036++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x70036++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x70038++0x03
|
|
line.long 0x00 "TCD7_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x7003C++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x7003E++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x7003E++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x80000++0x03
|
|
line.long 0x00 "CH8_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x80004++0x03
|
|
line.long 0x00 "CH8_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x80008++0x03
|
|
line.long 0x00 "CH8_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x8000C++0x03
|
|
line.long 0x00 "CH8_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x80010++0x03
|
|
line.long 0x00 "CH8_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x80020++0x03
|
|
line.long 0x00 "TCD8_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x80024++0x01
|
|
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x80026++0x01
|
|
line.word 0x00 "TCD8_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x80028++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x80028++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x8002C++0x03
|
|
line.long 0x00 "TCD8_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x80030++0x03
|
|
line.long 0x00 "TCD8_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x80034++0x01
|
|
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x80036++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x80036++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x80038++0x03
|
|
line.long 0x00 "TCD8_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x8003C++0x01
|
|
line.word 0x00 "TCD8_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x8003E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x8003E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x90000++0x03
|
|
line.long 0x00 "CH9_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x90004++0x03
|
|
line.long 0x00 "CH9_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x90008++0x03
|
|
line.long 0x00 "CH9_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x9000C++0x03
|
|
line.long 0x00 "CH9_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x90010++0x03
|
|
line.long 0x00 "CH9_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90020++0x03
|
|
line.long 0x00 "TCD9_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x90024++0x01
|
|
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x90026++0x01
|
|
line.word 0x00 "TCD9_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90028++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x90028++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x9002C++0x03
|
|
line.long 0x00 "TCD9_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x90030++0x03
|
|
line.long 0x00 "TCD9_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x90034++0x01
|
|
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x90036++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x90036++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x90038++0x03
|
|
line.long 0x00 "TCD9_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x9003C++0x01
|
|
line.word 0x00 "TCD9_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x9003E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x9003E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xA0000++0x03
|
|
line.long 0x00 "CH10_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xA0004++0x03
|
|
line.long 0x00 "CH10_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xA0008++0x03
|
|
line.long 0x00 "CH10_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xA000C++0x03
|
|
line.long 0x00 "CH10_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA0010++0x03
|
|
line.long 0x00 "CH10_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0020++0x03
|
|
line.long 0x00 "TCD10_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xA0024++0x01
|
|
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xA0026++0x01
|
|
line.word 0x00 "TCD10_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0028++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xA0028++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xA002C++0x03
|
|
line.long 0x00 "TCD10_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xA0030++0x03
|
|
line.long 0x00 "TCD10_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xA0034++0x01
|
|
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xA0036++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xA0036++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xA0038++0x03
|
|
line.long 0x00 "TCD10_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xA003C++0x01
|
|
line.word 0x00 "TCD10_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xA003E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xA003E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xB0000++0x03
|
|
line.long 0x00 "CH11_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xB0004++0x03
|
|
line.long 0x00 "CH11_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xB0008++0x03
|
|
line.long 0x00 "CH11_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xB000C++0x03
|
|
line.long 0x00 "CH11_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB0010++0x03
|
|
line.long 0x00 "CH11_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xB0020++0x03
|
|
line.long 0x00 "TCD11_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xB0024++0x01
|
|
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xB0026++0x01
|
|
line.word 0x00 "TCD11_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xB0028++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xB0028++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xB002C++0x03
|
|
line.long 0x00 "TCD11_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xB0030++0x03
|
|
line.long 0x00 "TCD11_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xB0034++0x01
|
|
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xB0036++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xB0036++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xB0038++0x03
|
|
line.long 0x00 "TCD11_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xB003C++0x01
|
|
line.word 0x00 "TCD11_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xB003E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xB003E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xC0000++0x03
|
|
line.long 0x00 "CH12_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xC0004++0x03
|
|
line.long 0x00 "CH12_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xC0008++0x03
|
|
line.long 0x00 "CH12_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xC000C++0x03
|
|
line.long 0x00 "CH12_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC0010++0x03
|
|
line.long 0x00 "CH12_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0020++0x03
|
|
line.long 0x00 "TCD12_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xC0024++0x01
|
|
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xC0026++0x01
|
|
line.word 0x00 "TCD12_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0028++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xC0028++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xC002C++0x03
|
|
line.long 0x00 "TCD12_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xC0030++0x03
|
|
line.long 0x00 "TCD12_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xC0034++0x01
|
|
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xC0036++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xC0036++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xC0038++0x03
|
|
line.long 0x00 "TCD12_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xC003C++0x01
|
|
line.word 0x00 "TCD12_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xC003E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xC003E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xD0000++0x03
|
|
line.long 0x00 "CH13_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xD0004++0x03
|
|
line.long 0x00 "CH13_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xD0008++0x03
|
|
line.long 0x00 "CH13_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xD000C++0x03
|
|
line.long 0x00 "CH13_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xD0010++0x03
|
|
line.long 0x00 "CH13_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD0020++0x03
|
|
line.long 0x00 "TCD13_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xD0024++0x01
|
|
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xD0026++0x01
|
|
line.word 0x00 "TCD13_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD0028++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xD0028++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xD002C++0x03
|
|
line.long 0x00 "TCD13_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xD0030++0x03
|
|
line.long 0x00 "TCD13_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xD0034++0x01
|
|
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xD0036++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xD0036++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xD0038++0x03
|
|
line.long 0x00 "TCD13_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xD003C++0x01
|
|
line.word 0x00 "TCD13_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xD003E++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xD003E++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xE0000++0x03
|
|
line.long 0x00 "CH14_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xE0004++0x03
|
|
line.long 0x00 "CH14_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xE0008++0x03
|
|
line.long 0x00 "CH14_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xE000C++0x03
|
|
line.long 0x00 "CH14_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE0010++0x03
|
|
line.long 0x00 "CH14_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE0020++0x03
|
|
line.long 0x00 "TCD14_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xE0024++0x01
|
|
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xE0026++0x01
|
|
line.word 0x00 "TCD14_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE0028++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xE0028++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xE002C++0x03
|
|
line.long 0x00 "TCD14_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xE0030++0x03
|
|
line.long 0x00 "TCD14_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xE0034++0x01
|
|
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xE0036++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xE0036++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xE0038++0x03
|
|
line.long 0x00 "TCD14_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xE003C++0x01
|
|
line.word 0x00 "TCD14_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xE003E++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xE003E++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xF0000++0x03
|
|
line.long 0x00 "CH15_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xF0004++0x03
|
|
line.long 0x00 "CH15_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xF0008++0x03
|
|
line.long 0x00 "CH15_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xF000C++0x03
|
|
line.long 0x00 "CH15_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF0010++0x03
|
|
line.long 0x00 "CH15_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xF0020++0x03
|
|
line.long 0x00 "TCD15_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xF0024++0x01
|
|
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xF0026++0x01
|
|
line.word 0x00 "TCD15_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xF0028++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xF0028++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xF002C++0x03
|
|
line.long 0x00 "TCD15_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xF0030++0x03
|
|
line.long 0x00 "TCD15_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xF0034++0x01
|
|
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xF0036++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xF0036++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xF0038++0x03
|
|
line.long 0x00 "TCD15_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xF003C++0x01
|
|
line.word 0x00 "TCD15_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xF003E++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xF003E++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x100000++0x03
|
|
line.long 0x00 "CH16_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x100004++0x03
|
|
line.long 0x00 "CH16_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x100008++0x03
|
|
line.long 0x00 "CH16_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x10000C++0x03
|
|
line.long 0x00 "CH16_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x100010++0x03
|
|
line.long 0x00 "CH16_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x100020++0x03
|
|
line.long 0x00 "TCD16_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x100024++0x01
|
|
line.word 0x00 "TCD16_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x100026++0x01
|
|
line.word 0x00 "TCD16_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x100028++0x03
|
|
line.long 0x00 "TCD16_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x100028++0x03
|
|
line.long 0x00 "TCD16_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x10002C++0x03
|
|
line.long 0x00 "TCD16_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x100030++0x03
|
|
line.long 0x00 "TCD16_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x100034++0x01
|
|
line.word 0x00 "TCD16_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x100036++0x01
|
|
line.word 0x00 "TCD16_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x100036++0x01
|
|
line.word 0x00 "TCD16_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x100038++0x03
|
|
line.long 0x00 "TCD16_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x10003C++0x01
|
|
line.word 0x00 "TCD16_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x10003E++0x01
|
|
line.word 0x00 "TCD16_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x10003E++0x01
|
|
line.word 0x00 "TCD16_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x110000++0x03
|
|
line.long 0x00 "CH17_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x110004++0x03
|
|
line.long 0x00 "CH17_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x110008++0x03
|
|
line.long 0x00 "CH17_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x11000C++0x03
|
|
line.long 0x00 "CH17_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x110010++0x03
|
|
line.long 0x00 "CH17_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x110020++0x03
|
|
line.long 0x00 "TCD17_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x110024++0x01
|
|
line.word 0x00 "TCD17_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x110026++0x01
|
|
line.word 0x00 "TCD17_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x110028++0x03
|
|
line.long 0x00 "TCD17_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x110028++0x03
|
|
line.long 0x00 "TCD17_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x11002C++0x03
|
|
line.long 0x00 "TCD17_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x110030++0x03
|
|
line.long 0x00 "TCD17_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x110034++0x01
|
|
line.word 0x00 "TCD17_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x110036++0x01
|
|
line.word 0x00 "TCD17_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x110036++0x01
|
|
line.word 0x00 "TCD17_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x110038++0x03
|
|
line.long 0x00 "TCD17_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x11003C++0x01
|
|
line.word 0x00 "TCD17_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x11003E++0x01
|
|
line.word 0x00 "TCD17_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x11003E++0x01
|
|
line.word 0x00 "TCD17_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x120000++0x03
|
|
line.long 0x00 "CH18_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x120004++0x03
|
|
line.long 0x00 "CH18_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x120008++0x03
|
|
line.long 0x00 "CH18_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x12000C++0x03
|
|
line.long 0x00 "CH18_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x120010++0x03
|
|
line.long 0x00 "CH18_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x120020++0x03
|
|
line.long 0x00 "TCD18_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x120024++0x01
|
|
line.word 0x00 "TCD18_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x120026++0x01
|
|
line.word 0x00 "TCD18_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x120028++0x03
|
|
line.long 0x00 "TCD18_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x120028++0x03
|
|
line.long 0x00 "TCD18_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x12002C++0x03
|
|
line.long 0x00 "TCD18_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x120030++0x03
|
|
line.long 0x00 "TCD18_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x120034++0x01
|
|
line.word 0x00 "TCD18_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x120036++0x01
|
|
line.word 0x00 "TCD18_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x120036++0x01
|
|
line.word 0x00 "TCD18_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x120038++0x03
|
|
line.long 0x00 "TCD18_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x12003C++0x01
|
|
line.word 0x00 "TCD18_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x12003E++0x01
|
|
line.word 0x00 "TCD18_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x12003E++0x01
|
|
line.word 0x00 "TCD18_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x130000++0x03
|
|
line.long 0x00 "CH19_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x130004++0x03
|
|
line.long 0x00 "CH19_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x130008++0x03
|
|
line.long 0x00 "CH19_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x13000C++0x03
|
|
line.long 0x00 "CH19_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x130010++0x03
|
|
line.long 0x00 "CH19_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x130020++0x03
|
|
line.long 0x00 "TCD19_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x130024++0x01
|
|
line.word 0x00 "TCD19_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x130026++0x01
|
|
line.word 0x00 "TCD19_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x130028++0x03
|
|
line.long 0x00 "TCD19_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x130028++0x03
|
|
line.long 0x00 "TCD19_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x13002C++0x03
|
|
line.long 0x00 "TCD19_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x130030++0x03
|
|
line.long 0x00 "TCD19_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x130034++0x01
|
|
line.word 0x00 "TCD19_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x130036++0x01
|
|
line.word 0x00 "TCD19_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x130036++0x01
|
|
line.word 0x00 "TCD19_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x130038++0x03
|
|
line.long 0x00 "TCD19_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x13003C++0x01
|
|
line.word 0x00 "TCD19_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x13003E++0x01
|
|
line.word 0x00 "TCD19_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x13003E++0x01
|
|
line.word 0x00 "TCD19_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x140000++0x03
|
|
line.long 0x00 "CH20_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x140004++0x03
|
|
line.long 0x00 "CH20_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x140008++0x03
|
|
line.long 0x00 "CH20_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x14000C++0x03
|
|
line.long 0x00 "CH20_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x140010++0x03
|
|
line.long 0x00 "CH20_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x140020++0x03
|
|
line.long 0x00 "TCD20_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x140024++0x01
|
|
line.word 0x00 "TCD20_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x140026++0x01
|
|
line.word 0x00 "TCD20_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x140028++0x03
|
|
line.long 0x00 "TCD20_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x140028++0x03
|
|
line.long 0x00 "TCD20_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x14002C++0x03
|
|
line.long 0x00 "TCD20_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x140030++0x03
|
|
line.long 0x00 "TCD20_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x140034++0x01
|
|
line.word 0x00 "TCD20_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x140036++0x01
|
|
line.word 0x00 "TCD20_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x140036++0x01
|
|
line.word 0x00 "TCD20_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x140038++0x03
|
|
line.long 0x00 "TCD20_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x14003C++0x01
|
|
line.word 0x00 "TCD20_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x14003E++0x01
|
|
line.word 0x00 "TCD20_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x14003E++0x01
|
|
line.word 0x00 "TCD20_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x150000++0x03
|
|
line.long 0x00 "CH21_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x150004++0x03
|
|
line.long 0x00 "CH21_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x150008++0x03
|
|
line.long 0x00 "CH21_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x15000C++0x03
|
|
line.long 0x00 "CH21_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x150010++0x03
|
|
line.long 0x00 "CH21_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x150020++0x03
|
|
line.long 0x00 "TCD21_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x150024++0x01
|
|
line.word 0x00 "TCD21_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x150026++0x01
|
|
line.word 0x00 "TCD21_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x150028++0x03
|
|
line.long 0x00 "TCD21_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x150028++0x03
|
|
line.long 0x00 "TCD21_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x15002C++0x03
|
|
line.long 0x00 "TCD21_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x150030++0x03
|
|
line.long 0x00 "TCD21_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x150034++0x01
|
|
line.word 0x00 "TCD21_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x150036++0x01
|
|
line.word 0x00 "TCD21_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x150036++0x01
|
|
line.word 0x00 "TCD21_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x150038++0x03
|
|
line.long 0x00 "TCD21_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x15003C++0x01
|
|
line.word 0x00 "TCD21_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x15003E++0x01
|
|
line.word 0x00 "TCD21_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x15003E++0x01
|
|
line.word 0x00 "TCD21_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x160000++0x03
|
|
line.long 0x00 "CH22_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x160004++0x03
|
|
line.long 0x00 "CH22_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x160008++0x03
|
|
line.long 0x00 "CH22_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x16000C++0x03
|
|
line.long 0x00 "CH22_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x160010++0x03
|
|
line.long 0x00 "CH22_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x160020++0x03
|
|
line.long 0x00 "TCD22_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x160024++0x01
|
|
line.word 0x00 "TCD22_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x160026++0x01
|
|
line.word 0x00 "TCD22_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x160028++0x03
|
|
line.long 0x00 "TCD22_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x160028++0x03
|
|
line.long 0x00 "TCD22_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x16002C++0x03
|
|
line.long 0x00 "TCD22_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x160030++0x03
|
|
line.long 0x00 "TCD22_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x160034++0x01
|
|
line.word 0x00 "TCD22_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x160036++0x01
|
|
line.word 0x00 "TCD22_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x160036++0x01
|
|
line.word 0x00 "TCD22_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x160038++0x03
|
|
line.long 0x00 "TCD22_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x16003C++0x01
|
|
line.word 0x00 "TCD22_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x16003E++0x01
|
|
line.word 0x00 "TCD22_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x16003E++0x01
|
|
line.word 0x00 "TCD22_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x170000++0x03
|
|
line.long 0x00 "CH23_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x170004++0x03
|
|
line.long 0x00 "CH23_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x170008++0x03
|
|
line.long 0x00 "CH23_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x17000C++0x03
|
|
line.long 0x00 "CH23_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x170010++0x03
|
|
line.long 0x00 "CH23_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x170020++0x03
|
|
line.long 0x00 "TCD23_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x170024++0x01
|
|
line.word 0x00 "TCD23_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x170026++0x01
|
|
line.word 0x00 "TCD23_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x170028++0x03
|
|
line.long 0x00 "TCD23_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x170028++0x03
|
|
line.long 0x00 "TCD23_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x17002C++0x03
|
|
line.long 0x00 "TCD23_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x170030++0x03
|
|
line.long 0x00 "TCD23_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x170034++0x01
|
|
line.word 0x00 "TCD23_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x170036++0x01
|
|
line.word 0x00 "TCD23_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x170036++0x01
|
|
line.word 0x00 "TCD23_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x170038++0x03
|
|
line.long 0x00 "TCD23_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x17003C++0x01
|
|
line.word 0x00 "TCD23_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x17003E++0x01
|
|
line.word 0x00 "TCD23_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x17003E++0x01
|
|
line.word 0x00 "TCD23_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x180000++0x03
|
|
line.long 0x00 "CH24_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x180004++0x03
|
|
line.long 0x00 "CH24_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x180008++0x03
|
|
line.long 0x00 "CH24_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x18000C++0x03
|
|
line.long 0x00 "CH24_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x180010++0x03
|
|
line.long 0x00 "CH24_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x180020++0x03
|
|
line.long 0x00 "TCD24_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x180024++0x01
|
|
line.word 0x00 "TCD24_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x180026++0x01
|
|
line.word 0x00 "TCD24_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x180028++0x03
|
|
line.long 0x00 "TCD24_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x180028++0x03
|
|
line.long 0x00 "TCD24_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x18002C++0x03
|
|
line.long 0x00 "TCD24_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x180030++0x03
|
|
line.long 0x00 "TCD24_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x180034++0x01
|
|
line.word 0x00 "TCD24_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x180036++0x01
|
|
line.word 0x00 "TCD24_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x180036++0x01
|
|
line.word 0x00 "TCD24_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x180038++0x03
|
|
line.long 0x00 "TCD24_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x18003C++0x01
|
|
line.word 0x00 "TCD24_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x18003E++0x01
|
|
line.word 0x00 "TCD24_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x18003E++0x01
|
|
line.word 0x00 "TCD24_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x190000++0x03
|
|
line.long 0x00 "CH25_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x190004++0x03
|
|
line.long 0x00 "CH25_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x190008++0x03
|
|
line.long 0x00 "CH25_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x19000C++0x03
|
|
line.long 0x00 "CH25_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x190010++0x03
|
|
line.long 0x00 "CH25_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x190020++0x03
|
|
line.long 0x00 "TCD25_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x190024++0x01
|
|
line.word 0x00 "TCD25_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x190026++0x01
|
|
line.word 0x00 "TCD25_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x190028++0x03
|
|
line.long 0x00 "TCD25_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x190028++0x03
|
|
line.long 0x00 "TCD25_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x19002C++0x03
|
|
line.long 0x00 "TCD25_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x190030++0x03
|
|
line.long 0x00 "TCD25_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x190034++0x01
|
|
line.word 0x00 "TCD25_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x190036++0x01
|
|
line.word 0x00 "TCD25_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x190036++0x01
|
|
line.word 0x00 "TCD25_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x190038++0x03
|
|
line.long 0x00 "TCD25_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x19003C++0x01
|
|
line.word 0x00 "TCD25_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x19003E++0x01
|
|
line.word 0x00 "TCD25_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x19003E++0x01
|
|
line.word 0x00 "TCD25_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1A0000++0x03
|
|
line.long 0x00 "CH26_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x1A0004++0x03
|
|
line.long 0x00 "CH26_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x1A0008++0x03
|
|
line.long 0x00 "CH26_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1A000C++0x03
|
|
line.long 0x00 "CH26_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1A0010++0x03
|
|
line.long 0x00 "CH26_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1A0020++0x03
|
|
line.long 0x00 "TCD26_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1A0024++0x01
|
|
line.word 0x00 "TCD26_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x1A0026++0x01
|
|
line.word 0x00 "TCD26_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1A0028++0x03
|
|
line.long 0x00 "TCD26_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1A0028++0x03
|
|
line.long 0x00 "TCD26_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1A002C++0x03
|
|
line.long 0x00 "TCD26_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x1A0030++0x03
|
|
line.long 0x00 "TCD26_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1A0034++0x01
|
|
line.word 0x00 "TCD26_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1A0036++0x01
|
|
line.word 0x00 "TCD26_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1A0036++0x01
|
|
line.word 0x00 "TCD26_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1A0038++0x03
|
|
line.long 0x00 "TCD26_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1A003C++0x01
|
|
line.word 0x00 "TCD26_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1A003E++0x01
|
|
line.word 0x00 "TCD26_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1A003E++0x01
|
|
line.word 0x00 "TCD26_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1B0000++0x03
|
|
line.long 0x00 "CH27_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x1B0004++0x03
|
|
line.long 0x00 "CH27_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x1B0008++0x03
|
|
line.long 0x00 "CH27_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1B000C++0x03
|
|
line.long 0x00 "CH27_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1B0010++0x03
|
|
line.long 0x00 "CH27_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1B0020++0x03
|
|
line.long 0x00 "TCD27_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1B0024++0x01
|
|
line.word 0x00 "TCD27_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x1B0026++0x01
|
|
line.word 0x00 "TCD27_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1B0028++0x03
|
|
line.long 0x00 "TCD27_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1B0028++0x03
|
|
line.long 0x00 "TCD27_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1B002C++0x03
|
|
line.long 0x00 "TCD27_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x1B0030++0x03
|
|
line.long 0x00 "TCD27_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1B0034++0x01
|
|
line.word 0x00 "TCD27_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1B0036++0x01
|
|
line.word 0x00 "TCD27_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1B0036++0x01
|
|
line.word 0x00 "TCD27_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1B0038++0x03
|
|
line.long 0x00 "TCD27_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1B003C++0x01
|
|
line.word 0x00 "TCD27_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1B003E++0x01
|
|
line.word 0x00 "TCD27_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1B003E++0x01
|
|
line.word 0x00 "TCD27_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1C0000++0x03
|
|
line.long 0x00 "CH28_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x1C0004++0x03
|
|
line.long 0x00 "CH28_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x1C0008++0x03
|
|
line.long 0x00 "CH28_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1C000C++0x03
|
|
line.long 0x00 "CH28_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1C0010++0x03
|
|
line.long 0x00 "CH28_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C0020++0x03
|
|
line.long 0x00 "TCD28_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1C0024++0x01
|
|
line.word 0x00 "TCD28_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x1C0026++0x01
|
|
line.word 0x00 "TCD28_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C0028++0x03
|
|
line.long 0x00 "TCD28_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1C0028++0x03
|
|
line.long 0x00 "TCD28_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1C002C++0x03
|
|
line.long 0x00 "TCD28_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x1C0030++0x03
|
|
line.long 0x00 "TCD28_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1C0034++0x01
|
|
line.word 0x00 "TCD28_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1C0036++0x01
|
|
line.word 0x00 "TCD28_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1C0036++0x01
|
|
line.word 0x00 "TCD28_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1C0038++0x03
|
|
line.long 0x00 "TCD28_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1C003C++0x01
|
|
line.word 0x00 "TCD28_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1C003E++0x01
|
|
line.word 0x00 "TCD28_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1C003E++0x01
|
|
line.word 0x00 "TCD28_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1D0000++0x03
|
|
line.long 0x00 "CH29_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x1D0004++0x03
|
|
line.long 0x00 "CH29_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x1D0008++0x03
|
|
line.long 0x00 "CH29_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1D000C++0x03
|
|
line.long 0x00 "CH29_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1D0010++0x03
|
|
line.long 0x00 "CH29_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1D0020++0x03
|
|
line.long 0x00 "TCD29_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1D0024++0x01
|
|
line.word 0x00 "TCD29_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x1D0026++0x01
|
|
line.word 0x00 "TCD29_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1D0028++0x03
|
|
line.long 0x00 "TCD29_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1D0028++0x03
|
|
line.long 0x00 "TCD29_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1D002C++0x03
|
|
line.long 0x00 "TCD29_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x1D0030++0x03
|
|
line.long 0x00 "TCD29_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1D0034++0x01
|
|
line.word 0x00 "TCD29_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1D0036++0x01
|
|
line.word 0x00 "TCD29_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1D0036++0x01
|
|
line.word 0x00 "TCD29_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1D0038++0x03
|
|
line.long 0x00 "TCD29_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1D003C++0x01
|
|
line.word 0x00 "TCD29_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1D003E++0x01
|
|
line.word 0x00 "TCD29_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1D003E++0x01
|
|
line.word 0x00 "TCD29_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1E0000++0x03
|
|
line.long 0x00 "CH30_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x1E0004++0x03
|
|
line.long 0x00 "CH30_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x1E0008++0x03
|
|
line.long 0x00 "CH30_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1E000C++0x03
|
|
line.long 0x00 "CH30_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1E0010++0x03
|
|
line.long 0x00 "CH30_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1E0020++0x03
|
|
line.long 0x00 "TCD30_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1E0024++0x01
|
|
line.word 0x00 "TCD30_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x1E0026++0x01
|
|
line.word 0x00 "TCD30_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1E0028++0x03
|
|
line.long 0x00 "TCD30_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1E0028++0x03
|
|
line.long 0x00 "TCD30_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1E002C++0x03
|
|
line.long 0x00 "TCD30_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x1E0030++0x03
|
|
line.long 0x00 "TCD30_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1E0034++0x01
|
|
line.word 0x00 "TCD30_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1E0036++0x01
|
|
line.word 0x00 "TCD30_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1E0036++0x01
|
|
line.word 0x00 "TCD30_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1E0038++0x03
|
|
line.long 0x00 "TCD30_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1E003C++0x01
|
|
line.word 0x00 "TCD30_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1E003E++0x01
|
|
line.word 0x00 "TCD30_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1E003E++0x01
|
|
line.word 0x00 "TCD30_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1F0000++0x03
|
|
line.long 0x00 "CH31_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x1F0004++0x03
|
|
line.long 0x00 "CH31_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x1F0008++0x03
|
|
line.long 0x00 "CH31_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1F000C++0x03
|
|
line.long 0x00 "CH31_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1F0010++0x03
|
|
line.long 0x00 "CH31_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1F0020++0x03
|
|
line.long 0x00 "TCD31_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1F0024++0x01
|
|
line.word 0x00 "TCD31_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x1F0026++0x01
|
|
line.word 0x00 "TCD31_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1F0028++0x03
|
|
line.long 0x00 "TCD31_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1F0028++0x03
|
|
line.long 0x00 "TCD31_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1F002C++0x03
|
|
line.long 0x00 "TCD31_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x1F0030++0x03
|
|
line.long 0x00 "TCD31_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1F0034++0x01
|
|
line.word 0x00 "TCD31_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1F0036++0x01
|
|
line.word 0x00 "TCD31_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x1F0036++0x01
|
|
line.word 0x00 "TCD31_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1F0038++0x03
|
|
line.long 0x00 "TCD31_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1F003C++0x01
|
|
line.word 0x00 "TCD31_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1F003E++0x01
|
|
line.word 0x00 "TCD31_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1F003E++0x01
|
|
line.word 0x00 "TCD31_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
tree.end
|
|
tree "ADMA__EDMA3_TCD"
|
|
base ad:0x5AA00000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CH0_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CH0_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CH0_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CH0_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x26++0x01
|
|
line.word 0x00 "TCD0_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TCD0_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TCD0_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCD0_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x10000++0x03
|
|
line.long 0x00 "CH1_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x10004++0x03
|
|
line.long 0x00 "CH1_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x10008++0x03
|
|
line.long 0x00 "CH1_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x1000C++0x03
|
|
line.long 0x00 "CH1_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10010++0x03
|
|
line.long 0x00 "CH1_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10020++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10024++0x01
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x10026++0x01
|
|
line.word 0x00 "TCD1_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x10028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x1002C++0x03
|
|
line.long 0x00 "TCD1_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x10030++0x03
|
|
line.long 0x00 "TCD1_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10034++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x10036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10038++0x03
|
|
line.long 0x00 "TCD1_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x1003C++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x1003E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x1003E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x20000++0x03
|
|
line.long 0x00 "CH2_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x20004++0x03
|
|
line.long 0x00 "CH2_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x20008++0x03
|
|
line.long 0x00 "CH2_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x2000C++0x03
|
|
line.long 0x00 "CH2_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20010++0x03
|
|
line.long 0x00 "CH2_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20020++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x20024++0x01
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x20026++0x01
|
|
line.word 0x00 "TCD2_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20028++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x20028++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x2002C++0x03
|
|
line.long 0x00 "TCD2_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x20030++0x03
|
|
line.long 0x00 "TCD2_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x20034++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x20036++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x20036++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x20038++0x03
|
|
line.long 0x00 "TCD2_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x2003C++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x2003E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x2003E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x30000++0x03
|
|
line.long 0x00 "CH3_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x30004++0x03
|
|
line.long 0x00 "CH3_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x30008++0x03
|
|
line.long 0x00 "CH3_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x3000C++0x03
|
|
line.long 0x00 "CH3_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x30010++0x03
|
|
line.long 0x00 "CH3_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x30020++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x30024++0x01
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x30026++0x01
|
|
line.word 0x00 "TCD3_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x30028++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x30028++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x3002C++0x03
|
|
line.long 0x00 "TCD3_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x30030++0x03
|
|
line.long 0x00 "TCD3_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x30034++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x30036++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x30036++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x30038++0x03
|
|
line.long 0x00 "TCD3_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x3003C++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x3003E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x3003E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x40000++0x03
|
|
line.long 0x00 "CH4_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x40004++0x03
|
|
line.long 0x00 "CH4_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x40008++0x03
|
|
line.long 0x00 "CH4_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x4000C++0x03
|
|
line.long 0x00 "CH4_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x40010++0x03
|
|
line.long 0x00 "CH4_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40020++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x40024++0x01
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x40026++0x01
|
|
line.word 0x00 "TCD4_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40028++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x40028++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x4002C++0x03
|
|
line.long 0x00 "TCD4_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x40030++0x03
|
|
line.long 0x00 "TCD4_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x40034++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x40036++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x40036++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x40038++0x03
|
|
line.long 0x00 "TCD4_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x4003C++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x4003E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x4003E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x50000++0x03
|
|
line.long 0x00 "CH5_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x50004++0x03
|
|
line.long 0x00 "CH5_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x50008++0x03
|
|
line.long 0x00 "CH5_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x5000C++0x03
|
|
line.long 0x00 "CH5_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x50010++0x03
|
|
line.long 0x00 "CH5_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50020++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x50024++0x01
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x50026++0x01
|
|
line.word 0x00 "TCD5_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x50028++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x50028++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x5002C++0x03
|
|
line.long 0x00 "TCD5_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x50030++0x03
|
|
line.long 0x00 "TCD5_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x50034++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x50036++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x50036++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x50038++0x03
|
|
line.long 0x00 "TCD5_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x5003C++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x5003E++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x5003E++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x60000++0x03
|
|
line.long 0x00 "CH6_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x60004++0x03
|
|
line.long 0x00 "CH6_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x60008++0x03
|
|
line.long 0x00 "CH6_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x6000C++0x03
|
|
line.long 0x00 "CH6_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x60010++0x03
|
|
line.long 0x00 "CH6_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60020++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x60024++0x01
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x60026++0x01
|
|
line.word 0x00 "TCD6_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60028++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x60028++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x6002C++0x03
|
|
line.long 0x00 "TCD6_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x60030++0x03
|
|
line.long 0x00 "TCD6_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x60034++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x60036++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x60036++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x60038++0x03
|
|
line.long 0x00 "TCD6_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x6003C++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x6003E++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x6003E++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x70000++0x03
|
|
line.long 0x00 "CH7_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x70004++0x03
|
|
line.long 0x00 "CH7_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x70008++0x03
|
|
line.long 0x00 "CH7_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x7000C++0x03
|
|
line.long 0x00 "CH7_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x70010++0x03
|
|
line.long 0x00 "CH7_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x70020++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x70024++0x01
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x70026++0x01
|
|
line.word 0x00 "TCD7_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x70028++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x70028++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x7002C++0x03
|
|
line.long 0x00 "TCD7_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x70030++0x03
|
|
line.long 0x00 "TCD7_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x70034++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x70036++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x70036++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x70038++0x03
|
|
line.long 0x00 "TCD7_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x7003C++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x7003E++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x7003E++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x80000++0x03
|
|
line.long 0x00 "CH8_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x80004++0x03
|
|
line.long 0x00 "CH8_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x80008++0x03
|
|
line.long 0x00 "CH8_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x8000C++0x03
|
|
line.long 0x00 "CH8_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x80010++0x03
|
|
line.long 0x00 "CH8_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x80020++0x03
|
|
line.long 0x00 "TCD8_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x80024++0x01
|
|
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x80026++0x01
|
|
line.word 0x00 "TCD8_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x80028++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x80028++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x8002C++0x03
|
|
line.long 0x00 "TCD8_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x80030++0x03
|
|
line.long 0x00 "TCD8_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x80034++0x01
|
|
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x80036++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x80036++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x80038++0x03
|
|
line.long 0x00 "TCD8_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x8003C++0x01
|
|
line.word 0x00 "TCD8_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x8003E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x8003E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x90000++0x03
|
|
line.long 0x00 "CH9_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0x90004++0x03
|
|
line.long 0x00 "CH9_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0x90008++0x03
|
|
line.long 0x00 "CH9_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0x9000C++0x03
|
|
line.long 0x00 "CH9_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x90010++0x03
|
|
line.long 0x00 "CH9_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90020++0x03
|
|
line.long 0x00 "TCD9_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x90024++0x01
|
|
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0x90026++0x01
|
|
line.word 0x00 "TCD9_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90028++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x90028++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0x9002C++0x03
|
|
line.long 0x00 "TCD9_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0x90030++0x03
|
|
line.long 0x00 "TCD9_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x90034++0x01
|
|
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x90036++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0x90036++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x90038++0x03
|
|
line.long 0x00 "TCD9_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0x9003C++0x01
|
|
line.word 0x00 "TCD9_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0x9003E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0x9003E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xA0000++0x03
|
|
line.long 0x00 "CH10_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xA0004++0x03
|
|
line.long 0x00 "CH10_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xA0008++0x03
|
|
line.long 0x00 "CH10_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xA000C++0x03
|
|
line.long 0x00 "CH10_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA0010++0x03
|
|
line.long 0x00 "CH10_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0020++0x03
|
|
line.long 0x00 "TCD10_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xA0024++0x01
|
|
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xA0026++0x01
|
|
line.word 0x00 "TCD10_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA0028++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xA0028++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xA002C++0x03
|
|
line.long 0x00 "TCD10_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xA0030++0x03
|
|
line.long 0x00 "TCD10_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xA0034++0x01
|
|
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xA0036++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xA0036++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xA0038++0x03
|
|
line.long 0x00 "TCD10_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xA003C++0x01
|
|
line.word 0x00 "TCD10_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xA003E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xA003E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xB0000++0x03
|
|
line.long 0x00 "CH11_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xB0004++0x03
|
|
line.long 0x00 "CH11_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xB0008++0x03
|
|
line.long 0x00 "CH11_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xB000C++0x03
|
|
line.long 0x00 "CH11_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xB0010++0x03
|
|
line.long 0x00 "CH11_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xB0020++0x03
|
|
line.long 0x00 "TCD11_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xB0024++0x01
|
|
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xB0026++0x01
|
|
line.word 0x00 "TCD11_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xB0028++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xB0028++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xB002C++0x03
|
|
line.long 0x00 "TCD11_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xB0030++0x03
|
|
line.long 0x00 "TCD11_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xB0034++0x01
|
|
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xB0036++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xB0036++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xB0038++0x03
|
|
line.long 0x00 "TCD11_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xB003C++0x01
|
|
line.word 0x00 "TCD11_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xB003E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xB003E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xC0000++0x03
|
|
line.long 0x00 "CH12_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xC0004++0x03
|
|
line.long 0x00 "CH12_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xC0008++0x03
|
|
line.long 0x00 "CH12_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xC000C++0x03
|
|
line.long 0x00 "CH12_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xC0010++0x03
|
|
line.long 0x00 "CH12_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0020++0x03
|
|
line.long 0x00 "TCD12_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xC0024++0x01
|
|
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xC0026++0x01
|
|
line.word 0x00 "TCD12_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0028++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xC0028++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xC002C++0x03
|
|
line.long 0x00 "TCD12_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xC0030++0x03
|
|
line.long 0x00 "TCD12_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xC0034++0x01
|
|
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xC0036++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xC0036++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xC0038++0x03
|
|
line.long 0x00 "TCD12_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xC003C++0x01
|
|
line.word 0x00 "TCD12_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xC003E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xC003E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xD0000++0x03
|
|
line.long 0x00 "CH13_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xD0004++0x03
|
|
line.long 0x00 "CH13_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xD0008++0x03
|
|
line.long 0x00 "CH13_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xD000C++0x03
|
|
line.long 0x00 "CH13_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xD0010++0x03
|
|
line.long 0x00 "CH13_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD0020++0x03
|
|
line.long 0x00 "TCD13_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xD0024++0x01
|
|
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xD0026++0x01
|
|
line.word 0x00 "TCD13_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD0028++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xD0028++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xD002C++0x03
|
|
line.long 0x00 "TCD13_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xD0030++0x03
|
|
line.long 0x00 "TCD13_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xD0034++0x01
|
|
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xD0036++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xD0036++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xD0038++0x03
|
|
line.long 0x00 "TCD13_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xD003C++0x01
|
|
line.word 0x00 "TCD13_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xD003E++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xD003E++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xE0000++0x03
|
|
line.long 0x00 "CH14_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xE0004++0x03
|
|
line.long 0x00 "CH14_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xE0008++0x03
|
|
line.long 0x00 "CH14_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xE000C++0x03
|
|
line.long 0x00 "CH14_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xE0010++0x03
|
|
line.long 0x00 "CH14_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE0020++0x03
|
|
line.long 0x00 "TCD14_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xE0024++0x01
|
|
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xE0026++0x01
|
|
line.word 0x00 "TCD14_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE0028++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xE0028++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xE002C++0x03
|
|
line.long 0x00 "TCD14_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xE0030++0x03
|
|
line.long 0x00 "TCD14_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xE0034++0x01
|
|
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xE0036++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xE0036++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xE0038++0x03
|
|
line.long 0x00 "TCD14_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xE003C++0x01
|
|
line.word 0x00 "TCD14_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xE003E++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xE003E++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0xF0000++0x03
|
|
line.long 0x00 "CH15_CSR,Channel Control and Status"
|
|
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
|
|
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
|
|
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
|
|
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
|
|
group.long 0xF0004++0x03
|
|
line.long 0x00 "CH15_ES,Channel Error Status"
|
|
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
|
|
newline
|
|
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
|
|
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
|
|
newline
|
|
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
|
|
group.long 0xF0008++0x03
|
|
line.long 0x00 "CH15_INT,Channel Interrupt Status"
|
|
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
|
|
group.long 0xF000C++0x03
|
|
line.long 0x00 "CH15_SBR,Channel System Bus"
|
|
bitfld.long 0x00 17.--22. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
|
|
newline
|
|
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xF0010++0x03
|
|
line.long 0x00 "CH15_PRI,Channel Priority"
|
|
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
|
|
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xF0020++0x03
|
|
line.long 0x00 "TCD15_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0xF0024++0x01
|
|
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
|
|
group.word 0xF0026++0x01
|
|
line.word 0x00 "TCD15_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: SSIZE_0,1: SSIZE_1,2: SSIZE_2,3: SSIZE_3,4: SSIZE_4,5: SSIZE_5,6: SSIZE_6,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
|
|
group.long 0xF0028++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xF0028++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
|
|
group.long 0xF002C++0x03
|
|
line.long 0x00 "TCD15_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
|
|
group.long 0xF0030++0x03
|
|
line.long 0x00 "TCD15_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0xF0034++0x01
|
|
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0xF0036++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.word 0xF0036++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0xF0038++0x03
|
|
line.long 0x00 "TCD15_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
|
|
group.word 0xF003C++0x01
|
|
line.word 0x00 "TCD15_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
|
|
bitfld.word 0x00 6. "EEOP,Enable End-Of-Packet Processing" "0: End-of-packet operation disabled,1: End-of-packet hardware input signal enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.."
|
|
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
|
|
group.word 0xF003E++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.word 0xF003E++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
|
|
tree.end
|
|
tree.end
|
|
tree "SS_ADMA__ACM (ACM control IPS slave)"
|
|
base ad:0x59E00000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "AUD_CLK0,Audio Clock Multiplexer #0 selector"
|
|
bitfld.long 0x00 0.--4. "SEL,Clock multiplexer selection control" "0: ADMA_SLSLICE2 Internal recovery clock #0..,1: ADMA_SLSLICE3 Internal recovery clock #1..,2: EXT_AUD_MCLK0 External (input pin),3: EXT_AUD_MCLK1 External (input pin),?,?,?,?,8: SPDIF0_RX Internal,9: SAI0_RX_BCLK External (input pin),10: SAI0_TX_BCLK External (input pin),11: SAI1_RX_BCLK External (input pin),12: SAI1_TX_BCLK External (input pin),13: SAI2_RX_BCLK External (input pin),14: SAI3_RX_BCLK External (input pin),?..."
|
|
group.long 0x10000++0x03
|
|
line.long 0x00 "AUD_CLK1,Audio Clock Multiplexer #1 selector"
|
|
bitfld.long 0x00 0.--4. "SEL,Clock multiplexer selection control" "0: ADMA_SLSLICE2 Internal recovery clock #0..,1: ADMA_SLSLICE3 Internal recovery clock #1..,2: EXT_AUD_MCLK0 External (input pin),3: EXT_AUD_MCLK1 External (input pin),?,?,?,?,8: SPDIF0_RX Internal,9: SAI0_RX_BCLK External (input pin),10: SAI0_TX_BCLK External (input pin),11: SAI1_RX_BCLK External (input pin),12: SAI1_TX_BCLK External (input pin),13: SAI2_RX_BCLK External (input pin),14: SAI3_RX_BCLK External (input pin),?..."
|
|
group.long 0x20000++0x03
|
|
line.long 0x00 "MCLKOUT0,Master Clock Output #0 selector"
|
|
bitfld.long 0x00 0.--2. "SEL,Clock multiplexer selection control" "0: ADMA_SLSLICE2 Internal (from DSC clock slice),1: ADMA_SLSLICE3 Internal (from DSC clock slice),?,?,4: SPDIF0_RX Internal,?..."
|
|
group.long 0x30000++0x03
|
|
line.long 0x00 "MCLKOUT1,Master Clock Output #1 selector"
|
|
bitfld.long 0x00 0.--2. "SEL,Clock multiplexer selection control" "0: ADMA_SLSLICE2 Internal (from DSC clock slice),1: ADMA_SLSLICE3 Internal (from DSC clock slice),?,?,4: SPDIF0_RX Internal,?..."
|
|
group.long 0x80000++0x03
|
|
line.long 0x00 "GPT0_CLK,GP Timer #0 clock selector"
|
|
bitfld.long 0x00 0.--2. "SEL,Clock multiplexer selection control" "0: AUD_PLL_DIV_CLK0 Internal free running clock..,1: AUD_PLL_DIV_CLK1 Internal free running clock..,2: AUD_CLK0 ACM pre-muxed clock #0,3: AUD_CLK1 ACM pre-muxed clock #1,4: 24 MHz system reference clock,?..."
|
|
group.long 0x90000++0x03
|
|
line.long 0x00 "GPT1_CLK,GP Timer #1 clock selector"
|
|
bitfld.long 0x00 0.--2. "SEL,Clock multiplexer selection control" "0: AUD_PLL_DIV_CLK0 Internal free running clock..,1: AUD_PLL_DIV_CLK1 Internal free running clock..,2: AUD_CLK0 ACM pre-muxed clock #0,3: AUD_CLK1 ACM pre-muxed clock #1,4: 24 MHz system reference clock,?..."
|
|
group.long 0xA0000++0x03
|
|
line.long 0x00 "GPT2_CLK,GP Timer #2 clock selector"
|
|
bitfld.long 0x00 0.--2. "SEL,Clock multiplexer selection control" "0: AUD_PLL_DIV_CLK0 Internal free running clock..,1: AUD_PLL_DIV_CLK1 Internal free running clock..,2: AUD_CLK0 ACM pre-muxed clock #0,3: AUD_CLK1 ACM pre-muxed clock #1,4: 24 MHz system reference clock,?..."
|
|
group.long 0xB0000++0x03
|
|
line.long 0x00 "GPT3_CLK,GP Timer #3 clock selector"
|
|
bitfld.long 0x00 0.--2. "SEL,Clock multiplexer selection control" "0: AUD_PLL_DIV_CLK0 Internal free running clock..,1: AUD_PLL_DIV_CLK1 Internal free running clock..,2: AUD_CLK0 ACM pre-muxed clock #0,3: AUD_CLK1 ACM pre-muxed clock #1,4: 24 MHz system reference clock,?..."
|
|
group.long 0xE0000++0x03
|
|
line.long 0x00 "SAI0_MCLK,SAI #0 clock selector"
|
|
bitfld.long 0x00 0.--1. "SEL,Clock multiplexer selection control" "0: AUD_PLL_DIV_CLK0 Internal free running clock..,1: AUD_PLL_DIV_CLK1 Internal free running clock..,2: AUD_CLK0 ACM pre-muxed clock #0,3: AUD_CLK1 ACM pre-muxed clock #1"
|
|
group.long 0xF0000++0x03
|
|
line.long 0x00 "SAI1_MCLK,SAI #1 clock selector"
|
|
bitfld.long 0x00 0.--1. "SEL,Clock multiplexer selection control" "0: AUD_PLL_DIV_CLK0 Internal free running clock..,1: AUD_PLL_DIV_CLK1 Internal free running clock..,2: AUD_CLK0 ACM pre-muxed clock #0,3: AUD_CLK1 ACM pre-muxed clock #1"
|
|
group.long 0x100000++0x03
|
|
line.long 0x00 "SAI2_MCLK,SAI #2 clock selector"
|
|
bitfld.long 0x00 0.--1. "SEL,Clock multiplexer selection control" "0: AUD_PLL_DIV_CLK0 Internal free running clock..,1: AUD_PLL_DIV_CLK1 Internal free running clock..,2: AUD_CLK0 ACM pre-muxed clock #0,3: AUD_CLK1 ACM pre-muxed clock #1"
|
|
group.long 0x110000++0x03
|
|
line.long 0x00 "SAI3_MCLK,SAI #3 clock selector"
|
|
bitfld.long 0x00 0.--1. "SEL,Clock multiplexer selection control" "0: AUD_PLL_DIV_CLK0 Internal free running clock..,1: AUD_PLL_DIV_CLK1 Internal free running clock..,2: AUD_CLK0 ACM pre-muxed clock #0,3: AUD_CLK1 ACM pre-muxed clock #1"
|
|
group.long 0x1A0000++0x03
|
|
line.long 0x00 "SPDIF0_TX_CLK,SPDI/F #0 clock selector"
|
|
bitfld.long 0x00 0.--1. "SEL,Clock multiplexer selection control" "0: AUD_PLL_DIV_CLK0 Internal free running clock..,1: AUD_PLL_DIV_CLK1 Internal free running clock..,2: AUD_CLK0 ACM pre-muxed clock #0,3: AUD_CLK1 ACM pre-muxed clock #1"
|
|
group.long 0x1C0000++0x03
|
|
line.long 0x00 "MQS_HMCLK,MQS HM clock selector"
|
|
bitfld.long 0x00 0.--1. "SEL,Clock multiplexer selection control" "0: AUD_PLL_DIV_CLK0 Internal free running clock..,1: AUD_PLL_DIV_CLK1 Internal free running clock..,2: AUD_CLK0 ACM pre-muxed clock #0,3: AUD_CLK1 ACM pre-muxed clock #1"
|
|
tree.end
|
|
tree "TSTMR (Timestamp Timer)"
|
|
tree "CM4__TSTMR"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x414100F0
|
|
else
|
|
base ad:0x374100F0
|
|
endif
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "L,Time Stamp Timer Register Low"
|
|
hexmask.long 0x00 0.--31. 1. "VALUE,Time Stamp Timer Low"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "H,Time Stamp Timer Register High"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VALUE,Time Stamp Timer High"
|
|
tree.end
|
|
tree "SCU__TSTMR"
|
|
base ad:0x334100F0
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "L,Time Stamp Timer Register Low"
|
|
hexmask.long 0x00 0.--31. 1. "VALUE,Time Stamp Timer Low"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "H,Time Stamp Timer Register High"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VALUE,Time Stamp Timer High"
|
|
tree.end
|
|
tree.end
|
|
tree "USB (Universal Serial Bus)"
|
|
base ad:0x5B0D0000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "UOG1_ID,Identification register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "REVISION,REVISION"
|
|
bitfld.long 0x00 8.--13. "NID,NID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ID,ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "UOG1_HWGENERAL,Hardware General"
|
|
bitfld.long 0x00 9.--10. "SM,SM" "0: No Serial Engine always use parallel signalling,1: Serial Engine present always use serial..,2: Software programmable - Reset to use parallel..,3: Software programmable - Reset to use serial.."
|
|
bitfld.long 0x00 6.--8. "PHYM,PHYM" "0: UTMI/UMTI+,1: ULPI_DDR,2: ULPI,3: Serial Only,4: Software programmable - reset to UTMI/UTMI+,5: Software programmable - reset to ULPI DDR,6: Software programmable - reset to ULPI,7: Software programmable - reset to Serial"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "PHYW,PHYW" "0: 8 bit wide data bus (Software non-programmable),1: 16 bit wide data bus (Software..,2: Reset to 8 bit wide data bus (Software..,3: Reset to 16 bit wide data bus (Software.."
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "UOG1_HWHOST,Host Hardware Parameters"
|
|
bitfld.long 0x00 1.--3. "NPORT,NPORT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "HC,HC" "0: Not supported,1: HOST_OP_EN"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "UOG1_HWDEVICE,Device Hardware Parameters"
|
|
bitfld.long 0x00 1.--5. "DEVEP,DEVEP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. "DC,DC" "0: DEVICE_OP_DIS,1: DEVICE_OP_EN"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "UOG1_HWTXBUF,TX Buffer Hardware Parameters"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TXCHANADD,TXCHANADD"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXBURST,TXBURST"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "UOG1_HWRXBUF,RX Buffer Hardware Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXADD,RXADD"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RXBURST,RXBURST"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "UOG1_GPTIMER0LD,General Purpose Timer #0 Load"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTLD,GPTLD"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "UOG1_GPTIMER0CTRL,General Purpose Timer #0 Controller"
|
|
bitfld.long 0x00 31. "GPTRUN,GPTRUN" "0: Stop counting,1: RUN"
|
|
bitfld.long 0x00 30. "GPTRST,GPTRST" "0: NO_ACTION,1: Load counter value from GPTLD bits in.."
|
|
newline
|
|
bitfld.long 0x00 24. "GPTMODE,GPTMODE" "0: One Shot Mode,1: Repeat Mode"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTCNT,GPTCNT"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "UOG1_GPTIMER1LD,General Purpose Timer #1 Load"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTLD,GPTLD"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "UOG1_GPTIMER1CTRL,General Purpose Timer #1 Controller"
|
|
bitfld.long 0x00 31. "GPTRUN,GPTRUN" "0: Stop counting,1: RUN"
|
|
bitfld.long 0x00 30. "GPTRST,GPTRST" "0: NO_ACTION,1: Load counter value from GPTLD bits in.."
|
|
newline
|
|
bitfld.long 0x00 24. "GPTMODE,GPTMODE" "0: One Shot Mode,1: Repeat Mode"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTCNT,GPTCNT"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "UOG1_SBUSCFG,System Bus Config"
|
|
bitfld.long 0x00 0.--2. "AHBBRST,AHBBRST" "0: Incremental burst of unspecified length only,1: INCR4 burst then single transfer,2: INCR8 burst INCR4 burst then single transfer,3: INCR16 burst INCR8 burst INCR4 burst then..,?,5: INCR4 burst then incremental burst of..,6: INCR8 burst INCR4 burst then incremental..,7: INCR16 burst INCR8 burst INCR4 burst then.."
|
|
rgroup.byte 0x100++0x00
|
|
line.byte 0x00 "UOG1_CAPLENGTH,Capability Registers Length"
|
|
hexmask.byte 0x00 0.--7. 1. "CAPLENGTH,CAPLENGTH"
|
|
rgroup.word 0x102++0x01
|
|
line.word 0x00 "UOG1_HCIVERSION,Host Controller Interface Version"
|
|
hexmask.word 0x00 0.--15. 1. "HCIVERSION,HCIVERSION"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "UOG1_HCSPARAMS,Host Controller Structural Parameters"
|
|
bitfld.long 0x00 24.--27. "N_TT,N_TT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "N_PTT,N_PTT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16. "PI,PI" "0,1"
|
|
bitfld.long 0x00 12.--15. "N_CC,N_CC" "0: There is no internal Companion Controller and..,1: There are internal companion controller(s)..,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "N_PCC,N_PCC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. "PPC,PPC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "N_PORTS,N_PORTS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "UOG1_HCCPARAMS,Host Controller Capability Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EECP,EECP"
|
|
bitfld.long 0x00 4.--7. "IST,IST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2. "ASP,ASP" "0,1"
|
|
bitfld.long 0x00 1. "PFL,PFL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ADC,ADC" "0,1"
|
|
rgroup.word 0x120++0x01
|
|
line.word 0x00 "UOG1_DCIVERSION,Device Controller Interface Version"
|
|
hexmask.word 0x00 0.--15. 1. "DCIVERSION,DCIVERSION"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "UOG1_DCCPARAMS,Device Controller Capability Parameters"
|
|
bitfld.long 0x00 8. "HC,HC" "0,1"
|
|
bitfld.long 0x00 7. "DC,DC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "DEN,DEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UOG1_USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ITC,ITC"
|
|
bitfld.long 0x00 15. "FS_2,FS_2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "ATDTW,ATDTW" "0,1"
|
|
bitfld.long 0x00 13. "SUTW,SUTW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "ASPE,ASPE" "0,1"
|
|
bitfld.long 0x00 8.--9. "ASP,ASP" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6. "IAA,IAA" "0,1"
|
|
bitfld.long 0x00 5. "ASE,ASE" "0: Do not process the Asynchronous Schedule,1: Use the ASYNCLISTADDR register to access the.."
|
|
newline
|
|
bitfld.long 0x00 4. "PSE,PSE" "0: Do not process the Periodic Schedule,1: Use the PERIODICLISTBASE register to access.."
|
|
bitfld.long 0x00 2.--3. "FS_1,FS_1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,RST" "0,1"
|
|
bitfld.long 0x00 0. "RS,RS" "0,1"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "UOG1_USBSTS,USB Status Register"
|
|
bitfld.long 0x00 25. "TI1,TI1" "0,1"
|
|
bitfld.long 0x00 24. "TI0,TI0" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "NAKI,NAKI" "0,1"
|
|
bitfld.long 0x00 15. "AS,AS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "PS,PS" "0,1"
|
|
bitfld.long 0x00 13. "RCL,RCL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "HCH,HCH" "0,1"
|
|
bitfld.long 0x00 10. "ULPII,ULPII" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "SLI,SLI" "0,1"
|
|
bitfld.long 0x00 7. "SRI,SRI" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "URI,URI" "0,1"
|
|
bitfld.long 0x00 5. "AAI,AAI" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SEI,SEI" "0,1"
|
|
bitfld.long 0x00 3. "FRI,FRI" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PCI,PCI" "0,1"
|
|
bitfld.long 0x00 1. "UEI,UEI" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UI,UI" "0,1"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "UOG1_USBINTR,Interrupt Enable Register"
|
|
bitfld.long 0x00 25. "TIE1,TIE1" "0,1"
|
|
bitfld.long 0x00 24. "TIE0,TIE0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "UPIE,UPIE" "0,1"
|
|
bitfld.long 0x00 18. "UAIE,UAIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "NAKE,NAKE" "0,1"
|
|
bitfld.long 0x00 10. "ULPIE,ULPIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "SLE,SLE" "0,1"
|
|
bitfld.long 0x00 7. "SRE,SRE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "URE,URE" "0,1"
|
|
bitfld.long 0x00 5. "AAE,AAE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SEE,SEE" "0,1"
|
|
bitfld.long 0x00 3. "FRE,FRE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PCE,PCE" "0,1"
|
|
bitfld.long 0x00 1. "UEE,UEE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UE,UE" "0,1"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "UOG1_FRINDEX,USB Frame Index"
|
|
hexmask.long.word 0x00 0.--13. 1. "FRINDEX,FRINDEX"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "UOG1_PERIODICLISTBASE,Frame List Base Address"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "BASEADR,BASEADR"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "UOG1_DEVICEADDR,Device Address"
|
|
hexmask.long.byte 0x00 25.--31. 1. "USBADR,USBADR"
|
|
bitfld.long 0x00 24. "USBADRA,USBADRA" "0,1"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "UOG1_ASYNCLISTADDR,Next Asynch"
|
|
hexmask.long 0x00 5.--31. 1. "ASYBASE,ASYBASE"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "UOG1_ENDPTLISTADDR,Endpoint List Address"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "EPBASE,EPBASE"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "UOG1_BURSTSIZE,Programmable Burst Size"
|
|
hexmask.long.word 0x00 8.--16. 1. "TXPBURST,TXPBURST"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RXPBURST,RXPBURST"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "UOG1_TXFILLTUNING,TX FIFO Fill Tuning"
|
|
bitfld.long 0x00 16.--21. "TXFIFOTHRES,TXFIFOTHRES" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--12. "TXSCHHEALTH,TXSCHHEALTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXSCHOH,TXSCHOH"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "UOG1_ENDPTNAK,Endpoint NAK"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EPTN,EPTN"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EPRN,EPRN"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "UOG1_ENDPTNAKEN,Endpoint NAK Enable"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EPTNE,EPTNE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EPRNE,EPRNE"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "UOG1_CONFIGFLAG,Configure Flag Register"
|
|
bitfld.long 0x00 0. "CF,CF" "0: Port routing control logic default-routes..,1: Port routing control logic default-routes all.."
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "UOG1_PORTSC1,Port Status & Control"
|
|
bitfld.long 0x00 30.--31. "PTS_1,PTS_1" "0,1,2,3"
|
|
bitfld.long 0x00 29. "STS,STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "PTW,PTW" "0: Select the 8-bit UTMI interface [60MHz],1: Select the 16-bit UTMI interface [30MHz]"
|
|
bitfld.long 0x00 26.--27. "PSPD,PSPD" "0: Full Speed,1: Low Speed,2: High Speed,3: UNDEFINED"
|
|
newline
|
|
bitfld.long 0x00 25. "PTS_2,PTS_2" "0,1"
|
|
bitfld.long 0x00 24. "PFSC,PFSC" "0: Normal operation,1: Forced to full speed"
|
|
newline
|
|
bitfld.long 0x00 23. "PHCD,PHCD" "0: Enable PHY clock,1: Disable PHY clock"
|
|
bitfld.long 0x00 22. "WKOC,WKOC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WKDC,WKDC" "0,1"
|
|
bitfld.long 0x00 20. "WKCN,WKCN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "PTC,PTC" "0: TEST_MODE_DISABLE,1: J_STATE,2: K_STATE,3: SE0 (host) / NAK (device),4: Packet,5: FORCE_ENABLE_HS,6: FORCE_ENABLE_FS,7: FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x00 14.--15. "PIC,PIC" "0: Port indicators are off,1: PORT_IND_AMBER,2: PORT_IND_GREEN,3: UNDEFINED"
|
|
newline
|
|
bitfld.long 0x00 13. "PO,PO" "0,1"
|
|
bitfld.long 0x00 12. "PP,PP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "LS,LS" "0: SE0,1: K_STATE,2: J_STATE,3: UNDEFINED"
|
|
rbitfld.long 0x00 9. "HSP,HSP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PR,PR" "0,1"
|
|
bitfld.long 0x00 7. "SUSP,SUSP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "FPR,FPR" "0,1"
|
|
bitfld.long 0x00 5. "OCC,OCC" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4. "OCA,OCA" "0: This port does not have an over-current..,1: This port currently has an over-current.."
|
|
bitfld.long 0x00 3. "PEC,PEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 1. "CSC,CSC" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "CCS,CCS" "0,1"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "UOG1_OTGSC,On-The-Go Status & control"
|
|
bitfld.long 0x00 30. "DPIE,DPIE" "0,1"
|
|
bitfld.long 0x00 29. "EN_1MS,EN_1MS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "BSEIE,BSEIE" "0,1"
|
|
bitfld.long 0x00 27. "BSVIE,BSVIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "ASVIE,ASVIE" "0,1"
|
|
bitfld.long 0x00 25. "AVVIE,AVVIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "IDIE,IDIE" "0,1"
|
|
bitfld.long 0x00 22. "DPIS,DPIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "STATUS_1MS,STATUS_1MS" "0,1"
|
|
bitfld.long 0x00 20. "BSEIS,BSEIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "BSVIS,BSVIS" "0,1"
|
|
bitfld.long 0x00 18. "ASVIS,ASVIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "AVVIS,AVVIS" "0,1"
|
|
bitfld.long 0x00 16. "IDIS,IDIS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 14. "DPS,DPS" "0,1"
|
|
rbitfld.long 0x00 13. "TOG_1MS,TOG_1MS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 12. "BSE,BSE" "0,1"
|
|
rbitfld.long 0x00 11. "BSV,BSV" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. "ASV,ASV" "0,1"
|
|
rbitfld.long 0x00 9. "AVV,AVV" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8. "ID,ID" "0,1"
|
|
bitfld.long 0x00 5. "IDPU,IDPU" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DP,DP" "0,1"
|
|
bitfld.long 0x00 3. "OT,OT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "VC,VC" "0,1"
|
|
bitfld.long 0x00 0. "VD,VD" "0,1"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "UOG1_USBMODE,USB Device Mode"
|
|
bitfld.long 0x00 4. "SDIS,SDIS" "0,1"
|
|
bitfld.long 0x00 3. "SLOM,SLOM" "0: Setup Lockouts On (default),1: Setup Lockouts Off"
|
|
newline
|
|
bitfld.long 0x00 2. "ES,ES" "0: Little Endian [Default],1: BIG_ENDIAN"
|
|
bitfld.long 0x00 0.--1. "CM,CM" "0: Idle [Default for combination host/device],?,2: Device Controller [Default for device only..,3: Host Controller [Default for host only.."
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "UOG1_ENDPTSETUPSTAT,Endpoint Setup Status"
|
|
hexmask.long.word 0x00 0.--15. 1. "ENDPTSETUPSTAT,ENDPTSETUPSTAT"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "UOG1_ENDPTPRIME,Endpoint Prime"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PETB,PETB"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PERB,PERB"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "UOG1_ENDPTFLUSH,Endpoint Flush"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FETB,FETB"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FERB,FERB"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "UOG1_ENDPTSTAT,Endpoint Status"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ETBR,ETBR"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERBR,ERBR"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "UOG1_ENDPTCOMPLETE,Endpoint Complete"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ETCE,ETCE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERCE,ERCE"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UOG1_ENDPTCTRL0,Endpoint Control0"
|
|
bitfld.long 0x00 23. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 18.--19. "TXT,TXT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16. "TXS,TXS" "0,1"
|
|
bitfld.long 0x00 7. "RXE,RXE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RXT,RXT" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RXS,RXS" "0,1"
|
|
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x1C4)++0x03
|
|
line.long 0x00 "UOG1_ENDPTCTRL$1,Endpoint Control $1"
|
|
bitfld.long 0x00 23. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 22. "TXR,TXR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "TXI,TXI" "0,1"
|
|
bitfld.long 0x00 18.--19. "TXT,TXT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "TXD,TXD" "0,1"
|
|
bitfld.long 0x00 16. "TXS,TXS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RXE,RXE" "0,1"
|
|
bitfld.long 0x00 6. "RXR,RXR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RXI,RXI" "0,1"
|
|
bitfld.long 0x00 2.--3. "RXT,RXT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "RXD,RXD" "0,1"
|
|
bitfld.long 0x00 0. "RXS,RXS" "0,1"
|
|
repeat.end
|
|
rgroup.long 0x200++0x03
|
|
line.long 0x00 "UOG2_ID,Identification register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "REVISION,REVISION"
|
|
bitfld.long 0x00 8.--13. "NID,NID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ID,ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "UOG2_HWGENERAL,Hardware General"
|
|
bitfld.long 0x00 9.--10. "SM,SM" "0: No Serial Engine always use parallel signalling,1: Serial Engine present always use serial..,2: Software programmable - Reset to use parallel..,3: Software programmable - Reset to use serial.."
|
|
bitfld.long 0x00 6.--8. "PHYM,PHYM" "0: UTMI/UMTI+,1: ULPI_DDR,2: ULPI,3: Serial Only,4: Software programmable - reset to UTMI/UTMI+,5: Software programmable - reset to ULPI DDR,6: Software programmable - reset to ULPI,7: Software programmable - reset to Serial"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "PHYW,PHYW" "0: 8 bit wide data bus (Software non-programmable),1: 16 bit wide data bus (Software..,2: Reset to 8 bit wide data bus (Software..,3: Reset to 16 bit wide data bus (Software.."
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "UOG2_HWHOST,Host Hardware Parameters"
|
|
bitfld.long 0x00 1.--3. "NPORT,NPORT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. "HC,HC" "0: Not supported,1: HOST_OP_EN"
|
|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "UOG2_HWDEVICE,Device Hardware Parameters"
|
|
bitfld.long 0x00 1.--5. "DEVEP,DEVEP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0. "DC,DC" "0: DEVICE_OP_DIS,1: DEVICE_OP_EN"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "UOG2_HWTXBUF,TX Buffer Hardware Parameters"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TXCHANADD,TXCHANADD"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXBURST,TXBURST"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "UOG2_HWRXBUF,RX Buffer Hardware Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXADD,RXADD"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RXBURST,RXBURST"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "UOG2_GPTIMER0LD,General Purpose Timer #0 Load"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTLD,GPTLD"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "UOG2_GPTIMER0CTRL,General Purpose Timer #0 Controller"
|
|
bitfld.long 0x00 31. "GPTRUN,GPTRUN" "0: Stop counting,1: RUN"
|
|
bitfld.long 0x00 30. "GPTRST,GPTRST" "0: NO_ACTION,1: Load counter value from GPTLD bits in.."
|
|
newline
|
|
bitfld.long 0x00 24. "GPTMODE,GPTMODE" "0: One Shot Mode,1: Repeat Mode"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTCNT,GPTCNT"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "UOG2_GPTIMER1LD,General Purpose Timer #1 Load"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTLD,GPTLD"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "UOG2_GPTIMER1CTRL,General Purpose Timer #1 Controller"
|
|
bitfld.long 0x00 31. "GPTRUN,GPTRUN" "0: Stop counting,1: RUN"
|
|
bitfld.long 0x00 30. "GPTRST,GPTRST" "0: NO_ACTION,1: Load counter value from GPTLD bits in.."
|
|
newline
|
|
bitfld.long 0x00 24. "GPTMODE,GPTMODE" "0: One Shot Mode,1: Repeat Mode"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "GPTCNT,GPTCNT"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "UOG2_SBUSCFG,System Bus Config"
|
|
bitfld.long 0x00 0.--2. "AHBBRST,AHBBRST" "0: Incremental burst of unspecified length only,1: INCR4 burst then single transfer,2: INCR8 burst INCR4 burst then single transfer,3: INCR16 burst INCR8 burst INCR4 burst then..,?,5: INCR4 burst then incremental burst of..,6: INCR8 burst INCR4 burst then incremental..,7: INCR16 burst INCR8 burst INCR4 burst then.."
|
|
rgroup.byte 0x300++0x00
|
|
line.byte 0x00 "UOG2_CAPLENGTH,Capability Registers Length"
|
|
hexmask.byte 0x00 0.--7. 1. "CAPLENGTH,CAPLENGTH"
|
|
rgroup.word 0x302++0x01
|
|
line.word 0x00 "UOG2_HCIVERSION,Host Controller Interface Version"
|
|
hexmask.word 0x00 0.--15. 1. "HCIVERSION,HCIVERSION"
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "UOG2_HCSPARAMS,Host Controller Structural Parameters"
|
|
bitfld.long 0x00 24.--27. "N_TT,N_TT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "N_PTT,N_PTT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16. "PI,PI" "0,1"
|
|
bitfld.long 0x00 12.--15. "N_CC,N_CC" "0: There is no internal Companion Controller and..,1: There are internal companion controller(s)..,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "N_PCC,N_PCC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. "PPC,PPC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "N_PORTS,N_PORTS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "UOG2_HCCPARAMS,Host Controller Capability Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EECP,EECP"
|
|
bitfld.long 0x00 4.--7. "IST,IST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2. "ASP,ASP" "0,1"
|
|
bitfld.long 0x00 1. "PFL,PFL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ADC,ADC" "0,1"
|
|
rgroup.word 0x320++0x01
|
|
line.word 0x00 "UOG2_DCIVERSION,Device Controller Interface Version"
|
|
hexmask.word 0x00 0.--15. 1. "DCIVERSION,DCIVERSION"
|
|
rgroup.long 0x324++0x03
|
|
line.long 0x00 "UOG2_DCCPARAMS,Device Controller Capability Parameters"
|
|
bitfld.long 0x00 8. "HC,HC" "0,1"
|
|
bitfld.long 0x00 7. "DC,DC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "DEN,DEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "UOG2_USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ITC,ITC"
|
|
bitfld.long 0x00 15. "FS_2,FS_2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "ATDTW,ATDTW" "0,1"
|
|
bitfld.long 0x00 13. "SUTW,SUTW" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "ASPE,ASPE" "0,1"
|
|
bitfld.long 0x00 8.--9. "ASP,ASP" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6. "IAA,IAA" "0,1"
|
|
bitfld.long 0x00 5. "ASE,ASE" "0: Do not process the Asynchronous Schedule,1: Use the ASYNCLISTADDR register to access the.."
|
|
newline
|
|
bitfld.long 0x00 4. "PSE,PSE" "0: Do not process the Periodic Schedule,1: Use the PERIODICLISTBASE register to access.."
|
|
bitfld.long 0x00 2.--3. "FS_1,FS_1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,RST" "0,1"
|
|
bitfld.long 0x00 0. "RS,RS" "0,1"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "UOG2_USBSTS,USB Status Register"
|
|
bitfld.long 0x00 25. "TI1,TI1" "0,1"
|
|
bitfld.long 0x00 24. "TI0,TI0" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 16. "NAKI,NAKI" "0,1"
|
|
bitfld.long 0x00 15. "AS,AS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "PS,PS" "0,1"
|
|
bitfld.long 0x00 13. "RCL,RCL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "HCH,HCH" "0,1"
|
|
bitfld.long 0x00 10. "ULPII,ULPII" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "SLI,SLI" "0,1"
|
|
bitfld.long 0x00 7. "SRI,SRI" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "URI,URI" "0,1"
|
|
bitfld.long 0x00 5. "AAI,AAI" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SEI,SEI" "0,1"
|
|
bitfld.long 0x00 3. "FRI,FRI" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PCI,PCI" "0,1"
|
|
bitfld.long 0x00 1. "UEI,UEI" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UI,UI" "0,1"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "UOG2_USBINTR,Interrupt Enable Register"
|
|
bitfld.long 0x00 25. "TIE1,TIE1" "0,1"
|
|
bitfld.long 0x00 24. "TIE0,TIE0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "UPIE,UPIE" "0,1"
|
|
bitfld.long 0x00 18. "UAIE,UAIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "NAKE,NAKE" "0,1"
|
|
bitfld.long 0x00 10. "ULPIE,ULPIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "SLE,SLE" "0,1"
|
|
bitfld.long 0x00 7. "SRE,SRE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "URE,URE" "0,1"
|
|
bitfld.long 0x00 5. "AAE,AAE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SEE,SEE" "0,1"
|
|
bitfld.long 0x00 3. "FRE,FRE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PCE,PCE" "0,1"
|
|
bitfld.long 0x00 1. "UEE,UEE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UE,UE" "0,1"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "UOG2_FRINDEX,USB Frame Index"
|
|
hexmask.long.word 0x00 0.--13. 1. "FRINDEX,FRINDEX"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "UOG2_PERIODICLISTBASE,Frame List Base Address"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. "BASEADR,BASEADR"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "UOG2_DEVICEADDR,Device Address"
|
|
hexmask.long.byte 0x00 25.--31. 1. "USBADR,USBADR"
|
|
bitfld.long 0x00 24. "USBADRA,USBADRA" "0,1"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "UOG2_ASYNCLISTADDR,Next Asynch"
|
|
hexmask.long 0x00 5.--31. 1. "ASYBASE,ASYBASE"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "UOG2_ENDPTLISTADDR,Endpoint List Address"
|
|
hexmask.long.tbyte 0x00 11.--31. 1. "EPBASE,EPBASE"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "UOG2_BURSTSIZE,Programmable Burst Size"
|
|
hexmask.long.word 0x00 8.--16. 1. "TXPBURST,TXPBURST"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RXPBURST,RXPBURST"
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "UOG2_TXFILLTUNING,TX FIFO Fill Tuning"
|
|
bitfld.long 0x00 16.--21. "TXFIFOTHRES,TXFIFOTHRES" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--12. "TXSCHHEALTH,TXSCHHEALTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXSCHOH,TXSCHOH"
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "UOG2_ENDPTNAK,Endpoint NAK"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EPTN,EPTN"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EPRN,EPRN"
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "UOG2_ENDPTNAKEN,Endpoint NAK Enable"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EPTNE,EPTNE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "EPRNE,EPRNE"
|
|
rgroup.long 0x380++0x03
|
|
line.long 0x00 "UOG2_CONFIGFLAG,Configure Flag Register"
|
|
bitfld.long 0x00 0. "CF,CF" "0: Port routing control logic default-routes..,1: Port routing control logic default-routes all.."
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "UOG2_PORTSC1,Port Status & Control"
|
|
bitfld.long 0x00 30.--31. "PTS_1,PTS_1" "0,1,2,3"
|
|
bitfld.long 0x00 29. "STS,STS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "PTW,PTW" "0: Select the 8-bit UTMI interface [60MHz],1: Select the 16-bit UTMI interface [30MHz]"
|
|
bitfld.long 0x00 26.--27. "PSPD,PSPD" "0: Full Speed,1: Low Speed,2: High Speed,3: UNDEFINED"
|
|
newline
|
|
bitfld.long 0x00 25. "PTS_2,PTS_2" "0,1"
|
|
bitfld.long 0x00 24. "PFSC,PFSC" "0: Normal operation,1: Forced to full speed"
|
|
newline
|
|
bitfld.long 0x00 23. "PHCD,PHCD" "0: Enable PHY clock,1: Disable PHY clock"
|
|
bitfld.long 0x00 22. "WKOC,WKOC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WKDC,WKDC" "0,1"
|
|
bitfld.long 0x00 20. "WKCN,WKCN" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "PTC,PTC" "0: TEST_MODE_DISABLE,1: J_STATE,2: K_STATE,3: SE0 (host) / NAK (device),4: Packet,5: FORCE_ENABLE_HS,6: FORCE_ENABLE_FS,7: FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x00 14.--15. "PIC,PIC" "0: Port indicators are off,1: PORT_IND_AMBER,2: PORT_IND_GREEN,3: UNDEFINED"
|
|
newline
|
|
bitfld.long 0x00 13. "PO,PO" "0,1"
|
|
bitfld.long 0x00 12. "PP,PP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "LS,LS" "0: SE0,1: K_STATE,2: J_STATE,3: UNDEFINED"
|
|
rbitfld.long 0x00 9. "HSP,HSP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "PR,PR" "0,1"
|
|
bitfld.long 0x00 7. "SUSP,SUSP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "FPR,FPR" "0,1"
|
|
bitfld.long 0x00 5. "OCC,OCC" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4. "OCA,OCA" "0: This port does not have an over-current..,1: This port currently has an over-current.."
|
|
bitfld.long 0x00 3. "PEC,PEC" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PE,PE" "0,1"
|
|
bitfld.long 0x00 1. "CSC,CSC" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "CCS,CCS" "0,1"
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "UOG2_OTGSC,On-The-Go Status & control"
|
|
bitfld.long 0x00 30. "DPIE,DPIE" "0,1"
|
|
bitfld.long 0x00 29. "EN_1MS,EN_1MS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "BSEIE,BSEIE" "0,1"
|
|
bitfld.long 0x00 27. "BSVIE,BSVIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "ASVIE,ASVIE" "0,1"
|
|
bitfld.long 0x00 25. "AVVIE,AVVIE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "IDIE,IDIE" "0,1"
|
|
bitfld.long 0x00 22. "DPIS,DPIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "STATUS_1MS,STATUS_1MS" "0,1"
|
|
bitfld.long 0x00 20. "BSEIS,BSEIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "BSVIS,BSVIS" "0,1"
|
|
bitfld.long 0x00 18. "ASVIS,ASVIS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "AVVIS,AVVIS" "0,1"
|
|
bitfld.long 0x00 16. "IDIS,IDIS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 14. "DPS,DPS" "0,1"
|
|
rbitfld.long 0x00 13. "TOG_1MS,TOG_1MS" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 12. "BSE,BSE" "0,1"
|
|
rbitfld.long 0x00 11. "BSV,BSV" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 10. "ASV,ASV" "0,1"
|
|
rbitfld.long 0x00 9. "AVV,AVV" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8. "ID,ID" "0,1"
|
|
bitfld.long 0x00 5. "IDPU,IDPU" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "DP,DP" "0,1"
|
|
bitfld.long 0x00 3. "OT,OT" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "VC,VC" "0,1"
|
|
bitfld.long 0x00 0. "VD,VD" "0,1"
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "UOG2_USBMODE,USB Device Mode"
|
|
bitfld.long 0x00 4. "SDIS,SDIS" "0,1"
|
|
bitfld.long 0x00 3. "SLOM,SLOM" "0: Setup Lockouts On (default),1: Setup Lockouts Off"
|
|
newline
|
|
bitfld.long 0x00 2. "ES,ES" "0: Little Endian [Default],1: BIG_ENDIAN"
|
|
bitfld.long 0x00 0.--1. "CM,CM" "0: Idle [Default for combination host/device],?,2: Device Controller [Default for device only..,3: Host Controller [Default for host only.."
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "UOG2_ENDPTSETUPSTAT,Endpoint Setup Status"
|
|
hexmask.long.word 0x00 0.--15. 1. "ENDPTSETUPSTAT,ENDPTSETUPSTAT"
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "UOG2_ENDPTPRIME,Endpoint Prime"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PETB,PETB"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PERB,PERB"
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "UOG2_ENDPTFLUSH,Endpoint Flush"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FETB,FETB"
|
|
hexmask.long.byte 0x00 0.--7. 1. "FERB,FERB"
|
|
rgroup.long 0x3B8++0x03
|
|
line.long 0x00 "UOG2_ENDPTSTAT,Endpoint Status"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ETBR,ETBR"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERBR,ERBR"
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "UOG2_ENDPTCOMPLETE,Endpoint Complete"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ETCE,ETCE"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERCE,ERCE"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "UOG2_ENDPTCTRL0,Endpoint Control0"
|
|
bitfld.long 0x00 23. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 18.--19. "TXT,TXT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16. "TXS,TXS" "0,1"
|
|
bitfld.long 0x00 7. "RXE,RXE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "RXT,RXT" "0,1,2,3"
|
|
bitfld.long 0x00 0. "RXS,RXS" "0,1"
|
|
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x3C4)++0x03
|
|
line.long 0x00 "UOG2_ENDPTCTRL$1,Endpoint Control $1"
|
|
bitfld.long 0x00 23. "TXE,TXE" "0,1"
|
|
bitfld.long 0x00 22. "TXR,TXR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "TXI,TXI" "0,1"
|
|
bitfld.long 0x00 18.--19. "TXT,TXT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 17. "TXD,TXD" "0,1"
|
|
bitfld.long 0x00 16. "TXS,TXS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "RXE,RXE" "0,1"
|
|
bitfld.long 0x00 6. "RXR,RXR" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RXI,RXI" "0,1"
|
|
bitfld.long 0x00 2.--3. "RXT,RXT" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "RXD,RXD" "0,1"
|
|
bitfld.long 0x00 0. "RXS,RXS" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
tree "USBNC (Universal Serial Bus)"
|
|
base ad:0x5B0D0000
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "OTG1_CTRL1,USB n Control Register"
|
|
rbitfld.long 0x00 31. "WIR,WIR" "0: No wake-up interrupt request received,1: Wake-up Interrupt Request received"
|
|
bitfld.long 0x00 29. "WKUP_DPDM_EN,WKUP_DPDM_EN" "0: DPDM changes wake-up to be disabled only when..,1: (Default) DPDM changes wake-up to be enabled.."
|
|
newline
|
|
bitfld.long 0x00 17. "WKUP_VBUS_EN,WKUP_VBUS_EN" "0: WKUP_VBUS_EN_0,1: WKUP_VBUS_EN_1"
|
|
bitfld.long 0x00 16. "WKUP_ID_EN,WKUP_ID_EN" "0: WKUP_ID_EN_0,1: WKUP_ID_EN_1"
|
|
newline
|
|
bitfld.long 0x00 15. "WKUP_SW,WKUP_SW" "0: WKUP_SW_0,1: Force wake-up"
|
|
bitfld.long 0x00 14. "WKUP_SW_EN,WKUP_SW_EN" "0: WKUP_SW_EN_0,1: WKUP_SW_EN_1"
|
|
newline
|
|
bitfld.long 0x00 10. "WIE,WIE" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 9. "PWR_POL,PWR_POL" "0: PMIC Power Pin is Low active,1: PMIC Power Pin is High active"
|
|
newline
|
|
bitfld.long 0x00 8. "OVER_CUR_POL,OVER_CUR_POL" "0: High active (high on this signal represents..,1: Low active (low on this signal represents an.."
|
|
bitfld.long 0x00 7. "OVER_CUR_DIS,OVER_CUR_DIS" "0: Enables overcurrent detection,1: Disables overcurrent detection"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "OTG1_CTRL2,USB n Control 2 Register"
|
|
eventfld.long 0x00 31. "UTMI_CLK_VLD,UTMI_CLK_VLD" "0: UTMI clock to USB PHY is not toggling (Default),1: UTMI clock to USB PHY has toggled several times"
|
|
bitfld.long 0x00 3. "LOWSPEED_EN,LOWSPEED_EN" "0: LOWSPEED_EN_0,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTURESUME_EN,Auto Resume Enable" "0: AUTURESUME_EN_0,?..."
|
|
bitfld.long 0x00 0.--1. "VBUS_SOURCE_SEL,VBUS_SOURCE_SEL" "0: VBUS_SOURCE_SEL_0,?..."
|
|
group.long 0x10200++0x03
|
|
line.long 0x00 "OTG2_CTRL1,USB n Control Register"
|
|
rbitfld.long 0x00 31. "WIR,WIR" "0: No wake-up interrupt request received,1: Wake-up Interrupt Request received"
|
|
bitfld.long 0x00 29. "WKUP_DPDM_EN,WKUP_DPDM_EN" "0: DPDM changes wake-up to be disabled only when..,1: (Default) DPDM changes wake-up to be enabled.."
|
|
newline
|
|
bitfld.long 0x00 17. "WKUP_VBUS_EN,WKUP_VBUS_EN" "0: WKUP_VBUS_EN_0,1: WKUP_VBUS_EN_1"
|
|
bitfld.long 0x00 16. "WKUP_ID_EN,WKUP_ID_EN" "0: WKUP_ID_EN_0,1: WKUP_ID_EN_1"
|
|
newline
|
|
bitfld.long 0x00 15. "WKUP_SW,WKUP_SW" "0: WKUP_SW_0,1: Force wake-up"
|
|
bitfld.long 0x00 14. "WKUP_SW_EN,WKUP_SW_EN" "0: WKUP_SW_EN_0,1: WKUP_SW_EN_1"
|
|
newline
|
|
bitfld.long 0x00 10. "WIE,WIE" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 9. "PWR_POL,PWR_POL" "0: PMIC Power Pin is Low active,1: PMIC Power Pin is High active"
|
|
newline
|
|
bitfld.long 0x00 8. "OVER_CUR_POL,OVER_CUR_POL" "0: High active (high on this signal represents..,1: Low active (low on this signal represents an.."
|
|
bitfld.long 0x00 7. "OVER_CUR_DIS,OVER_CUR_DIS" "0: Enables overcurrent detection,1: Disables overcurrent detection"
|
|
group.long 0x10204++0x03
|
|
line.long 0x00 "OTG2_CTRL2,USB n Control 2 Register"
|
|
eventfld.long 0x00 31. "UTMI_CLK_VLD,UTMI_CLK_VLD" "0: UTMI clock to USB PHY is not toggling (Default),1: UTMI clock to USB PHY has toggled several times"
|
|
bitfld.long 0x00 3. "LOWSPEED_EN,LOWSPEED_EN" "0: LOWSPEED_EN_0,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTURESUME_EN,Auto Resume Enable" "0: AUTURESUME_EN_0,?..."
|
|
bitfld.long 0x00 0.--1. "VBUS_SOURCE_SEL,VBUS_SOURCE_SEL" "0: VBUS_SOURCE_SEL_0,?..."
|
|
tree.end
|
|
tree "USBPHY (USBPHY Register Reference Index)"
|
|
repeat 2. (list 1. 2.) (list ad:0x5B100000 ad:0x5B110000)
|
|
tree "CONNECTIVITY__USBPHY$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWD,USB PHY Power-Down Register"
|
|
bitfld.long 0x00 20. "RXPWDRX,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the entire USB PHY receiver block.."
|
|
newline
|
|
bitfld.long 0x00 19. "RXPWDDIFF,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed differential.."
|
|
newline
|
|
bitfld.long 0x00 18. "RXPWD1PT1,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed differential.."
|
|
newline
|
|
bitfld.long 0x00 17. "RXPWDENV,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed receiver.."
|
|
newline
|
|
bitfld.long 0x00 12. "TXPWDV2I,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.."
|
|
newline
|
|
bitfld.long 0x00 11. "TXPWDIBIAS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY current bias block for.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXPWDFS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed drivers"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWD_SET,USB PHY Power-Down Register"
|
|
bitfld.long 0x00 20. "RXPWDRX,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the entire USB PHY receiver block.."
|
|
newline
|
|
bitfld.long 0x00 19. "RXPWDDIFF,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed differential.."
|
|
newline
|
|
bitfld.long 0x00 18. "RXPWD1PT1,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed differential.."
|
|
newline
|
|
bitfld.long 0x00 17. "RXPWDENV,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed receiver.."
|
|
newline
|
|
bitfld.long 0x00 12. "TXPWDV2I,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.."
|
|
newline
|
|
bitfld.long 0x00 11. "TXPWDIBIAS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY current bias block for.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXPWDFS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed drivers"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PWD_CLR,USB PHY Power-Down Register"
|
|
bitfld.long 0x00 20. "RXPWDRX,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the entire USB PHY receiver block.."
|
|
newline
|
|
bitfld.long 0x00 19. "RXPWDDIFF,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed differential.."
|
|
newline
|
|
bitfld.long 0x00 18. "RXPWD1PT1,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed differential.."
|
|
newline
|
|
bitfld.long 0x00 17. "RXPWDENV,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed receiver.."
|
|
newline
|
|
bitfld.long 0x00 12. "TXPWDV2I,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.."
|
|
newline
|
|
bitfld.long 0x00 11. "TXPWDIBIAS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY current bias block for.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXPWDFS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed drivers"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWD_TOG,USB PHY Power-Down Register"
|
|
bitfld.long 0x00 20. "RXPWDRX,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the entire USB PHY receiver block.."
|
|
newline
|
|
bitfld.long 0x00 19. "RXPWDDIFF,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed differential.."
|
|
newline
|
|
bitfld.long 0x00 18. "RXPWD1PT1,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed differential.."
|
|
newline
|
|
bitfld.long 0x00 17. "RXPWDENV,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed receiver.."
|
|
newline
|
|
bitfld.long 0x00 12. "TXPWDV2I,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.."
|
|
newline
|
|
bitfld.long 0x00 11. "TXPWDIBIAS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY current bias block for.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXPWDFS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHY_CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed drivers"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TX,USB PHY Transmitter Control Register"
|
|
bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0: TXCAL45DP_0,1: TXCAL45DP_1,2: TXCAL45DP_2,3: TXCAL45DP_3,4: TXCAL45DP_4,5: TXCAL45DP_5,6: TXCAL45DP_6,7: TXCAL45DP_7,8: TXCAL45DP_8,9: TXCAL45DP_9,10: TXCAL45DP_10,11: TXCAL45DP_11,12: TXCAL45DP_12,13: TXCAL45DP_13,14: TXCAL45DP_14,15: TXCAL45DP_15"
|
|
newline
|
|
bitfld.long 0x00 13. "TXENCAL45DM,Enable resistance calibration on DM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TXCAL45DM,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0: TXCAL45DM_0,1: TXCAL45DM_1,2: TXCAL45DM_2,3: TXCAL45DM_3,4: TXCAL45DM_4,5: TXCAL45DM_5,6: TXCAL45DM_6,7: TXCAL45DM_7,8: TXCAL45DM_8,9: TXCAL45DM_9,10: TXCAL45DM_10,11: TXCAL45DM_11,12: TXCAL45DM_12,13: TXCAL45DM_13,14: TXCAL45DM_14,15: TXCAL45DM_15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "D_CAL,Decode to trim the nominal 17" "0: Maximum current approximately 19% above nominal,?,?,?,?,?,?,7: D_CAL_7,?,?,?,?,?,?,?,15: Minimum current approximately 19% below.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TX_SET,USB PHY Transmitter Control Register"
|
|
bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0: TXCAL45DP_0,1: TXCAL45DP_1,2: TXCAL45DP_2,3: TXCAL45DP_3,4: TXCAL45DP_4,5: TXCAL45DP_5,6: TXCAL45DP_6,7: TXCAL45DP_7,8: TXCAL45DP_8,9: TXCAL45DP_9,10: TXCAL45DP_10,11: TXCAL45DP_11,12: TXCAL45DP_12,13: TXCAL45DP_13,14: TXCAL45DP_14,15: TXCAL45DP_15"
|
|
newline
|
|
bitfld.long 0x00 13. "TXENCAL45DM,Enable resistance calibration on DM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TXCAL45DM,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0: TXCAL45DM_0,1: TXCAL45DM_1,2: TXCAL45DM_2,3: TXCAL45DM_3,4: TXCAL45DM_4,5: TXCAL45DM_5,6: TXCAL45DM_6,7: TXCAL45DM_7,8: TXCAL45DM_8,9: TXCAL45DM_9,10: TXCAL45DM_10,11: TXCAL45DM_11,12: TXCAL45DM_12,13: TXCAL45DM_13,14: TXCAL45DM_14,15: TXCAL45DM_15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "D_CAL,Decode to trim the nominal 17" "0: Maximum current approximately 19% above nominal,?,?,?,?,?,?,7: D_CAL_7,?,?,?,?,?,?,?,15: Minimum current approximately 19% below.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TX_CLR,USB PHY Transmitter Control Register"
|
|
bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0: TXCAL45DP_0,1: TXCAL45DP_1,2: TXCAL45DP_2,3: TXCAL45DP_3,4: TXCAL45DP_4,5: TXCAL45DP_5,6: TXCAL45DP_6,7: TXCAL45DP_7,8: TXCAL45DP_8,9: TXCAL45DP_9,10: TXCAL45DP_10,11: TXCAL45DP_11,12: TXCAL45DP_12,13: TXCAL45DP_13,14: TXCAL45DP_14,15: TXCAL45DP_15"
|
|
newline
|
|
bitfld.long 0x00 13. "TXENCAL45DM,Enable resistance calibration on DM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TXCAL45DM,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0: TXCAL45DM_0,1: TXCAL45DM_1,2: TXCAL45DM_2,3: TXCAL45DM_3,4: TXCAL45DM_4,5: TXCAL45DM_5,6: TXCAL45DM_6,7: TXCAL45DM_7,8: TXCAL45DM_8,9: TXCAL45DM_9,10: TXCAL45DM_10,11: TXCAL45DM_11,12: TXCAL45DM_12,13: TXCAL45DM_13,14: TXCAL45DM_14,15: TXCAL45DM_15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "D_CAL,Decode to trim the nominal 17" "0: Maximum current approximately 19% above nominal,?,?,?,?,?,?,7: D_CAL_7,?,?,?,?,?,?,?,15: Minimum current approximately 19% below.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TX_TOG,USB PHY Transmitter Control Register"
|
|
bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0: TXCAL45DP_0,1: TXCAL45DP_1,2: TXCAL45DP_2,3: TXCAL45DP_3,4: TXCAL45DP_4,5: TXCAL45DP_5,6: TXCAL45DP_6,7: TXCAL45DP_7,8: TXCAL45DP_8,9: TXCAL45DP_9,10: TXCAL45DP_10,11: TXCAL45DP_11,12: TXCAL45DP_12,13: TXCAL45DP_13,14: TXCAL45DP_14,15: TXCAL45DP_15"
|
|
newline
|
|
bitfld.long 0x00 13. "TXENCAL45DM,Enable resistance calibration on DM" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TXCAL45DM,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0: TXCAL45DM_0,1: TXCAL45DM_1,2: TXCAL45DM_2,3: TXCAL45DM_3,4: TXCAL45DM_4,5: TXCAL45DM_5,6: TXCAL45DM_6,7: TXCAL45DM_7,8: TXCAL45DM_8,9: TXCAL45DM_9,10: TXCAL45DM_10,11: TXCAL45DM_11,12: TXCAL45DM_12,13: TXCAL45DM_13,14: TXCAL45DM_14,15: TXCAL45DM_15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "D_CAL,Decode to trim the nominal 17" "0: Maximum current approximately 19% above nominal,?,?,?,?,?,?,7: D_CAL_7,?,?,?,?,?,?,?,15: Minimum current approximately 19% below.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RX,USB PHY Receiver Control Register"
|
|
bitfld.long 0x00 22. "RXDBYPASS,This test mode is intended for lab use only replace FS differential receiver with DP single ended receiver" "0: Normal operation,1: Use the output of the USB_DP single-ended.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "RX_SET,USB PHY Receiver Control Register"
|
|
bitfld.long 0x00 22. "RXDBYPASS,This test mode is intended for lab use only replace FS differential receiver with DP single ended receiver" "0: Normal operation,1: Use the output of the USB_DP single-ended.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RX_CLR,USB PHY Receiver Control Register"
|
|
bitfld.long 0x00 22. "RXDBYPASS,This test mode is intended for lab use only replace FS differential receiver with DP single ended receiver" "0: Normal operation,1: Use the output of the USB_DP single-ended.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RX_TOG,USB PHY Receiver Control Register"
|
|
bitfld.long 0x00 22. "RXDBYPASS,This test mode is intended for lab use only replace FS differential receiver with DP single ended receiver" "0: Normal operation,1: Use the output of the USB_DP single-ended.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CTRL,USB PHY General Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the USBPHY_PWD USBPHY_TX USBPHY_RX and USBPHY_CTRL registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 27. "OTG_ID_VALUE,Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "FSDLL_RST_EN,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in USBPHY_PWD if there is wakeup event while USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "AUTORESUME_EN,Enable the auto resume feature when set HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.."
|
|
newline
|
|
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in High-Speed mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL_SET,USB PHY General Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the USBPHY_PWD USBPHY_TX USBPHY_RX and USBPHY_CTRL registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 27. "OTG_ID_VALUE,Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "FSDLL_RST_EN,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in USBPHY_PWD if there is wakeup event while USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "AUTORESUME_EN,Enable the auto resume feature when set HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.."
|
|
newline
|
|
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in High-Speed mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CTRL_CLR,USB PHY General Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the USBPHY_PWD USBPHY_TX USBPHY_RX and USBPHY_CTRL registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 27. "OTG_ID_VALUE,Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "FSDLL_RST_EN,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in USBPHY_PWD if there is wakeup event while USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "AUTORESUME_EN,Enable the auto resume feature when set HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.."
|
|
newline
|
|
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in High-Speed mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CTRL_TOG,USB PHY General Control Register"
|
|
bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the USBPHY_PWD USBPHY_TX USBPHY_RX and USBPHY_CTRL registers" "0,1"
|
|
newline
|
|
bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 27. "OTG_ID_VALUE,Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "FSDLL_RST_EN,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in USBPHY_PWD if there is wakeup event while USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "AUTORESUME_EN,Enable the auto resume feature when set HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.."
|
|
newline
|
|
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in High-Speed mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "STATUS,USB PHY Status Register"
|
|
rbitfld.long 0x00 10. "RESUME_STATUS,Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "OTGID_STATUS,Indicates the results of USB_ID pin on the USB cable plugged into the local Micro- or Mini-AB receptacle" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 6. "DEVPLUGIN_STATUS,Status indicator for non-standard resistive plugged-in detection" "0: No attachment to a USB host is detected,1: Cable attachment to a USB host is detected"
|
|
newline
|
|
rbitfld.long 0x00 3. "HOSTDISCONDETECT_STATUS,Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode" "0: USB cable disconnect has not been detected at..,1: USB cable disconnect has been detected at the.."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DEBUG0,USB PHY Debug Register 0"
|
|
bitfld.long 0x00 30. "CLKGATE,Gate Test Clocks" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "HOST_RESUME_DEBUG,Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--28. "SQUELCHRESETLENGTH,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24. "ENSQUELCHRESET,Set bit to allow squelch to reset high-speed receive" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SQUELCHRESETCOUNT,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 12. "ENTX2RXCOUNT,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TX2RXCOUNT,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "ENHSTPULLDOWN,This bit field selects host pulldown overdrive mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "HSTPULLDOWN,This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through USBPHY_DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "DEBUG_INTERFACE_HOLD,Use holding registers to assist in timing for external UTMI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OTGIDPIOLOCK,Once OTG ID from USBPHY_STATUS_OTGID_STATUS is sampled use this to hold the value" "0,1"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DEBUG0_SET,USB PHY Debug Register 0"
|
|
bitfld.long 0x00 30. "CLKGATE,Gate Test Clocks" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "HOST_RESUME_DEBUG,Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--28. "SQUELCHRESETLENGTH,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24. "ENSQUELCHRESET,Set bit to allow squelch to reset high-speed receive" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SQUELCHRESETCOUNT,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 12. "ENTX2RXCOUNT,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TX2RXCOUNT,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "ENHSTPULLDOWN,This bit field selects host pulldown overdrive mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "HSTPULLDOWN,This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through USBPHY_DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "DEBUG_INTERFACE_HOLD,Use holding registers to assist in timing for external UTMI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OTGIDPIOLOCK,Once OTG ID from USBPHY_STATUS_OTGID_STATUS is sampled use this to hold the value" "0,1"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DEBUG0_CLR,USB PHY Debug Register 0"
|
|
bitfld.long 0x00 30. "CLKGATE,Gate Test Clocks" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "HOST_RESUME_DEBUG,Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--28. "SQUELCHRESETLENGTH,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24. "ENSQUELCHRESET,Set bit to allow squelch to reset high-speed receive" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SQUELCHRESETCOUNT,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 12. "ENTX2RXCOUNT,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TX2RXCOUNT,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "ENHSTPULLDOWN,This bit field selects host pulldown overdrive mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "HSTPULLDOWN,This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through USBPHY_DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "DEBUG_INTERFACE_HOLD,Use holding registers to assist in timing for external UTMI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OTGIDPIOLOCK,Once OTG ID from USBPHY_STATUS_OTGID_STATUS is sampled use this to hold the value" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "DEBUG0_TOG,USB PHY Debug Register 0"
|
|
bitfld.long 0x00 30. "CLKGATE,Gate Test Clocks" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "HOST_RESUME_DEBUG,Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25.--28. "SQUELCHRESETLENGTH,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 24. "ENSQUELCHRESET,Set bit to allow squelch to reset high-speed receive" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "SQUELCHRESETCOUNT,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 12. "ENTX2RXCOUNT,Set this bit to allow a countdown to transition in between TX and RX" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TX2RXCOUNT,Delay in between the end of transmit to the beginning of receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "ENHSTPULLDOWN,This bit field selects host pulldown overdrive mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "HSTPULLDOWN,This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through USBPHY_DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 1. "DEBUG_INTERFACE_HOLD,Use holding registers to assist in timing for external UTMI interface" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "OTGIDPIOLOCK,Once OTG ID from USBPHY_STATUS_OTGID_STATUS is sampled use this to hold the value" "0,1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DEBUG1,UTMI Debug Status Register 1"
|
|
bitfld.long 0x00 21.--22. "USB2_REFBIAS_TST,Bias current control for usb2_phy" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "USB2_REFBIAS_VBGADJ,Adjustment bits on bandgap" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "ENTAILADJVD,Delay increment of the rise of squelch" "0: Delay is nominal,1: ENTAILADJVD_1,2: ENTAILADJVD_2,3: ENTAILADJVD_3"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DEBUG1_SET,UTMI Debug Status Register 1"
|
|
bitfld.long 0x00 21.--22. "USB2_REFBIAS_TST,Bias current control for usb2_phy" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "USB2_REFBIAS_VBGADJ,Adjustment bits on bandgap" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "ENTAILADJVD,Delay increment of the rise of squelch" "0: Delay is nominal,1: ENTAILADJVD_1,2: ENTAILADJVD_2,3: ENTAILADJVD_3"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "DEBUG1_CLR,UTMI Debug Status Register 1"
|
|
bitfld.long 0x00 21.--22. "USB2_REFBIAS_TST,Bias current control for usb2_phy" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "USB2_REFBIAS_VBGADJ,Adjustment bits on bandgap" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "ENTAILADJVD,Delay increment of the rise of squelch" "0: Delay is nominal,1: ENTAILADJVD_1,2: ENTAILADJVD_2,3: ENTAILADJVD_3"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "DEBUG1_TOG,UTMI Debug Status Register 1"
|
|
bitfld.long 0x00 21.--22. "USB2_REFBIAS_TST,Bias current control for usb2_phy" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 18.--20. "USB2_REFBIAS_VBGADJ,Adjustment bits on bandgap" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "ENTAILADJVD,Delay increment of the rise of squelch" "0: Delay is nominal,1: ENTAILADJVD_1,2: ENTAILADJVD_2,3: ENTAILADJVD_3"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "VERSION,UTMI RTL Version"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Fixed read-only value reflecting the MAJOR field of the RTL version"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Fixed read-only value reflecting the MINOR field of the RTL version"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "STEP,Fixed read-only value reflecting the stepping of the RTL version"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PLL_SIC,USB PHY PLL Control/Status Register"
|
|
rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "PLL_DIV_SEL,This field controls the USB PLL feedback loop divider" "0: PLL_DIV_SEL_0,1: PLL_DIV_SEL_1,2: PLL_DIV_SEL_2,3: PLL_DIV_SEL_3,4: PLL_DIV_SEL_4,5: PLL_DIV_SEL_5,6: PLL_DIV_SEL_6,7: PLL_DIV_SEL_7"
|
|
newline
|
|
bitfld.long 0x00 21. "PLL_REG_ENABLE,This field controls the USB PLL regulator set to enable the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "REFBIAS_PWD,Power down the reference bias" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.."
|
|
newline
|
|
bitfld.long 0x00 16. "PLL_BYPASS,Bypass the USB PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "PLL_ENABLE,Enables the clock output from the USB PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "PLL_POWER,Power up the USB PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PLL_EN_USB_CLKS,Enables the USB clock from PLL to USB PHY" "0,1"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "PLL_SIC_SET,USB PHY PLL Control/Status Register"
|
|
rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "PLL_DIV_SEL,This field controls the USB PLL feedback loop divider" "0: PLL_DIV_SEL_0,1: PLL_DIV_SEL_1,2: PLL_DIV_SEL_2,3: PLL_DIV_SEL_3,4: PLL_DIV_SEL_4,5: PLL_DIV_SEL_5,6: PLL_DIV_SEL_6,7: PLL_DIV_SEL_7"
|
|
newline
|
|
bitfld.long 0x00 21. "PLL_REG_ENABLE,This field controls the USB PLL regulator set to enable the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "REFBIAS_PWD,Power down the reference bias" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.."
|
|
newline
|
|
bitfld.long 0x00 16. "PLL_BYPASS,Bypass the USB PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "PLL_ENABLE,Enables the clock output from the USB PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "PLL_POWER,Power up the USB PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PLL_EN_USB_CLKS,Enables the USB clock from PLL to USB PHY" "0,1"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PLL_SIC_CLR,USB PHY PLL Control/Status Register"
|
|
rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "PLL_DIV_SEL,This field controls the USB PLL feedback loop divider" "0: PLL_DIV_SEL_0,1: PLL_DIV_SEL_1,2: PLL_DIV_SEL_2,3: PLL_DIV_SEL_3,4: PLL_DIV_SEL_4,5: PLL_DIV_SEL_5,6: PLL_DIV_SEL_6,7: PLL_DIV_SEL_7"
|
|
newline
|
|
bitfld.long 0x00 21. "PLL_REG_ENABLE,This field controls the USB PLL regulator set to enable the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "REFBIAS_PWD,Power down the reference bias" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.."
|
|
newline
|
|
bitfld.long 0x00 16. "PLL_BYPASS,Bypass the USB PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "PLL_ENABLE,Enables the clock output from the USB PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "PLL_POWER,Power up the USB PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PLL_EN_USB_CLKS,Enables the USB clock from PLL to USB PHY" "0,1"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "PLL_SIC_TOG,USB PHY PLL Control/Status Register"
|
|
rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
|
|
newline
|
|
bitfld.long 0x00 22.--24. "PLL_DIV_SEL,This field controls the USB PLL feedback loop divider" "0: PLL_DIV_SEL_0,1: PLL_DIV_SEL_1,2: PLL_DIV_SEL_2,3: PLL_DIV_SEL_3,4: PLL_DIV_SEL_4,5: PLL_DIV_SEL_5,6: PLL_DIV_SEL_6,7: PLL_DIV_SEL_7"
|
|
newline
|
|
bitfld.long 0x00 21. "PLL_REG_ENABLE,This field controls the USB PLL regulator set to enable the regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "REFBIAS_PWD,Power down the reference bias" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.."
|
|
newline
|
|
bitfld.long 0x00 16. "PLL_BYPASS,Bypass the USB PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "PLL_ENABLE,Enables the clock output from the USB PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "PLL_POWER,Power up the USB PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PLL_EN_USB_CLKS,Enables the USB clock from PLL to USB PHY" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "USB1_VBUS_DETECT,USB PHY VBUS Detect Control Register"
|
|
bitfld.long 0x00 31. "EN_CHARGER_RESISTOR,Enables resistors used for an older method of resistive battery charger detection" "0: Disable resistive charger detection resistors..,1: Enable resistive charger detection resistors.."
|
|
newline
|
|
bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "PWRUP_CMPS,Enables the VBUS_VALID comparator" "0: Powers down the VBUS_VALID comparator,1: Enables the VBUS_VALID comparator (default)"
|
|
newline
|
|
bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.."
|
|
newline
|
|
bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..."
|
|
newline
|
|
bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.."
|
|
newline
|
|
bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Sets the threshold for the VBUSVALID comparator" "0: VBUSVALID_THRESH_0,1: VBUSVALID_THRESH_1,2: VBUSVALID_THRESH_2,3: VBUSVALID_THRESH_3,4: VBUSVALID_THRESH_4,5: VBUSVALID_THRESH_5,6: VBUSVALID_THRESH_6,7: VBUSVALID_THRESH_7"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "USB1_VBUS_DETECT_SET,USB PHY VBUS Detect Control Register"
|
|
bitfld.long 0x00 31. "EN_CHARGER_RESISTOR,Enables resistors used for an older method of resistive battery charger detection" "0: Disable resistive charger detection resistors..,1: Enable resistive charger detection resistors.."
|
|
newline
|
|
bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "PWRUP_CMPS,Enables the VBUS_VALID comparator" "0: Powers down the VBUS_VALID comparator,1: Enables the VBUS_VALID comparator (default)"
|
|
newline
|
|
bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.."
|
|
newline
|
|
bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..."
|
|
newline
|
|
bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.."
|
|
newline
|
|
bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Sets the threshold for the VBUSVALID comparator" "0: VBUSVALID_THRESH_0,1: VBUSVALID_THRESH_1,2: VBUSVALID_THRESH_2,3: VBUSVALID_THRESH_3,4: VBUSVALID_THRESH_4,5: VBUSVALID_THRESH_5,6: VBUSVALID_THRESH_6,7: VBUSVALID_THRESH_7"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "USB1_VBUS_DETECT_CLR,USB PHY VBUS Detect Control Register"
|
|
bitfld.long 0x00 31. "EN_CHARGER_RESISTOR,Enables resistors used for an older method of resistive battery charger detection" "0: Disable resistive charger detection resistors..,1: Enable resistive charger detection resistors.."
|
|
newline
|
|
bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "PWRUP_CMPS,Enables the VBUS_VALID comparator" "0: Powers down the VBUS_VALID comparator,1: Enables the VBUS_VALID comparator (default)"
|
|
newline
|
|
bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.."
|
|
newline
|
|
bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..."
|
|
newline
|
|
bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.."
|
|
newline
|
|
bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Sets the threshold for the VBUSVALID comparator" "0: VBUSVALID_THRESH_0,1: VBUSVALID_THRESH_1,2: VBUSVALID_THRESH_2,3: VBUSVALID_THRESH_3,4: VBUSVALID_THRESH_4,5: VBUSVALID_THRESH_5,6: VBUSVALID_THRESH_6,7: VBUSVALID_THRESH_7"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "USB1_VBUS_DETECT_TOG,USB PHY VBUS Detect Control Register"
|
|
bitfld.long 0x00 31. "EN_CHARGER_RESISTOR,Enables resistors used for an older method of resistive battery charger detection" "0: Disable resistive charger detection resistors..,1: Enable resistive charger detection resistors.."
|
|
newline
|
|
bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "PWRUP_CMPS,Enables the VBUS_VALID comparator" "0: Powers down the VBUS_VALID comparator,1: Enables the VBUS_VALID comparator (default)"
|
|
newline
|
|
bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.."
|
|
newline
|
|
bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..."
|
|
newline
|
|
bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.."
|
|
newline
|
|
bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.."
|
|
newline
|
|
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Sets the threshold for the VBUSVALID comparator" "0: VBUSVALID_THRESH_0,1: VBUSVALID_THRESH_1,2: VBUSVALID_THRESH_2,3: VBUSVALID_THRESH_3,4: VBUSVALID_THRESH_4,5: VBUSVALID_THRESH_5,6: VBUSVALID_THRESH_6,7: VBUSVALID_THRESH_7"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "USB1_VBUS_DET_STAT,USB PHY VBUS Detector Status Register"
|
|
bitfld.long 0x00 4. "VBUS_VALID_3V,VBUS_VALID_3V detector status" "0: VBUS voltage is below VBUS_VALID_3V threshold,1: VBUS voltage is above VBUS_VALID_3V threshold"
|
|
newline
|
|
bitfld.long 0x00 3. "VBUS_VALID,VBUS voltage status" "0: VBUS is below the comparator threshold,1: VBUS is above the comparator threshold"
|
|
newline
|
|
bitfld.long 0x00 2. "AVALID,A-Device Session Valid status" "0: The VBUS voltage is below the Session Valid..,1: The VBUS voltage is above the Session Valid.."
|
|
newline
|
|
bitfld.long 0x00 1. "BVALID,B-Device Session Valid status" "0: The VBUS voltage is below the Session Valid..,1: The VBUS voltage is above the Session Valid.."
|
|
newline
|
|
bitfld.long 0x00 0. "SESSEND,Session End indicator" "0: The VBUS voltage is above the Session Valid..,1: The VBUS voltage is below the Session Valid.."
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "USB1_CHRG_DETECT,USB PHY Charger Detect Control Register"
|
|
bitfld.long 0x00 23. "BGR_IBIAS,USB charge detector bias current reference" "0: Bias current is derived from the USB PHY..,1: Bias current is derived from the reference.."
|
|
newline
|
|
bitfld.long 0x00 2. "PULLUP_DP,This bit is used to pull up DP for digital charge detect" "0,1"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "USB1_CHRG_DETECT_SET,USB PHY Charger Detect Control Register"
|
|
bitfld.long 0x00 23. "BGR_IBIAS,USB charge detector bias current reference" "0: Bias current is derived from the USB PHY..,1: Bias current is derived from the reference.."
|
|
newline
|
|
bitfld.long 0x00 2. "PULLUP_DP,This bit is used to pull up DP for digital charge detect" "0,1"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "USB1_CHRG_DETECT_CLR,USB PHY Charger Detect Control Register"
|
|
bitfld.long 0x00 23. "BGR_IBIAS,USB charge detector bias current reference" "0: Bias current is derived from the USB PHY..,1: Bias current is derived from the reference.."
|
|
newline
|
|
bitfld.long 0x00 2. "PULLUP_DP,This bit is used to pull up DP for digital charge detect" "0,1"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "USB1_CHRG_DETECT_TOG,USB PHY Charger Detect Control Register"
|
|
bitfld.long 0x00 23. "BGR_IBIAS,USB charge detector bias current reference" "0: Bias current is derived from the USB PHY..,1: Bias current is derived from the reference.."
|
|
newline
|
|
bitfld.long 0x00 2. "PULLUP_DP,This bit is used to pull up DP for digital charge detect" "0,1"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "USB1_CHRG_DET_STAT,USB PHY Charger Detect Status Register"
|
|
bitfld.long 0x00 4. "SECDET_DCP,Battery Charging Secondary Detection phase output" "0: Charging Downstream Port (CDP) has been..,1: Downstream Charging Port (DCP) has been.."
|
|
newline
|
|
bitfld.long 0x00 3. "DP_STATE,Single ended receiver output for the USB_DP pin from charger detection circuits" "0: USB_DP pin voltage is < 0.8V,1: USB_DP pin voltage is > 2.0V"
|
|
newline
|
|
bitfld.long 0x00 2. "DM_STATE,Single ended receiver output for the USB_DM pin from charger detection circuits" "0: USB_DM pin voltage is < 0.8V,1: USB_DM pin voltage is > 2.0V"
|
|
newline
|
|
bitfld.long 0x00 1. "CHRG_DETECTED,Battery Charging Primary Detection phase output" "0: Standard Downstream Port (SDP) has been..,1: Charging Port has been detected"
|
|
newline
|
|
bitfld.long 0x00 0. "PLUG_CONTACT,Battery Charging Data Contact Detection phase output" "0: No USB cable attachment has been detected,1: A USB cable attachment between the device and.."
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ANACTRL,USB PHY Analog Control Register"
|
|
bitfld.long 0x00 10. "DEV_PULLDOWN,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP..,1: The 15kohm nominal pulldowns on the USB_DP.."
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "ANACTRL_SET,USB PHY Analog Control Register"
|
|
bitfld.long 0x00 10. "DEV_PULLDOWN,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP..,1: The 15kohm nominal pulldowns on the USB_DP.."
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "ANACTRL_CLR,USB PHY Analog Control Register"
|
|
bitfld.long 0x00 10. "DEV_PULLDOWN,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP..,1: The 15kohm nominal pulldowns on the USB_DP.."
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "ANACTRL_TOG,USB PHY Analog Control Register"
|
|
bitfld.long 0x00 10. "DEV_PULLDOWN,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP..,1: The 15kohm nominal pulldowns on the USB_DP.."
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "USB1_LOOPBACK,USB PHY Loopback Control/Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TSTPKT,Selects the packet data byte used for USB loopback testing in Pulse mode"
|
|
newline
|
|
bitfld.long 0x00 15. "TSTI_HSFS_MODE_EN,Setting this bit field to value 1'b1 will enable the loopback test to dynamically change the packet speed" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8. "UTMO_DIG_TST1,This read-only bit is a status bit for USB loopback test" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "UTMO_DIG_TST0,This read-only bit is a status bit for USB loopback test results" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TSTI_TX_HIZ,Sets TX Hi-Z for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TSTI_TX_EN,Enable TX for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TSTI_TX_LS_MODE,Set to value 1'b1 to choose LS for USB loopback testing set to value 1'b0 to choose HS or FS mode which is defined by TSTI1_TX_HS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TSTI_TX_HS_MODE,Select HS or FS mode for USB loopback testing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UTMI_DIG_TST1,Mode control for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "UTMI_DIG_TST0,Mode control for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UTMI_TESTSTART,This bit enables the USB loopback test" "0,1"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "USB1_LOOPBACK_SET,USB PHY Loopback Control/Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TSTPKT,Selects the packet data byte used for USB loopback testing in Pulse mode"
|
|
newline
|
|
bitfld.long 0x00 15. "TSTI_HSFS_MODE_EN,Setting this bit field to value 1'b1 will enable the loopback test to dynamically change the packet speed" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8. "UTMO_DIG_TST1,This read-only bit is a status bit for USB loopback test" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "UTMO_DIG_TST0,This read-only bit is a status bit for USB loopback test results" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TSTI_TX_HIZ,Sets TX Hi-Z for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TSTI_TX_EN,Enable TX for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TSTI_TX_LS_MODE,Set to value 1'b1 to choose LS for USB loopback testing set to value 1'b0 to choose HS or FS mode which is defined by TSTI1_TX_HS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TSTI_TX_HS_MODE,Select HS or FS mode for USB loopback testing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UTMI_DIG_TST1,Mode control for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "UTMI_DIG_TST0,Mode control for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UTMI_TESTSTART,This bit enables the USB loopback test" "0,1"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "USB1_LOOPBACK_CLR,USB PHY Loopback Control/Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TSTPKT,Selects the packet data byte used for USB loopback testing in Pulse mode"
|
|
newline
|
|
bitfld.long 0x00 15. "TSTI_HSFS_MODE_EN,Setting this bit field to value 1'b1 will enable the loopback test to dynamically change the packet speed" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8. "UTMO_DIG_TST1,This read-only bit is a status bit for USB loopback test" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "UTMO_DIG_TST0,This read-only bit is a status bit for USB loopback test results" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TSTI_TX_HIZ,Sets TX Hi-Z for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TSTI_TX_EN,Enable TX for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TSTI_TX_LS_MODE,Set to value 1'b1 to choose LS for USB loopback testing set to value 1'b0 to choose HS or FS mode which is defined by TSTI1_TX_HS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TSTI_TX_HS_MODE,Select HS or FS mode for USB loopback testing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UTMI_DIG_TST1,Mode control for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "UTMI_DIG_TST0,Mode control for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UTMI_TESTSTART,This bit enables the USB loopback test" "0,1"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "USB1_LOOPBACK_TOG,USB PHY Loopback Control/Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TSTPKT,Selects the packet data byte used for USB loopback testing in Pulse mode"
|
|
newline
|
|
bitfld.long 0x00 15. "TSTI_HSFS_MODE_EN,Setting this bit field to value 1'b1 will enable the loopback test to dynamically change the packet speed" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 8. "UTMO_DIG_TST1,This read-only bit is a status bit for USB loopback test" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "UTMO_DIG_TST0,This read-only bit is a status bit for USB loopback test results" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TSTI_TX_HIZ,Sets TX Hi-Z for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TSTI_TX_EN,Enable TX for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TSTI_TX_LS_MODE,Set to value 1'b1 to choose LS for USB loopback testing set to value 1'b0 to choose HS or FS mode which is defined by TSTI1_TX_HS" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TSTI_TX_HS_MODE,Select HS or FS mode for USB loopback testing" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "UTMI_DIG_TST1,Mode control for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "UTMI_DIG_TST0,Mode control for USB loopback test" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UTMI_TESTSTART,This bit enables the USB loopback test" "0,1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "USB1_LOOPBACK_HSFSCNT,USB PHY Loopback Packet Number Select Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "TSTI_FS_NUMBER,Full speed packet number used when USBPHY_USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "TSTI_HS_NUMBER,High speed packet number used when USBPHY_USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "USB1_LOOPBACK_HSFSCNT_SET,USB PHY Loopback Packet Number Select Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "TSTI_FS_NUMBER,Full speed packet number used when USBPHY_USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "TSTI_HS_NUMBER,High speed packet number used when USBPHY_USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "USB1_LOOPBACK_HSFSCNT_CLR,USB PHY Loopback Packet Number Select Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "TSTI_FS_NUMBER,Full speed packet number used when USBPHY_USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "TSTI_HS_NUMBER,High speed packet number used when USBPHY_USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "USB1_LOOPBACK_HSFSCNT_TOG,USB PHY Loopback Packet Number Select Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "TSTI_FS_NUMBER,Full speed packet number used when USBPHY_USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "TSTI_HS_NUMBER,High speed packet number used when USBPHY_USB1_LOOPBACK[TSTI_HSFS_MODE_EN] is set to value 1'b1"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TRIM_OVERRIDE_EN,USB PHY Trim Override Enable Register"
|
|
rbitfld.long 0x00 28.--31. "TRIM_USBPHY_TX_CAL45DM,IFR value of TX_CAL45DM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "TRIM_USBPHY_TX_CAL45DP,IFR value of TX_CAL45DP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "TRIM_USBPHY_TX_D_CAL,IFR value of TX_D_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 18.--19. "TRIM_USB_REG_ENV_TAIL_ADJ_VD,IFR value of ENV_TAIL_ADJ" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 15.--17. "TRIM_PLL_CTRL0_DIV_SEL,IFR value of PLL_DIV_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 13.--14. "TRIM_USB2_REFBIAS_TST,Bias current control for usb2_phy" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 10.--12. "TRIM_USB2_REFBIAS_VBGADJ,Adjustment bits for bandgap" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6. "TRIM_REFBIAS_TST_OVERRIDE,Override enable for bias current control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TRIM_REFBIAS_VBGADJ_OVERRIDE,Override enable for bandgap adjustment" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TRIM_TX_CAL45DM_OVERRIDE,Override enable for TX_CAL45DM when set the register value in USBPHY_TX[11:8] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TRIM_TX_CAL45DP_OVERRIDE,Override enable for TX_CAL45DP when set the register value in USBPHY_TX[19:16] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TRIM_TX_D_CAL_OVERRIDE,Override enable for TX_D_CAL when set the register value in USBPHY_TX[3:0] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TRIM_ENV_TAIL_ADJ_VD_OVERRIDE,Override enable for ENV_TAIL_ADJ when set the register value in USBPHY_DEBUG1[14:13] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRIM_DIV_SEL_OVERRIDE,Override enable for PLL_DIV_SEL when set the register value in USBPHY_PLL_SIC[1:0] will be used" "0,1"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TRIM_OVERRIDE_EN_SET,USB PHY Trim Override Enable Register"
|
|
rbitfld.long 0x00 28.--31. "TRIM_USBPHY_TX_CAL45DM,IFR value of TX_CAL45DM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "TRIM_USBPHY_TX_CAL45DP,IFR value of TX_CAL45DP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "TRIM_USBPHY_TX_D_CAL,IFR value of TX_D_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 18.--19. "TRIM_USB_REG_ENV_TAIL_ADJ_VD,IFR value of ENV_TAIL_ADJ" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 15.--17. "TRIM_PLL_CTRL0_DIV_SEL,IFR value of PLL_DIV_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 13.--14. "TRIM_USB2_REFBIAS_TST,Bias current control for usb2_phy" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 10.--12. "TRIM_USB2_REFBIAS_VBGADJ,Adjustment bits for bandgap" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6. "TRIM_REFBIAS_TST_OVERRIDE,Override enable for bias current control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TRIM_REFBIAS_VBGADJ_OVERRIDE,Override enable for bandgap adjustment" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TRIM_TX_CAL45DM_OVERRIDE,Override enable for TX_CAL45DM when set the register value in USBPHY_TX[11:8] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TRIM_TX_CAL45DP_OVERRIDE,Override enable for TX_CAL45DP when set the register value in USBPHY_TX[19:16] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TRIM_TX_D_CAL_OVERRIDE,Override enable for TX_D_CAL when set the register value in USBPHY_TX[3:0] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TRIM_ENV_TAIL_ADJ_VD_OVERRIDE,Override enable for ENV_TAIL_ADJ when set the register value in USBPHY_DEBUG1[14:13] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRIM_DIV_SEL_OVERRIDE,Override enable for PLL_DIV_SEL when set the register value in USBPHY_PLL_SIC[1:0] will be used" "0,1"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TRIM_OVERRIDE_EN_CLR,USB PHY Trim Override Enable Register"
|
|
rbitfld.long 0x00 28.--31. "TRIM_USBPHY_TX_CAL45DM,IFR value of TX_CAL45DM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "TRIM_USBPHY_TX_CAL45DP,IFR value of TX_CAL45DP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "TRIM_USBPHY_TX_D_CAL,IFR value of TX_D_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 18.--19. "TRIM_USB_REG_ENV_TAIL_ADJ_VD,IFR value of ENV_TAIL_ADJ" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 15.--17. "TRIM_PLL_CTRL0_DIV_SEL,IFR value of PLL_DIV_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 13.--14. "TRIM_USB2_REFBIAS_TST,Bias current control for usb2_phy" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 10.--12. "TRIM_USB2_REFBIAS_VBGADJ,Adjustment bits for bandgap" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6. "TRIM_REFBIAS_TST_OVERRIDE,Override enable for bias current control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TRIM_REFBIAS_VBGADJ_OVERRIDE,Override enable for bandgap adjustment" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TRIM_TX_CAL45DM_OVERRIDE,Override enable for TX_CAL45DM when set the register value in USBPHY_TX[11:8] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TRIM_TX_CAL45DP_OVERRIDE,Override enable for TX_CAL45DP when set the register value in USBPHY_TX[19:16] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TRIM_TX_D_CAL_OVERRIDE,Override enable for TX_D_CAL when set the register value in USBPHY_TX[3:0] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TRIM_ENV_TAIL_ADJ_VD_OVERRIDE,Override enable for ENV_TAIL_ADJ when set the register value in USBPHY_DEBUG1[14:13] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRIM_DIV_SEL_OVERRIDE,Override enable for PLL_DIV_SEL when set the register value in USBPHY_PLL_SIC[1:0] will be used" "0,1"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TRIM_OVERRIDE_EN_TOG,USB PHY Trim Override Enable Register"
|
|
rbitfld.long 0x00 28.--31. "TRIM_USBPHY_TX_CAL45DM,IFR value of TX_CAL45DM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "TRIM_USBPHY_TX_CAL45DP,IFR value of TX_CAL45DP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "TRIM_USBPHY_TX_D_CAL,IFR value of TX_D_CAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 18.--19. "TRIM_USB_REG_ENV_TAIL_ADJ_VD,IFR value of ENV_TAIL_ADJ" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 15.--17. "TRIM_PLL_CTRL0_DIV_SEL,IFR value of PLL_DIV_SEL" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 13.--14. "TRIM_USB2_REFBIAS_TST,Bias current control for usb2_phy" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 10.--12. "TRIM_USB2_REFBIAS_VBGADJ,Adjustment bits for bandgap" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6. "TRIM_REFBIAS_TST_OVERRIDE,Override enable for bias current control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "TRIM_REFBIAS_VBGADJ_OVERRIDE,Override enable for bandgap adjustment" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TRIM_TX_CAL45DM_OVERRIDE,Override enable for TX_CAL45DM when set the register value in USBPHY_TX[11:8] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "TRIM_TX_CAL45DP_OVERRIDE,Override enable for TX_CAL45DP when set the register value in USBPHY_TX[19:16] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "TRIM_TX_D_CAL_OVERRIDE,Override enable for TX_D_CAL when set the register value in USBPHY_TX[3:0] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TRIM_ENV_TAIL_ADJ_VD_OVERRIDE,Override enable for ENV_TAIL_ADJ when set the register value in USBPHY_DEBUG1[14:13] will be used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TRIM_DIV_SEL_OVERRIDE,Override enable for PLL_DIV_SEL when set the register value in USBPHY_PLL_SIC[1:0] will be used" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "USDHC (Ultra Secured Digital Host Controller)"
|
|
repeat 3. (list 0. 1. 2.) (list ad:0x5B010000 ad:0x5B020000 ad:0x5B030000)
|
|
tree "CONNECTIVITY__USDHC$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DS_ADDR,DMA System Address"
|
|
hexmask.long 0x00 0.--31. 1. "DS_ADDR,System address"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BLK_ATT,Block Attributes"
|
|
hexmask.long.word 0x00 16.--31. 1. "BLKCNT,Blocks count for current transfer"
|
|
newline
|
|
hexmask.long.word 0x00 0.--12. 1. "BLKSIZE,Transfer block size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMD_ARG,Command Argument"
|
|
hexmask.long 0x00 0.--31. 1. "CMDARG,Command argument"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CMD_XFR_TYP,Command Transfer Type"
|
|
bitfld.long 0x00 24.--29. "CMDINX,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "CMDTYP,Command type" "0: Normal other commands,1: Suspend CMD52 for writing bus suspend in CCCR,2: Resume CMD52 for writing function select in..,3: Abort CMD12 CMD52 for writing I/O Abort in CCCR"
|
|
newline
|
|
bitfld.long 0x00 21. "DPSEL,Data present select" "0: No data present,1: Data present"
|
|
newline
|
|
bitfld.long 0x00 20. "CICEN,Command index check enable" "0: Disable command index check,1: Enables command index check"
|
|
newline
|
|
bitfld.long 0x00 19. "CCCEN,Command CRC check enable" "0: Disables command CRC check,1: Enables command CRC check"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "RSPTYP,Response type select" "0: No response,1: Response length 136,2: Response length 48,3: Response length 48 check busy after response"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CMD_RSP0,Command Response0"
|
|
hexmask.long 0x00 0.--31. 1. "CMDRSP0,Command response 0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CMD_RSP1,Command Response1"
|
|
hexmask.long 0x00 0.--31. 1. "CMDRSP1,Command response 1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CMD_RSP2,Command Response2"
|
|
hexmask.long 0x00 0.--31. 1. "CMDRSP2,Command response 2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CMD_RSP3,Command Response3"
|
|
hexmask.long 0x00 0.--31. 1. "CMDRSP3,Command response 3"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DATA_BUFF_ACC_PORT,Data Buffer Access Port"
|
|
hexmask.long 0x00 0.--31. 1. "DATCONT,Data content"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "PRES_STATE,Present State"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DLSL,DATA[7:0] line signal level"
|
|
newline
|
|
bitfld.long 0x00 23. "CLSL,CMD line signal level" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "WPSPL,Write protect switch pin level" "0: Write protected (WP = 1),1: Write enabled (WP = 0)"
|
|
newline
|
|
bitfld.long 0x00 18. "CDPL,Card detect pin level" "0: No card present (CD_B = 1),1: Card present (CD_B = 0)"
|
|
newline
|
|
bitfld.long 0x00 16. "CINST,Card inserted" "0: Power on reset or no card,1: Card inserted"
|
|
newline
|
|
bitfld.long 0x00 15. "TSCD,Tape select change done" "0: Delay cell select change is not finished,1: Delay cell select change is finished"
|
|
newline
|
|
bitfld.long 0x00 12. "RTR,Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Fixed or well tuned sampling clock,1: Sampling clock needs re-tuning"
|
|
newline
|
|
bitfld.long 0x00 11. "BREN,Buffer read enable" "0: Read disable,1: Read enable"
|
|
newline
|
|
bitfld.long 0x00 10. "BWEN,Buffer write enable" "0: Write disable,1: Write enable"
|
|
newline
|
|
bitfld.long 0x00 9. "RTA,Read transfer active" "0: No valid data,1: Transferring data"
|
|
newline
|
|
bitfld.long 0x00 8. "WTA,Write transfer active" "0: No valid data,1: Transferring data"
|
|
newline
|
|
bitfld.long 0x00 7. "SDOFF,SD clock gated off internally" "0: SD clock is active,1: SD clock is gated off"
|
|
newline
|
|
bitfld.long 0x00 6. "PEROFF,IPG_PERCLK gated off internally" "0: IPG_PERCLK is active,1: IPG_PERCLK is gated off"
|
|
newline
|
|
bitfld.long 0x00 5. "HCKOFF,HCLK gated off internally" "0: HCLK is active,1: HCLK is gated off"
|
|
newline
|
|
bitfld.long 0x00 4. "IPGOFF,Peripheral clock gated off internally" "0: Peripheral clock is active,1: Peripheral clock is gated off"
|
|
newline
|
|
bitfld.long 0x00 3. "SDSTB,SD clock stable" "0: Clock is changing frequency and not stable,1: Clock is stable"
|
|
newline
|
|
bitfld.long 0x00 2. "DLA,Data line active" "0: DATA line inactive,1: DATA line active"
|
|
newline
|
|
bitfld.long 0x00 1. "CDIHB,Command inhibit (DATA)" "0: Can issue command that uses the DATA line,1: Cannot issue command that uses the DATA line"
|
|
newline
|
|
bitfld.long 0x00 0. "CIHB,Command inhibit (CMD)" "0: Can issue command using only CMD line,1: Cannot issue command"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PROT_CTRL,Protocol Control"
|
|
bitfld.long 0x00 30. "NON_EXACT_BLK_RD,Non-exact block" "0: The block read is exact block,1: The block read is non-exact block"
|
|
newline
|
|
bitfld.long 0x00 26. "WECRM,Wakeup event enable on SD card removal" "0: Disables wakeup event enable on SD card removal,1: Enables wakeup event enable on SD card removal"
|
|
newline
|
|
bitfld.long 0x00 25. "WECINS,Wakeup event enable on SD card insertion" "0: Disable wakeup event enable on SD card..,1: Enable wakeup event enable on SD card insertion"
|
|
newline
|
|
bitfld.long 0x00 24. "WECINT,Wakeup event enable on card interrupt" "0: Disables wakeup event enable on card interrupt,1: Enables wakeup event enable on card interrupt"
|
|
newline
|
|
bitfld.long 0x00 20. "RD_DONE_NO_8CLK,Read performed number 8 clock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "IABG,Interrupt at block gap" "0: Disables interrupt at block gap,1: Enables interrupt at block gap"
|
|
newline
|
|
bitfld.long 0x00 18. "RWCTL,Read wait control" "0: Disables read wait control and stop SD clock..,1: Enables read wait control and assert read.."
|
|
newline
|
|
bitfld.long 0x00 17. "CREQ,Continue request" "0: No effect,1: Restart"
|
|
newline
|
|
bitfld.long 0x00 16. "SABGREQ,Stop at block gap request" "0: SABGREQ_0,1: SABGREQ_1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "DMASEL,DMA select" "0: No DMA or simple DMA is selected,1: ADMA1 is selected,2: ADMA2 is selected,?..."
|
|
newline
|
|
bitfld.long 0x00 7. "CDSS,Card detect signal selection" "0: Card detection level is selected (for normal..,1: Card detection test level is selected (for.."
|
|
newline
|
|
bitfld.long 0x00 6. "CDTL,Card detect test level" "0: Card detect test level is 0 no card inserted,1: Card detect test level is 1 card inserted"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "EMODE,Endian mode" "0: Big endian mode,1: Half word big endian mode,2: Little endian mode,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "D3CD,DATA3 as card detection pin" "0: DATA3 does not monitor card insertion,1: DATA3 as card detection pin"
|
|
newline
|
|
bitfld.long 0x00 1.--2. "DTW,Data transfer width" "0: 1-bit mode,1: 4-bit mode,2: 8-bit mode,?..."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SYS_CTRL,System Control"
|
|
bitfld.long 0x00 28. "RSTT,Reset tuning" "0,1"
|
|
newline
|
|
bitfld.long 0x00 27. "INITA,Initialization active" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "RSTD,Software reset for data line" "0: No reset,1: RSTD_1"
|
|
newline
|
|
bitfld.long 0x00 25. "RSTC,Software reset for CMD line" "0: No reset,1: RSTC_1"
|
|
newline
|
|
bitfld.long 0x00 24. "RSTA,Software reset for all" "0: No reset,1: RSTA_1"
|
|
newline
|
|
bitfld.long 0x00 23. "IPP_RST_N,Hardware reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "DTOCV,Data timeout counter value" "0: SDCLK x 2 14,1: SDCLK x 2 15,2: SDCLK x 2 16,3: SDCLK x 2 17,4: SDCLK x 2 18,5: SDCLK x 2 19,6: SDCLK x 2 20,7: SDCLK x 2 21,8: SDCLK x 2 22,9: SDCLK x 2 23,10: SDCLK x 2 24,11: SDCLK x 2 25,12: SDCLK x 2 26,13: SDCLK x 2 27,14: SDCLK x 2 28,15: SDCLK x 2 29"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "SDCLKFS,SDCLK frequency select"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DVS,Divisor" "0: Divide-by-1,1: Divide-by-2,?,?,?,?,?,?,?,?,?,?,?,?,14: Divide-by-15,15: Divide-by-16"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "INT_STATUS,Interrupt Status"
|
|
eventfld.long 0x00 28. "DMAE,DMA error" "0: No error,1: DMAE_1"
|
|
newline
|
|
eventfld.long 0x00 26. "TNE,Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0,1"
|
|
newline
|
|
eventfld.long 0x00 24. "AC12E,Auto CMD12 error" "0: No error,1: AC12E_1"
|
|
newline
|
|
eventfld.long 0x00 22. "DEBE,Data end bit error" "0: No error,1: DEBE_1"
|
|
newline
|
|
eventfld.long 0x00 21. "DCE,Data CRC error" "0: No error,1: DCE_1"
|
|
newline
|
|
eventfld.long 0x00 20. "DTOE,Data timeout error" "0: No error,1: Time out"
|
|
newline
|
|
eventfld.long 0x00 19. "CIE,Command index error" "0: No error,1: CIE_1"
|
|
newline
|
|
eventfld.long 0x00 18. "CEBE,Command end bit error" "0: No error,1: End bit error generated"
|
|
newline
|
|
eventfld.long 0x00 17. "CCE,Command CRC error" "0: No error,1: CRC error generated"
|
|
newline
|
|
eventfld.long 0x00 16. "CTOE,Command timeout error" "0: No error,1: Time out"
|
|
newline
|
|
eventfld.long 0x00 14. "CQI,Command queuing interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 13. "TP,Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0,1"
|
|
newline
|
|
eventfld.long 0x00 12. "RTE,Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Re-tuning is not required,1: Re-tuning should be performed"
|
|
newline
|
|
eventfld.long 0x00 8. "CINT,Card interrupt" "0: No card interrupt,1: Generate card interrupt"
|
|
newline
|
|
eventfld.long 0x00 7. "CRM,Card removal" "0: Card state unstable or inserted,1: Card removed"
|
|
newline
|
|
eventfld.long 0x00 6. "CINS,Card insertion" "0: Card state unstable or removed,1: Card inserted"
|
|
newline
|
|
eventfld.long 0x00 5. "BRR,Buffer read ready" "0: Not ready to read buffer,1: Ready to read buffer"
|
|
newline
|
|
eventfld.long 0x00 4. "BWR,Buffer write ready" "0: Not ready to write buffer,1: Ready to write buffer"
|
|
newline
|
|
eventfld.long 0x00 3. "DINT,DMA interrupt" "0: No DMA interrupt,1: DMA interrupt is generated"
|
|
newline
|
|
eventfld.long 0x00 2. "BGE,Block gap event" "0: No block gap event,1: Transaction stopped at block gap"
|
|
newline
|
|
eventfld.long 0x00 1. "TC,Transfer complete" "0: Transfer does not complete,1: Transfer complete"
|
|
newline
|
|
eventfld.long 0x00 0. "CC,Command complete" "0: Command not complete,1: Command complete"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "INT_STATUS_EN,Interrupt Status Enable"
|
|
bitfld.long 0x00 28. "DMAESEN,DMA error status enable" "0: DMAESEN_0,1: DMAESEN_1"
|
|
newline
|
|
bitfld.long 0x00 26. "TNESEN,Tuning error status enable" "0: TNESEN_0,1: TNESEN_1"
|
|
newline
|
|
bitfld.long 0x00 24. "AC12ESEN,Auto CMD12 error status enable" "0: AC12ESEN_0,1: AC12ESEN_1"
|
|
newline
|
|
bitfld.long 0x00 22. "DEBESEN,Data end bit error status enable" "0: DEBESEN_0,1: DEBESEN_1"
|
|
newline
|
|
bitfld.long 0x00 21. "DCESEN,Data CRC error status enable" "0: DCESEN_0,1: DCESEN_1"
|
|
newline
|
|
bitfld.long 0x00 20. "DTOESEN,Data timeout error status enable" "0: DTOESEN_0,1: DTOESEN_1"
|
|
newline
|
|
bitfld.long 0x00 19. "CIESEN,Command index error status enable" "0: CIESEN_0,1: CIESEN_1"
|
|
newline
|
|
bitfld.long 0x00 18. "CEBESEN,Command end bit error status enable" "0: CEBESEN_0,1: CEBESEN_1"
|
|
newline
|
|
bitfld.long 0x00 17. "CCESEN,Command CRC error status enable" "0: CCESEN_0,1: CCESEN_1"
|
|
newline
|
|
bitfld.long 0x00 16. "CTOESEN,Command timeout error status enable" "0: CTOESEN_0,1: CTOESEN_1"
|
|
newline
|
|
bitfld.long 0x00 14. "CQISEN,Command queuing status enable" "0: CQISEN_0,1: CQISEN_1"
|
|
newline
|
|
bitfld.long 0x00 13. "TPSEN,Tuning pass status enable" "0: TPSEN_0,1: TPSEN_1"
|
|
newline
|
|
bitfld.long 0x00 12. "RTESEN,Re-tuning event status enable" "0: RTESEN_0,1: RTESEN_1"
|
|
newline
|
|
bitfld.long 0x00 8. "CINTSEN,Card interrupt status enable" "0: CINTSEN_0,1: CINTSEN_1"
|
|
newline
|
|
bitfld.long 0x00 7. "CRMSEN,Card removal status enable" "0: CRMSEN_0,1: CRMSEN_1"
|
|
newline
|
|
bitfld.long 0x00 6. "CINSSEN,Card insertion status enable" "0: CINSSEN_0,1: CINSSEN_1"
|
|
newline
|
|
bitfld.long 0x00 5. "BRRSEN,Buffer read ready status enable" "0: BRRSEN_0,1: BRRSEN_1"
|
|
newline
|
|
bitfld.long 0x00 4. "BWRSEN,Buffer write ready status enable" "0: BWRSEN_0,1: BWRSEN_1"
|
|
newline
|
|
bitfld.long 0x00 3. "DINTSEN,DMA interrupt status enable" "0: DINTSEN_0,1: DINTSEN_1"
|
|
newline
|
|
bitfld.long 0x00 2. "BGESEN,Block gap event status enable" "0: BGESEN_0,1: BGESEN_1"
|
|
newline
|
|
bitfld.long 0x00 1. "TCSEN,Transfer complete status enable" "0: TCSEN_0,1: TCSEN_1"
|
|
newline
|
|
bitfld.long 0x00 0. "CCSEN,Command complete status enable" "0: CCSEN_0,1: CCSEN_1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "INT_SIGNAL_EN,Interrupt Signal Enable"
|
|
bitfld.long 0x00 28. "DMAEIEN,DMA error interrupt enable" "0: DMAEIEN_0,1: DMAEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 26. "TNEIEN,Tuning error interrupt enable" "0: TNEIEN_0,1: TNEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 24. "AC12EIEN,Auto CMD12 error interrupt enable" "0: AC12EIEN_0,1: AC12EIEN_1"
|
|
newline
|
|
bitfld.long 0x00 22. "DEBEIEN,Data end bit error interrupt enable" "0: DEBEIEN_0,1: DEBEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 21. "DCEIEN,Data CRC error interrupt enable" "0: DCEIEN_0,1: DCEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 20. "DTOEIEN,Data timeout error interrupt enable" "0: DTOEIEN_0,1: DTOEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 19. "CIEIEN,Command index error interrupt enable" "0: CIEIEN_0,1: CIEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 18. "CEBEIEN,Command end bit error interrupt enable" "0: CEBEIEN_0,1: CEBEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 17. "CCEIEN,Command CRC error interrupt enable" "0: CCEIEN_0,1: CCEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 16. "CTOEIEN,Command timeout error interrupt enable" "0: CTOEIEN_0,1: CTOEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 14. "CQIIEN,Command queuing signal enable" "0: CQIIEN_0,1: CQIIEN_1"
|
|
newline
|
|
bitfld.long 0x00 13. "TPIEN,Tuning pass interrupt enable" "0: TPIEN_0,1: TPIEN_1"
|
|
newline
|
|
bitfld.long 0x00 12. "RTEIEN,Re-tuning event interrupt enable" "0: RTEIEN_0,1: RTEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 8. "CINTIEN,Card interrupt enable" "0: CINTIEN_0,1: CINTIEN_1"
|
|
newline
|
|
bitfld.long 0x00 7. "CRMIEN,Card removal interrupt enable" "0: CRMIEN_0,1: CRMIEN_1"
|
|
newline
|
|
bitfld.long 0x00 6. "CINSIEN,Card insertion interrupt enable" "0: CINSIEN_0,1: CINSIEN_1"
|
|
newline
|
|
bitfld.long 0x00 5. "BRRIEN,Buffer read ready interrupt enable" "0: BRRIEN_0,1: BRRIEN_1"
|
|
newline
|
|
bitfld.long 0x00 4. "BWRIEN,Buffer write ready interrupt enable" "0: BWRIEN_0,1: BWRIEN_1"
|
|
newline
|
|
bitfld.long 0x00 3. "DINTIEN,DMA interrupt enable" "0: DINTIEN_0,1: DINTIEN_1"
|
|
newline
|
|
bitfld.long 0x00 2. "BGEIEN,Block gap event interrupt enable" "0: BGEIEN_0,1: BGEIEN_1"
|
|
newline
|
|
bitfld.long 0x00 1. "TCIEN,Transfer complete interrupt enable" "0: TCIEN_0,1: TCIEN_1"
|
|
newline
|
|
bitfld.long 0x00 0. "CCIEN,Command complete interrupt enable" "0: CCIEN_0,1: CCIEN_1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "AUTOCMD12_ERR_STATUS,Auto CMD12 Error Status"
|
|
bitfld.long 0x00 23. "SMP_CLK_SEL,Sample clock select" "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data"
|
|
newline
|
|
bitfld.long 0x00 22. "EXECUTE_TUNING,Execute tuning" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "CNIBAC12E,Command not issued by Auto CMD12 error" "0: CNIBAC12E_0,1: CNIBAC12E_1"
|
|
newline
|
|
rbitfld.long 0x00 4. "AC12IE,Auto CMD12 / 23 index error" "0: AC12IE_0,1: Error the CMD index in response is not CMD12/23"
|
|
newline
|
|
rbitfld.long 0x00 3. "AC12CE,Auto CMD12 / 23 CRC error" "0: No CRC error,1: CRC error met in Auto CMD12/23 response"
|
|
newline
|
|
rbitfld.long 0x00 2. "AC12EBE,Auto CMD12 / 23 end bit error" "0: AC12EBE_0,1: End bit error generated"
|
|
newline
|
|
rbitfld.long 0x00 1. "AC12TOE,Auto CMD12 / 23 timeout error" "0: AC12TOE_0,1: AC12TOE_1"
|
|
newline
|
|
rbitfld.long 0x00 0. "AC12NE,Auto CMD12 not executed" "0: AC12NE_0,1: Not executed"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "HOST_CTRL_CAP,Host Controller Capabilities"
|
|
rbitfld.long 0x00 26. "VS18,Voltage support 1.8 V" "0: 1.8 V not supported,1: 1.8 V supported"
|
|
newline
|
|
rbitfld.long 0x00 25. "VS30,Voltage support 3.0 V" "0: 3.0 V not supported,1: 3.0 V supported"
|
|
newline
|
|
rbitfld.long 0x00 24. "VS33,Voltage support 3.3 V" "0: 3.3 V not supported,1: 3.3 V supported"
|
|
newline
|
|
rbitfld.long 0x00 23. "SRS,Suspend / resume support" "0: Not supported,1: Supported"
|
|
newline
|
|
rbitfld.long 0x00 22. "DMAS,DMA support" "0: DMA not supported,1: DMA supported"
|
|
newline
|
|
rbitfld.long 0x00 21. "HSS,High speed support" "0: High speed not supported,1: High speed supported"
|
|
newline
|
|
rbitfld.long 0x00 20. "ADMAS,ADMA support" "0: Advanced DMA not supported,1: Advanced DMA supported"
|
|
newline
|
|
rbitfld.long 0x00 16.--18. "MBL,Max block length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,3: 4096 bytes,?..."
|
|
newline
|
|
rbitfld.long 0x00 14.--15. "RETUNING_MODE,Retuning Mode" "0: RETUNING_MODE_0,1: RETUNING_MODE_1,2: RETUNING_MODE_2,?..."
|
|
newline
|
|
bitfld.long 0x00 13. "USE_TUNING_SDR50,Use Tuning for SDR50" "0: SDR does not require tuning,1: SDR50 requires tuning"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "TIME_COUNT_RETUNING,Time counter for retuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 2. "DDR50_SUPPORT,DDR50 support" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1. "SDR104_SUPPORT,SDR104 support" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0. "SDR50_SUPPORT,SDR50 support" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "WTMK_LVL,Watermark Level"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WR_WML,Write watermark level"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "RD_WML,Read watermark level"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MIX_CTRL,Mixer Control"
|
|
bitfld.long 0x00 27. "EN_HS400_MODE,Enable enhance HS400 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "HS400_MODE,Enable HS400 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "FBCLK_SEL,Feedback clock source selection (Only used for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Feedback clock comes from the loopback CLK,1: Feedback clock comes from the ipp_card_clk_out"
|
|
newline
|
|
bitfld.long 0x00 24. "AUTO_TUNE_EN,Auto tuning enable (Only used for SD3.0 SDR104 mode and and EMMC HS200 mode)" "0: Disable auto tuning,1: Enable auto tuning"
|
|
newline
|
|
bitfld.long 0x00 23. "SMP_CLK_SEL,Clock selection" "0: Fixed clock is used to sample data / cmd,1: Tuned clock is used to sample data / cmd"
|
|
newline
|
|
bitfld.long 0x00 22. "EXE_TUNE,Execute tuning: (Only used for SD3.0 SDR104 mode and EMMC HS200 mode)" "0: Not tuned or tuning completed,1: Execute tuning"
|
|
newline
|
|
bitfld.long 0x00 7. "AC23EN,Auto CMD23 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "NIBBLE_POS,Nibble position indication" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "MSBSEL,Multi / Single block select" "0: Single block,1: Multiple blocks"
|
|
newline
|
|
bitfld.long 0x00 4. "DTDSEL,Data transfer direction select" "0: Write (Host to card),1: Read (Card to host)"
|
|
newline
|
|
bitfld.long 0x00 3. "DDR_EN,Dual data rate mode selection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "AC12EN,Auto CMD12 enable" "0: AC12EN_0,1: AC12EN_1"
|
|
newline
|
|
bitfld.long 0x00 1. "BCEN,Block count enable" "0: Disable,1: BCEN_1"
|
|
newline
|
|
bitfld.long 0x00 0. "DMAEN,DMA enable" "0: DMAEN_0,1: DMAEN_1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FORCE_EVENT,Force Event"
|
|
bitfld.long 0x00 31. "FEVTCINT,Force event card interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "FEVTDMAE,Force event DMA error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "FEVTTNE,Force tuning error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "FEVTAC12E,Force event Auto Command 12 error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "FEVTDEBE,Force event data end bit error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "FEVTDCE,Force event data CRC error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "FEVTDTOE,Force event data time out error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "FEVTCIE,Force event command index error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "FEVTCEBE,Force event command end bit error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "FEVTCCE,Force event command CRC error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "FEVTCTOE,Force event command time out error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "FEVTCNIBAC12E,Force event command not executed by Auto Command 12 error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "FEVTAC12IE,Force event Auto Command 12 index error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "FEVTAC12EBE,Force event Auto Command 12 end bit error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "FEVTAC12CE,Force event auto command 12 CRC error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "FEVTAC12TOE,Force event auto command 12 time out error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "FEVTAC12NE,Force event auto command 12 not executed" "0,1"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADMA_ERR_STATUS,ADMA Error Status"
|
|
bitfld.long 0x00 3. "ADMADCE,ADMA descriptor error" "0: ADMADCE_0,1: ADMADCE_1"
|
|
newline
|
|
bitfld.long 0x00 2. "ADMALME,ADMA length mismatch error" "0: ADMALME_0,1: ADMALME_1"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "ADMAES,ADMA error state (when ADMA error is occurred)" "0,1,2,3"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADMA_SYS_ADDR,ADMA System Address"
|
|
hexmask.long 0x00 2.--31. 1. "ADS_ADDR,ADMA system address"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DLL_CTRL,DLL (Delay Line) Control"
|
|
bitfld.long 0x00 28.--31. "DLL_CTRL_REF_UPDATE_INT,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 20.--27. 1. "DLL_CTRL_SLV_UPDATE_INT,Slave delay line update interval"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "DLL_CTRL_SLV_DLY_TARGET1,DLL slave delay target1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "DLL_CTRL_SLV_OVERRIDE_VAL,DLL slave override val"
|
|
newline
|
|
bitfld.long 0x00 8. "DLL_CTRL_SLV_OVERRIDE,DLL slave override" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "DLL_CTRL_GATE_UPDATE,DLL gate update" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--6. "DLL_CTRL_SLV_DLY_TARGET0,DLL slave delay target0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2. "DLL_CTRL_SLV_FORCE_UPD,DLL slave delay line" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "DLL_CTRL_RESET,DLL reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DLL_CTRL_ENABLE,DLL and delay chain" "0,1"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "DLL_STATUS,DLL Status"
|
|
hexmask.long.byte 0x00 9.--15. 1. "DLL_STS_REF_SEL,Reference delay line select taps"
|
|
newline
|
|
hexmask.long.byte 0x00 2.--8. 1. "DLL_STS_SLV_SEL,Slave delay line select status"
|
|
newline
|
|
bitfld.long 0x00 1. "DLL_STS_REF_LOCK,Reference DLL lock status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DLL_STS_SLV_LOCK,Slave delay-line lock status" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CLK_TUNE_CTRL_STATUS,CLK Tuning Control and Status"
|
|
rbitfld.long 0x00 31. "PRE_ERR,PRE error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 24.--30. 1. "TAP_SEL_PRE,TAP_SEL_PRE"
|
|
newline
|
|
rbitfld.long 0x00 20.--23. "TAP_SEL_OUT,Delay cells added on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 16.--19. "TAP_SEL_POST,Delay cells added on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 15. "NXT_ERR,NXT error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "DLY_CELL_SET_PRE,delay cells on the feedback clock between the feedback clock and CLK_PRE"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DLY_CELL_SET_OUT,Delay cells on the feedback clock between CLK_PRE and CLK_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DLY_CELL_SET_POST,Delay cells on the feedback clock between CLK_OUT and CLK_POST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "STROBE_DLL_CTRL,Strobe DLL control"
|
|
bitfld.long 0x00 28.--31. "STROBE_DLL_CTRL_REF_UPDATE_INT,Strobe DLL control reference update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 20.--27. 1. "STROBE_DLL_CTRL_SLV_UPDATE_INT,Strobe DLL control slave update interval"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "STROBE_DLL_CTRL_SLV_OVERRIDE_VAL,Strobe DLL control slave Override value"
|
|
newline
|
|
bitfld.long 0x00 8. "STROBE_DLL_CTRL_SLV_OVERRIDE,Strobe DLL control slave override" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "STROBE_DLL_CTRL_GATE_UPDATE,Strobe DLL control gate update" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--6. "STROBE_DLL_CTRL_SLV_DLY_TARGET,Strobe DLL Control Slave Delay Target" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 2. "STROBE_DLL_CTRL_SLV_FORCE_UPD,Strobe DLL control slave force updated" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "STROBE_DLL_CTRL_RESET,Strobe DLL control reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "STROBE_DLL_CTRL_ENABLE,Strobe DLL control enable" "0,1"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "STROBE_DLL_STATUS,Strobe DLL status"
|
|
hexmask.long.byte 0x00 9.--15. 1. "STROBE_DLL_STS_REF_SEL,Strobe DLL status reference select"
|
|
newline
|
|
hexmask.long.byte 0x00 2.--8. 1. "STROBE_DLL_STS_SLV_SEL,Strobe DLL status slave select"
|
|
newline
|
|
bitfld.long 0x00 1. "STROBE_DLL_STS_REF_LOCK,Strobe DLL status reference lock" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "STROBE_DLL_STS_SLV_LOCK,Strobe DLL status slave lock" "0,1"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "VEND_SPEC,Vendor Specific Register"
|
|
bitfld.long 0x00 31. "CMD_BYTE_EN,Byte access" "0: CMD_BYTE_EN_0,1: CMD_BYTE_EN_1"
|
|
newline
|
|
bitfld.long 0x00 15. "CRC_CHK_DIS,CRC Check Disable" "0: Check CRC16 for every read data packet and..,1: Ignore CRC16 check for every read data packet.."
|
|
newline
|
|
bitfld.long 0x00 8. "FRC_SDCLK_ON,Force CLK" "0: CLK active or inactive is fully controlled by..,1: Force CLK active"
|
|
newline
|
|
bitfld.long 0x00 3. "AC12_WR_CHKBUSY_EN,Check busy enable" "0: Do not check busy after auto CMD12 for write..,1: Check busy after auto CMD12 for write data.."
|
|
newline
|
|
bitfld.long 0x00 2. "CONFLICT_CHK_EN,Conflict check enable" "0: Conflict check disable,1: Conflict check enable"
|
|
newline
|
|
bitfld.long 0x00 1. "VSELECT,Voltage selection" "0: Change the voltage to high voltage range..,1: Change the voltage to low voltage range.."
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "MMC_BOOT,MMC Boot"
|
|
hexmask.long.word 0x00 16.--31. 1. "BOOT_BLK_CNT,Stop At Block Gap value of automatic mode"
|
|
newline
|
|
bitfld.long 0x00 8. "DISABLE_TIME_OUT,Time out" "0: DISABLE_TIME_OUT_0,1: DISABLE_TIME_OUT_1"
|
|
newline
|
|
bitfld.long 0x00 7. "AUTO_SABG_EN,Auto stop at block gap" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "BOOT_EN,Boot enable" "0: Fast boot disable,1: Fast boot enable"
|
|
newline
|
|
bitfld.long 0x00 5. "BOOT_MODE,Boot mode" "0: BOOT_MODE_0,1: Alternative boot"
|
|
newline
|
|
bitfld.long 0x00 4. "BOOT_ACK,BOOT ACK" "0: BOOT_ACK_0,1: BOOT_ACK_1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DTOCV_ACK,DTOCV_ACK" "0: SDCLK x 2^32,1: SDCLK x 2^33,2: SDCLK x 2^18,3: SDCLK x 2^19,4: SDCLK x 2^20,5: SDCLK x 2^21,6: SDCLK x 2^22,7: SDCLK x 2^23,?,?,?,?,?,?,14: DTOCV_ACK_14,15: DTOCV_ACK_15"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "VEND_SPEC2,Vendor Specific 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "FBCLK_TAP_SEL,Enable extra delay on internal feedback clock"
|
|
newline
|
|
bitfld.long 0x00 15. "EN_32K_CLK,Enable 32khz clock for card detection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "ACMD23_ARGU2_EN,Argument2 register enable for ACMD23" "0: ACMD23_ARGU2_EN_0,1: Argument2 register enable for ACMD23 sharing.."
|
|
newline
|
|
bitfld.long 0x00 11. "HS400_RD_CLK_STOP_EN,HS400 read clock stop enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. "HS400_WR_CLK_STOP_EN,HS400 write clock stop enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "TUNING_CMD_EN,Tuning command enable" "0: Auto tuning circuit does not check the CMD line,1: Auto tuning circuit checks the CMD line"
|
|
newline
|
|
bitfld.long 0x00 5. "TUNING_1bit_EN,Tuning 1bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "TUNING_8bit_EN,Tuning 8bit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "CARD_INT_D3_TEST,Card interrupt detection test" "0: Check the card interrupt only when DATA3 is..,1: Check the card interrupt by ignoring the.."
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TUNING_CTRL,Tuning Control"
|
|
bitfld.long 0x00 24. "STD_TUNING_EN,Standard tuning circuit and procedure enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "TUNING_WINDOW,Data window" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "TUNING_STEP,TUNING_STEP" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TUNING_COUNTER,Tuning counter"
|
|
newline
|
|
bitfld.long 0x00 7. "DIS_CMD_CHK_FOR_STD_TUNING,Disable command check for standard tuning" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "TUNING_START_TAP,Tuning start"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CQVER,Command Queuing Version"
|
|
bitfld.long 0x00 8.--11. "MAJOR_VN,e MMC major version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "MINOR_VN,e MMC minor version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "VERSION_SUFFIX,e MMC version suffix" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CQCAP,Command Queuing Capabilities"
|
|
bitfld.long 0x00 12.--15. "ITCFMUL,Internal timer clock frequency multiplier" "?,1: ITCFMUL_1,2: ITCFMUL_2,3: ITCFMUL_3,4: ITCFMUL_4,5: ITCFMUL_5,?..."
|
|
newline
|
|
hexmask.long.word 0x00 0.--9. 1. "ITCFVAL,Internal timer clock frequency value"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CQCFG,Command Queuing Configuration"
|
|
bitfld.long 0x00 12. "DCMDE,Direct command (DCMD) enable" "0: Task descriptor in slot #31 is a Data..,1: Task descriptor in slot #31 is a DCMD Task.."
|
|
newline
|
|
bitfld.long 0x00 8. "TDS,Task descriptor size" "0: Task descriptor size is 64 bits,1: Task descriptor size is 128 bits"
|
|
newline
|
|
bitfld.long 0x00 0. "CQUE,Command queuing enable" "0,1"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "CQCTL,Command Queuing Control"
|
|
bitfld.long 0x00 8. "CLEAR,Clear all tasks" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "HALT,Halt" "0,1"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CQIS,Command Queuing Interrupt Status"
|
|
eventfld.long 0x00 3. "TCL,Task cleared" "0,1"
|
|
newline
|
|
eventfld.long 0x00 2. "RED,Response error detected interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 1. "TCC,Task complete interrupt" "0,1"
|
|
newline
|
|
eventfld.long 0x00 0. "HAC,Halt complete interrupt" "0,1"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CQISTE,Command Queuing Interrupt Status Enable"
|
|
bitfld.long 0x00 3. "TCL_STE,Task cleared status enable" "0: CQIS[TCL] is disabled,1: CQIS[TCL] is set when its interrupt condition.."
|
|
newline
|
|
bitfld.long 0x00 2. "RED_STE,Response error detected status enable" "0: CQIS[RED] is disabled,1: CQIS[RED] is set when its interrupt condition.."
|
|
newline
|
|
bitfld.long 0x00 1. "TCC_STE,Task complete status enable" "0: CQIS[TCC] is disabled,1: CQIS[TCC] is set when its interrupt condition.."
|
|
newline
|
|
bitfld.long 0x00 0. "HAC_STE,Halt complete status enable" "0: CQIS[HAC] is disabled,1: CQIS[HAC] is set when its interrupt condition.."
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CQISGE,Command Queuing Interrupt Signal Enable"
|
|
bitfld.long 0x00 3. "TCL_SGE,Task cleared signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "RED_SGE,Response error detected signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "TCC_SGE,Task complete signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "HAC_SGE,Halt complete signal enable" "0,1"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CQIC,Command Queuing Interrupt Coalescing"
|
|
bitfld.long 0x00 31. "ICENDIS,Interrupt coalescing enable/disable" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 20. "ICSB,Interrupt coalescing status" "0: No task completions have occurred since last..,1: At least one task completion has been counted.."
|
|
newline
|
|
bitfld.long 0x00 16. "ICCTR,Counter and timer reset" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "ICCTHWEN,Interrupt coalescing counter threshold write enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "ICCTH,Interrupt coalescing counter threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 7. "ICTOVALWEN,Interrupt coalescing timeout value write enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "ICTOVAL,Interrupt coalescing timeout value"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CQTDLBA,Command Queuing Task Descriptor List Base Address"
|
|
hexmask.long 0x00 0.--31. 1. "TDLBA,Task descriptor list base address"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CQTDLBAU,Command Queuing Task Descriptor List Base Address Upper 32 Bits"
|
|
hexmask.long 0x00 0.--31. 1. "TDLBAU,Task descriptor list base address"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CQTDBR,Command Queuing Task Doorbell"
|
|
hexmask.long 0x00 0.--31. 1. "TDBR,Task doorbell"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CQTCN,Command Queuing Task Completion Notification"
|
|
hexmask.long 0x00 0.--31. 1. "TCN,Task complete notification"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "CQDQS,Command Queuing Device Queue Status"
|
|
hexmask.long 0x00 0.--31. 1. "DQS,Device queue status"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "CQDPT,Command Queuing Device Pending Tasks"
|
|
hexmask.long 0x00 0.--31. 1. "DPT,Device pending tasks"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CQTCLR,Command Queuing Task Clear"
|
|
hexmask.long 0x00 0.--31. 1. "TCLR,Task clear"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CQSSC1,Command Queuing Send Status Configuration 1"
|
|
bitfld.long 0x00 16.--19. "CBC,Send status command block counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "CIT,Send status command idle timer"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CQSSC2,Command Queuing Send Status Configuration 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "SSC2,Send queue status RCA"
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "CQCRDCT,Command Queuing Command Response for Direct-Command Task"
|
|
hexmask.long 0x00 0.--31. 1. "CRDCT,Direct command last response"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CQRMEM,Command Queuing Response Mode Error Mask"
|
|
hexmask.long 0x00 0.--31. 1. "RMEM,Response mode error mask"
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "CQTERRI,Command Queuing Task Error Information"
|
|
bitfld.long 0x00 31. "DTEFV,Data transfer error fields valid" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24.--28. "DTETID,Data transfer error task ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "DTECI,Data transfer error command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 15. "RMEFV,Response mode error fields valid" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "RMETID,Response mode error task ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "RMECI,Response mode error command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "CQCRI,Command Queuing Command Response Index"
|
|
bitfld.long 0x00 0.--5. "LCMDRI,Last command response index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "CQCRA,Command Queuing Command Response Argument"
|
|
hexmask.long 0x00 0.--31. 1. "LCMDRA,Last command response argument"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "WDOG (Watchdog Timer Unit)"
|
|
tree "CM4__WDOG"
|
|
sif cpuis("IMX8D?L-CM4")
|
|
base ad:0x41420000
|
|
else
|
|
base ad:0x37420000
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,Watchdog Control and Status Register"
|
|
bitfld.long 0x00 15. "WIN,Watchdog Window" "0: Window mode disabled,1: Window mode enabled"
|
|
eventfld.long 0x00 14. "FLG,Watchdog Interrupt Flag" "0: No interrupt occurred,1: An interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 13. "CMD32EN,Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words" "0: Disables support for 32-bit refresh/unlock..,1: Enables support for 32-bit refresh/unlock.."
|
|
bitfld.long 0x00 12. "PRES,Watchdog prescaler" "0: 256 prescaler disabled,1: 256 prescaler enabled"
|
|
newline
|
|
rbitfld.long 0x00 11. "ULK,Unlock status" "0: WDOG is locked,1: WDOG is unlocked"
|
|
rbitfld.long 0x00 10. "RCS,Reconfiguration Success" "0: Reconfiguring WDOG,1: Reconfiguration is successful"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CLK,Watchdog Clock" "0,1,2,3"
|
|
bitfld.long 0x00 7. "EN,Watchdog Enable" "0: Watchdog disabled,1: Watchdog enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "INT,Watchdog Interrupt" "0: Watchdog interrupts are disabled,1: Watchdog interrupts are enabled"
|
|
bitfld.long 0x00 5. "UPDATE,Allow updates" "0: Updates not allowed,1: Updates allowed"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "TST,Watchdog Test" "0: Watchdog test mode disabled,1: Watchdog user mode enabled,2: Watchdog test mode enabled only the low byte..,3: Watchdog test mode enabled only the high byte.."
|
|
bitfld.long 0x00 2. "DBG,Debug Enable" "0: Watchdog disabled in chip debug mode,1: Watchdog enabled in chip debug mode"
|
|
newline
|
|
bitfld.long 0x00 1. "WAIT,Wait Enable" "0: Watchdog disabled in chip wait mode,1: Watchdog enabled in chip wait mode"
|
|
bitfld.long 0x00 0. "STOP,Stop Enable" "0: Watchdog disabled in chip stop mode,1: Watchdog enabled in chip stop mode"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Watchdog Counter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CNTHIGH,High byte of the Watchdog Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CNTLOW,Low byte of the Watchdog Counter"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TOVAL,Watchdog Timeout Value Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOVALHIGH,High byte of the timeout value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TOVALLOW,Low byte of the timeout value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WIN,Watchdog Window Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "WINHIGH,High byte of Watchdog Window"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WINLOW,Low byte of Watchdog Window"
|
|
tree.end
|
|
tree "SCU__WDOG"
|
|
base ad:0x33420000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,Watchdog Control and Status Register"
|
|
bitfld.long 0x00 15. "WIN,Watchdog Window" "0: Window mode disabled,1: Window mode enabled"
|
|
eventfld.long 0x00 14. "FLG,Watchdog Interrupt Flag" "0: No interrupt occurred,1: An interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 13. "CMD32EN,Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words" "0: Disables support for 32-bit refresh/unlock..,1: Enables support for 32-bit refresh/unlock.."
|
|
bitfld.long 0x00 12. "PRES,Watchdog prescaler" "0: 256 prescaler disabled,1: 256 prescaler enabled"
|
|
newline
|
|
rbitfld.long 0x00 11. "ULK,Unlock status" "0: WDOG is locked,1: WDOG is unlocked"
|
|
rbitfld.long 0x00 10. "RCS,Reconfiguration Success" "0: Reconfiguring WDOG,1: Reconfiguration is successful"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CLK,Watchdog Clock" "0,1,2,3"
|
|
bitfld.long 0x00 7. "EN,Watchdog Enable" "0: Watchdog disabled,1: Watchdog enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "INT,Watchdog Interrupt" "0: Watchdog interrupts are disabled,1: Watchdog interrupts are enabled"
|
|
bitfld.long 0x00 5. "UPDATE,Allow updates" "0: Updates not allowed,1: Updates allowed"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "TST,Watchdog Test" "0: Watchdog test mode disabled,1: Watchdog user mode enabled,2: Watchdog test mode enabled only the low byte..,3: Watchdog test mode enabled only the high byte.."
|
|
bitfld.long 0x00 2. "DBG,Debug Enable" "0: Watchdog disabled in chip debug mode,1: Watchdog enabled in chip debug mode"
|
|
newline
|
|
bitfld.long 0x00 1. "WAIT,Wait Enable" "0: Watchdog disabled in chip wait mode,1: Watchdog enabled in chip wait mode"
|
|
bitfld.long 0x00 0. "STOP,Stop Enable" "0: Watchdog disabled in chip stop mode,1: Watchdog enabled in chip stop mode"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Watchdog Counter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CNTHIGH,High byte of the Watchdog Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CNTLOW,Low byte of the Watchdog Counter"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TOVAL,Watchdog Timeout Value Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOVALHIGH,High byte of the timeout value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TOVALLOW,Low byte of the timeout value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WIN,Watchdog Window Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "WINHIGH,High byte of Watchdog Window"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WINLOW,Low byte of Watchdog Window"
|
|
tree.end
|
|
tree.end
|
|
autoindent.off
|
|
newline
|