15843 lines
1.1 MiB
15843 lines
1.1 MiB
; --------------------------------------------------------------------------------
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; @Title: PSOCC3 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2025-06-26 NEJ
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; @Manufacturer: INFINEON - Infineon Technologies AG
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; @Doc: Generated (TRACE32, build: 180251.), based on:
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; psc3.svd (CAT1B_DFP 1.1.0, 2025-03-13)
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; @Core: Cortex-M33F
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; @Chip: PSC3P2*, PSC3M3*, PSC3P5*, PSC3M5*
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; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company)\n
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; or an affiliate of Cypress Semiconductor Corporation.\n
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; \n
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; SPDX-License-Identifier: Apache-2.0\n
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; \n
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; Licensed under the Apache License, Version 2.0 (the "License");\n
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; you may not use this file except in compliance with the License.\n
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; You may obtain a copy of the License at\n
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; \n
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; http://www.apache.org/licenses/LICENSE-2.0\n
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; \n
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; Unless required by applicable law or agreed to in writing, software\n
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; distributed under the License is distributed on an "AS IS" BASIS,\n
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; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
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; See the License for the specific language governing permissions and\n
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; limitations under the License.
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; --------------------------------------------------------------------------------
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; $Id: perpsocc3.per 19681 2025-07-02 10:15:20Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M33F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
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bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
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bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
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textline " "
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bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes"
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group.long 0x0C++0x0F
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line.long 0x00 "CPPWR,Coprocessor Power Control Register"
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bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only"
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textline " "
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bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
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textline " "
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bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only"
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textline " "
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bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
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textline " "
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bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only"
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textline " "
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bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
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line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x0C "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main Extension"
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newline
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xD21=Cortex-M33"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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textline " "
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bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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textline " "
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
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textline " "
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bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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line.long 0x14 "SHPR1,System Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
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bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
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bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
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bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active"
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textline " "
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bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
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bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "UFSR,Usage Fault Status Register"
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eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error"
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textline " "
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eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
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textline " "
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eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x03
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line.long 0x00 "HFSR,HardFault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
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if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
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group.long 0xD8C++0x03
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line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
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bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
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bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
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bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
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bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
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bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
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bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
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bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
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else
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hgroup.long 0xD8C++0x03
|
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hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
|
|
endif
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wgroup.long 0xF00++0x03
|
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line.long 0x00 "STIR,Software Triggered Interrupt Register"
|
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended"
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tree "Memory System"
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width 10.
|
|
rgroup.long 0xD78++0x03
|
|
line.long 0x00 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
|
|
bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
|
|
rgroup.long 0xD7C++0x03
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
|
|
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0xD7C++0x03
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
|
|
endif
|
|
rgroup.long 0xD80++0x03
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
|
|
bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
|
|
group.long 0xD84++0x03
|
|
line.long 0x00 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
|
|
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
|
|
wgroup.long 0xF50++0x03
|
|
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
|
|
wgroup.long 0xF58++0x23
|
|
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
|
|
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
|
|
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
|
|
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
|
|
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
|
|
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
|
|
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
|
|
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
|
|
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
width 10.
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
|
|
rgroup.long 0xD4C++0x03
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
|
|
rgroup.long 0xD54++0x03
|
|
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD5C++0x03
|
|
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
|
|
bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x03
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
rgroup.long 0xD64++0x03
|
|
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
|
|
rgroup.long 0xD68++0x03
|
|
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
|
|
bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
|
|
rgroup.long 0xD6C++0x03
|
|
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
|
|
rgroup.long 0xD70++0x03
|
|
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
|
|
bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
|
|
bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 11.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DPIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DPIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DPIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DPIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DCIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DCIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DCIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit (SAU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree.close "SAU regions"
|
|
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x03 "Region 0"
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x03 "Region 1"
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x03 "Region 2"
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x03 "Region 3"
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x03 "Region 4"
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x03 "Region 5"
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x03 "Region 6"
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x03 "Region 7"
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
tree.end
|
|
group.long 0xDE4++0x03
|
|
line.long 0x00 "SFSR,Secure Fault Status Register"
|
|
bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred"
|
|
group.long 0xDE8++0x03
|
|
line.long 0x00 "SFAR,Secure Fault Address Register"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
|
|
width 24.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x120++0x03
|
|
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x124++0x03
|
|
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x134++0x03
|
|
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x138++0x03
|
|
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x13C++0x03
|
|
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
width 24.
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x224++0x03
|
|
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x228++0x03
|
|
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x22C++0x03
|
|
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x234++0x03
|
|
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x238++0x03
|
|
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x23C++0x03
|
|
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
width 11.
|
|
tree "Interrupt Active Bit Registers"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
rgroup.long 0x320++0x03
|
|
line.long 0x00 "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
rgroup.long 0x324++0x03
|
|
line.long 0x00 "ACTIVE9,Active Bit Register 9"
|
|
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x324++0x03
|
|
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
rgroup.long 0x328++0x03
|
|
line.long 0x00 "ACTIVE10,Active Bit Register 10"
|
|
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x328++0x03
|
|
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
rgroup.long 0x32C++0x03
|
|
line.long 0x00 "ACTIVE11,Active Bit Register 11"
|
|
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x32C++0x03
|
|
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
rgroup.long 0x330++0x03
|
|
line.long 0x00 "ACTIVE12,Active Bit Register 12"
|
|
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
rgroup.long 0x334++0x03
|
|
line.long 0x00 "ACTIVE13,Active Bit Register 13"
|
|
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x334++0x03
|
|
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
rgroup.long 0x338++0x03
|
|
line.long 0x00 "ACTIVE14,Active Bit Register 14"
|
|
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x338++0x03
|
|
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
|
|
rgroup.long 0x33C++0x03
|
|
line.long 0x00 "ACTIVE15,Active Bit Register 15"
|
|
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x33C++0x03
|
|
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
|
|
endif
|
|
tree.end
|
|
width 13.
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
|
|
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
|
|
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A4++0x03
|
|
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
|
|
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A8++0x03
|
|
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
|
|
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3AC++0x03
|
|
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
|
|
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
|
|
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B4++0x03
|
|
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
|
|
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B8++0x03
|
|
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
|
|
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3BC++0x03
|
|
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x1F
|
|
line.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0xC "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x1C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
else
|
|
hgroup.long 0x420++0x1F
|
|
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hide.long 0xC "IPR11,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x1F
|
|
line.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0xC "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x1C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
else
|
|
hgroup.long 0x440++0x1F
|
|
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hide.long 0xC "IPR19,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x1F
|
|
line.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0xC "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x1C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
else
|
|
hgroup.long 0x460++0x1F
|
|
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hide.long 0xC "IPR27,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x1F
|
|
line.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0xC "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x1C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
else
|
|
hgroup.long 0x480++0x1F
|
|
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hide.long 0xC "IPR35,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x1F
|
|
line.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0x1C "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
else
|
|
hgroup.long 0x4A0++0x1F
|
|
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xC "IPR43,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x1F
|
|
line.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0x1C "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
else
|
|
hgroup.long 0x4C0++0x1F
|
|
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xC "IPR51,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x1F
|
|
line.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
line.long 0x10 "IPR60,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority"
|
|
line.long 0x14 "IPR61,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority"
|
|
line.long 0x18 "IPR62,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority"
|
|
line.long 0x1C "IPR63,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority"
|
|
else
|
|
hgroup.long 0x4E0++0x1F
|
|
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xC "IPR59,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR60,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR61,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR62,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR63,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x500++0x1F
|
|
line.long 0x0 "IPR64,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority"
|
|
line.long 0x4 "IPR65,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority"
|
|
line.long 0x8 "IPR66,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority"
|
|
line.long 0xC "IPR67,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority"
|
|
line.long 0x10 "IPR68,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority"
|
|
line.long 0x14 "IPR69,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority"
|
|
line.long 0x18 "IPR70,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority"
|
|
line.long 0x1C "IPR71,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority"
|
|
else
|
|
hgroup.long 0x500++0x1F
|
|
hide.long 0x0 "IPR64,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR65,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR66,Interrupt Priority Register"
|
|
hide.long 0xC "IPR67,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR68,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR69,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR70,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR71,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x520++0x1F
|
|
line.long 0x0 "IPR72,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority"
|
|
line.long 0x4 "IPR73,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority"
|
|
line.long 0x8 "IPR74,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority"
|
|
line.long 0xC "IPR75,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority"
|
|
line.long 0x10 "IPR76,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority"
|
|
line.long 0x14 "IPR77,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority"
|
|
line.long 0x18 "IPR78,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority"
|
|
line.long 0x1C "IPR79,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority"
|
|
else
|
|
hgroup.long 0x520++0x1F
|
|
hide.long 0x0 "IPR72,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR73,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR74,Interrupt Priority Register"
|
|
hide.long 0xC "IPR75,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR76,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR77,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR78,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR79,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x540++0x1F
|
|
line.long 0x0 "IPR80,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority"
|
|
line.long 0x4 "IPR81,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority"
|
|
line.long 0x8 "IPR82,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority"
|
|
line.long 0xC "IPR83,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority"
|
|
line.long 0x10 "IPR84,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority"
|
|
line.long 0x14 "IPR85,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority"
|
|
line.long 0x18 "IPR86,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority"
|
|
line.long 0x1C "IPR87,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority"
|
|
else
|
|
hgroup.long 0x540++0x1F
|
|
hide.long 0x0 "IPR80,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR81,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR82,Interrupt Priority Register"
|
|
hide.long 0xC "IPR83,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR84,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR85,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR86,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR87,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x560++0x1F
|
|
line.long 0x0 "IPR88,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority"
|
|
line.long 0x4 "IPR89,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority"
|
|
line.long 0x8 "IPR90,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority"
|
|
line.long 0xC "IPR91,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority"
|
|
line.long 0x10 "IPR92,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority"
|
|
line.long 0x14 "IPR93,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority"
|
|
line.long 0x18 "IPR94,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority"
|
|
line.long 0x1C "IPR95,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority"
|
|
else
|
|
hgroup.long 0x560++0x1F
|
|
hide.long 0x0 "IPR88,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR89,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR90,Interrupt Priority Register"
|
|
hide.long 0xC "IPR91,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR92,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR93,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR94,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR95,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x580++0x1F
|
|
line.long 0x0 "IPR96,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority"
|
|
line.long 0x4 "IPR97,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority"
|
|
line.long 0x8 "IPR98,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority"
|
|
line.long 0xC "IPR99,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority"
|
|
line.long 0x10 "IPR100,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority"
|
|
line.long 0x14 "IPR101,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority"
|
|
line.long 0x18 "IPR102,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority"
|
|
line.long 0x1C "IPR103,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority"
|
|
else
|
|
hgroup.long 0x580++0x1F
|
|
hide.long 0x0 "IPR96,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR97,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR98,Interrupt Priority Register"
|
|
hide.long 0xC "IPR99,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR100,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR101,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR102,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR103,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x5A0++0x1F
|
|
line.long 0x0 "IPR104,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority"
|
|
line.long 0x4 "IPR105,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority"
|
|
line.long 0x8 "IPR106,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority"
|
|
line.long 0xC "IPR107,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority"
|
|
line.long 0x10 "IPR108,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority"
|
|
line.long 0x14 "IPR109,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority"
|
|
line.long 0x18 "IPR110,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority"
|
|
line.long 0x1C "IPR111,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority"
|
|
else
|
|
hgroup.long 0x5A0++0x1F
|
|
hide.long 0x0 "IPR104,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR105,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR106,Interrupt Priority Register"
|
|
hide.long 0xC "IPR107,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR108,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR109,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR110,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR111,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x5C0++0x1F
|
|
line.long 0x0 "IPR112,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority"
|
|
line.long 0x4 "IPR113,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority"
|
|
line.long 0x8 "IPR114,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority"
|
|
line.long 0xC "IPR115,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority"
|
|
line.long 0x10 "IPR116,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority"
|
|
line.long 0x14 "IPR117,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority"
|
|
line.long 0x18 "IPR118,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority"
|
|
line.long 0x1C "IPR119,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority"
|
|
else
|
|
hgroup.long 0x5C0++0x1F
|
|
hide.long 0x0 "IPR112,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR113,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR114,Interrupt Priority Register"
|
|
hide.long 0xC "IPR115,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR116,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR117,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR118,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR119,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif (CORENAME()=="CORTEXM33F")
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
|
|
newline
|
|
bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
|
|
bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
|
|
newline
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
|
|
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 13.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
|
|
hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
tree "CoreSight Identification Registers"
|
|
width 12.
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "FP_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
tree "CoreSight Identification Registers"
|
|
width 13.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DWT_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "BACKUP (SRSS Backup Registers)"
|
|
base ad:0x42220000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "EN_CHARGE_KEY,When set to 3C the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A.."
|
|
bitfld.long 0x0 19. "VBACKUP_MEAS,Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup so it is within the supply range of the ADC." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "VDDBAK_CTL,Controls the behavior of the switch that generates vddbak from vbackup or vddd." "0: automatically select vddd if its brownout..,?,?,3: force vddbak and vmax to select vbackup"
|
|
bitfld.long 0x0 16. "WCO_BYPASS,Configures the WCO for different board-level connections to the WCO pins. For example this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases the two related GPIO pins (WCO input and.." "0: Watch crystal,1: Clock signal"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PRESCALER,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 8.--10. "CLK_SEL,Clock select for RTC clock" "0: Watch-crystal oscillator input available in..,1: This allows to use the LFCLK selection as an..,2: Internal Low frequency Oscillator available in..,3: Low-power external crystal oscillator prescaler..,4: Precision internal low-speed oscillator..,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 3. "WCO_EN,Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared the WCO will be internally kept on until the write completes." "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "RTC_RW,RTC Read Write register"
|
|
bitfld.long 0x0 1. "WRITE,Write bit" "0,1"
|
|
bitfld.long 0x0 0. "READ,Read bit" "0,1"
|
|
line.long 0x4 "CAL_CTL,Oscillator calibration for absolute frequency"
|
|
bitfld.long 0x4 31. "CAL_OUT,Output enable for wave signal for calibration and allow CALIB_VAL to be written." "0,1"
|
|
bitfld.long 0x4 28.--29. "CAL_SEL,Select calibration wave output signal" "0: 512Hz wave not affected by calibration setting..,1: N/A,2: 2Hz wave includes the effect of the calibration..,3: 1Hz wave includes the effect of the calibration.."
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CAL_COMP_PER_MIN,Select how many time calibration is performed per minute per step of 64 each time a 64 step is added or substracted one unit 2/4/8/16*CALIB_VAL is substracted." "0: Calibration of 64 each is performed twice per..,1: Calibration of 64 each is performed four times..,2: Calibration of 64 each is performed eight times..,3: Calibration of 64 each is performed sixteen.."
|
|
bitfld.long 0x4 6. "CALIB_SIGN,Calibration sign:" "0: Negative sign: remove pulses,1: Positive sign: add pulses"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "CALIB_VAL,Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32 768)) when CAL_COMP_PER_MIN is set at default.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 2. "WCO_OK,Obsolete. Use WCO_STATUS.WCO_OK for future designs." "0,1"
|
|
bitfld.long 0x0 0. "RTC_BUSY,Pending RTC write" "0,1"
|
|
group.long 0x14++0x23
|
|
line.long 0x0 "RTC_TIME,Calendar Seconds. Minutes. Hours. Day of Week"
|
|
bitfld.long 0x0 24.--26. "RTC_DAY,Calendar Day of the week 1-7" "?,1: Monday is recommended,?,?,?,?,?,?"
|
|
bitfld.long 0x0 22. "CTRL_12HR,Select 12/24HR mode: 1=12HR 0=24HR" "0: 24HR,1: 12HR"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "RTC_HOUR,Calendar hours value depending on 12/24HR mode"
|
|
hexmask.long.byte 0x0 8.--13. 1. "RTC_MIN,Calendar minutes 0-59"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "RTC_SEC,Calendar seconds 0-59"
|
|
line.long 0x4 "RTC_DATE,Calendar Day of Month. Month. Year"
|
|
hexmask.long.byte 0x4 16.--22. 1. "RTC_YEAR,Calendar year 0-99"
|
|
hexmask.long.byte 0x4 8.--11. 1. "RTC_MON,Calendar Month 1-12"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "RTC_DATE,Calendar Day of the Month 1-31"
|
|
line.long 0x8 "ALM1_TIME,Alarm 1 Seconds. Minute. Hours. Day of Week"
|
|
bitfld.long 0x8 31. "ALM_DAY_EN,Alarm Day of the Week enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
bitfld.long 0x8 24.--26. "ALM_DAY,Alarm Day of the week 1-7" "?,1: Monday is recommended,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 23. "ALM_HOUR_EN,Alarm hour enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
hexmask.long.byte 0x8 16.--20. 1. "ALM_HOUR,Alarm hours value depending on 12/24HR mode"
|
|
newline
|
|
bitfld.long 0x8 15. "ALM_MIN_EN,Alarm minutes enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
hexmask.long.byte 0x8 8.--13. 1. "ALM_MIN,Alarm minutes 0-59"
|
|
newline
|
|
bitfld.long 0x8 7. "ALM_SEC_EN,Alarm second enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
hexmask.long.byte 0x8 0.--5. 1. "ALM_SEC,Alarm seconds 0-59"
|
|
line.long 0xC "ALM1_DATE,Alarm 1 Day of Month. Month"
|
|
bitfld.long 0xC 31. "ALM_EN,Master enable for alarm 1." "0: Alarm 1 is disabled,1: Alarm 1 is enabled"
|
|
bitfld.long 0xC 15. "ALM_MON_EN,Alarm Month enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "ALM_MON,Alarm Month 1-12"
|
|
bitfld.long 0xC 7. "ALM_DATE_EN,Alarm Day of the Month enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "ALM_DATE,Alarm Day of the Month 1-31"
|
|
line.long 0x10 "ALM2_TIME,Alarm 2 Seconds. Minute. Hours. Day of Week"
|
|
bitfld.long 0x10 31. "ALM_DAY_EN,Alarm Day of the Week enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
bitfld.long 0x10 24.--26. "ALM_DAY,Alarm Day of the week 1-7" "?,1: Monday is recommended,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 23. "ALM_HOUR_EN,Alarm hour enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
hexmask.long.byte 0x10 16.--20. 1. "ALM_HOUR,Alarm hours value depending on 12/24HR mode"
|
|
newline
|
|
bitfld.long 0x10 15. "ALM_MIN_EN,Alarm minutes enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
hexmask.long.byte 0x10 8.--13. 1. "ALM_MIN,Alarm minutes 0-59"
|
|
newline
|
|
bitfld.long 0x10 7. "ALM_SEC_EN,Alarm second enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
hexmask.long.byte 0x10 0.--5. 1. "ALM_SEC,Alarm seconds 0-59"
|
|
line.long 0x14 "ALM2_DATE,Alarm 2 Day of Month. Month"
|
|
bitfld.long 0x14 31. "ALM_EN,Master enable for alarm 2." "0: Alarm 2 is disabled,1: Alarm 2 is enabled"
|
|
bitfld.long 0x14 15. "ALM_MON_EN,Alarm Month enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--11. 1. "ALM_MON,Alarm Month 1-12"
|
|
bitfld.long 0x14 7. "ALM_DATE_EN,Alarm Day of the Month enable: 0=ignore 1=match" "0: ignore,1: match"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--4. 1. "ALM_DATE,Alarm Day of the Month 1-31"
|
|
line.long 0x18 "INTR,Interrupt request register"
|
|
bitfld.long 0x18 2. "CENTURY,Century overflow interrupt" "0,1"
|
|
bitfld.long 0x18 1. "ALARM2,Alarm 2 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "ALARM1,Alarm 1 Interrupt" "0,1"
|
|
line.long 0x1C "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x1C 2. "CENTURY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x1C 1. "ALARM2,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ALARM1,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x20 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x20 2. "CENTURY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x20 1. "ALARM2,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "ALARM1,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 2. "CENTURY,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "ALARM2,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALARM1,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "PMIC_CTL,PMIC control register"
|
|
bitfld.long 0x0 31. "PMIC_EN,Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0 the system functions normally until vddd is no longer present.." "0,1"
|
|
bitfld.long 0x0 30. "PMIC_ALWAYSEN,Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware." "0: Normal operation,1: PMIC_EN and PMIC_OUTEN are ignored and the.."
|
|
newline
|
|
bitfld.long 0x0 29. "PMIC_EN_OUTEN,Output enable for the output driver in the PMIC_EN pad." "0: Output pad is tristate for PMIC_EN pin,1: Output pad is enabled for PMIC_EN pin"
|
|
bitfld.long 0x0 16. "POLARITY,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "UNLOCK,This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the.."
|
|
line.long 0x4 "RESET,Backup reset register"
|
|
bitfld.long 0x4 31. "RESET,Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register firmware should confirm it reads as 0 before attempting to write other backup registers." "0,1"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "WCO_STATUS,WCO Status Register"
|
|
bitfld.long 0x0 2. "WCO_OK,Indicates that output has transitioned." "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "BREG_SET0[$1],Backup register region 0"
|
|
hexmask.long 0x0 0.--31. 1. "BREG,Backup memory that contains application-specific data. Memory is retained on vbackup supply."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1010)++0x3
|
|
line.long 0x0 "BREG_SET1[$1],Backup register region 1"
|
|
hexmask.long 0x0 0.--31. 1. "BREG,Backup memory that contains application-specific data. Memory is retained on vbackup supply."
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1020)++0x3
|
|
line.long 0x0 "BREG_SET2[$1],Backup register region 2"
|
|
hexmask.long 0x0 0.--31. 1. "BREG,Backup memory that contains application-specific data. Memory is retained on vbackup supply."
|
|
repeat.end
|
|
repeat 48. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1080)++0x3
|
|
line.long 0x0 "BREG_SET3[$1],Backup register region 3"
|
|
hexmask.long 0x0 0.--31. 1. "BREG,Backup memory that contains application-specific data. Memory is retained on vbackup supply."
|
|
repeat.end
|
|
tree.end
|
|
tree "CANFD (Controller Area Network Flexible Data-Rate)"
|
|
base ad:0x42800000
|
|
repeat 2. (list 0x0 0x1)(list ad:0x42800000 ad:0x42800200)
|
|
tree "CH[$1]"
|
|
base $2
|
|
tree "M_TTCAN (TTCAN 3PIP includes FD)"
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "CREL,Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
|
|
line.long 0x4 "ENDN,Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long ($2+0xC)++0x23
|
|
line.long 0x0 "DBTP,Data Bit Timing & Prescaler Register"
|
|
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width"
|
|
line.long 0x4 "TEST,Test Register"
|
|
rbitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant,1: The CAN bus is recessive"
|
|
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value,1: Loop Back Mode is enabled"
|
|
bitfld.long 0x4 3. "CAT,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_asct = '0',?"
|
|
newline
|
|
bitfld.long 0x4 2. "CAM,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_ascm = '0',1: Output pin m_ttcan_ascm = '1'"
|
|
bitfld.long 0x4 1. "TAT,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_asct controlled by FSE,1: Level at pin m_ttcan_asct = '1'"
|
|
newline
|
|
bitfld.long 0x4 0. "TAM,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_ascm controlled by FSE,1: Level at pin m_ttcan_ascm = '1'"
|
|
line.long 0x8 "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration"
|
|
line.long 0xC "CCCR,CC Control Register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test Mode Enable" "0: Normal operation,1: Test Mode"
|
|
bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON_,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock Stop Request not supported by M_TTCAN use CTL.STOP_REQ at the group level instead." "0: No clock stop is requested,1: Clock stop requested"
|
|
newline
|
|
bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_TTCAN may be set in power down by stopping.."
|
|
bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started"
|
|
line.long 0x10 "NBTP,Nominal Bit Timing & Prescaler Register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
|
|
line.long 0x14 "TSCC,Timestamp Counter Configuration"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler (still used for TOCC)"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp Select should always be set to external timestamp counter" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
|
|
line.long 0x18 "TSCV,Timestamp Counter Value"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter not used for M_TTCAN"
|
|
line.long 0x1C "TOCC,Timeout Counter Configuration"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled"
|
|
line.long 0x20 "TOCV,Timeout Counter Value"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
|
|
rgroup.long ($2+0x40)++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0: Since this bit was reset by the CPU,1: Message in CAN FD format with FDF flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set"
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state"
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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|
newline
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state,1: The M_CAN is in the Error_Passive state"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing,1: Idle,?,?"
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|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code " "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the M_TTCAN..,4: Bit1Error: During the transmission of a message,5: Bit0Error: During the transmission of a message,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.."
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|
group.long ($2+0x48)++0x3
|
|
line.long 0x0 "TDCR,Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
|
|
group.long ($2+0x50)++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,N/A" "0,1"
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|
bitfld.long 0x0 28. "PED,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 27. "PEA,N/A" "0,1"
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|
bitfld.long 0x0 26. "WDI,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 25. "BO_,N/A" "0,1"
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|
bitfld.long 0x0 24. "EW_,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 23. "EP_,N/A" "0,1"
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|
bitfld.long 0x0 22. "ELO,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected"
|
|
bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1"
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|
newline
|
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bitfld.long 0x0 19. "DRX,N/A" "0,1"
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|
bitfld.long 0x0 18. "TOO,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 17. "MRAF,N/A" "0,1"
|
|
bitfld.long 0x0 16. "TSW,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "TEFL_,N/A" "0,1"
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|
bitfld.long 0x0 14. "TEFF,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 13. "TEFW,N/A" "0,1"
|
|
bitfld.long 0x0 12. "TEFN,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "TFE,N/A" "0,1"
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|
bitfld.long 0x0 10. "TCF,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TC,N/A" "0,1"
|
|
bitfld.long 0x0 8. "HPM,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RF1L_,N/A" "0,1"
|
|
bitfld.long 0x0 6. "RF1F,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1W,N/A" "0,1"
|
|
bitfld.long 0x0 4. "RF1N,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RF0L_,N/A" "0,1"
|
|
bitfld.long 0x0 2. "RF0F,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 1. "RF0W,N/A" "0,1"
|
|
bitfld.long 0x0 0. "RF0N,N/A" "0,1"
|
|
line.long 0x4 "IE,Interrupt Enable"
|
|
bitfld.long 0x4 29. "ARAE,N/A" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable (not used in M_TTCAN)" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIDO New Entry Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt Disabled,1: Interrupt EnabledTx FIFO Empty Interrupt Enable"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
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bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
line.long 0x8 "ILS,Interrupt Line Select"
|
|
bitfld.long 0x8 29. "ARAL,N/A" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Select (not used in M_TTCAN)" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
line.long 0xC "ILE,Interrupt Line Enable"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_ttcan_int1 disabled,1: Interrupt line m_ttcan_int1 enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_ttcan_int0 disabled,1: Interrupt line m_ttcan_int0 enabled"
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long ($2+0x90)++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long ($2+0x94)++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long ($2+0x98)++0xB
|
|
line.long 0x0 "NDAT1,New Data 1"
|
|
hexmask.long 0x0 0.--31. 1. "ND,New Data"
|
|
line.long 0x4 "NDAT2,New Data 2"
|
|
hexmask.long 0x4 0.--31. 1. "ND,New Data"
|
|
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
rgroup.long ($2+0xA4)++0x3
|
|
line.long 0x0 "RXF0S,Rx FIFO 0 Status"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
|
|
group.long ($2+0xA8)++0xB
|
|
line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Rx FIFO 1 Configuration"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
|
|
rgroup.long ($2+0xB4)++0x3
|
|
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state,1: Debug message A received,?,?"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
|
|
group.long ($2+0xB8)++0xB
|
|
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
line.long 0x8 "TXBC,Tx Buffer Configuration"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long ($2+0xC4)++0x3
|
|
line.long 0x0 "TXFQS,Tx FIFO/Queue Status"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long ($2+0xC8)++0x3
|
|
line.long 0x0 "TXESC,Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,?,?,?,?,?,?"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
|
|
hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending"
|
|
group.long ($2+0xD0)++0x7
|
|
line.long 0x0 "TXBAR,Tx Buffer Add Request"
|
|
hexmask.long 0x0 0.--31. 1. "AR,Add Request"
|
|
line.long 0x4 "TXBCR,Tx Buffer Cancellation Request"
|
|
hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request"
|
|
rgroup.long ($2+0xD8)++0x7
|
|
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
|
|
hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred"
|
|
line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished"
|
|
hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished"
|
|
group.long ($2+0xE0)++0x7
|
|
line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable"
|
|
line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long ($2+0xF4)++0x3
|
|
line.long 0x0 "TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long ($2+0xF8)++0x3
|
|
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
group.long ($2+0x100)++0x2B
|
|
line.long 0x0 "TTTMC,TT Trigger Memory Configuration"
|
|
hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements"
|
|
hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start Address"
|
|
line.long 0x4 "TTRMC,TT Reference Message Configuration"
|
|
bitfld.long 0x4 31. "RMPS,Reference Message Payload Select" "0: Message Marker MM,1: bytes 2-8"
|
|
bitfld.long 0x4 30. "XTD,Extended Identifier" "0: 11-bit standard identifier,1: 29-bit extended identifier"
|
|
newline
|
|
hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier"
|
|
line.long 0x8 "TTOCF,TT Operation Configuration"
|
|
bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0: Automatic clock calibration in TTCAN Level 0,1: Automatic clock calibration in TTCAN Level 0"
|
|
newline
|
|
bitfld.long 0x8 24. "EGTF,Enable Global Time Filtering" "0: Global time filtering in TTCAN Level 0,1: Global time filtering in TTCAN Level 0"
|
|
hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit"
|
|
newline
|
|
bitfld.long 0x8 15. "EECS,Enable External Clock Synchronization" "0: External clock synchronization in TTCAN Level 0,1: External clock synchronization in TTCAN Level 0"
|
|
hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger Offset"
|
|
newline
|
|
bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation Limit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 4. "TM,Time Master" "0: Time Master function disabled,1: Potential Time Master"
|
|
newline
|
|
bitfld.long 0x8 3. "GEN,Gap Enable" "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.."
|
|
bitfld.long 0x8 0.--1. "OM,Operation Mode" "0: Event-driven CAN communication,1: TTCAN level 1,?,?"
|
|
line.long 0xC "TTMLM,TT Matrix Limits"
|
|
hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx Triggers"
|
|
hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "CSS,N/A" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--5. 1. "CCM,N/A"
|
|
line.long 0x10 "TURCF,TUR Configuration"
|
|
bitfld.long 0x10 31. "ELT,Enable Local Time" "0: Local time is stopped,1: Local time is enabled"
|
|
hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration Low"
|
|
line.long 0x14 "TTOCN,TT Operation Control"
|
|
rbitfld.long 0x14 15. "LCKC,TT Operation Control Register Locked" "0: Write access to TTOCN enabled,1: Write access to TTOCN locked"
|
|
bitfld.long 0x14 13. "ESCN,External Synchronization Control" "0: External synchronization disabled,1: External synchronization enabled"
|
|
newline
|
|
bitfld.long 0x14 12. "NIG,Next is Gap" "0: No action,1: Transmit next reference message with Next_is_Gap.."
|
|
bitfld.long 0x14 11. "TMG,Time Mark Gap" "0: Reset by each reference message,1: Next reference message started when Register.."
|
|
newline
|
|
bitfld.long 0x14 10. "FGP,Finish Gap" "0: No reference message requested,1: Application requested start of reference message"
|
|
bitfld.long 0x14 9. "GCS,Gap Control Select" "0: Gap control independent from m_ttcan_evt,1: Gap control by input pin m_ttcan_evt"
|
|
newline
|
|
bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse Enable" "0: Trigger Time Mark Interrupt output m_ttcan_tmp..,1: Trigger Time Mark Interrupt output m_ttcan_tmp.."
|
|
bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0: No Register Time Mark Interrupt generated,1: Register Time Mark Interrupt if Time Mark =..,?,?"
|
|
newline
|
|
bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse Enable" "0: Register Time Mark Interrupt output m_ttcan_rtp..,1: Register Time Mark Interrupt output m_ttcan_rtp.."
|
|
bitfld.long 0x14 3.--4. "SWS,Stop Watch Source" "0: Stop Watch disabled,1: Actual value of cycle time is copied to TTCPT,?,?"
|
|
newline
|
|
bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x14 1. "ECS,External Clock Synchronization" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "SGT,Set Global time" "0,1"
|
|
line.long 0x18 "TTGTP,TT Global Time Preset"
|
|
hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase"
|
|
hexmask.long.word 0x18 0.--15. 1. "TP,N/A"
|
|
line.long 0x1C "TTTMK,TT Time Mark"
|
|
rbitfld.long 0x1C 31. "LCKM,TT Time Mark Register Locked" "0: Write access to TTTMK enabled,1: Write access to TTTMK locked"
|
|
hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "TM_,Time Mark"
|
|
line.long 0x20 "TTIR,TT Interrupt Register"
|
|
bitfld.long 0x20 18. "CER,Configuration Error" "0: No error found in trigger list,1: Error found in trigger list"
|
|
bitfld.long 0x20 17. "AW,Application Watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time"
|
|
newline
|
|
bitfld.long 0x20 16. "WT,Watch Trigger" "0: cycle time 0xFF00,1: Missing reference message"
|
|
bitfld.long 0x20 15. "IWT,Initialization Watch Trigger" "0: No missing reference message during system startup,1: No system startup due to missing reference message"
|
|
newline
|
|
bitfld.long 0x20 14. "ELC,Error Level Changed" "0: No change in error level,1: Error level changed"
|
|
bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred"
|
|
newline
|
|
bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred"
|
|
bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0: Number of Tx Trigger as expected,1: More Tx trigger than expected in one matrix cycle"
|
|
newline
|
|
bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0: Number of Tx Trigger as expected,1: Less Tx trigger than expected in one matrix cycle"
|
|
bitfld.long 0x20 9. "GTE,Global Time Error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit"
|
|
newline
|
|
bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time"
|
|
bitfld.long 0x20 7. "GTW,Global Time Wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred"
|
|
newline
|
|
bitfld.long 0x20 6. "SWE,Stop Watch Event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.."
|
|
bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event Internal" "0: cycle time TTOCF,1: Time mark reached"
|
|
newline
|
|
bitfld.long 0x20 4. "RTMI,Register Time Mark Interrupt" "0: Time mark not reached,1: Time mark reached"
|
|
bitfld.long 0x20 3. "SOG,Start of Gap" "0: No reference message seen with Next_is_Gap bit set,1: Reference message with Next_is_Gap bit set.."
|
|
newline
|
|
bitfld.long 0x20 2. "CSM_,Change of Synchronization Mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.."
|
|
bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0: No Matrix Cycle started since bit has been reset,1: Matrix Cycle started"
|
|
newline
|
|
bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0: No Basic Cycle started since bit has been reset,1: Basic Cycle started"
|
|
line.long 0x24 "TTIE,TT Interrupt Enable"
|
|
bitfld.long 0x24 18. "CERE,Configuration Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 17. "AWE_,Application Watchdog Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 15. "IWTE,Initialization Watch Trigger Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
line.long 0x28 "TTILS,TT Interrupt Line Select"
|
|
bitfld.long 0x28 18. "CERL,Configuration Error Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 17. "AWL_,Application Watchdog Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 15. "IWTL,Initialization Watch Trigger Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
rgroup.long ($2+0x12C)++0x17
|
|
line.long 0x0 "TTOST,TT Operation Status"
|
|
bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0: Phase outside range,1: Phase inside range"
|
|
bitfld.long 0x0 30. "WECS,Wait for External Clock Synchronization" "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.."
|
|
newline
|
|
bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0: Application Watchdog served in time,1: Failed to serve Application Watchdog in time"
|
|
bitfld.long 0x0 28. "WFE,Wait for Event" "0: No Gap announced,1: Reference message with Next_is_Gap = '1' received"
|
|
newline
|
|
bitfld.long 0x0 27. "GSI,Gap Started Indicator" "0: No Gap in schedule,1: Gap time after Basic Cycle has started"
|
|
bitfld.long 0x0 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "GFI,Gap Finished Indicator" "0: Reset at the end of each reference message,1: Gap finished by M_TTCAN"
|
|
bitfld.long 0x0 22. "WGTD,Wait for Global Time Discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset"
|
|
bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0: Local clock speed not synchronized to Time..,1: Synchronization Deviation <= SDL"
|
|
newline
|
|
bitfld.long 0x0 6. "QGTP,Quality of Global Time Phase" "0: Global time not valid,1: Global time in phase with Time Master"
|
|
bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0: Out of Synchronization,1: Synchronizing to TTCAN communication,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MS,Master State" "0: Master_Off,1: Operating as Time Slave,?,?"
|
|
bitfld.long 0x0 0.--1. "EL,Error Level" "0: Severity 0,1: Severity 1,?,?"
|
|
line.long 0x4 "TURNA,TUR Numerator Actual"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "NAV,N/A"
|
|
line.long 0x8 "TTLGT,TT Local & Global Time"
|
|
hexmask.long.word 0x8 16.--31. 1. "GT,Global Time"
|
|
hexmask.long.word 0x8 0.--15. 1. "LT,Local Time"
|
|
line.long 0xC "TTCTC,TT Cycle Time & Count"
|
|
hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count"
|
|
hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time"
|
|
line.long 0x10 "TTCPT,TT Capture Time"
|
|
hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value"
|
|
hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle Count Value"
|
|
line.long 0x14 "TTCSM,TT Cycle Sync Mark"
|
|
hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark"
|
|
tree.end
|
|
newline
|
|
group.long ($2+0x180)++0x3
|
|
newline
|
|
line.long 0x0 "RXFTOP_CTL,Receive FIFO Top control"
|
|
bitfld.long 0x0 1. "F1TPE,FIFO 1 Top Pointer Enable." "0,1"
|
|
bitfld.long 0x0 0. "F0TPE,FIFO 0 Top Pointer Enable." "0,1"
|
|
rgroup.long ($2+0x1A0)++0x3
|
|
line.long 0x0 "RXFTOP0_STAT,Receive FIFO 0 Top Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "F0TA,Current FIFO 0 Top Address."
|
|
rgroup.long ($2+0x1A8)++0x3
|
|
line.long 0x0 "RXFTOP0_DATA,Receive FIFO 0 Top Data"
|
|
hexmask.long 0x0 0.--31. 1. "F0TD,When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met:"
|
|
rgroup.long ($2+0x1B0)++0x3
|
|
line.long 0x0 "RXFTOP1_STAT,Receive FIFO 1 Top Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "F1TA,See F0TA description"
|
|
rgroup.long ($2+0x1B8)++0x3
|
|
line.long 0x0 "RXFTOP1_DATA,Receive FIFO 1 Top Data"
|
|
hexmask.long 0x0 0.--31. 1. "F1TD,See F0TD description"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x42800000
|
|
newline
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CTL,Global CAN control register"
|
|
bitfld.long 0x0 31. "MRAM_OFF,MRAM off" "0: Default MRAM on,1: Switch MRAM off"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STOP_REQ,N/A"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "STATUS,Global CAN status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STOP_ACK,Clock Stop Acknowledge for each TTCAN IP."
|
|
rgroup.long 0x1010++0x7
|
|
line.long 0x0 "INTR0_CAUSE,Consolidated interrupt0 cause register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT0,Show pending m_ttcan_int0 of each channel"
|
|
line.long 0x4 "INTR1_CAUSE,Consolidated interrupt1 cause register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INT1,Show pending m_ttcan_int1 of each channel"
|
|
group.long 0x1020++0x7
|
|
line.long 0x0 "TS_CTL,Time Stamp control register"
|
|
bitfld.long 0x0 31. "ENABLED,Counter enable bit" "0: Count disabled,1: Count enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. "PRESCALE,Time Stamp counter prescale value."
|
|
line.long 0x4 "TS_CNT,Time Stamp counter value"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALUE,The counter value of the Time Stamp Counter."
|
|
tree.end
|
|
tree "CPUSS (CPU Subsystem)"
|
|
base ad:0x421C0000
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|
rgroup.long 0x0++0x3
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|
line.long 0x0 "IDENTITY,Identity"
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|
hexmask.long.byte 0x0 8.--15. 1. "MS,This field specifies the bus master identifier of the transfer that reads the register."
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|
newline
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|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context of the transfer that reads the register."
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|
newline
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bitfld.long 0x0 1. "NS,This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register." "0: secure mode,1: non-secure mode"
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|
newline
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bitfld.long 0x0 0. "P,This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register." "0: user mode,1: privileged mode"
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|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "PRODUCT_ID,Product identifier and version (same as CoreSight RomTables)"
|
|
hexmask.long.byte 0x0 20.--23. 1. "MINOR_REV,Minor Revision starts with 1 increments with metal layer only tape-out (implemented with metal ECO-able tie-off)"
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|
newline
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|
hexmask.long.byte 0x0 16.--19. 1. "MAJOR_REV,Major Revision starts with 1 increments with all layer tape-out (implemented with metal ECO-able tie-off)"
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|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "FAMILY_ID,Family ID. Common ID for a product family."
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|
rgroup.long 0x20++0x3
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|
line.long 0x0 "DP_STATUS,Debug port status"
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|
bitfld.long 0x0 3. "SWJ_SWD_SEL,Specifies if the SWD interface is selected." "0: SWD not selected,1: SWD selected"
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|
newline
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bitfld.long 0x0 2. "SWJ_JTAG_SEL,Specifies if the JTAG interface is selected." "0: JTAG not selected,1: JTAG selected"
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newline
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bitfld.long 0x0 1. "SWJ_DEBUG_EN,Specifies if SWJ debug is enabled i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:" "0: Disabled,1: Enabled"
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|
newline
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bitfld.long 0x0 0. "SWJ_CONNECTED,Specifies if the SWJ debug port is connected; i.e. debug host interface is active:" "0: Not connected/not active,1: Connected/active"
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group.long 0x30++0x3
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|
line.long 0x0 "BUFF_CTL,Buffer control"
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|
bitfld.long 0x0 0. "WRITE_BUFF,Specifies if write transfer can be buffered in the bus infrastructure bridges:" "0: Write transfers are not buffered,1: Write transfers can be buffered"
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group.long 0x40++0x7
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|
line.long 0x0 "CAL_SUP_SET,Calibration support set and read"
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|
hexmask.long 0x0 0.--31. 1. "DATA,Read without side effect write 1 to set"
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|
line.long 0x4 "CAL_SUP_CLR,Calibration support clear and reset"
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|
hexmask.long 0x4 0.--31. 1. "DATA,Read side effect: when read all bits are cleared write 1 to clear a specific bit"
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group.long 0x50++0x3
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line.long 0x0 "INFRA_CTL,Infrastructure Control"
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|
bitfld.long 0x0 0. "CLOCK_FORCE,Force Infrastructure clock gating to be always ON." "0: Disabled,1: Enabled"
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group.long 0x100++0x3
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line.long 0x0 "SYSTICK_S_CTL,Secure SysTick timer control"
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bitfld.long 0x0 31. "NOREF,Specifies if an external clock source is provided:" "0: An external clock source is provided,1: An external clock source is NOT provided and.."
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newline
|
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bitfld.long 0x0 30. "SKEW,Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:" "0: Precise,1: Imprecise"
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newline
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bitfld.long 0x0 24.--25. "CLOCK_SOURCE,Specifies an external clock source:" "0: The low frequency clock 'clk_lf' is selected,1: The internal main oscillator,2: The external crystal oscillator,3: The SRSS 'clk_timer' is selected"
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newline
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hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g. for a 32 768 Hz reference clock TENMS is 328 - 1 = 327."
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group.long 0x120++0x3
|
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line.long 0x0 "SYSTICK_NS_CTL,Non Secure SysTick timer control"
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bitfld.long 0x0 31. "NOREF,Specifies if an external clock source is provided:" "0: An external clock source is provided,1: An external clock source is NOT provided and.."
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newline
|
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bitfld.long 0x0 30. "SKEW,Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:" "0: Precise,1: Imprecise"
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|
newline
|
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bitfld.long 0x0 24.--25. "CLOCK_SOURCE,Specifies an external clock source:" "0: The low frequency clock 'clk_lf' is selected,1: The internal main oscillator,2: The external crystal oscillator,3: The SRSS 'clk_timer' is selected"
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newline
|
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hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g. for a 32 768 Hz reference clock TENMS is 328 - 1 = 327."
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|
group.long 0x200++0x3
|
|
line.long 0x0 "INTR_MSC,Master security controller Interrupt"
|
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bitfld.long 0x0 5. "DMAC1_MSC,N/A" "0,1"
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newline
|
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bitfld.long 0x0 4. "DMAC0_MSC,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 3. "EXP_MS_MSC,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "SYS_MS1_MSC,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 1. "SYS_MS0_MSC,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "CODE_MS0_MSC,This interrupt cause field is activated (HW sets the field to '1') when there is a MSC interrupt violation." "0,1"
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group.long 0x208++0x3
|
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line.long 0x0 "INTR_MASK_MSC,Master security controller Interrupt mask"
|
|
bitfld.long 0x0 5. "DMAC1_MSC,Mask bit for corresponding field in the INTR register." "0,1"
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newline
|
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bitfld.long 0x0 4. "DMAC0_MSC,Mask bit for corresponding field in the INTR register." "0,1"
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|
newline
|
|
bitfld.long 0x0 3. "EXP_MS_MSC,Mask bit for corresponding field in the INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SYS_MS1_MSC,Mask bit for corresponding field in the INTR register." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "SYS_MS0_MSC,Mask bit for corresponding field in the INTR register." "0,1"
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|
newline
|
|
bitfld.long 0x0 0. "CODE_MS0_MSC,Mask bit for corresponding field in the INTR register." "0,1"
|
|
rgroup.long 0x20C++0x3
|
|
line.long 0x0 "INTR_MASKED_MSC,Master security controller Interrupt masked"
|
|
bitfld.long 0x0 5. "DMAC1_MSC,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
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|
newline
|
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bitfld.long 0x0 4. "DMAC0_MSC,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
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|
newline
|
|
bitfld.long 0x0 3. "EXP_MS_MSC,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "SYS_MS1_MSC,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "SYS_MS0_MSC,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CODE_MS0_MSC,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "AP_CTL,Access port control"
|
|
bitfld.long 0x0 30. "SYS_SECURE_DISABLE,Disables the system secure AP interface:" "0: Enabled,1: Disabled"
|
|
newline
|
|
bitfld.long 0x0 29. "CM33_1_SECURE_DISABLE,Disables the CM33_1 secure AP interface:" "0: Enabled,1: Disabled"
|
|
newline
|
|
bitfld.long 0x0 28. "CM33_0_SECURE_DISABLE,Disables the CM33_0 secure AP interface:" "0: Enabled,1: Disabled"
|
|
newline
|
|
bitfld.long 0x0 27. "CM33_1_SPNID_DISABLE,Refer CM33_0_SPNID_DISABLE description." "0,1"
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|
newline
|
|
bitfld.long 0x0 26. "CM33_1_SPID_DISABLE,Refer CM33_0_SPID_DISABLE description." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "CM33_1_NID_DISABLE,Refer CM33_0_NID_DISABLE description." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CM33_1_DBG_DISABLE,Refer CM33_0_DBG_DISABLE description." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "CM33_0_SPNID_DISABLE,Secure non-invasive debug disable for CM33_0." "0: Enables non-invasive debug features when the..,1: Disables non-invasive debug features when the.."
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|
newline
|
|
bitfld.long 0x0 22. "CM33_0_SPID_DISABLE,Secure invasive debug disable for CM33_0." "0: Enables all halt mode and invasive debug..,1: disables all halt mode and invasive debug.."
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newline
|
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bitfld.long 0x0 21. "CM33_0_NID_DISABLE,Disable Non-invasive debug for CM33_0." "0: Enables all trace and non-invasive debug features,1: Disables all trace and non-invasive debug features"
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newline
|
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bitfld.long 0x0 20. "CM33_0_DBG_DISABLE,Disable Invasive debug for CM33_0." "0: Enables invasive debug features,1: Disables all halt-mode and invasive debug features"
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|
newline
|
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bitfld.long 0x0 18. "SYS_DISABLE,Disables the system AP interface:" "0: Enabled,1: Disabled"
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|
newline
|
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bitfld.long 0x0 17. "CM33_1_DISABLE,Disables the CM33_1 AP interface:" "0: Enabled,1: Disabled"
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newline
|
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bitfld.long 0x0 16. "CM33_0_DISABLE,Disables the CM33_0 AP interface:" "0: Enabled,1: Disabled"
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newline
|
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bitfld.long 0x0 14. "SYS_SECURE_ENABLE,Enables the system secure AP interface:" "0: Disabled,1: Enabled"
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newline
|
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bitfld.long 0x0 13. "CM33_1_SECURE_ENABLE,Enables the CM33_1 secure AP interface:" "0: Disabled,1: Enabled"
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newline
|
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bitfld.long 0x0 12. "CM33_0_SECURE_ENABLE,Enables the CM33_0 secure AP interface:" "0: Disabled,1: Enabled"
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newline
|
|
bitfld.long 0x0 11. "CM33_1_SPNID_ENABLE,Refer CM33_0_SPNID_ENABLE." "0,1"
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newline
|
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bitfld.long 0x0 10. "CM33_1_SPID_ENABLE,Refer CM33_0_SPID_ENABLE." "0,1"
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newline
|
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bitfld.long 0x0 9. "CM33_1_NID_ENABLE,Refer CM33_0_NID_ENABLE." "0,1"
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newline
|
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bitfld.long 0x0 8. "CM33_1_DBG_ENABLE,Refer CM33_0_DBG_ENABLE." "0,1"
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newline
|
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bitfld.long 0x0 7. "CM33_0_SPNID_ENABLE,Secure non-invasive debug enable for CM33_0." "0: Disables non-invasive debug features when the..,1: Enables non-invasive debug features when the.."
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newline
|
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bitfld.long 0x0 6. "CM33_0_SPID_ENABLE,Secure invasive debug enable for CM33_0." "0: disables all halt mode and invasive debug..,1: Enables all halt mode and invasive debug.."
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newline
|
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bitfld.long 0x0 5. "CM33_0_NID_ENABLE,Non-invasive debug enable for CM33_0." "0: Disables all trace and non-invasive debug features,1: Enables all trace and non-invasive debug features"
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newline
|
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bitfld.long 0x0 4. "CM33_0_DBG_ENABLE,Invasive debug enable for CM33_0." "0: Disables all halt-mode and invasive debug features,1: Enables invasive debug features"
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newline
|
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bitfld.long 0x0 2. "SYS_ENABLE,Enables the system AP interface:" "0: Disabled,1: Enabled"
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newline
|
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bitfld.long 0x0 1. "CM33_1_ENABLE,Enables the CM33_1 AP interface:" "0: Disabled,1: Enabled"
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newline
|
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bitfld.long 0x0 0. "CM33_0_ENABLE,Enables the CM33_0 AP interface:" "0: Disabled,1: Enabled"
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group.long 0x2004++0x3
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line.long 0x0 "PROTECTION,Protection status"
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hexmask.long 0x0 0.--31. 1. "STATE,Protection state:"
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tree.end
|
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tree "CPUSS_PPU (Power Policy Unit Registers for CPUSS)"
|
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base ad:0x42105000
|
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group.long 0x0++0x7
|
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line.long 0x0 "PWPR,Power Policy Register"
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bitfld.long 0x0 24. "OP_DYN_EN,N/A" "0,1"
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hexmask.long.byte 0x0 16.--19. 1. "OP_POLICY,N/A"
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bitfld.long 0x0 12. "LOCK_EN,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "PWR_DYN_EN,Power mode dynamic transition enable. When this bit is set to 1 dynamic transitions are enabled for power modes allowing transitions to be initiated by changes on power mode DEVACTIVE inputs." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "PWR_POLICY,Power mode policy. When static power mode transitions are enabled PWR_DYN_EN is set to 0 this is the target power mode for the PPU. When dynamic power mode transitions are enabled PWR_DYN_EN is set to 1 this is the minimum power mode for.."
|
|
line.long 0x4 "PMER,Power Mode Emulation Register"
|
|
bitfld.long 0x4 0. "EMU_EN,N/A" "0,1"
|
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rgroup.long 0x8++0x3
|
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line.long 0x0 "PWSR,Power Status Register"
|
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bitfld.long 0x0 24. "OP_DYN_STATUS,N/A" "0,1"
|
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hexmask.long.byte 0x0 16.--19. 1. "OP_STATUS,N/A"
|
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bitfld.long 0x0 12. "LOCK_STATUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PWR_DYN_STATUS,Power mode dynamic transition status. When set to 1 power mode dynamic transitions are enabled. There might be a delay in dynamic transitions becoming active or inactive if the PPU is transitioning when PWR_DYN_EN is programmed." "0,1"
|
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hexmask.long.byte 0x0 0.--3. 1. "PWR_STATUS,Power mode status. These bits reflect the current power mode of the PPU. See PPU_PWPR.PWR_POLICY for power mode enumeration."
|
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rgroup.long 0x10++0xB
|
|
line.long 0x0 "DISR,Device Interface Input Current Status Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "OP_DEVACTIVE_STATUS,N/A"
|
|
hexmask.long.word 0x0 0.--10. 1. "PWR_DEVACTIVE_STATUS,Status of the power mode DEVACTIVE inputs."
|
|
line.long 0x4 "MISR,Miscellaneous Input Current Status Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DEVDENY_STATUS,Status of the device interface DEVDENY inputs."
|
|
hexmask.long.byte 0x4 8.--15. 1. "DEVACCEPT_STATUS,Status of the device interface DEVACCEPT inputs."
|
|
bitfld.long 0x4 0. "PCSMPACCEPT_STATUS,The status of the PCSMPACCEPT input." "0,1"
|
|
line.long 0x8 "STSR,Stored Status Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "STORED_DEVDENY,Status of the DEVDENY signals from the last device interface Q-Channel transition. For Q-Channel: There is one bit for each device interface DEVQDENY. For example bit 0 is for Q-Channel 0 DEVQDENY and bit 1 for Q-Channel 1 DEVQDENY."
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "UNLK,Unlock register"
|
|
bitfld.long 0x0 0. "UNLOCK,N/A" "0,1"
|
|
line.long 0x4 "PWCR,Power Configuration Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "OP_DEVACTIVEEN,N/A"
|
|
hexmask.long.word 0x4 8.--18. 1. "PWR_DEVACTIVEEN,These bits enable the power mode DEVACTIVE inputs. When a bit is to 1 the related DEVACTIVE input is enabled when set to 0 it is disabled. All available bits are reset to 1."
|
|
hexmask.long.byte 0x4 0.--7. 1. "DEVREQEN,When set to 1 enables the device interface handshake for transitions. All available bits are reset to 1."
|
|
line.long 0x8 "PTCR,Power Mode Transition Configuration Register"
|
|
bitfld.long 0x8 1. "DBG_RECOV_PORST_EN,N/A" "0,1"
|
|
bitfld.long 0x8 0. "WARM_RST_DEVREQEN,Transition behavior between ON and WARM_RST. This bit should not be modified when the PPU is in WARM_RST or if the PPU is performing a transition otherwise PPU behavior is UNPREDICTABLE." "0: The PPU does not perform a device interface..,1: The PPU performs a device interface handshake.."
|
|
group.long 0x30++0x17
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 5. "LOCKED_IRQ_MASK,N/A" "0,1"
|
|
bitfld.long 0x0 4. "EMU_DENY_IRQ_MASK,N/A" "0,1"
|
|
bitfld.long 0x0 3. "EMU_ACCEPT_IRQ_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STA_DENY_IRQ_MASK,Static transition denial event mask." "0,1"
|
|
bitfld.long 0x0 1. "STA_ACCEPT_IRQ_MASK,Static transition acceptance event mask." "0,1"
|
|
bitfld.long 0x0 0. "STA_POLICY_TRN_IRQ_MASK,Static full policy transition completion event mask." "0,1"
|
|
line.long 0x4 "AIMR,Additional Interrupt Mask Register"
|
|
bitfld.long 0x4 4. "STA_POLICY_OP_IRQ_MASK,N/A" "0,1"
|
|
bitfld.long 0x4 3. "STA_POLICY_PWR_IRQ_MASK,N/A" "0,1"
|
|
bitfld.long 0x4 2. "DYN_DENY_IRQ_MASK,Dynamic transition denial event mask." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DYN_ACCEPT_IRQ_MASK,Dynamic transition acceptance event mask." "0,1"
|
|
bitfld.long 0x4 0. "UNSPT_POLICY_IRQ_MASK,Unsupported Policy event mask." "0,1"
|
|
line.long 0x8 "ISR,Interrupt Status Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "OP_ACTIVE_EDGE_IRQ,N/A"
|
|
hexmask.long.word 0x8 8.--18. 1. "PWR_ACTIVE_EDGE_IRQ,N/A"
|
|
rbitfld.long 0x8 7. "OTHER_IRQ,Indicates there is an interrupt event pending in the Additional Interrupt Status Register (PPU_AISR)." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "LOCKED_IRQ,N/A" "0,1"
|
|
bitfld.long 0x8 4. "EMU_DENY_IRQ,N/A" "0,1"
|
|
bitfld.long 0x8 3. "EMU_ACCEPT_IRQ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "STA_DENY_IRQ,Static transition denial event status." "0,1"
|
|
bitfld.long 0x8 1. "STA_ACCEPT_IRQ,Static transition acceptance event status." "0,1"
|
|
bitfld.long 0x8 0. "STA_POLICY_TRN_IRQ,Static full policy transition completion event status." "0,1"
|
|
line.long 0xC "AISR,Additional Interrupt Status Register"
|
|
bitfld.long 0xC 4. "STA_POLICY_OP_IRQ,N/A" "0,1"
|
|
bitfld.long 0xC 3. "STA_POLICY_PWR_IRQ,N/A" "0,1"
|
|
bitfld.long 0xC 2. "DYN_DENY_IRQ,Dynamic transition denial event status." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "DYN_ACCEPT_IRQ,Dynamic transition acceptance event status." "0,1"
|
|
bitfld.long 0xC 0. "UNSPT_POLICY_IRQ,Unsupported Policy event status." "0,1"
|
|
line.long 0x10 "IESR,Input Edge Sensitivity Register"
|
|
bitfld.long 0x10 20.--21. "DEVACTIVE10_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "DEVACTIVE09_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "DEVACTIVE08_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "DEVACTIVE07_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "DEVACTIVE06_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "DEVACTIVE05_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 8.--9. "DEVACTIVE04_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "DEVACTIVE03_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "DEVACTIVE02_EDGE,DEVACTIVE 2 edge sensitivity." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 2.--3. "DEVACTIVE01_EDGE,DEVACTIVE 1 edge sensitivity." "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "DEVACTIVE00_EDGE,DEVACTIVE 0 edge sensitivity." "0,1,2,3"
|
|
line.long 0x14 "OPSR,Operating Mode Active Edge Sensitivity Register"
|
|
bitfld.long 0x14 14.--15. "DEVACTIVE23_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. "DEVACTIVE22_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. "DEVACTIVE21_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 8.--9. "DEVACTIVE20_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "DEVACTIVE19_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. "DEVACTIVE18_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 2.--3. "DEVACTIVE17_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. "DEVACTIVE16_EDGE,N/A" "0,1,2,3"
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "FUNRR,Functional Retention RAM Configuration Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FUNC_RET_RAM_CFG,N/A"
|
|
line.long 0x4 "FULRR,Full Retention RAM Configuration Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "FULL_RET_RAM_CFG,N/A"
|
|
line.long 0x8 "MEMRR,Memory Retention RAM Configuration Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "MEM_RET_RAM_CFG,N/A"
|
|
group.long 0x160++0x7
|
|
line.long 0x0 "EDTR0,Power Mode Entry Delay Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "FULL_RET_DEL,N/A"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LOGIC_RET_DEL,N/A"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MEM_RET_DEL,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "OFF_DEL,N/A"
|
|
line.long 0x4 "EDTR1,Power Mode Entry Delay Register 1"
|
|
hexmask.long.byte 0x4 8.--15. 1. "FUNC_RET_DEL,N/A"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MEM_OFF_DEL,N/A"
|
|
rgroup.long 0x170++0x7
|
|
line.long 0x0 "DCDR0,Device Control Delay Configuration Register 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RST_HWSTAT_DLY,N/A"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ISO_CLKEN_DLY,N/A"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CLKEN_RST_DLY,N/A"
|
|
line.long 0x4 "DCDR1,Device Control Delay Configuration Register 1"
|
|
hexmask.long.byte 0x4 8.--15. 1. "CLKEN_ISO_DLY,N/A"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ISO_RST_DLY,N/A"
|
|
rgroup.long 0xFB0++0x7
|
|
line.long 0x0 "IDR0,PPU Identification Register 0"
|
|
bitfld.long 0x0 29. "DYN_WRM_RST_SPT,Dynamic WARM_RST support." "0,1"
|
|
bitfld.long 0x0 28. "DYN_ON_SPT,Dynamic ON support." "0,1"
|
|
bitfld.long 0x0 27. "DYN_FUNC_RET_SPT,Dynamic FUNC_RET support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "DYN_FULL_RET_SPT,Dynamic FULL_RET support." "0,1"
|
|
bitfld.long 0x0 25. "DYN_MEM_OFF_SPT,Dynamic MEM_OFF support." "0,1"
|
|
bitfld.long 0x0 24. "DYN_LGC_RET_SPT,Dynamic LOGIC_RET support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DYN_MEM_RET_EMU_SPT,Dynamic MEM_RET_EMU support" "0,1"
|
|
bitfld.long 0x0 22. "DYN_MEM_RET_SPT,Dynamic MEM_RET support." "0,1"
|
|
bitfld.long 0x0 21. "DYN_OFF_EMU_SPT,Dynamic OFF_EMU support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DYN_OFF_SPT,Dynamic OFF support." "0,1"
|
|
bitfld.long 0x0 18. "STA_DBG_RECOV_SPT,DBG_RECOV support." "0,1"
|
|
bitfld.long 0x0 17. "STA_WRM_RST_SPT,WARM_RST support. Ignore this bit. Do not use WARM_RST." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "STA_ON_SPT,ON support." "0,1"
|
|
bitfld.long 0x0 15. "STA_FUNC_RET_SPT,FUNC_RET support." "0,1"
|
|
bitfld.long 0x0 14. "STA_FULL_RET_SPT,FULL_RET support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "STA_MEM_OFF_SPT,MEM_OFF support." "0,1"
|
|
bitfld.long 0x0 12. "STA_LGC_RET_SPT,LOGIC_RET support." "0,1"
|
|
bitfld.long 0x0 11. "STA_MEM_RET_EMU_SPT,MEM_RET_EMU support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STA_MEM_RET_SPT,MEM_RET support." "0,1"
|
|
bitfld.long 0x0 9. "STA_OFF_EMU_SPT,OFF_EMU support." "0,1"
|
|
bitfld.long 0x0 8. "STA_OFF_SPT,OFF support." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "NUM_OPMODE,No. of operating modes supported is NUM_OPMODE + 1."
|
|
hexmask.long.byte 0x0 0.--3. 1. "DEVCHAN,No. of Device Interface Channels."
|
|
line.long 0x4 "IDR1,PPU Identification Register 1"
|
|
bitfld.long 0x4 12. "OFF_MEM_RET_TRANS,OFF to MEM_RET direct transition. Indicates if direct transitions from OFF to MEM_RET and from OFF_EMU to MEM_RET_EMU are supported." "0,1"
|
|
bitfld.long 0x4 10. "OP_ACTIVE,N/A" "0,1"
|
|
bitfld.long 0x4 9. "STA_POLICY_OP_IRQ_SPT,Operating policy transition completion event status." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "STA_POLICY_PWR_IRQ_SPT,Power policy transition completion event status." "0,1"
|
|
bitfld.long 0x4 6. "FUNC_RET_RAM_REG,N/A" "0,1"
|
|
bitfld.long 0x4 5. "FULL_RET_RAM_REG,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MEM_RET_RAM_REG,N/A" "0,1"
|
|
bitfld.long 0x4 2. "LOCK_SPT,Lock and the lock interrupt event are supported." "0,1"
|
|
bitfld.long 0x4 1. "SW_DEV_DEL_SPT,Software device delay control configuration support." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PWR_MODE_ENTRY_DEL_SPT,Power mode entry delay support." "0,1"
|
|
rgroup.long 0xFC8++0xB
|
|
line.long 0x0 "IIDR,Implementation Identification Register"
|
|
hexmask.long.word 0x0 20.--31. 1. "PRODUCT_ID,PPU part identification."
|
|
hexmask.long.byte 0x0 16.--19. 1. "VARIANT,Major revision of the product."
|
|
hexmask.long.byte 0x0 12.--15. 1. "REVISION,Minor revision of the product."
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "IMPLEMENTER,Implementer identification. [11:8] The JEP106 continuation code of the implementer. [7] Always 0. [6:0] The JEP106 identity code of the implementer. For an Arm implementation bits [11:0] are 0x43B."
|
|
line.long 0x4 "AIDR,Architecture Identification Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "ARCH_REV_MAJOR,N/A"
|
|
hexmask.long.byte 0x4 0.--3. 1. "ARCH_REV_MINOR,N/A"
|
|
line.long 0x8 "PID4,Implementation Defined Identification Register (PID4)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "IMPLEMENTER_11_8,The JEP106 continuation code of the implementer which is 0x4 hardcoded value."
|
|
rgroup.long 0xFE0++0x1F
|
|
line.long 0x0 "PID0,Implementation Defined Identification Register (PID0)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PRODUCT_ID_7_0,PPU part identification bits [7:0]."
|
|
line.long 0x4 "PID1,Implementation Defined Identification Register (PID1)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "IMPLEMENTER_3_0,JEP106_ID bits [3:0]"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRODUCT_ID_11_8,PPU part identification bits [11:8]"
|
|
line.long 0x8 "PID2,Implementation Defined Identification Register (PID2)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "REV_CONST,Constant LOW Revision (4 bits)"
|
|
bitfld.long 0x8 3. "CONST_HIGH,Constant HIGH" "0,1"
|
|
bitfld.long 0x8 0.--2. "IMPLEMENTER_6_4,JEP106_ID bits [6:4]" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "PID3,Implementation Defined Identification Register (PID3)"
|
|
hexmask.long.byte 0xC 4.--7. 1. "PID3_REVISION,Minor revision of the product."
|
|
hexmask.long.byte 0xC 0.--3. 1. "PID3_REV_CONST,Constant LOW (4 bits)"
|
|
line.long 0x10 "ID0,Implementation Defined Identification Register (ID0)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "ID0,ID0 hard coded value"
|
|
line.long 0x14 "ID1,Implementation Defined Identification Register (ID1)"
|
|
hexmask.long.byte 0x14 0.--7. 1. "ID1,ID1 hardcoded value"
|
|
line.long 0x18 "ID2,Implementation Defined Identification Register (ID2)"
|
|
hexmask.long.byte 0x18 0.--7. 1. "ID2,ID2 hardcoded value"
|
|
line.long 0x1C "ID3,Implementation Defined Identification Register (ID3)"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "ID3,ID3 hardcoded value"
|
|
tree.end
|
|
tree "CPUSS_SL_CTL (SYSCPUSS Internal Slave Control Registers)"
|
|
base ad:0x421C8000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "SL_CTL,Slave control (Clock enables)"
|
|
bitfld.long 0x0 11. "FAULT_ENABLED,N/A" "0,1"
|
|
bitfld.long 0x0 10. "IPC_ENABLED,N/A" "0,1"
|
|
bitfld.long 0x0 9. "DMAC1_ENABLED,N/A" "0,1"
|
|
bitfld.long 0x0 8. "DMAC0_ENABLED,N/A" "0,1"
|
|
bitfld.long 0x0 7. "DW1_ENABLED,N/A" "0,1"
|
|
bitfld.long 0x0 6. "DW0_ENABLED,N/A" "0,1"
|
|
bitfld.long 0x0 5. "RAMC2_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RAMC1_ENABLED,N/A" "0,1"
|
|
bitfld.long 0x0 3. "RAMC0_ENABLED,N/A" "0,1"
|
|
bitfld.long 0x0 2. "FLASHC_ENABLED,N/A" "0,1"
|
|
bitfld.long 0x0 1. "RRAMC_ENABLED,N/A" "0,1"
|
|
bitfld.long 0x0 0. "PROMC_ENABLED,Slave enable controls. Each bit indicates whether the respective slave is enabled or not." "0: Disabled,1: Enabled"
|
|
line.long 0x4 "SL_CTL2,Slave control2 (Reset enables)"
|
|
bitfld.long 0x4 11. "FAULT_RST,N/A" "0,1"
|
|
bitfld.long 0x4 10. "IPC_RST,N/A" "0,1"
|
|
bitfld.long 0x4 9. "DMAC1_RST,N/A" "0,1"
|
|
bitfld.long 0x4 8. "DMAC0_RST,N/A" "0,1"
|
|
bitfld.long 0x4 7. "DW1_RST,N/A" "0,1"
|
|
bitfld.long 0x4 6. "DW0_RST,N/A" "0,1"
|
|
bitfld.long 0x4 5. "RAMC2_RST,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RAMC1_RST,N/A" "0,1"
|
|
bitfld.long 0x4 3. "RAMC0_RST,N/A" "0,1"
|
|
bitfld.long 0x4 2. "FLASHC_RST,N/A" "0,1"
|
|
bitfld.long 0x4 1. "RRAMC_RST,N/A" "0,1"
|
|
bitfld.long 0x4 0. "PROMC_RST,Slave reset controls. Each bit indicates whether the respective slave reset is enabled or not." "0: Disabled,1: Enabled"
|
|
tree.end
|
|
tree "CRYPTOLITE (Cryptographic Accelerator)"
|
|
base ad:0x42230000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CTL,Control"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,Master identifier of the cryptography IP. This is a design time configurable parameter."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
line.long 0x4 "STATUS,Status"
|
|
bitfld.long 0x4 0. "BUSY,Busy indication:" "0: IP not busy,1: IP busy"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "AES_DESCR,AES descriptor pointer"
|
|
hexmask.long 0x0 2.--31. 1. "PTR,AES descriptor pointer. The descriptor points to a structure with 32-bit words:"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "VU_DESCR,VU descriptor pointer"
|
|
hexmask.long 0x0 2.--31. 1. "PTR,VU descriptor pointer. The descriptor points to a structure with 32-bit words:"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "SHA_DESCR,SHA descriptor pointer"
|
|
hexmask.long 0x0 2.--31. 1. "PTR,SHA-256 descriptor pointer. The descriptor points to a structure with 32-bit words:"
|
|
group.long 0xF0++0xB
|
|
line.long 0x0 "INTR_ERROR,Error interrupt"
|
|
bitfld.long 0x0 0. "BUS_ERROR,AHB-Lite master interface bus error or ECC error. Note that the IP terminates its AES SHA or VU functionality when it detects an error." "0,1"
|
|
line.long 0x4 "INTR_ERROR_SET,Error interrupt set"
|
|
bitfld.long 0x4 0. "BUS_ERROR,Write this field with '1' to set corresponding INTR_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_ERROR_MASK,Error interrupt mask"
|
|
bitfld.long 0x8 0. "BUS_ERROR,Mask for corresponding field in INTR_ERROR register." "0,1"
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "INTR_ERROR_MASKED,Error interrupt masked"
|
|
bitfld.long 0x0 0. "BUS_ERROR,Logical and of corresponding INTR_ERROR and INTR_ERROR_MASK fields." "0,1"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "TRNG_CTL0,TRNG control 0"
|
|
bitfld.long 0x0 29. "STOP_ON_RC_DETECT,Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR_ERROR.TRNG_RC_DETECT to '1'):" "0: Functionality is NOT stopped,1: Functionality is stopped"
|
|
bitfld.long 0x0 28. "STOP_ON_AP_DETECT,Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR_ERROR.TRNG_AP_DETECT to '1'):" "0: Functionality is NOT stopped,1: Functionality is stopped"
|
|
newline
|
|
bitfld.long 0x0 25. "FEEDBACK_EN,Specifies if the feedback of the reducution state is enabled:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 24. "VON_NEUMANN_CORR,Specifies if the 'von Neumann corrector' is disabled or enabled:" "0: no bit is produced,1: '0' bit is produced"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "INIT_DELAY,Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range [1 255]. After starting the oscillators at least the first 2 samples should be.."
|
|
hexmask.long.byte 0x0 8.--15. 1. "RED_CLOCK_DIV,Specifies the clock divider that is used to produce reduced bits."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "SAMPLE_CLOCK_DIV,Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. The IP clock."
|
|
line.long 0x4 "TRNG_CTL1,TRNG control 1"
|
|
bitfld.long 0x4 5. "FIRO31_EN,FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TRNG_FIRO_CTL register specifies the programmable polynomial." "0,1"
|
|
bitfld.long 0x4 4. "FIRO15_EN,FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "GARO31_EN,FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters. The TRNG_GARO_CTL register specifies the programmable polynomial." "0,1"
|
|
bitfld.long 0x4 2. "GARO15_EN,FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RO15_EN,FW sets this field to '1' to enable the ring oscillator with 15 inverters." "0,1"
|
|
bitfld.long 0x4 0. "RO11_EN,FW sets this field to '1' to enable the ring oscillator with 11 inverters." "0,1"
|
|
rgroup.long 0x10C++0x7
|
|
line.long 0x0 "TRNG_STATUS,TRNG status"
|
|
bitfld.long 0x0 0. "INITIALIZED,Reflects the state of the true random number generator:" "0: Not initialized,1: Initialized"
|
|
line.long 0x4 "TRNG_RESULT,TRNG result"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Generated 32-bit true random number. The INTR.DATA_AVAILABLE interrupt cause is activated when the number is generated."
|
|
group.long 0x120++0x7
|
|
line.long 0x0 "TRNG_GARO_CTL,TRNG GARO control"
|
|
hexmask.long 0x0 0.--30. 1. "POLYNOMIAL,Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the.."
|
|
line.long 0x4 "TRNG_FIRO_CTL,TRNG FIRO control"
|
|
hexmask.long 0x4 0.--30. 1. "POLYNOMIAL,Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain.."
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "TRNG_MON_CTL,TRNG monitor control"
|
|
bitfld.long 0x0 9. "RC,Repetition count (RC) test enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 8. "AP,Adaptive proportion (AP) test enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "BITSTREAM_SEL,Selection of the bitstream:" "0: DAS bitstream,1: RED bitstream,2: TR bitstream,3: Undefined"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "TRNG_MON_RC_CTL,TRNG monitor RC control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CUTOFF_COUNT8,Cutoff count (legal range is [1 255]):"
|
|
rgroup.long 0x158++0x7
|
|
line.long 0x0 "TRNG_MON_RC_STATUS0,TRNG monitor RC status 0"
|
|
bitfld.long 0x0 0. "BIT,Current active bit value:" "0: '0',1: '1'"
|
|
line.long 0x4 "TRNG_MON_RC_STATUS1,TRNG monitor RC status 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "REP_COUNT,Number of repetitions of the current active bit counter:"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "TRNG_MON_AP_CTL,TRNG monitor AP control"
|
|
hexmask.long.word 0x0 16.--31. 1. "WINDOW_SIZE,Window size (minus 1) :"
|
|
hexmask.long.word 0x0 0.--15. 1. "CUTOFF_COUNT16,Cutoff count (legal range is [1 65535])."
|
|
rgroup.long 0x168++0x7
|
|
line.long 0x0 "TRNG_MON_AP_STATUS0,TRNG monitor AP status 0"
|
|
bitfld.long 0x0 0. "BIT,Current active bit value:" "0: '0',1: '1'"
|
|
line.long 0x4 "TRNG_MON_AP_STATUS1,TRNG monitor AP status 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "WINDOW_INDEX,Counter to keep track of the current index in the window (counts from '0' to TRNG_MON_AP_CTL.WINDOW_SIZE to '0')."
|
|
hexmask.long.word 0x4 0.--15. 1. "OCC_COUNT,Number of occurrences of the current active bit counter:"
|
|
group.long 0x1F0++0xB
|
|
line.long 0x0 "INTR_TRNG,TRNG interrupt"
|
|
bitfld.long 0x0 3. "RC_DETECT,This interrupt cause is activated (HW sets the field to '1') when the TRNG monitor detects an 'repetition count' error." "0,1"
|
|
bitfld.long 0x0 2. "AP_DETECT,This interrupt cause is activated (HW sets the field to '1') when the TRNG monitor detects an 'adaptive proportion' error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when 32 bits of TRNG data becomes available in TRNG_RESULT." "0,1"
|
|
bitfld.long 0x0 0. "INITIALIZED,This interrupt cause is activated (HW sets the field to '1') when the TRNG is initialized." "0,1"
|
|
line.long 0x4 "INTR_TRNG_SET,TRNG Interrupt set"
|
|
bitfld.long 0x4 3. "RC_DETECT,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 2. "AP_DETECT,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "INITIALIZED,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TRNG_MASK,TRNG Interrupt mask"
|
|
bitfld.long 0x8 3. "RC_DETECT,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 2. "AP_DETECT,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "INITIALIZED,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
rgroup.long 0x1FC++0x3
|
|
line.long 0x0 "INTR_TRNG_MASKED,TRNG Interrupt masked"
|
|
bitfld.long 0x0 3. "RC_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 2. "AP_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "INITIALIZED,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "DEBUG600 (Debug Interface)"
|
|
base ad:0x42250000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "VERSION,IP Version Information"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MAJOR,IP Major Revision Number"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MINOR,IP Minor Revision Number"
|
|
tree.end
|
|
tree "DW (Data Wire)"
|
|
base ad:0x0
|
|
tree "DW0"
|
|
base ad:0x42180000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,Enable SECDED ECC checking (Single Error Correction Double Error Detection Error Correcting Code Functionality)." "0: Disabled,1: Enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "ACTIVE,Active channel present:" "0: No,1: Yes"
|
|
bitfld.long 0x0 28.--30. "STATE,State of the DW controller." "0: Default/inactive state,1: Loading descriptor,2: Loading data element from source location,3: Storing data element to destination location,4: CRC functionality,5: Update of active control information,6: Error,?"
|
|
hexmask.long.word 0x0 16.--24. 1. "CH_IDX,Active channel index."
|
|
newline
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Active channel preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Active channel priority." "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Active channel protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Active channel non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Active channel secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,Active channel user/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor."
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor."
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ACT_SRC,Active source"
|
|
hexmask.long 0x0 0.--31. 1. "SRC_ADDR,Current address of source location."
|
|
line.long 0x4 "ACT_DST,Active destination"
|
|
hexmask.long 0x4 0.--31. 1. "DST_ADDR,Current address of destination location."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x0 0.--9. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0: No,1: Yes"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0: Most significant bit,1: Least significant bit"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "CRC_LFSR_CTL,CRC LFSR control"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value."
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x148++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x42188000 ad:0x42188040 ad:0x42188080 ad:0x421880C0 ad:0x42188100 ad:0x42188140 ad:0x42188180 ad:0x421881C0 ad:0x42188200 ad:0x42188240 ad:0x42188280 ad:0x421882C0 ad:0x42188300 ad:0x42188340 ad:0x42188380 ad:0x421883C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0: Not preemptable,1: Preemptable"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Refer SRAM_DATA0"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "DW1"
|
|
base ad:0x42190000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,Enable SECDED ECC checking (Single Error Correction Double Error Detection Error Correcting Code Functionality)." "0: Disabled,1: Enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "ACTIVE,Active channel present:" "0: No,1: Yes"
|
|
bitfld.long 0x0 28.--30. "STATE,State of the DW controller." "0: Default/inactive state,1: Loading descriptor,2: Loading data element from source location,3: Storing data element to destination location,4: CRC functionality,5: Update of active control information,6: Error,?"
|
|
hexmask.long.word 0x0 16.--24. 1. "CH_IDX,Active channel index."
|
|
newline
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Active channel preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Active channel priority." "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Active channel protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Active channel non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Active channel secure/non-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,Active channel user/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor."
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor."
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ACT_SRC,Active source"
|
|
hexmask.long 0x0 0.--31. 1. "SRC_ADDR,Current address of source location."
|
|
line.long 0x4 "ACT_DST,Active destination"
|
|
hexmask.long 0x4 0.--31. 1. "DST_ADDR,Current address of destination location."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x0 0.--9. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0: No,1: Yes"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0: Most significant bit,1: Least significant bit"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "CRC_LFSR_CTL,CRC LFSR control"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value."
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x148++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x42198000 ad:0x42198040 ad:0x42198080 ad:0x421980C0 ad:0x42198100 ad:0x42198140 ad:0x42198180 ad:0x421981C0 ad:0x42198200 ad:0x42198240 ad:0x42198280 ad:0x421982C0 ad:0x42198300 ad:0x42198340 ad:0x42198380 ad:0x421983C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0: Not preemptable,1: Preemptable"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0: highest priority,?,?,3: lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0: non-bufferable,1: bufferable"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0: secure,1: non-secure"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0: user mode,1: privileged mode"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Refer SRAM_DATA0"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "EFUSE (EFUSE MXS40 Registers)"
|
|
base ad:0x42610000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "LOCK_CC312_REGION,CC312 lock - when set locks 8 bytes beyond the end of the PROT_MASTER defined space for read access." "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 31. "START,FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed." "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "MACRO_ADDR,Macro address. This field specifies an eFUSE macro."
|
|
hexmask.long.byte 0x0 8.--12. 1. "BYTE_ADDR,Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B)."
|
|
bitfld.long 0x0 4.--6. "BIT_ADDR,Bit address. This field specifies a bit within a Byte." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "BIT_DATA,Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR BYTE_ADDR and MACRO_ADDR fields." "0,1"
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "SEQ_DEFAULT,Sequencer Default value"
|
|
bitfld.long 0x0 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x0 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x0 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x0 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x0 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x0 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
group.long 0x140++0x3F
|
|
line.long 0x0 "SEQ_READ_CTL_0,Sequencer read control 0"
|
|
bitfld.long 0x0 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x0 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x0 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x0 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x0 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x0 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x0 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x4 "SEQ_READ_CTL_1,Sequencer read control 1"
|
|
bitfld.long 0x4 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x4 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x4 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x4 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x4 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x4 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x4 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x8 "SEQ_READ_CTL_2,Sequencer read control 2"
|
|
bitfld.long 0x8 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x8 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x8 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x8 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x8 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x8 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x8 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0xC "SEQ_READ_CTL_3,Sequencer read control 3"
|
|
bitfld.long 0xC 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0xC 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0xC 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0xC 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0xC 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0xC 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0xC 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x10 "SEQ_READ_CTL_4,Sequencer read control 4"
|
|
bitfld.long 0x10 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x10 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x10 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x10 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x10 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x10 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x10 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x10 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x14 "SEQ_READ_CTL_5,Sequencer read control 5"
|
|
bitfld.long 0x14 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x14 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x14 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x14 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x14 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x14 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x14 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x14 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x18 "SEQ_READ_CTL_6,Sequencer read control 6"
|
|
bitfld.long 0x18 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x18 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x18 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x18 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x18 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x18 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x18 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x18 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x18 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x1C "SEQ_READ_CTL_7,Sequencer read control 7"
|
|
bitfld.long 0x1C 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x1C 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x1C 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x1C 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x1C 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x1C 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x1C 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x1C 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x20 "SEQ_PROGRAM_CTL_0,Sequencer program control 0"
|
|
bitfld.long 0x20 31. "DONE,When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x20 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x20 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x20 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x20 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x20 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x20 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x20 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x20 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x24 "SEQ_PROGRAM_CTL_1,Sequencer program control 1"
|
|
bitfld.long 0x24 31. "DONE,When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x24 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x24 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x24 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x24 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x24 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x24 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x24 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x24 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x28 "SEQ_PROGRAM_CTL_2,Sequencer program control 2"
|
|
bitfld.long 0x28 31. "DONE,When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x28 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x28 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x28 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x28 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x28 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x28 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x28 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x28 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x2C "SEQ_PROGRAM_CTL_3,Sequencer program control 3"
|
|
bitfld.long 0x2C 31. "DONE,When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x2C 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x2C 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x2C 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x2C 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x2C 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x2C 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x2C 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x30 "SEQ_PROGRAM_CTL_4,Sequencer program control 4"
|
|
bitfld.long 0x30 31. "DONE,When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x30 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x30 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x30 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x30 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x30 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x30 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x30 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x30 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x34 "SEQ_PROGRAM_CTL_5,Sequencer program control 5"
|
|
bitfld.long 0x34 31. "DONE,When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x34 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x34 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x34 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x34 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x34 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x34 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x34 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x34 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x38 "SEQ_PROGRAM_CTL_6,Sequencer program control 6"
|
|
bitfld.long 0x38 31. "DONE,When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x38 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x38 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x38 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x38 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x38 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x38 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x38 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x38 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x3C "SEQ_PROGRAM_CTL_7,Sequencer program control 7"
|
|
bitfld.long 0x3C 31. "DONE,When set to 1 indicates that the Program cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x3C 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x3C 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x3C 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x3C 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x3C 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x3C 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x3C 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
rgroup.long 0x180++0x3
|
|
line.long 0x0 "BOOTROW,Content of Boot Row latches at power-on-reset"
|
|
hexmask.long 0x0 0.--31. 1. "BOOT_ROW_DATA,Contains the Boot Row data held by the Boot Row latches."
|
|
tree.end
|
|
tree "FAULT (Fault Monitoring)"
|
|
base ad:0x421E0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Fault control"
|
|
bitfld.long 0x0 2. "RESET_REQ_EN,Reset request enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 1. "OUT_EN,IO output signal enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "TR_EN,Trigger output enable:" "0: Disabled,1: Enabled"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "STATUS,Fault status"
|
|
bitfld.long 0x0 31. "VALID,N/A" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "IDX,The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "DATA[$1],Fault data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Captured fault source data."
|
|
repeat.end
|
|
rgroup.long 0x40++0xB
|
|
line.long 0x0 "PENDING0,Fault pending 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,This field specifies the fault source. The list of fault sources is in the product.xls in the 'Faults' tab."
|
|
line.long 0x4 "PENDING1,Fault pending 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x8 "PENDING2,Fault pending 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "MASK0,Fault mask 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x4 "MASK1,Fault mask 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x8 "MASK2,Fault mask 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,Fault source enables:"
|
|
group.long 0xC0++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "FAULT,This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured:" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 0. "FAULT,SW writes a '1' to this field to set the corresponding field in the INTR register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 0. "FAULT,Mask bit for corresponding field in the INTR register." "0,1"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "FAULT,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
tree "FLASHC (FLASH Registers)"
|
|
base ad:0x42150000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLASH_CTL,Flash control"
|
|
bitfld.long 0x0 27. "BLOCK_BULK_OPERATIONS,This bit can be set once and not cleared thereafter. When set it is no longer possible to perform bulk erase or bulk DFT operations. The flash controller will block any write operations to the FM_CTL register pertaining to such.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "BLOCK_SUBSECTOR_OPERATIONS,This bit can be set once and not cleared thereafter. When set it is no longer possible to perform subsector erase or subsector DFT operations. The flash controller will block any write operations to the FM_CTL register.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "BLOCK_SECTOR_OPERATIONS,This bit can be set once and not cleared thereafter. When set it is no longer possible to perform sector erase or sector DFT operations. The flash controller will block any write operations to the FM_CTL register pertaining to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "ENFORCE_PC_LOCK,This bit can be set once and not cleared thereafter. When set the PC inheritiance and locking mechanism described with the FLASH_LOCK register is enabled. When cleared access to the flash controller and flash macro is possible from any.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RBUS_ERR_SILENT,Please note that it is SW's responsibility that I of M33 must be disabled before setting RBUS_ERR_SILENT HIGH. Otherwise the erroneous goes to I which is NOT desired." "0: Bus transfer has a bus error,1: Bus transfer does NOT have a bus error"
|
|
newline
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking for FLASH main (R-bus) interface:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 12. "BANK_MODE,Specifies bank mode of FLASH macro main array." "0: Single bank mode,1: Dual bank mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "BANK_MAPPING,Specifies mapping of FLASH macro main subregion." "0: MAIN,1: MAIN,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "RBUS_WS,FLASH macro main interface (R-bus) wait states:"
|
|
rgroup.long 0x104++0x13
|
|
line.long 0x0 "FLASH_SECTOR_M,# of sector of a FM"
|
|
hexmask.long 0x0 0.--31. 1. "SECTOR_M,# of sectors of a FM must be an even number same value as RTL parameter SECTOR_M."
|
|
line.long 0x4 "FLASH_MAIN_N,Size of MAIN in 8KB block for each pair of sectors"
|
|
hexmask.long 0x4 0.--31. 1. "MAIN_N,Size of MAIN_NVM in 8KB blocks for each pair of sectors same value as RTL parameter MAIN_N."
|
|
line.long 0x8 "FLASH_WORK_Z,Size of WORK in 8KB block for each pair of sectors"
|
|
hexmask.long 0x8 0.--31. 1. "WORK_Z,Size of WORK_NVM in 8KB blocks for each pair of sectors same value as RTL parameter WORK_Z the value WORK_Z can be zero."
|
|
line.long 0xC "FLASH_SFLASH_Y,Size of SLFASH in 8KB block in Sector 1"
|
|
bitfld.long 0xC 31. "SFLASH_SECNUM,0: Not allowed" "0: Not allowed,1: SM only in Sector 1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "SFLASH_Y,Size of SFLASH_NVM in 8KB blocks in Sector 1 same value as RTL parameter SFLASH_Y."
|
|
line.long 0x10 "FLASH_REFRESH_ROW,Size of refresh rows for each sector"
|
|
hexmask.long 0x10 0.--31. 1. "REFRESH_ROW,Size of refresh rows for each sector same value as RTL parameter REFRESH_ROW"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "FLASH_CMD,Command"
|
|
bitfld.long 0x0 1. "BUFF_INV,Invalidation of ALL buffers. SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles." "0,1"
|
|
line.long 0x4 "FLASH_LOCK,Flash Controller Lock Register"
|
|
bitfld.long 0x4 31. "LOCKED,Software writes this register bit to 1 to 'lock' the flash controller to its own protection context (after setting the protection context by writing to a flash memory location)." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "PC,When FLASH_LOCK is acquired even PPC allows further MMIO access is possible only to this FLASH_LOCK.PC (& same HMASTER_ID) irrespective of corresponding PPC attributes. Other PCs or the same PC but different HMASTER_ID violation results in bus error.."
|
|
line.long 0x8 "FLASH_PWR_CTL,Flash power control"
|
|
bitfld.long 0x8 1. "ENABLE_HV,Controls 'enable_hv' pin of the Flash memory." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ENABLE,Controls 'enable' pin of the Flash memory." "0,1"
|
|
rgroup.long 0x20C++0x3
|
|
line.long 0x0 "ENFORCE_PC_LOCK_SHADOW,Shadow bit of FLASH_CTL.ENFORCE_PC_LOCK"
|
|
bitfld.long 0x0 0. "PC_LOCK_SHADOW,Shadow register of FLASH_CTL.ENFORCE_PC_LOCK. Read only irrespective of PPC's configuration." "0,1"
|
|
group.long 0x800++0xB
|
|
line.long 0x0 "ECC_INJ_EN,ECC injection enable on read"
|
|
hexmask.long.byte 0x0 28.--31. 1. "ECC_INJ_PC,The PC is inherited from the master who enabled ECC_INJ_ENABLE (while ECC_INJ_ENABLE is low)"
|
|
newline
|
|
bitfld.long 0x0 8. "ECC_ERROR,1'b0: If the injected ECC does not trigger any non-recoverable error (ECC errors <= 1)." "0: If the injected ECC does not trigger any..,1: If the injected ECC triggers non-recoverable error"
|
|
newline
|
|
bitfld.long 0x0 0. "ECC_INJ_ENABLE,Enable ECC error injection for FLASH R-bus interface (while FLASH_CTL.ECC_EN enabled) ." "0: ECC_INJ_EN is disabled,1: ECC_INJ_EN is enabled"
|
|
line.long 0x4 "ECC_INJ_CTL,ECC injection control"
|
|
hexmask.long.word 0x4 23.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
newline
|
|
hexmask.long.tbyte 0x4 0.--22. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
line.long 0x8 "ECC_LOGIR,Interrupt threshold for number of ECC correctable error"
|
|
hexmask.long.word 0x8 16.--31. 1. "ECC1CNT,Number of ECC single-bit failures detected and corrected during the memory read operations"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "ECCTHRESHOLD,Interrupt/fault threshold for number of ECC single-bit failures indicated in"
|
|
tree "FM_CTL"
|
|
base ad:0x42152000
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "RED_CTL01,Redundancy Control normal sectors 0.1"
|
|
bitfld.long 0x0 25. "RED_AXA,'1': Redundancy Enable for SM Rows in Sector 1; Uses RED_ADDR_1 bits for Bad Row Pair Address" "?,1: Redundancy Enable for SM Rows in Sector 1"
|
|
newline
|
|
bitfld.long 0x0 24. "RED_EN_1,'1': Redundancy Enable for Sector 1" "?,1: Redundancy Enable for Sector 1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RED_ADDR_1,Bad Row Pair Address for Sector 1"
|
|
newline
|
|
bitfld.long 0x0 8. "RED_EN_0,'1': Redundancy Enable for Sector 0" "?,1: Redundancy Enable for Sector 0"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RED_ADDR_0,Bad Row Pair Address for Sector 0"
|
|
line.long 0x4 "RED_CTL23,Redundancy Control normal sectors 2.3"
|
|
bitfld.long 0x4 24. "RED_EN_3,1': Redundancy Enable for Sector 3" "?,1: Redundancy Enable for Sector 3"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "RED_ADDR_3,Bad Row Pair Address for Sector 3"
|
|
newline
|
|
bitfld.long 0x4 8. "RED_EN_2,1': Redundancy Enable for Sector 2" "?,1: Redundancy Enable for Sector 2"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RED_ADDR_2,Bad Row Pair Address for Sector 2"
|
|
repeat 132. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x800)++0x3
|
|
line.long 0x0 "FM_PL_DATA[$1],Flash macro Page Latches data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Normal PL data read: four page latch Bytes"
|
|
repeat.end
|
|
group.long 0xA10++0x3
|
|
line.long 0x0 "FLASH_MACRO_CTL,Flash macro control"
|
|
bitfld.long 0x0 25. "WR_EN,0: normal mode" "0: normal mode,1: Fm Write Enable"
|
|
newline
|
|
bitfld.long 0x0 24. "IF_SEL,Interface selection. Specifies the interface that is used for flash memory read operations:" "0: R interface is used,1: C interface is used"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DAA_MUX_SEL,Direct memory cell access address."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FM_SEQ,Requires (IF_SEL|WR_EN)=1" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "FM_MODE,Requires (IF_SEL|WR_EN)=1"
|
|
rgroup.long 0xA14++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PUMP_NDAC,Test_only internal node: regif ndac outputs to pos pump"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PUMP_PDAC,Test_only internal node: regif pdac outputs to pos pump"
|
|
newline
|
|
bitfld.long 0x0 23. "RQ_ERROR,Test_only internal node: rq_error sync-de in clk_c domain" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CBUS_RED_ROW_EN,Test_only internal node: mpcon red_row_en" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CBUS_RA_MATCH,Test_only internal node: mpcon ra match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "HVOP_BULK_ALL,Test_only internal node: mpcon bk_all" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "HVOP_SECTOR,Test_only internal node: mpcon bk_sec" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "HVOP_SUB_SECTOR_N,Test_only internal node: mpcon bk_subb" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ROW_EVEN,Test_only internal node: mpcon row_even" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ROW_ODD,Test_only internal node: mpcon row_odd" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RESET_MM,Test_only internal node: mpcon reset_mm" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "SECTOR1_SR,0: Sector 1 does not contain special rows. The special rows are located in separate special sectors." "0: Sector 1 does not contain special rows,1: Sector 1 contains special rows"
|
|
newline
|
|
bitfld.long 0x0 13. "ECC_CFG,Geometry ECC configuration:" "0: FM with No ECC,1: FM with ECC"
|
|
newline
|
|
bitfld.long 0x0 12. "RWW,FM Type (Read While Write or Not Read While Write):" "0: Non RWW FM Type,1: RWW FM Type"
|
|
newline
|
|
bitfld.long 0x0 11. "NEG_PUMP_VHI,NEG pump VHI" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "POS_PUMP_VLO,POS pump VLO" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "FM_READY,0: FM not ready" "0: FM not ready,1: FM ready"
|
|
newline
|
|
bitfld.long 0x0 8. "FM_BUSY,0': FM not busy" "0: FM not busy,1: FM BUSY : R_GRANT is 0 as result of a busy.."
|
|
newline
|
|
bitfld.long 0x0 7. "R_GRANT_DELAY_STATUS,0: R_GRANT_DELAY timer is not running" "0: R_GRANT_DELAY timer is not running,1: R_GRANT_DELAY timer is running"
|
|
newline
|
|
bitfld.long 0x0 6. "TIMER_PE_SYNC,The actual timer state sync-ed in clk_c domain:" "0: timer is not running:,1: timer is running"
|
|
newline
|
|
bitfld.long 0x0 5. "IF_SEL_MON,FM_CTL.IF_SEL bit after being synchronized in clk_r domain" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "WR_EN_MON,FM_CTL.WR_EN bit after being synchronized in clk_r domain" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TURBO_N,After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.." "0: turbo mode,1: normal mode"
|
|
newline
|
|
bitfld.long 0x0 2. "ILLEGAL_HVOP,Indicates a bulk sector erase program has been requested when axa=1" "0: no error,1: illegal HV operation error"
|
|
newline
|
|
bitfld.long 0x0 1. "HV_REGS_ISOLATED,Indicates the isolation status at HV trim and redundancy registers inputs" "0: Not isolated,1: isolated writing disabled"
|
|
newline
|
|
bitfld.long 0x0 0. "TIMER_STATUS,This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires" "0: timer not running,1: Timer is enabled and not expired yet"
|
|
group.long 0xA18++0x7
|
|
line.long 0x0 "FM_ADDR,Flash macro address"
|
|
bitfld.long 0x0 24. "AXA,Auxiliairy address field:" "0: regular flash memory,1: supervisory flash memory"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "BA,Bank address."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RA,Row address."
|
|
line.long 0x4 "BOOKMARK,Bookmark register - keeps the current FW HV seq"
|
|
hexmask.long 0x4 0.--31. 1. "BOOKMARK,Used by FW. Keeps the Current HV cycle sequence"
|
|
rgroup.long 0xA20++0x7
|
|
line.long 0x0 "GEOMETRY,Regular flash geometry"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PAGE_SIZE_LOG2,Number of Bytes per page (log 2):"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "WORD_SIZE_LOG2,Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access:"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "BANK_COUNT,Number of banks (minus 1):"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "ROW_COUNT,Number of rows (minus 1):"
|
|
line.long 0x4 "GEOMETRY_SUPERVISORY,Supervisory flash geometry"
|
|
hexmask.long.byte 0x4 28.--31. 1. "PAGE_SIZE_LOG2,Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2."
|
|
newline
|
|
hexmask.long.byte 0x4 24.--27. 1. "WORD_SIZE_LOG2,Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "BANK_COUNT,Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT."
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "ROW_COUNT,Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT"
|
|
group.long 0xA28++0x2F
|
|
line.long 0x0 "ANA_CTL0,Analog control 0"
|
|
bitfld.long 0x0 30.--31. "SCALE_PRG_PEOFF,PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "SCALE_PRG_PEON,PROG&PRE_PROG: Scale for R_GRANT_DELAY on PE On transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SCALE_SEQ30,PROG&PRE_PROG& ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SCALE_PRG_SEQ23,PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "SCALE_PRG_SEQ12,PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SCALE_PRG_SEQ01,PROG&PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PDAC_MIN,PDAC staircase min value"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "NDAC_MIN,NDAC staircase min value"
|
|
newline
|
|
bitfld.long 0x0 11. "FLIP_AMUXBUS_AB,Flips amuxbusa and amuxbusb" "0: amuxbusa,1: amuxbusb"
|
|
newline
|
|
bitfld.long 0x0 10. "RST_SFT_HVPL,1: Page Latches Soft Reset" "?,1: Page Latches Soft Reset"
|
|
newline
|
|
rbitfld.long 0x0 9. "DNU_2_TM_ECC_DIS,Do Not Use this bit as it is for test Mode use only. Write only to 0 in normal mode (tm_ecc_dis in RTL)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ECC_ENC_DIS,0': ECC encoder is enabled for the FM with ECC feature. The PL ECC bits are loaded automatically" "0: ECC encoder is enabled for the FM with ECC feature,1: ECC encoder disabled"
|
|
newline
|
|
bitfld.long 0x0 7. "SPARE_ANA_CTL0,Spare bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "MDAC,Trimming of the output margin Voltage as a function of Vpos and Vneg."
|
|
line.long 0x4 "ANA_CTL1,Analog control 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "NPDAC_ZERO_TIME,Ndac/Pdac LO duration: (1uS .. 255uS) * 8"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "NPDAC_STEP_TIME,Ndac/Pdac step duration: (1uS .. 255uS) * 8"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "PDAC_STEP,Pdac step increment"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "PDAC_MAX,Pdac Max Value.Trimming of positive pump output Voltage:"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "NDAC_STEP,Ndac step increment"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "NDAC_MAX,Ndac Max Value.Trimming of negative pump output Voltage."
|
|
line.long 0x8 "FM_PL_WRDATA_ALL,Flash macro write page latches all"
|
|
hexmask.long 0x8 0.--31. 1. "DATA32,Write all high Voltage page latches with the same 32-bit data in a single write cycle. In order to also write same lower 8bit from 32-bit data to all the ECC bits in the page latches set ANA_CTL0.ECC_ENC_DIS=1."
|
|
line.long 0xC "FM_REFRESH_ADDR,Address bit to point to scratch area"
|
|
bitfld.long 0xC 4. "FM_CXA,Address bit to point to Column 33" "0: Point to normal columns in sector,1: Point to Column 33 used for BL Disturb Counter"
|
|
newline
|
|
bitfld.long 0xC 0. "FM_BXA,Address bit to point to scratch area" "0: Point to normal rows in sector,1: Point to scratch rows in sector"
|
|
line.long 0x10 "RGRANT_DELAY_ERS,R-grant delay for erase"
|
|
hexmask.long.byte 0x10 16.--23. 1. "RGRANT_DELAY_ERS_SEQ23,ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "RGRANT_DELAY_ERS_SEQ12,ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "RGRANT_DELAY_ERS_SEQ01,ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01"
|
|
line.long 0x14 "RGRANT_SCALE_ERS,R-grant delay scale for erase"
|
|
hexmask.long.byte 0x14 24.--31. 1. "RGRANT_DELAY_ERS_PEOFF,ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--23. 1. "RGRANT_DELAY_ERS_PEON,ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON"
|
|
newline
|
|
bitfld.long 0x14 8.--9. "SCALE_ERS_PEOFF,ERASE: Scale for R_GRANT_DELAY on PE OFF transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
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bitfld.long 0x14 6.--7. "SCALE_ERS_PEON,ERASE: Scale for R_GRANT_DELAY on PE On transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
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bitfld.long 0x14 4.--5. "SCALE_ERS_SEQ23,ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
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bitfld.long 0x14 2.--3. "SCALE_ERS_SEQ12,ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition:" "0: 0,1: 1uS,?,?"
|
|
newline
|
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bitfld.long 0x14 0.--1. "SCALE_ERS_SEQ01,ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition:" "0: 0,1: 1uS,?,?"
|
|
line.long 0x18 "PW_SEQ23,HV Pulse Delay for seq2 post & seq3"
|
|
hexmask.long.word 0x18 16.--31. 1. "PW_SEQ3,Seq3 delay"
|
|
newline
|
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hexmask.long.word 0x18 0.--15. 1. "PW_SEQ2_POST,Seq2 post delay"
|
|
line.long 0x1C "PW_SEQ12,HV Pulse Delay for seq 1&2 pre"
|
|
hexmask.long.word 0x1C 16.--31. 1. "PW_SEQ2_PRE,Seq2 pre delay"
|
|
newline
|
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hexmask.long.word 0x1C 0.--15. 1. "PW_SEQ1,Seq1 delay"
|
|
line.long 0x20 "WAIT_CTL,Wait State control"
|
|
bitfld.long 0x20 29. "PL_SOFT_SET_EN,Page latch soft set enable 0 = disabled 1 = enabled (at end of seq_2) taken care in API" "0: disabled,1: enabled"
|
|
newline
|
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bitfld.long 0x20 26. "LV_SPARE_1,Spare register" "0,1"
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|
newline
|
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bitfld.long 0x20 24.--25. "FM_RWW_MODE,2'b00: Full CBUS MODE" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x20 16.--18. "WAIT_FM_HV_WR,Number of C interface wait cycles (on 'clk_c') for a write to the Page Latches." "0,1,2,3,4,5,6,7"
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|
newline
|
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hexmask.long.byte 0x20 8.--11. 1. "WAIT_FM_HV_RD,Number of C interface wait cycles (on 'clk_c') for a read from the Page Latches."
|
|
newline
|
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hexmask.long.byte 0x20 0.--3. 1. "WAIT_FM_MEM_RD,Number of C interface wait cycles (on 'clk_c') for a read from the memory"
|
|
line.long 0x24 "RGRANT_DELAY_PRG,R-grant delay for program"
|
|
bitfld.long 0x24 31. "HV_PARAMS_LOADED,0': HV Pulse common params not loaded" "0: HV Pulse common params not loaded,1: HV Pulse common params loaded: r-grant delays"
|
|
newline
|
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hexmask.long.byte 0x24 24.--27. 1. "RGRANT_DELAY_CLK,Frequency divider from clk_t to create the 8MHz reference clock for R_grant delay."
|
|
newline
|
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hexmask.long.byte 0x24 16.--23. 1. "RGRANT_DELAY_SEQ30,PROG&PRE_PROG & ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30"
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|
newline
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hexmask.long.byte 0x24 8.--15. 1. "RGRANT_DELAY_PRG_SEQ23,PROG&PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23"
|
|
newline
|
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hexmask.long.byte 0x24 0.--7. 1. "RGRANT_DELAY_PRG_SEQ12,PROG&PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12"
|
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line.long 0x28 "TIMER_CLK_CTL,Timer prescaler (clk_t to timer clock frequency divider)"
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hexmask.long.byte 0x28 24.--31. 1. "RGRANT_DELAY_PRG_SEQ01,PROG&PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01"
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|
newline
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hexmask.long.byte 0x28 16.--23. 1. "RGRANT_DELAY_PRG_PEOFF,PROG&PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF"
|
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newline
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hexmask.long.byte 0x28 8.--15. 1. "RGRANT_DELAY_PRG_PEON,PROG&PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON"
|
|
newline
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hexmask.long.byte 0x28 0.--7. 1. "TIMER_CLOCK_FREQ,Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer."
|
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line.long 0x2C "TIMER_CTL,Timer control"
|
|
bitfld.long 0x2C 31. "TIMER_EN,Timer enable:" "0: disabled,1: enabled"
|
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newline
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bitfld.long 0x2C 30. "ACLK_EN,ACLK enable (generates a single cycle pulse for the FM):" "0: disabled,1: enabled"
|
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newline
|
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bitfld.long 0x2C 29. "PUMP_EN,Pump enable:" "0: disabled,1: enabled"
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newline
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bitfld.long 0x2C 26. "PRE_PROG_CSL,0: CSL lines driven by MDAC" "0: CSL lines driven by MDAC,1: CSL lines driven by VNEG_G"
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newline
|
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bitfld.long 0x2C 25. "PRE_PROG,1 during pre-program operation" "0,1"
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newline
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bitfld.long 0x2C 24. "AUTO_SEQUENCE,1': Starts1 the HV automatic sequencing" "?,1: Starts1 the HV automatic sequencing"
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newline
|
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bitfld.long 0x2C 15. "SCALE,Timer tick scale:" "0: 1 microsecond,1: 100 microseconds"
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newline
|
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hexmask.long.word 0x2C 0.--14. 1. "PERIOD,Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples."
|
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wgroup.long 0xA58++0x3
|
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line.long 0x0 "ACLK_CTL,MPCON clock"
|
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bitfld.long 0x0 0. "ACLK_GEN,Write '1b1' to generate one clock pulse for HV control registers (mpcon outputs)" "0,1"
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group.long 0xA5C++0xB
|
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line.long 0x0 "INTR,Interrupt"
|
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bitfld.long 0x0 0. "TIMER_EXPIRED,Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit." "0,1"
|
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line.long 0x4 "INTR_SET,Interrupt set"
|
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bitfld.long 0x4 0. "TIMER_EXPIRED,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
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line.long 0x8 "INTR_MASK,Interrupt mask"
|
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bitfld.long 0x8 0. "TIMER_EXPIRED,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long 0xA68++0x3
|
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line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "TIMER_EXPIRED,Logical and of corresponding request and mask fields." "0,1"
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|
group.long 0xA6C++0x1F
|
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line.long 0x0 "CAL_CTL0,Cal control - VCT. VBG. CDAC. IPREF"
|
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bitfld.long 0x0 19. "SPARE_CTL0_HV,Spare trim bits DNU" "0,1"
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newline
|
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bitfld.long 0x0 18. "IPREF_TRIMA_HV,Adds 100-150nA boost on IPREF" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 14.--17. 1. "VBG_TC_TRIM_HV,Bandgap Voltage Temperature Compensation trim control"
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|
newline
|
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hexmask.long.byte 0x0 8.--13. 1. "VBG_TRIM_HV,Bandgap Voltage trim control."
|
|
newline
|
|
bitfld.long 0x0 5.--7. "CDAC_HV,Temperature compensated trim DAC. To control Vctat slope for VNEG." "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.byte 0x0 0.--4. 1. "VCT_TRIM_HV,Bandgap Voltage Temperature Compensation trim control."
|
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line.long 0x4 "CAL_CTL1,Cal control - ICREF. IPREF"
|
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bitfld.long 0x4 19. "SPARE_CTL1_HV,Spare trim bit DNU" "0,1"
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newline
|
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hexmask.long.byte 0x4 15.--18. 1. "IPREF_TC_HV,IPREF Slope Control"
|
|
newline
|
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hexmask.long.byte 0x4 10.--14. 1. "IPREF_TRIM_HV,Bandgap IPTAT trim control."
|
|
newline
|
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hexmask.long.byte 0x4 6.--9. 1. "ICREF_TC_TRIM_HV,Bandgap Current Temperature Compensation trim control"
|
|
newline
|
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hexmask.long.byte 0x4 0.--5. 1. "ICREF_TRIM_HV,Bandgap Current trim control."
|
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line.long 0x8 "CAL_CTL2,Cal control - IDAC. IBS_CTL. LAT_DIS"
|
|
bitfld.long 0x8 19. "VREF_SEL_LP_HV,0: Uses VBG as reference for VLIM - LP Mode" "0: Uses VBG as reference for VLIM,1: Uses VCTAT as reference for VLIM"
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newline
|
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bitfld.long 0x8 18. "SPARE_LP_CTL2_HV,Spare bit to be used in LP configuration" "0,1"
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newline
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hexmask.long.byte 0x8 10.--17. 1. "IDAC_LP_HV,Sets the sense current reference offset value. Refer to trim tables for details."
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newline
|
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bitfld.long 0x8 9. "VREF_SEL_ULP_HV,0: Uses VBG as reference for VLIM - ULP Mode" "0: Uses VBG as reference for VLIM,1: Uses VCTAT as reference for VLIM"
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newline
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bitfld.long 0x8 8. "SPARE_ULP_CTL2_HV,Spare bit to be used in ULP configuration" "0,1"
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newline
|
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hexmask.long.byte 0x8 0.--7. 1. "IDAC_ULP_HV,Sets the sense current reference offset value. Refer to trim tables for details."
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line.long 0xC "CAL_CTL3,Cal control - OSC trims. FDIV. REG_ACT. TURBO. LP_ULP_SW"
|
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bitfld.long 0xC 19. "LP_ULP_SW_HV,LP<-->ULP switch for trim signals:" "0: LP,1: ULP"
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newline
|
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bitfld.long 0xC 18. "R_GRANT_EN_HV,0: r_grant handshake disabled r_grant always 1." "0: r_grant handshake disabled,1: r_grant handshake enabled"
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|
newline
|
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bitfld.long 0xC 17. "CL_ISO_DIS_HV,0: The internal logic controlls the CL isolation" "0: The internal logic controlls the CL isolation,1: Forces CL bypass"
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newline
|
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bitfld.long 0xC 15.--16. "IOSC_TRIM_HV,Oscillator Bias Current Trim during Standby" "0,1,2,3"
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|
newline
|
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bitfld.long 0xC 13.--14. "TURBO_PULSEW_HV,Turbo pulse width trim (Typical)" "0: 40 us,1: 20 us,?,?"
|
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newline
|
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bitfld.long 0xC 12. "VDDHI_HV,0: vdd < 2.3V" "0: vdd < 2,1: vdd >= 2"
|
|
newline
|
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bitfld.long 0xC 10.--11. "FDIV_TRIM_HV,FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby." "0: F = 0,1: F = 1MHz,?,?"
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newline
|
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bitfld.long 0xC 9. "REG_ACT_HV,0: VBST regulator will operate in active/standby mode based on control signal." "0: VBST regulator will operate in active/standby..,1: Forces the VBST regulator in active mode all the.."
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newline
|
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bitfld.long 0xC 8. "PM_EN_HV,0: Sense Amp bias similar to _ver2" "0: Sense Amp bias similar to _ver2,1: pbias enabled in Sense Amp for Better Margin"
|
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newline
|
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bitfld.long 0xC 7. "LAT_DIS3_HV,0: Enable saen3 control for data out latches" "0: Enable saen3 control for data out latches,1: Disable saen3 control for data out latches"
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newline
|
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bitfld.long 0xC 6. "OSC_TEMPCO_HV,0: Uses VBG as reference" "0: Uses VBG as reference,1: Uses VCTAT as reference"
|
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newline
|
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bitfld.long 0xC 5. "VPROT_ACT_HV,Forces VPROT in active mode all the time" "0,1"
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newline
|
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bitfld.long 0xC 4. "OSC_RANGE_TRIM_HV,0: Oscillator Low Frequency range" "0: Oscillator Low Frequency range,1: Oscillator High Frequency Range"
|
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newline
|
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hexmask.long.byte 0xC 0.--3. 1. "OSC_TRIM_HV,Flash macro pump clock trim control."
|
|
line.long 0x10 "CAL_CTL4,Cal control - VLIM. IDAC. SDAC. ITIM ULP trims"
|
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bitfld.long 0x10 19. "UGB_EN_HV,UGB enable in TM control" "0,1"
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newline
|
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bitfld.long 0x10 18. "AUTO_HVPULSE_HV,0: HV Pulse controlled by FW" "0: HV Pulse controlled by FW,1: HV Pulse controlled by Hardware"
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newline
|
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bitfld.long 0x10 17. "VBST_S_DIS_HV,0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector reducing coupling to GBL." "0: VBST_S voltage for each sector to allow VBST..,1: VBST_S voltage for each sector stays at VBST.."
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newline
|
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bitfld.long 0x10 16. "READY_RESTART_N_HV,Toggle: 1-->0 ready goes low ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only." "0,1"
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newline
|
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bitfld.long 0x10 15. "SA_CTL_TRIM_T8_ULP_HV,saen3 pulse width trim (Current trim)" "0,1"
|
|
newline
|
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bitfld.long 0x10 13.--14. "FM_READY_DEL_ULP_HV,00: Default : delay 1ns" "0: Default : delay 1ns,1: Delayed by 1,?,?"
|
|
newline
|
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hexmask.long.byte 0x10 7.--12. 1. "ITIM_ULP_HV,Trimming of timing current"
|
|
newline
|
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bitfld.long 0x10 5.--6. "SDAC_ULP_HV,Sets the sense current reference temp slope. Refer to trim tables for details." "0,1,2,3"
|
|
newline
|
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bitfld.long 0x10 2.--4. "SPARE_CTL4_ULP_HV,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x10 0.--1. "VLIM_TRIM_ULP_HV,VLIM_TRIM[1:0]:" "0: V2 = 650mV,1: V2 = 700mV,?,?"
|
|
line.long 0x14 "CAL_CTL5,Cal control - VLIM. IDAC. SDAC. ITIM LP trims"
|
|
bitfld.long 0x14 18.--19. "AMUX_SEL_HV,Amux Select in AMUX_UGB" "0: Bypass UGB for both amuxbusa and amuxbusb,1: Bypass UGB for amuxbusb while passing amuxbusa..,?,?"
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|
newline
|
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bitfld.long 0x14 16.--17. "SPARE2_CTL5_LP_HV,Spare Bit not used" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x14 15. "SA_CTL_TRIM_T8_LP_HV,saen3 pulse width trim (Current trim)" "0,1"
|
|
newline
|
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bitfld.long 0x14 13.--14. "FM_READY_DEL_LP_HV,00: Delayed by 1us" "0: Delayed by 1us,1: Delayed by 1,?,?"
|
|
newline
|
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hexmask.long.byte 0x14 7.--12. 1. "ITIM_LP_HV,Trimming of timing current"
|
|
newline
|
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bitfld.long 0x14 5.--6. "SDAC_LP_HV,Sets the sense current reference temp slope. Refer to trim tables for details." "0,1,2,3"
|
|
newline
|
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bitfld.long 0x14 2.--4. "SPARE_CTL5_LP_HV,Spare Bit not used" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x14 0.--1. "VLIM_TRIM_LP_HV,VLIM_TRIM[1:0]:" "0: V2 = 650mV,1: V2 = 700mV,?,?"
|
|
line.long 0x18 "CAL_CTL6,Cal control - SA CTL LP/ULP trims"
|
|
bitfld.long 0x18 18.--19. "SA_CTL_TRIM_T6_LP_HV,SA_CTL_TRIM_T6_LP_HV<1>= eni (enable current trim)" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x18 15.--17. "SA_CTL_TRIM_T5_LP_HV,SA_CTL_TRIM_T5_LP_HV<2>= evi (integration current trim)" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x18 12.--14. "SA_CTL_TRIM_T4_LP_HV,SA_CTL_TRIM_T4_LP_HV<2>= eqi (eq current trim)" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x18 10.--11. "SA_CTL_TRIM_T1_LP_HV,clk_trk delay" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 8.--9. "SA_CTL_TRIM_T6_ULP_HV,SA_CTL_TRIM_T6_ULP_HV<1>= eni (enable current trim)" "0,1,2,3"
|
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newline
|
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bitfld.long 0x18 5.--7. "SA_CTL_TRIM_T5_ULP_HV,SA_CTL_TRIM_T5_ULP_HV<2>= evi (integration current trim)" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x18 2.--4. "SA_CTL_TRIM_T4_ULP_HV,SA_CTL_TRIM_T4_ULP_HV<2>= eqi (eq current trim)" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x18 0.--1. "SA_CTL_TRIM_T1_ULP_HV,clk_trk delay" "0,1,2,3"
|
|
line.long 0x1C "CAL_CTL7,Cal control - ERSX8_CLK_SEL. FM_ACTIVE. TURBO_EXT"
|
|
bitfld.long 0x1C 17.--19. "SPARE3_CTL7_LP_HV,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x1C 15.--16. "PTRIM_LP_HV,SA PBIAS Trim for LP Operation" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 12.--14. "SPARE2_CTL7_ULP_HV,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x1C 10.--11. "PTRIM_ULP_HV,SA PBIAS Trim for ULP Operation" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 8.--9. "SPARE_CTL7_HV,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 7. "READY_DEL_HV,0: Ready Delay trim." "0: Ready Delay trim,1: Ready Delay trim"
|
|
newline
|
|
bitfld.long 0x1C 6. "ERSX8_EN_ALL_HV,0': Staggered turn on/off of GWL" "0: Staggered turn on/off of GWL,1: GWL are turned on/off at the same time"
|
|
newline
|
|
bitfld.long 0x1C 5. "FM_READY_DIS_HV,0': fm ready is enabled" "0: fm ready is enabled,1: fm ready is disabled"
|
|
newline
|
|
bitfld.long 0x1C 4. "NPDAC_HWCTL_DIS_HV,0': ndac pdac staircase hardware controlled" "0: ndac,1: ndac"
|
|
newline
|
|
bitfld.long 0x1C 3. "TURBO_EXT_HV,0: Normal operation" "0: Normal operation,1: Uses external turbo pulse"
|
|
newline
|
|
bitfld.long 0x1C 2. "FM_ACTIVE_HV,0: Normal operation" "0: Normal operation,1: Forces FM SYS in active mode"
|
|
newline
|
|
bitfld.long 0x1C 0.--1. "ERSX8_CLK_SEL_HV,Clock frequency into the ersx8 shift register block" "0: Oscillator clock,1: Oscillator clock / 2,?,?"
|
|
repeat 33. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xB00)++0x3
|
|
line.long 0x0 "FM_PL_ECC[$1],Flash macro Page Latches ECC"
|
|
hexmask.long.word 0x0 16.--24. 1. "DATA9_1,ECC encoder output. Can be read any time at address 0xa00"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "DATA9,if_sel must be 1"
|
|
repeat.end
|
|
repeat 132. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xC00)++0x3
|
|
line.long 0x0 "FM_MEM_DATA[$1],Flash macro memory sense amplifier data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL"
|
|
repeat.end
|
|
repeat 33. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xF00)++0x3
|
|
line.long 0x0 "FM_MEM_ECC[$1],Flash macro memory sense amplifier ECC."
|
|
hexmask.long.word 0x0 0.--8. 1. "ECC_PARITY,Sense amplifier ECC Bits. FM_CTL.IF_SEL must be 1."
|
|
repeat.end
|
|
tree.end
|
|
tree "MPC"
|
|
base ad:0x42151000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CFG,Config register with error response. RegionID PPC_MPC_MAIN is the security owner PC. The error response configuration is located in CFG.RESPONSE. only one such configuration exists applying to all protection contexts in the system."
|
|
bitfld.long 0x0 4. "RESPONSE,Response Configuration for Security and PC violations" "0: Read-Zero Write Ignore,1: Bus Error"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CTRL,Control register with lock bit and auto-increment only (Separate CTRL for each PC depends on access_pc)"
|
|
bitfld.long 0x0 31. "LOCK,Security lockdown for this protection context. Software can set this bit but not clear it once set. When set write operations to BLK_LUT are not possible from this protection context. Setting LOCK also blocks writes to CTRL itself (for that PC.." "0,1"
|
|
bitfld.long 0x0 8. "AUTO_INC,Auto-increment BLK_IDX by 1 for this protection context as a side effect of each read/write access to BLK_LUT" "0,1"
|
|
rgroup.long 0x104++0x7
|
|
line.long 0x0 "BLK_MAX,Max value of block-based index register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Maximum value of block-based index register. The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; See product datasheet for details on protection of.."
|
|
line.long 0x4 "BLK_CFG,Block size & initialization in progress"
|
|
bitfld.long 0x4 31. "INIT_IN_PROGRESS,During initialization INIT_IN_PROGRESS is '1' and MMIO register accesses to BLK_LUT is blocked (BLK_IDX increment is also ignored). The block attributes are retained in DeepSleep (and obviously Active) power mode. Initialization is only.." "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "BLOCK_SIZE,Block size of individually protected blocks (0: 32B 1: 64B ... up to 15: 1MB)"
|
|
group.long 0x10C++0x7
|
|
line.long 0x0 "BLK_IDX,Index of 32-block group accessed through BLK_LUT (Separate IDX for each PC depending on access_pc)"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Index value for accessing block-based lookup table using BLK_LUT. Programming out of LUT range is an user error and it loops back to '0' once overflow occurs."
|
|
line.long 0x4 "BLK_LUT,NS status for 32 blocks at BLK_IDX with PC=<access_pc>"
|
|
bitfld.long 0x4 31. "ATTR_NS31,NS bit for block 31 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 30. "ATTR_NS30,NS bit for block 30 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 29. "ATTR_NS29,NS bit for block 29 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 28. "ATTR_NS28,NS bit for block 28 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 27. "ATTR_NS27,NS bit for block 27 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "ATTR_NS26,NS bit for block 26 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 25. "ATTR_NS25,NS bit for block 25 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 24. "ATTR_NS24,NS bit for block 24 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 23. "ATTR_NS23,NS bit for block 23 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 22. "ATTR_NS22,NS bit for block 22 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "ATTR_NS21,NS bit for block 21 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 20. "ATTR_NS20,NS bit for block 20 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 19. "ATTR_NS19,NS bit for block 19 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 18. "ATTR_NS18,NS bit for block 18 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 17. "ATTR_NS17,NS bit for block 17 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "ATTR_NS16,NS bit for block 16 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 15. "ATTR_NS15,NS bit for block 15 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 14. "ATTR_NS14,NS bit for block 14 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 13. "ATTR_NS13,NS bit for block 13 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 12. "ATTR_NS12,NS bit for block 12 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ATTR_NS11,NS bit for block 11 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 10. "ATTR_NS10,NS bit for block 10 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 9. "ATTR_NS9,NS bit for block 9 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 8. "ATTR_NS8,NS bit for block 8 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 7. "ATTR_NS7,NS bit for block 7 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ATTR_NS6,NS bit for block 6 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 5. "ATTR_NS5,NS bit for block 5 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 4. "ATTR_NS4,NS bit for block 4 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 3. "ATTR_NS3,NS bit for block 3 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 2. "ATTR_NS2,NS bit for block 2 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ATTR_NS1,NS bit for block 1 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 0. "ATTR_NS0,NS bit for block 0 based on BLK_IDX" "0,1"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "ROT_CTRL,Control register with lock bit and auto-increment only"
|
|
bitfld.long 0x0 31. "LOCK,Security lockdown for the root-of-trust configuration registers. Software can set this bit but not clear it once set. When set write operations to ROT_BLK_LUT are not possible. Write is ignored." "0,1"
|
|
bitfld.long 0x0 8. "AUTO_INC,Auto-increment BLK_IDX by 1 for each read/write of ROT_BLK_LUT" "0,1"
|
|
rgroup.long 0x208++0x7
|
|
line.long 0x0 "ROT_BLK_MAX,Max value of block-based index register for ROT"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Maximum value of block-based index register. The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of.."
|
|
line.long 0x4 "ROT_BLK_CFG,Same as BLK_CFG"
|
|
bitfld.long 0x4 31. "INIT_IN_PROGRESS,During initialization INIT_IN_PROGRESS is '1' and MMIO register accesses to ROT_BLK_LUT is RAZWI. The block attributes are retained in DeepSleep (and obviously Active) power mode. Initialization is only required from a power mode in.." "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "BLOCK_SIZE,Block size of individually protected blocks (0: 32B 1: 64B ...up to 15:1MB)"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "ROT_BLK_IDX,Index of 8-block group accessed through ROT_BLK_LUT_*"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Index value for accessing block-based lookup table using ROT_BLK_LUT. Programming out of LUT range is an user error and it loops back to '0' once overflow occurs."
|
|
line.long 0x4 "ROT_BLK_PC,Protection context of 8-block group accesses through ROT_BLK_LUT"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PC,Specify PC values for ROT_BLK_IDX and ROT_BLK_LUT"
|
|
line.long 0x8 "ROT_BLK_LUT,(R.W.NS) bits for 8 blocks at ROT_BLK_IDX for PC=ROT_BKL_PC"
|
|
bitfld.long 0x8 28.--30. "ATTR7,W/R/NS bits for block 7 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24.--26. "ATTR6,W/R/NS bits for block 6 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 20.--22. "ATTR5,W/R/NS bits for block 5 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--18. "ATTR4,W/R/NS bits for block 4 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 12.--14. "ATTR3,W/R/NS bits for block 3 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "ATTR2,W/R/NS bits for block 2 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 4.--6. "ATTR1,W/R/NS bits for block 1 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "ATTR0,W/R/NS bits for block 0 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree.end
|
|
tree "GPIO (IO Subsystem)"
|
|
base ad:0x42410000
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x42410000 ad:0x42410080 ad:0x42410100 ad:0x42410180 ad:0x42410200 ad:0x42410280 ad:0x42410300 ad:0x42410380 ad:0x42410400 ad:0x42410480)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "OUT,Port output data register"
|
|
bitfld.long 0x0 7. "OUT7,IO output data for pin 7" "0,1"
|
|
bitfld.long 0x0 6. "OUT6,IO output data for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUT5,IO output data for pin 5" "0,1"
|
|
bitfld.long 0x0 4. "OUT4,IO output data for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OUT3,IO output data for pin 3" "0,1"
|
|
bitfld.long 0x0 2. "OUT2,IO output data for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OUT1,IO output data for pin 1" "0,1"
|
|
bitfld.long 0x0 0. "OUT0,IO output data for pin 0" "0: Output state set to '0',1: Output state set to '1'"
|
|
line.long 0x4 "OUT_CLR,Port output data clear register"
|
|
bitfld.long 0x4 7. "OUT7,IO clear output for pin 7" "0,1"
|
|
bitfld.long 0x4 6. "OUT6,IO clear output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OUT5,IO clear output for pin 5" "0,1"
|
|
bitfld.long 0x4 4. "OUT4,IO clear output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OUT3,IO clear output for pin 3" "0,1"
|
|
bitfld.long 0x4 2. "OUT2,IO clear output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OUT1,IO clear output for pin 1" "0,1"
|
|
bitfld.long 0x4 0. "OUT0,IO clear output for pin 0:" "0: Output state not affected,1: Output state set to '0'"
|
|
line.long 0x8 "OUT_SET,Port output data set register"
|
|
bitfld.long 0x8 7. "OUT7,IO set output for pin 7" "0,1"
|
|
bitfld.long 0x8 6. "OUT6,IO set output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OUT5,IO set output for pin 5" "0,1"
|
|
bitfld.long 0x8 4. "OUT4,IO set output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OUT3,IO set output for pin 3" "0,1"
|
|
bitfld.long 0x8 2. "OUT2,IO set output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OUT1,IO set output for pin 1" "0,1"
|
|
bitfld.long 0x8 0. "OUT0,IO set output for pin 0:" "0: Output state not affected,1: Output state set to '1'"
|
|
line.long 0xC "OUT_INV,Port output data invert register"
|
|
bitfld.long 0xC 7. "OUT7,IO invert output for pin 7" "0,1"
|
|
bitfld.long 0xC 6. "OUT6,IO invert output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "OUT5,IO invert output for pin 5" "0,1"
|
|
bitfld.long 0xC 4. "OUT4,IO invert output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OUT3,IO invert output for pin 3" "0,1"
|
|
bitfld.long 0xC 2. "OUT2,IO invert output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OUT1,IO invert output for pin 1" "0,1"
|
|
bitfld.long 0xC 0. "OUT0,IO invert output for pin 0:" "0: '1',1: '0'"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "IN,Port input state register"
|
|
bitfld.long 0x0 8. "FLT_IN,Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register." "0,1"
|
|
bitfld.long 0x0 7. "IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IN6,IO pin state for pin 6" "0,1"
|
|
bitfld.long 0x0 5. "IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IN4,IO pin state for pin 4" "0,1"
|
|
bitfld.long 0x0 3. "IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IN2,IO pin state for pin 2" "0,1"
|
|
bitfld.long 0x0 1. "IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN0,IO pin state for pin 0" "0: Low logic level present on pin,1: High logic level present on pin"
|
|
group.long ($2+0x14)++0x7
|
|
line.long 0x0 "INTR,Port interrupt status register"
|
|
rbitfld.long 0x0 24. "FLT_IN_IN,Filtered pin state for pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
rbitfld.long 0x0 23. "IN_IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 22. "IN_IN6,IO pin state for pin 6" "0,1"
|
|
rbitfld.long 0x0 21. "IN_IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 20. "IN_IN4,IO pin state for pin 4" "0,1"
|
|
rbitfld.long 0x0 19. "IN_IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "IN_IN2,IO pin state for pin 2" "0,1"
|
|
rbitfld.long 0x0 17. "IN_IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "IN_IN0,IO pin state for pin 0" "0,1"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EDGE7,Edge detect for IO pin 7" "0,1"
|
|
bitfld.long 0x0 6. "EDGE6,Edge detect for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EDGE5,Edge detect for IO pin 5" "0,1"
|
|
bitfld.long 0x0 4. "EDGE4,Edge detect for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EDGE3,Edge detect for IO pin 3" "0,1"
|
|
bitfld.long 0x0 2. "EDGE2,Edge detect for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EDGE1,Edge detect for IO pin 1" "0,1"
|
|
bitfld.long 0x0 0. "EDGE0,Edge detect for IO pin 0" "0: No edge was detected on pin,1: An edge was detected on pin"
|
|
line.long 0x4 "INTR_MASK,Port interrupt mask register"
|
|
bitfld.long 0x4 8. "FLT_EDGE,Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x4 7. "EDGE7,Masks edge interrupt on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EDGE6,Masks edge interrupt on IO pin 6" "0,1"
|
|
bitfld.long 0x4 5. "EDGE5,Masks edge interrupt on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EDGE4,Masks edge interrupt on IO pin 4" "0,1"
|
|
bitfld.long 0x4 3. "EDGE3,Masks edge interrupt on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EDGE2,Masks edge interrupt on IO pin 2" "0,1"
|
|
bitfld.long 0x4 1. "EDGE1,Masks edge interrupt on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EDGE0,Masks edge interrupt on IO pin 0" "0: Pin interrupt forwarding disabled,1: Pin interrupt forwarding enabled"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Port interrupt masked status register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Edge detected and masked on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Edge detected and masked on IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Edge detected and masked on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Edge detected and masked on IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Edge detected and masked on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Edge detected and masked on IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Edge detected and masked on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Edge detected AND masked on IO pin 0" "0: Interrupt was not forwarded to CPU,1: Interrupt occurred and was forwarded to CPU"
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "INTR_SET,Port interrupt set register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Sets edge detect interrupt for IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Sets edge detect interrupt for IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Sets edge detect interrupt for IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Sets edge detect interrupt for IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Sets edge detect interrupt for IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Sets edge detect interrupt for IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Sets edge detect interrupt for IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Sets edge detect interrupt for IO pin 0" "0: Interrupt state not affected,1: Interrupt set"
|
|
group.long ($2+0x40)++0x13
|
|
line.long 0x0 "INTR_CFG,Port interrupt configuration register"
|
|
bitfld.long 0x0 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "FLT_EDGE_SEL,Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pin 0" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
line.long 0x4 "CFG,Port configuration register"
|
|
bitfld.long 0x4 31. "IN_EN7,Enables the input buffer for IO pin 7" "0,1"
|
|
bitfld.long 0x4 28.--30. "DRIVE_MODE7,The GPIO drive mode for IO pin 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 27. "IN_EN6,Enables the input buffer for IO pin 6" "0,1"
|
|
bitfld.long 0x4 24.--26. "DRIVE_MODE6,The GPIO drive mode for IO pin 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 23. "IN_EN5,Enables the input buffer for IO pin 5" "0,1"
|
|
bitfld.long 0x4 20.--22. "DRIVE_MODE5,The GPIO drive mode for IO pin 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 19. "IN_EN4,Enables the input buffer for IO pin 4" "0,1"
|
|
bitfld.long 0x4 16.--18. "DRIVE_MODE4,The GPIO drive mode for IO pin4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 15. "IN_EN3,Enables the input buffer for IO pin 3" "0,1"
|
|
bitfld.long 0x4 12.--14. "DRIVE_MODE3,The GPIO drive mode for IO pin 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "IN_EN2,Enables the input buffer for IO pin 2" "0,1"
|
|
bitfld.long 0x4 8.--10. "DRIVE_MODE2,The GPIO drive mode for IO pin 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "IN_EN1,Enables the input buffer for IO pin 1" "0,1"
|
|
bitfld.long 0x4 4.--6. "DRIVE_MODE1,The GPIO drive mode for IO pin 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "IN_EN0,Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue." "0: Input buffer disabled,1: Input buffer enabled"
|
|
bitfld.long 0x4 0.--2. "DRIVE_MODE0,The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
line.long 0x8 "CFG_IN,Port input buffer configuration register"
|
|
bitfld.long 0x8 7. "VTRIP_SEL7_0,Configures the pin 7 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 6. "VTRIP_SEL6_0,Configures the pin 6 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "VTRIP_SEL5_0,Configures the pin 5 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 4. "VTRIP_SEL4_0,Configures the pin 4 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "VTRIP_SEL3_0,Configures the pin 3 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 2. "VTRIP_SEL2_0,Configures the pin 2 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "VTRIP_SEL1_0,Configures the pin 1 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 0. "VTRIP_SEL0_0,Configures the pin 0 input buffer mode (trip points and hysteresis)" "0: Input buffer compatible with CMOS and I2C..,1: Input buffer compatible with TTL and MediaLB.."
|
|
line.long 0xC "CFG_OUT,Port output buffer configuration register"
|
|
bitfld.long 0xC 30.--31. "DRIVE_SEL7,Sets the GPIO drive strength for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "DRIVE_SEL6,Sets the GPIO drive strength for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "DRIVE_SEL5,Sets the GPIO drive strength for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "DRIVE_SEL4,Sets the GPIO drive strength for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "DRIVE_SEL3,Sets the GPIO drive strength for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "DRIVE_SEL2,Sets the GPIO drive strength for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "DRIVE_SEL1,Sets the GPIO drive strength for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "DRIVE_SEL0,Sets the GPIO drive strength for IO pin 0" "0: N/A,1: N/A,2: N/A,3: N/A"
|
|
newline
|
|
bitfld.long 0xC 7. "SLOW7,Enables slow slew rate for IO pin 7" "0,1"
|
|
bitfld.long 0xC 6. "SLOW6,Enables slow slew rate for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "SLOW5,Enables slow slew rate for IO pin 5" "0,1"
|
|
bitfld.long 0xC 4. "SLOW4,Enables slow slew rate for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "SLOW3,Enables slow slew rate for IO pin 3" "0,1"
|
|
bitfld.long 0xC 2. "SLOW2,Enables slow slew rate for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "SLOW1,Enables slow slew rate for IO pin 1" "0,1"
|
|
bitfld.long 0xC 0. "SLOW0,Enables slow slew rate for IO pin 0" "0: Fast slew rate,1: Slow slew rate"
|
|
line.long 0x10 "CFG_SIO,Port SIO configuration register"
|
|
bitfld.long 0x10 29.--31. "VOH_SEL67,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 27.--28. "VREF_SEL67,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 26. "VTRIP_SEL67,N/A" "0,1"
|
|
bitfld.long 0x10 25. "IBUF_SEL67,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "VREG_EN67,N/A" "0,1"
|
|
bitfld.long 0x10 21.--23. "VOH_SEL45,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 19.--20. "VREF_SEL45,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 18. "VTRIP_SEL45,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "IBUF_SEL45,N/A" "0,1"
|
|
bitfld.long 0x10 16. "VREG_EN45,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13.--15. "VOH_SEL23,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 11.--12. "VREF_SEL23,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10. "VTRIP_SEL23,N/A" "0,1"
|
|
bitfld.long 0x10 9. "IBUF_SEL23,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "VREG_EN23,N/A" "0,1"
|
|
bitfld.long 0x10 5.--7. "VOH_SEL01,Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'):" "0: Trip point=0,1: a,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 3.--4. "VREF_SEL01,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 2. "VTRIP_SEL01,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "IBUF_SEL01,N/A" "0,1"
|
|
bitfld.long 0x10 0. "VREG_EN01,The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output.." "0,1"
|
|
group.long ($2+0x58)++0x3
|
|
line.long 0x0 "CFG_IN_AUTOLVL,Port input buffer AUTOLVL configuration register for S40E GPIO"
|
|
bitfld.long 0x0 7. "VTRIP_SEL7_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 6. "VTRIP_SEL6_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "VTRIP_SEL5_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 4. "VTRIP_SEL4_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "VTRIP_SEL3_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 2. "VTRIP_SEL2_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VTRIP_SEL1_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 0. "VTRIP_SEL0_1,Configures the input buffer mode (trip points and hysteresis) for S40E GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:" "0: input buffer is compatible with automotive,1: input buffer is compatible with MediaLB"
|
|
group.long ($2+0x60)++0xF
|
|
line.long 0x0 "CFG_OUT2,Port output buffer configuration register 2"
|
|
bitfld.long 0x0 21.--23. "DS_TRIM7,Sets the Drive Select Trim for IO pin 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 18.--20. "DS_TRIM6,Sets the Drive Select Trim for IO pin 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 15.--17. "DS_TRIM5,Sets the Drive Select Trim for IO pin 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "DS_TRIM4,Sets the Drive Select Trim for IO pin 4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "DS_TRIM3,Sets the Drive Select Trim for IO pin 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--8. "DS_TRIM2,Sets the Drive Select Trim for IO pin 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "DS_TRIM1,Sets the Drive Select Trim for IO pin 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "DS_TRIM0,Sets the Drive Select Trim for IO pin 0" "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,5: N/A,6: N/A,7: N/A"
|
|
line.long 0x4 "CFG_SLEW_EXT,Port output buffer slew extension configuration register"
|
|
bitfld.long 0x4 28.--30. "SLEW7,Slew rate for IO pin 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24.--26. "SLEW6,Slew rate for IO pin 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "SLEW5,Slew rate for IO pin 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "SLEW4,Slew rate for IO pin 4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "SLEW3,Slew rate for IO pin 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "SLEW2,Slew rate for IO pin 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "SLEW1,Slew rate for IO pin 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "SLEW0,Enables slow slew rate for IO pin 0" "0: Fast slew rate,1: Slow slew rate,?,?,?,?,?,?"
|
|
line.long 0x8 "CFG_DRIVE_EXT0,Port output buffer drive sel extension configuration register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "DRIVE_SEL_EXT3,Sets the GPIO drive strength for IO pin 3"
|
|
hexmask.long.byte 0x8 16.--20. 1. "DRIVE_SEL_EXT2,Sets the GPIO drive strength for IO pin 2"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--12. 1. "DRIVE_SEL_EXT1,Sets the GPIO drive strength for IO pin 1"
|
|
hexmask.long.byte 0x8 0.--4. 1. "DRIVE_SEL_EXT0,Sets the GPIO drive strength for IO pin 0"
|
|
line.long 0xC "CFG_DRIVE_EXT1,Port output buffer drive sel extension configuration register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "DRIVE_SEL_EXT7,Sets the GPIO drive strength for IO pin 7"
|
|
hexmask.long.byte 0xC 16.--20. 1. "DRIVE_SEL_EXT6,Sets the GPIO drive strength for IO pin 6"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--12. 1. "DRIVE_SEL_EXT5,Sets the GPIO drive strength for IO pin 5"
|
|
hexmask.long.byte 0xC 0.--4. 1. "DRIVE_SEL_EXT4,Sets the GPIO drive strength for IO pin 4"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x42410000
|
|
newline
|
|
rgroup.long 0x7000++0x3
|
|
line.long 0x0 "SEC_INTR_CAUSE0,Secure Interrupt port cause register 0"
|
|
hexmask.long 0x0 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
rgroup.long 0x8000++0x3
|
|
line.long 0x0 "INTR_CAUSE0,Interrupt port cause register 0"
|
|
hexmask.long 0x0 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
rgroup.long 0x8010++0x3
|
|
line.long 0x0 "VDD_ACTIVE,Extern power supply detection register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in.." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Indicates presence or absence of VDDIO supplies (i.e. other than VDDD VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate robust brown-out detection is.."
|
|
group.long 0x8014++0x7
|
|
line.long 0x0 "VDD_INTR,Supply detection interrupt register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Supply state change detected."
|
|
line.long 0x4 "VDD_INTR_MASK,Supply detection interrupt mask register"
|
|
bitfld.long 0x4 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD." "0,1"
|
|
bitfld.long 0x4 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "VDDIO_ACTIVE,Masks supply interrupt on VDDIO."
|
|
rgroup.long 0x801C++0x3
|
|
line.long 0x0 "VDD_INTR_MASKED,Supply detection interrupt masked register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Supply transition detected AND masked"
|
|
group.long 0x8020++0x3
|
|
line.long 0x0 "VDD_INTR_SET,Supply detection interrupt set register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Sets supply interrupt."
|
|
tree.end
|
|
tree "HPPASS (High Performance Programmable Analog Sub-System)"
|
|
base ad:0x42B00000
|
|
tree "ACTRLR (Autonomnous Controller)"
|
|
base ad:0x42BD0000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRL,Control register"
|
|
bitfld.long 0x0 31. "ENABLED,0: MCPASS IP disabled - All mision logic and status is reset all analog controls are disabled all clocking is disabled (only available function is AHB access)." "0: MCPASS IP disabled,1: MCPASS IP enabled"
|
|
line.long 0x4 "CMD_RUN,Run Command register"
|
|
bitfld.long 0x4 0. "RUN,When firmware writes a '1' here it will trigger the Autonomous Controller to run hardware clears this bit when the Autonomous Controller acknowledges the run command. This command has no action if the Autonomous Controller is already running." "0,1"
|
|
line.long 0x8 "CMD_STATE,State Override register"
|
|
hexmask.long.byte 0x8 0.--3. 1. "STATE,Autonomous Controller CMD_STATE register. This register indicates which instruction the AC will start execution from when it receives a RUN command. Software can overrwrite this field only when STATUS.STATUS=STOPPED to set the AC to execute from.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "BLOCK_STATUS,Block Ready status register"
|
|
bitfld.long 0x0 0. "READY,This bit reflects the AC BLOCK_READY condition which can be polled by SW to determine if all the enabled blocks have settled and are ready for use" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "STATUS,AC Status register"
|
|
bitfld.long 0x0 8.--9. "STATUS,This field indicates if the Autonomous Controller is busy" "0: Autonomous Controller is stopped,1: Autonomous Controller is running,2: N/A,3: N/A"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CUR_STATE,This register indicates where in memory the AC is currently executing instructions."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CFG,AC Config register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DOUT_EN,DOUT_EN controls the GPIO output drive mode though the HSIOM"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x100)++0x3
|
|
line.long 0x0 "CNTR_STATUS[$1],Loop/Interval counter status register"
|
|
bitfld.long 0x0 31. "BUSY,This field indicates if the counter is busy" "0,1"
|
|
hexmask.long.word 0x0 8.--19. 1. "CUR_CNT,This field indicates the count value for the given counter."
|
|
hexmask.long.byte 0x0 0.--3. 1. "CUR_STATE,This field indicates which Timer Table State the counter is assigned. Valid numbers are 0-15"
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x42BD0800 ad:0x42BD0810 ad:0x42BD0820 ad:0x42BD0830 ad:0x42BD0840 ad:0x42BD0850 ad:0x42BD0860 ad:0x42BD0870 ad:0x42BD0880 ad:0x42BD0890 ad:0x42BD08A0 ad:0x42BD08B0 ad:0x42BD08C0 ad:0x42BD08D0 ad:0x42BD08E0 ad:0x42BD08F0)
|
|
tree "TTCFG[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "TT_CFG0,AC Configuration 0"
|
|
hexmask.long.byte 0x0 20.--24. 1. "DOUT,MCPASS data out generation"
|
|
bitfld.long 0x0 16. "DOUT_UNLOCK,DOUT Unlock" "0: Lock: DOUT does NOT get updated,1: Unlock: DOUT does get updated"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CSG_UNLOCK,CSG Unlock"
|
|
bitfld.long 0x0 4. "SAR_UNLOCK,SAR Unlock" "0: Lock: SAR fields: EN does NOT get updated,1: Unlock: SAR fields: EN does get updated"
|
|
line.long 0x4 "TT_CFG1,AC Configuration 1"
|
|
hexmask.long.word 0x4 20.--31. 1. "CNT,This field is used to set the timer/counter values for either interval and loop counts. The actual count is CNT value + 1. Therefore the range is 1 to 4096. The value of 1 is degenerate."
|
|
bitfld.long 0x4 19. "INTR_SET,AC Interrupt Set. This will generate a CPU interrupt or Hardware Trigger output if configured. If ACTION=WAIT_FOR the interrupt is generated after the COND occurs." "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "ACTION,Autonomous Controller Action" "0: Stop the autonomous controller,1: Execute the current state and proceed to the..,2: Wait for the associated COND to occur before..,3: Check if COND has occurred If it has take the..,4: Check if COND has occurred If it has proceed to..,5: N/A,6: N/A,7: N/A"
|
|
bitfld.long 0x4 14.--15. "NC_15_14,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--13. 1. "COND,Autonomous Controller Condition"
|
|
hexmask.long.byte 0x4 4.--7. 1. "NC_7_4,N/A"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "BR_ADDR,Absolute address of the branch if taken (0-15 possible)"
|
|
line.long 0x8 "TT_CFG2,AC Configuration 2"
|
|
hexmask.long.word 0x8 16.--31. 1. "NC_31_16,N/A"
|
|
hexmask.long.byte 0x8 8.--15. 1. "CSG_DAC_TR,CSG Slice Triggers. After the block is ready for use - these bits may be used for CSG DAC START and UPDATE triggers. The type of trigger is programmed in the CSG_SLICE register block."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "CSG_EN,CSG Slice Enables. The CSG UNLOCK bits must be set in the same state as these bits (see TT_CFG0) to enable or disable. These bits are normally used in conjunction with ACTION=WAIT_FOR and COND=BLOCK_READY"
|
|
line.long 0xC "TT_CFG3,AC Configuration 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. "NC_31_24,N/A"
|
|
hexmask.long.byte 0xC 16.--23. 1. "SAR_AROUTE_SEL,SAR Route setting (2 bits per mux) to select the routing input. The routing bits in this field are only valid if the associated SAR_ROUTE_TR is set."
|
|
newline
|
|
hexmask.long.byte 0xC 12.--15. 1. "SAR_AROUTE_TR,SAR Aroute Trigger (1 bit per mux) to change Route setting for one or more AROUTE MUXes. Set this bit in conjuction with a new SAR_AROUTE_SEL value."
|
|
bitfld.long 0xC 9.--11. "NC_11_9,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 8. "SAR_EN,SARADC Enable The SAR UNLOCK bit must be set in the same state as this bit (see TT_CFG0) to enable or disable. This bit is normally used in conjunction with ACTION=WAIT_FOR and COND=BLOCK_READY" "0,1"
|
|
hexmask.long.byte 0xC 0.--7. 1. "SAR_TR,SAR Table Entry Triggers. After the block is ready for use - these bits may be used to trigger one ore more SAR Entries. If ACTION=WAIT_FOR the trigger always occurs in the fir cycle of that state"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "CSG (Comparator Slope Generator)"
|
|
base ad:0x42BB0000
|
|
repeat 5. (list 0x0 0x1 0x2 0x3 0x4)(list ad:0x42BB0000 ad:0x42BB0040 ad:0x42BB0080 ad:0x42BB00C0 ad:0x42BB0100)
|
|
tree "SLICE[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "CMP_CFG,Comparator Control Register"
|
|
bitfld.long 0x0 16. "CMP_POLARITY,Comparator Polarity" "0: Comparator output is not intverted,1: Comparator output is inverted"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CMP_EDGE_MODE,Comparator signal mode for Interrupt generation and AC status" "0: Disabled no interrupts will be asserted,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "CMP_BLANK_TR_SEL,Copmarator Blank Trigger Select. Select one of the available input MCPASS HW/FW LEVEL mode triggers."
|
|
newline
|
|
bitfld.long 0x0 4.--5. "CMP_BLANK_MODE,Comparator Blanking Mode. Select a level input trigger from CMP_BLANK_TR_SEL to gate the comparators output of this slice to 0. Polarity of active signal is selectable." "0: Comparator output is not gated,1: Comparator output is gated to 0 by a '1' level,2: Comparator output is gated to 0 by a '0' level,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "CMP_NEG_SEL,Comparator Negative Input Select (Select positive input from CMP_POS_SEL)" "0: DAC is negative input,1: N/A,2: Analog input NA,3: Analog input NB"
|
|
newline
|
|
bitfld.long 0x0 0. "CMP_POS_SEL,Comparator Positive Input Select (Select negative input from CMP_NEG_SEL)" "0: Analog input PA,1: Analog input PB"
|
|
line.long 0x4 "DAC_CFG,DAC Control Register"
|
|
bitfld.long 0x4 28.--30. "DAC_DEGLITCH,DAC Deglitch Configuration. Default is disabled. If enabled on any DAC value update the CMP output is latched in it's current state for the number of cycles indicated." "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,5: N/A,6: N/A,7: N/A"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--25. 1. "DAC_STEP,Static value of 6 bit DAC step size. Step size is DAC_STEP +1 (default is '1') range is 1 - 64 only valid in SLOPE/LUT modes."
|
|
newline
|
|
bitfld.long 0x4 15. "DAC_PARAM_SYNC_EN,Parameter Sync Enable." "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 14. "DAC_CASCADE_EN,Cascade Enable. Synchronize parameter update with previous CSG slice in the case of multi-phase operation." "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "DAC_SKIP_TR_EN,Skip the first DAC hardware update trigger afer a mode is enabled. Allows for a minimum of a full trigger period before the first hardware update occurs." "0: First trigger following DAC_MODE_EN updates the..,1: First trigger following DAC_MODE_EN is skipped"
|
|
newline
|
|
bitfld.long 0x4 12. "DAC_CONT,DAC Continuous Mode (Only valid for Slope and LUT modes)" "0: Slope/LUT operation is One-Shot,1: Slope/LUT operation is Continuous"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "DAC_MODE,DAC Operating Mode. This setting may only be changed when the mode is disabled. See DAC_MODE_START." "0: Single Value Buffered Mode Transfer data from..,1: Two Value Hysteretic Buffered Mode Toggle..,2: Rising Slope Mode DAC_VAL_A is the start value..,3: Falling Slope Mode Same operation as Rising..,4: Triangular Slope Mode This mode combines Rising..,5: LUT Forward Mode LUT waveform is output with..,6: LUT Reverse Mode LUT waveform is output with..,7: LUT Forward Reverse Mode LUT waveform is output.."
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "DAC_TR_UPDATE_SEL,DAC Trigger Update Select. Select one of the triggers or internal events. See DAC_MODE for detailed operation. If one of the MCPASS HW or FW triggers are selected (see INFRA) then the trigger must be PULSE mode. In addition the.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DAC_TR_START_SEL,DAC Trigger Start Select. Select one of the MCPASS HW or FW triggers. Trigger must be PULSE mode (see INFRA). See DAC_MODE_START register to select this as the DAC start trigger."
|
|
line.long 0x8 "DAC_PARAM_SYNC,DAC Parameter Synchronized Update"
|
|
bitfld.long 0x8 0. "READY,Use this bit to synchronize the update of multiple DAC parameters." "0,1"
|
|
line.long 0xC "DAC_MODE_START,DAC Mode Start"
|
|
bitfld.long 0xC 31. "FW_START,1: Starts the selected mode on this FW write." "0: Stops the selected mode,1: Starts the selected mode on this FW write"
|
|
newline
|
|
bitfld.long 0xC 30. "HW_START,1: Wait for subsequent DAC_START_TR to start the selected mode." "0: Stops the selected mode,1: Wait for subsequent DAC_START_TR to start the.."
|
|
newline
|
|
rbitfld.long 0xC 0. "BUSY,Read only bit to indicate that a DAC MODE has been enabled and is currently in progress." "0,1"
|
|
line.long 0x10 "DAC_VAL_A,DAC Vaue A Buffer"
|
|
hexmask.long.word 0x10 0.--9. 1. "VALUE,DAC A Value usage is mode dependent (see DAC_MODE)"
|
|
line.long 0x14 "DAC_VAL_B,DAC Value B Buffer"
|
|
hexmask.long.word 0x14 0.--9. 1. "VALUE,DAC B Value usage is mode dependent (see DAC_MODE)"
|
|
line.long 0x18 "DAC_PERIOD,DAC Period Buffer"
|
|
hexmask.long.word 0x18 8.--19. 1. "PERIOD_INT,12-bit Integer Divide Value."
|
|
newline
|
|
hexmask.long.byte 0x18 3.--7. 1. "PERIOD_FRAC,5-bit Fractional Divide Value. Allows for fractional count in the range [0 31/32]"
|
|
line.long 0x1C "DAC_VAL,DAC FW write"
|
|
hexmask.long.word 0x1C 0.--9. 1. "VALUE,Direct drive to DAC Hard IP for output."
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "DAC_STATUS,Read of Current DAC Value"
|
|
hexmask.long.word 0x0 0.--9. 1. "DAC_VAL,Read Only value of current digital DAC output"
|
|
line.long 0x4 "CMP_STATUS,Read of Comparator Value"
|
|
bitfld.long 0x4 0. "CMP_VAL,Read Only value of comparator output" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list ad:0x42BB0400 ad:0x42BB0600)
|
|
tree "LUT_CFG[$1]"
|
|
base $2
|
|
repeat 128. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "LUT_DATA[$1],LUT Waveform Data"
|
|
hexmask.long.word 0x0 0.--9. 1. "DATA,DAC waveform"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x42BB0000
|
|
newline
|
|
group.long 0xA00++0x3
|
|
line.long 0x0 "CSG_CTRL,CSG control register"
|
|
bitfld.long 0x0 8. "CSG_CLK_DIV_BYP,N/A" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "VDAC_OUT_SEL,Select the DAC output for SAR conversion"
|
|
group.long 0xB00++0xB
|
|
line.long 0x0 "DAC_INTR,DAC Interrupt register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DAC_BUF_EMPTY,When BUFFERED or HYSTERETIC mode is enabled this interrupt is set when there is a DAC UPDATE trigger that transfers the buffered value(s) to active value(s) (see mode operation) and it means that the user may write new values to the buffer.."
|
|
hexmask.long.byte 0x0 8.--15. 1. "DAC_SLOPE_DONE,When SLOPE or LUT mode is enabled this interrupt is set when the SLOPE (or LUT waveform) has completed."
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAC_HW_START,This DAC_MODE operation was started with a HW START trigger."
|
|
line.long 0x4 "DAC_INTR_SET,DAC Interrupt request set register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DAC_BUF_EMPTY,Write with '1' to set corresponding bit in interrupt request register."
|
|
hexmask.long.byte 0x4 8.--15. 1. "DAC_SLOPE_DONE,Write with '1' to set corresponding bit in interrupt request register."
|
|
hexmask.long.byte 0x4 0.--7. 1. "DAC_HW_START,Write with '1' to set corresponding bit in interrupt request register."
|
|
line.long 0x8 "DAC_INTR_MASK,DAC Interrupt request mask"
|
|
hexmask.long.byte 0x8 16.--23. 1. "DAC_BUF_EMPTY,Mask bit for corresponding bit in interrupt request register."
|
|
hexmask.long.byte 0x8 8.--15. 1. "DAC_SLOPE_DONE,Mask bit for corresponding bit in interrupt request register."
|
|
hexmask.long.byte 0x8 0.--7. 1. "DAC_HW_START,Mask bit for corresponding bit in interrupt request register."
|
|
rgroup.long 0xB0C++0x3
|
|
line.long 0x0 "DAC_INTR_MASKED,DAC Interrupt request masked"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DAC_BUF_EMPTY,Logical and of corresponding request and mask bits."
|
|
hexmask.long.byte 0x0 8.--15. 1. "DAC_SLOPE_DONE,Logical and of corresponding request and mask bits."
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAC_HW_START,Logical and of corresponding request and mask bits."
|
|
group.long 0xB10++0xB
|
|
line.long 0x0 "CMP_INTR,CMP Interrupt register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CMP,This CMP(n) state has generated an interrupt request (see CSG_SLICE.CMP_CTRL.CMP_MODE)"
|
|
line.long 0x4 "CMP_INTR_SET,CMP Interrupt request set register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "CMP,Write with '1' to set corresponding bit in interrupt request register."
|
|
line.long 0x8 "CMP_INTR_MASK,CMP Interrupt request mask"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CMP,Mask bit for corresponding bit in interrupt request register."
|
|
rgroup.long 0xB1C++0x3
|
|
line.long 0x0 "CMP_INTR_MASKED,CMP Interrupt request masked"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CMP,Logical and of corresponding request and mask bits."
|
|
group.long 0xB20++0x3
|
|
line.long 0x0 "VDAC_OUT_BLANK,Blanking control for DAC Observability"
|
|
hexmask.long.byte 0x0 0.--4. 1. "BLANK_CNT,This field enables blanking iin CLK_CSG cycles of the Comparator output when one of the DACs in a CSG SLICE is connected as an input for SAR conversion (See CTRL.VDAC_OUT_SEL)"
|
|
group.long 0xB30++0x3
|
|
line.long 0x0 "CSG_SYNC,CSG Sync Enable register"
|
|
bitfld.long 0x0 0. "SYNC_EN,Risk Mitigation only. By default the CSG Hard IP and comparator output is synchronous to CLK_CSG. When this bit is set to '1' the CSG comparator output is double synced." "0,1"
|
|
tree.end
|
|
tree "INFRA (MCPASS infrastructure)"
|
|
base ad:0x42BE0000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "TR_IN_SEL,Trigger Input Select"
|
|
bitfld.long 0x0 28.--30. "TR7_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. "TR6_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "TR5_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "TR4_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "TR3_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "TR2_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "TR1_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "TR0_SEL,Trigger selection." "0: Trigger is off,1: Select an external HW trigger from A trigger..,2: Select the external HW trigger from B trigger..,3: Select FW PULSE trigger. See FW_TR_IN_PULSE.,4: Select FW LEVEL trigger. See FW_TR_IN_LEVEL.,?,?,?"
|
|
line.long 0x4 "HW_TR_MODE,HW Trigger Mode"
|
|
hexmask.long.byte 0x4 28.--31. 1. "HW_TR7_MODE,N/A"
|
|
hexmask.long.byte 0x4 24.--27. 1. "HW_TR6_MODE,N/A"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "HW_TR5_MODE,N/A"
|
|
hexmask.long.byte 0x4 16.--19. 1. "HW_TR4_MODE,N/A"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "HW_TR3_MODE,N/A"
|
|
hexmask.long.byte 0x4 8.--11. 1. "HW_TR2_MODE,N/A"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "HW_TR1_MODE,N/A"
|
|
hexmask.long.byte 0x4 0.--3. 1. "HW_TR0_MODE,If HW trigger is selected this controls the trigger mode."
|
|
line.long 0x8 "FW_TR_PULSE,FW Pulse Mode Trigger"
|
|
hexmask.long.byte 0x8 0.--7. 1. "FW_TR_PULSE,If FW is selected in TR_IN_SEL A write of '1' to this register will generate an internal PULSE trigger. These bits will be cleared automatically by HW."
|
|
line.long 0xC "FW_TR_LEVEL,FW Level Mode Trigger"
|
|
hexmask.long.byte 0xC 0.--7. 1. "FW_TR_LEVEL,If FW is selected in TR_IN_SEL Writes to this register will be passed to the internal trigger as a LEVEL '1' or '0."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CLOCK_STARTUP_DIV,Startup Clock Divder"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_VAL,Divide MCPASS a prescaled clock divide to generate block startup delays. Actual divide value is DIV_VAL+1."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "STARTUP_CFG[$1],Startup configuration"
|
|
bitfld.long 0x0 11. "CSG_READY,CSG Auto Zero/Comparator gate startup" "0,1"
|
|
bitfld.long 0x0 10. "CSG_PWR_EN_SLICE,CSG Slice Enable startup" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CSG_CH_EN,CSG Channel Enable startup" "0,1"
|
|
bitfld.long 0x0 8. "SAR_EN,SAR startup" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "COUNT_VAL,Actual count value is COUNT_VAL+1"
|
|
repeat.end
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "VDDA_STATUS,Analog Voltage Status"
|
|
bitfld.long 0x0 0. "VDDA_OK,Read only status bit to determine the presence of VDDA. This bit is set by HW and it must be 1 prior to enabling the SAR or CSG." "0: VDDA is below minimum threshold,1: VDDA is at or above minimum threhold"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "ANA_CTRL,Analog Control"
|
|
bitfld.long 0x0 3. "FORCE_OVERLOAD_EN_1,Override for Analog OVERLOAD Hardware circuit" "0: (default,1: Force OVERLOAD enable on"
|
|
bitfld.long 0x0 2. "FORCE_OVERLOAD_EN_0,Override for Analog OVERLOAD Hardware circuit." "0: (default,1: Force OVERLOAD enable off"
|
|
newline
|
|
bitfld.long 0x0 1. "FORCE_POR_1,Override for Analog POR Hardware circuit." "0: (default,1: Force POR negated"
|
|
bitfld.long 0x0 0. "FORCE_POR_0,Override for Analog POR Hardware circuit." "0: (default,1: Force POR asserted"
|
|
tree "AREFV2 (AREF Configuration)"
|
|
base ad:0x42BE0E00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "AREF_CTRL,AREF control"
|
|
bitfld.long 0x0 31. "ENABLED,- 0: AREF disabled" "0: AREF disabled,1: AREF enabled"
|
|
bitfld.long 0x0 20.--21. "VREF_SEL,N/A" "0: N/A,1: Use locally generated Vref,2: Use externally supplied Vref (aref_ext_vref),?"
|
|
bitfld.long 0x0 16. "IZTAT_SEL,N/A" "0: N/A,1: Use locally generated 250nA"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CTB_IPTAT_REDIRECT,N/A"
|
|
bitfld.long 0x0 7. "CTB_IPTAT_SCALE,N/A" "0,1"
|
|
bitfld.long 0x0 4.--6. "AREF_RMB,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "AREF_BIAS_SCALE,N/A" "0,1,2,3"
|
|
bitfld.long 0x0 0. "AREF_MODE,N/A" "0,1"
|
|
tree.end
|
|
base ad:0x42BE0000
|
|
newline
|
|
group.long 0xF00++0x1F
|
|
newline
|
|
line.long 0x0 "VREF_TRIM0,VREF Trim bits"
|
|
hexmask.long.byte 0x0 0.--7. 1. "VREF_ABS_TRIM,N/A"
|
|
line.long 0x4 "VREF_TRIM1,VREF Trim bits"
|
|
hexmask.long.byte 0x4 0.--7. 1. "VREF_TEMPCO_TRIM,N/A"
|
|
line.long 0x8 "VREF_TRIM2,VREF Trim bits"
|
|
hexmask.long.byte 0x8 0.--7. 1. "VREF_CURV_TRIM,N/A"
|
|
line.long 0xC "VREF_TRIM3,VREF Trim bits"
|
|
hexmask.long.byte 0xC 0.--3. 1. "VREF_ATTEN_TRIM,Obsolete"
|
|
line.long 0x10 "IZTAT_TRIM0,IZTAT Trim bits"
|
|
hexmask.long.byte 0x10 0.--7. 1. "IZTAT_ABS_TRIM,N/A"
|
|
line.long 0x14 "IZTAT_TRIM1,IZTAT Trim bits"
|
|
hexmask.long.byte 0x14 0.--7. 1. "IZTAT_TC_TRIM,IZTAT temperature correction trim (RMB)"
|
|
line.long 0x18 "IPTAT_TRIM0,IPTAT Trim bits"
|
|
hexmask.long.byte 0x18 4.--7. 1. "IPTAT_CTBM_TRIM,CTMB PTAT Current Trim"
|
|
hexmask.long.byte 0x18 0.--3. 1. "IPTAT_CORE_TRIM,IPTAT trim"
|
|
line.long 0x1C "ICTAT_TRIM0,ICTAT Trim bits"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "ICTAT_TRIM,ICTAT trim"
|
|
tree.end
|
|
tree "MMIO (MCPASS top-level MMIO)"
|
|
base ad:0x42BF0000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "FIFO_INTR,FIFO Interrupt request register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FIFO_LEVEL,This field will be '1' when STATUS.USED >= CTRL.LEVEL+1 and '0' when STATUS.USED < CTRL.LEVEL+1 for the indicated FIFO. This interrupt is level based."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "FIFO_INTR_SET,FIFO Interrupt set request register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FIFO_LEVEL_SET,Write with '1' to set corresponding bit in interrupt request register."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FIFO_INTR_MASK,FIFO Interrupt mask register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FIFO_LEVEL_MASK,Mask bit for corresponding bit in interrupt request register."
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "FIFO_INTR_MASKED,FIFO Interrupt masked request register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FIFO_LEVEL_MASKED,Logical and of corresponding request and mask bits."
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "HPPASS_INTR,MCPASS Interrupt request register"
|
|
bitfld.long 0x0 12. "AC_INT,HW sets this field to '1' when the AC generates a programmed interrupt." "0,1"
|
|
bitfld.long 0x0 10. "ENTRY_HOLD_VIOLATION,HW sets this bit if the samplers in a SAR Entry are in HOLD state longer than the programmed count value ." "0,1"
|
|
bitfld.long 0x0 9. "ENTRY_TR_COLLISION,HW sets this bit if a SAR Entry trigger is asserted while that Entry is in progress from triggering until conversion is complete." "0,1"
|
|
bitfld.long 0x0 8. "RESULT_OVERFLOW,HW sets this field to '1 on RESULT overflow. This bit is set when new SAR Entry or FIR results are written and the associated bit the the INTR_SAR_RESULT register bit is set implying the previous results have not been read." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "FIFO_UNDERFLOW,HW sets this field to '1' when reading from an empty FIFO.. See FIFO_CFG/STATUS (read and write pointers) and FIFO_CFG/USED register for detailed infomration."
|
|
hexmask.long.byte 0x0 0.--3. 1. "FIFO_OVERFLOW,HW sets this field to '1' when writing to a full FIFO. See FIFO_CFG/STATUS (read and write pointers) and FIFO_CFG/USED register for detailed infomration."
|
|
line.long 0x4 "HPPASS_INTR_SET,MCPASS Interrupt set request register"
|
|
bitfld.long 0x4 12. "AC_INT_SET,Write with '1' to set corresponding bit in interrupt request register. (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 10. "ENTRY_HOLD_VIOLATION_SET,Write with '1' to set corresponding bit in interrupt request register. (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 9. "ENTRY_TR_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register. (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 8. "RESULT_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register. (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "FIFO_UNDERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register. (a write of '0' has no effect)."
|
|
hexmask.long.byte 0x4 0.--3. 1. "FIFO_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register. (a write of '0' has no effect)."
|
|
line.long 0x8 "HPPASS_INTR_MASK,MCPASS Interrupt mask register"
|
|
bitfld.long 0x8 12. "AC_INT_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 10. "ENTRY_HOLD_VIOLATION_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 9. "ENTRY_TR_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 8. "RESULT_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "FIFO_UNDERFLOW_MASK,Mask bit for corresponding bit in interrupt request register."
|
|
hexmask.long.byte 0x8 0.--3. 1. "FIFO_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register."
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "HPPASS_INTR_MASKED,MCPASS Interrupt masked request register"
|
|
bitfld.long 0x0 12. "AC_INT_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 10. "ENTRY_HOLD_VIOLATION_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 9. "ENTRY_TR_COLLISION_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 8. "RESULT_OVERFLOW_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "FIFO_UNDERFLOW_MASKED,Logical and of corresponding request and mask bits."
|
|
hexmask.long.byte 0x0 0.--3. 1. "FIFO_OVERFLOW_MASKED,Logical and of corresponding request and mask bits."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "TR_LEVEL_CFG,LEVEL Trigger out configuration"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BYPASS_SYNC,When this bit is set the output flip-flop for the given TR_LEVEL_OUT is bypassed."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x60)++0x3
|
|
line.long 0x0 "TR_LEVEL_OUT[$1],LEVEL Trigger out select register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SAR_RANGE_TR,Enable the selected SAR_RANGE output which are then ORed and routed to the associated trigger"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CMP_TR,Enable the selected CMP outputs which are then ORed and routed to the associated trigger"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "TR_PULSE_OUT[$1],PULSE Trigger out select register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SEL,Enable one of the available pulse trigger outputs for the associated trigger"
|
|
repeat.end
|
|
tree "FIFO (FIFO Configuration)"
|
|
base ad:0x42BF0100
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CFG,FIFO configuration register."
|
|
hexmask.long.byte 0x0 4.--7. 1. "FIFO_TR_EN,Enable associated FIFO trigger"
|
|
bitfld.long 0x0 0.--1. "SEL,N/A" "0,1,2,3"
|
|
line.long 0x4 "CLR,FIFO FW clear register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "CLR,Write a '1' to clear status for associtaed FIFO. This doesn't actually clear the data it just resets the pointers."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "LEVEL[$1],FIFO level register."
|
|
hexmask.long.byte 0x0 0.--4. 1. "LEVEL,FIFO level set. A trigger (and optional interrupt) event occurs when USED.USED = LEVEL+1."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x30)++0x3
|
|
line.long 0x0 "RD_DATA[$1],FIFO 32-bit read data register"
|
|
hexmask.long.tbyte 0x0 0.--20. 1. "RESULT,5-bit Channel ID (upper bits) 16-bit SAR/FIR result (lower bits)"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "USED[$1],FIFO used register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "USED,Number of used/occupied entries in the FIFO."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x70)++0x3
|
|
line.long 0x0 "STATUS[$1],FIFO status register"
|
|
hexmask.long.byte 0x0 16.--20. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data is written by the hardware."
|
|
hexmask.long.byte 0x0 0.--4. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data is read."
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "SAR (SAR ADC Controller)"
|
|
base ad:0x42B80000
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "SEQ_ENTRY[$1],SAR Sequencer Table Entries"
|
|
bitfld.long 0x0 31. "CONT,This bit enables continuous conversion for this entry. When this bit is set this entry will trigger immediately when the SAR is ENABLED and will be automatically re-triggered when this ENTRY has been completed." "0,1"
|
|
bitfld.long 0x0 30. "PRIORITY,This bit selects the priority for this entry. High Priority samplers ready for conversion witll be processed before Low Priority samplers." "0: Low Priority,1: High Priority"
|
|
bitfld.long 0x0 28.--29. "SAMP_TIME_SEL,Sample Time Select. By default there is no additional sample time after the trigger (samplers are transitioned to HOLD state immediately on a trigger event) or select 1 of 3 available Sample Times in SAR_CFG.SAMPLE_TIME registers" "0: N/A,1: N/A,2: N/A,3: N/A"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TR_SEL,Trigger select for this Entry. By default disabled or select 1 of 8 hardware triggers or AC trigger. Normally MCPASS internal triggers are PULSE triggers (see INFRA/TR_HW_MODE) however a LEVEL trigger may also be used but the trigger event.."
|
|
bitfld.long 0x0 22.--23. "MUX3_SEL,These bits control the input mux selection for sampler 15" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "MUX2_SEL,These bits control the input mux selection for sampler 14" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MUX1_SEL,These bits control the input mux selection for sampler 13" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MUX0_SEL,These bits control the input mux selection for sampler 12" "0,1,2,3"
|
|
hexmask.long.byte 0x0 12.--15. 1. "MUXED_SAMPLER_EN,These bits enable the 4 muxed samplers in this Entry. When this Entry is triggered any samplers with a bit set to '1' will be simultaneously sampled held and then converted. The mux setting for these samplers is determined by the.."
|
|
hexmask.long.word 0x0 0.--11. 1. "DIRECT_SAMPLER_EN,These bits enable the 12 direct samplers in this Entry. When this Entry is triggered any samplers with a bit set to '1' will be simultaneously sampled held and then converted. There is a 1-1 correspondence between these 12 samplers.."
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "ENTRY_MUX_SEL_ALIAS[$1],SAR Sequencer MUX select alias registers"
|
|
bitfld.long 0x0 22.--23. "MUX3_SEL,Update SEQ_ENTRY.MUX3_SEL field" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MUX2_SEL,Update SEQ_ENTRY.MUX2_SEL field" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MUX1_SEL,Update SEQ_ENTRY.MUX1_SEL field" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MUX0_SEL,Update SEQ_ENTRY.MUX0_SEL field" "0,1,2,3"
|
|
repeat.end
|
|
tree "CFG (SAR configuration and result registers)"
|
|
base ad:0x42B80400
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRL,Control register"
|
|
bitfld.long 0x0 8. "CHAN_ID_EN,FIFO Channel Number Identifier Enable" "0: When the FIFO is selected for a channel or FIR..,1: Result data is stored in FIFO is tagged with.."
|
|
newline
|
|
bitfld.long 0x0 6. "STARTUP_CAL_GAIN_EN,Calibrate Gain on SAR Enable" "0: N/A,1: N/A"
|
|
newline
|
|
bitfld.long 0x0 5. "STARTUP_CAL_LINEARITY_EN,Calibration Linearity on SAR Enable" "0: N/A,1: N/A"
|
|
newline
|
|
bitfld.long 0x0 4. "STARTUP_CAL_OFFSET_EN,Calibration Offset on SAR Enable" "0: N/A,1: N/A"
|
|
newline
|
|
bitfld.long 0x0 2. "LOW_SUPPLY_MODE,Low Supply Mode control - set this bit if VDDA supply range < 2.7V" "0: Disabled VDDA supply is >= 2.7V,1: Enabled VDDA supply is < 2.7V"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "VREF_SEL,SARADC VREF selection." "0: N/A,1: N/A,2: N/A,3: N/A"
|
|
line.long 0x4 "SAMP_EN,Sampler static enable configuration register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "MUXED_SAMP_EN,Static Enables for Muxed Samplers. Must be set if in use by application otherwise it is OFF and must not be selected in any SAR Entry."
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "DIRECT_SAMP_EN,Static Enables for Direct Samplers. Must be set if in use by application otherwise it is OFF and must not be selected in any SAR Entry."
|
|
line.long 0x8 "SAMP_GAIN,Sampler gain configuration register"
|
|
hexmask.long 0x8 0.--31. 1. "SAMP_GAIN,Static Sampler Gain"
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SAMPLE_TIME[$1],Sample Time configuration register"
|
|
hexmask.long.word 0x0 0.--9. 1. "SAMPLE_TIME,Sample time (aperture) in given by (SAMPLE_TIME+1) clock cycles of CLK_HF/2. The range is 0..1023 which results in:"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "FIR_CFG[$1],FIR configuration register"
|
|
bitfld.long 0x0 28.--30. "FIFO_SEL,FIFO selections. Select 1 of the 4 for FIFOs for data storage" "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,?,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "RANGE_SEL,Range detection. Select 1 of the 8 RANGE detection modules"
|
|
newline
|
|
bitfld.long 0x0 8. "WAIT_TAP_INIT,Wait for 16 samples before the first output is stored into a FIR_RESULT register or FIFO. This allows the user to ignore the FIR outputs until the FIR pipeline is initialized. ." "0: N/A,1: N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "CHANNEL_SEL,Select which SAR channel will be the source for a given FIR input. When a new conversion output is available the 16-tap FIR calculation is initiated (17 cycles for 16 taps) and a new FIR output is generated."
|
|
repeat.end
|
|
repeat 28. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "CHAN_CFG[$1],SAR Channel configuration register"
|
|
bitfld.long 0x0 28.--30. "FIFO_SEL,FIFO Select. Select 1 of the 4 for FIFO data storage." "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "AVG_SEL,Enable averaging for this channel. This implementation is accumulation only. There is no hardware shift option. For example if AVG_2 is selected the RESULT register (or FIFO) will contain a 13-bit result for AVG_4 the RESULT register will.." "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,5: N/A,6: N/A,7: N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "RANGE_SEL,Enable and select a RANGE resource for this channel"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "RSVD_15_12,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "RSVD_11_8,N/A"
|
|
newline
|
|
bitfld.long 0x0 1. "SIGNED,Signed Data Option" "0: Result data unsigned,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x0 0. "DIFFERENTIAL_EN,Differential Enable." "0: Single Ended operation,1: Pseudo Differential operation NOTE: Averaging.."
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xB0)++0x3
|
|
line.long 0x0 "RANGE_CFG[$1],Range detect configuration register."
|
|
bitfld.long 0x0 0.--1. "RANGE_COND,Range condition select." "0: result < RANGE_LOW,1: RANGE_LOW <= result < RANGE_HIGH,2: result > RANGE_HIGH,3: result < RANGE_LOW || result >= RANGE_HIGH"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xD0)++0x3
|
|
line.long 0x0 "RANGE_LOW[$1],Range detect low value register."
|
|
hexmask.long.word 0x0 0.--15. 1. "RANGE_LOW,Low threshold for range detect"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "RANGE_HIGH[$1],Range detect high value register."
|
|
hexmask.long.word 0x0 0.--15. 1. "RANGE_HIGH,High threshold for range detect"
|
|
repeat.end
|
|
repeat 28. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x110)++0x3
|
|
line.long 0x0 "CHAN_RESULT[$1],Channel result register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RESULT,SAR conversion working data of the channel. The data is written here if the corresponding bit if RESULT_MASK is set. (default is to write to CHAN_RESULT). The RESULT_MASK may be cleared if the channel data is targeted for the FIFO."
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x180)++0x3
|
|
line.long 0x0 "FIR_RESULT[$1],FIR result register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RESULT,FIR output data. The data is written here if the corresponding bit in RESULT_MASK is set. (default is to write to FIR_RESULT) . The RESULT_MASK may be cleared if the FIR data is targeted for the FIFO."
|
|
repeat.end
|
|
group.long 0x190++0xB
|
|
line.long 0x0 "RESULT_MASK,Channel result mask"
|
|
bitfld.long 0x0 30.--31. "FIR_RESULT_MASK,If set (default) the FIR_RESULT register will be used to store SAR conversion data for a given Entry and the associated ENTRY_DONE Interrupt will be generated. If this bit isn't set the channel must be configured to store the result in.." "0,1,2,3"
|
|
newline
|
|
hexmask.long 0x0 0.--27. 1. "CHAN_RESULT_MASK,If set (default) the CHAN_RESULT register will be used to store SAR conversion data for a given Entry and the associated ENTRY_DONE Interrupt will be generated. If this bit isn't set the channel must be configured to store the result.."
|
|
line.long 0x4 "RESULT_UPDATED,Channel result register status"
|
|
bitfld.long 0x4 30.--31. "FIR_RESULT_UPDATED,Each bit will be set when the corresponding FIR_RESULT register is updated with a new result. Write 1 to clear." "0,1,2,3"
|
|
newline
|
|
hexmask.long 0x4 0.--27. 1. "CHAN_RESULT_UPDATED,Each bit will be set when the corresponding CHAN_RESULT register is updated with a new result. Write 1 to clear."
|
|
line.long 0x8 "RANGE_STATUS,Range status register"
|
|
bitfld.long 0x8 30.--31. "FIR_RANGE,A given bit in this register will be set if the conversion result (after averaging) of that channel met the condition specified by the selected RANGE registers. Write with '1' to clear bit." "0,1,2,3"
|
|
newline
|
|
hexmask.long 0x8 0.--27. 1. "CHAN_RANGE,A given bit in this register will be set if the conversion result (after averaging) of that channel met the condition specified by the selected RANGE registers. Write with '1' to clear bit."
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x0 "SAR_STATUS,SAR status register"
|
|
bitfld.long 0x0 31. "BUSY,If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down." "0,1"
|
|
group.long 0x1A0++0xF
|
|
line.long 0x0 "RESULT_OVERFLOW,Entry overflow status"
|
|
bitfld.long 0x0 16.--17. "FIR_RESULT_OVF,The associated bit is set in this register if the new FIR results are written before the associated SAR_RESULT_INTR/FIR_DONE bit has been cleared from the previous trigger.. This bit may be cleared by writing a '1' to the associated bit." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ENTRY_RESULT_OVF,The associated bit is set in this register if the new Entry results are written before the associated SAR_RESULT_INTR/ENTRY_DONE bit has been cleared from the previous trigger. This bit may be cleared by writing a '1' to the associated.."
|
|
line.long 0x4 "ENTRY_TR_COLLISION,Entry trigger collision status"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ENTRY_COL,The associated bit is set in this register if an Entry is triggered while processing for the previous trigger is still in progress including sampling conversion and post processing."
|
|
line.long 0x8 "ENTRY_HOLD_VIOLATION,Entry hold violation status"
|
|
hexmask.long.byte 0x8 0.--7. 1. "HOLD_VIOL,The associated bit is set in this register if an Entry (and it's associated samplers) are in HOLD state greater than the ENTRY_HOLD_CNT value (see directly below) which indicates the associated channel results may not meet ADC accuracy specs."
|
|
line.long 0xC "ENTRY_HOLD_CNT,Entry hold violation count"
|
|
hexmask.long.byte 0xC 0.--7. 1. "HOLD_CNT,This is the a global max HOLD count applied to all Entries. (See ENTRY_HOLD_VIOLATION above)."
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "SAR_RESULT_INTR,SAR Interrupt register"
|
|
bitfld.long 0x0 16.--17. "FIR_DONE,The associated FIR_DONE(N) status is set. The FIR_RESULT registers for the FIR modules are ready for reading" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ENTRY_DONE,The associated ENTRY_DONE(N) status is set. The CHAN_RESULT registers for channels in this entry are ready for reading."
|
|
line.long 0x4 "SAR_RESULT_INTR_SET,SAR Interrupt request set register"
|
|
bitfld.long 0x4 16.--17. "FIR_DONE_SET,Write with '1' to set corresponding bit in interrupt request register. (a write of '0' has no effect)." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "ENTRY_DONE_SET,Write with '1' to set corresponding bit in interrupt request register. (a write of '0' has no effect)."
|
|
line.long 0x8 "SAR_RESULT_INTR_MASK,SAR Interrupt request mask"
|
|
bitfld.long 0x8 16.--17. "FIR_DONE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "ENTRY_DONE_MASK,Mask bit for corresponding bit in interrupt request register."
|
|
rgroup.long 0x20C++0x3
|
|
line.long 0x0 "SAR_RESULT_INTR_MASKED,SAR Interrupt request masked"
|
|
bitfld.long 0x0 16.--17. "FIR_DONE_MASKED,Logical and of corresponding request and mask bits." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ENTRY_DONE_MASKED,Logical and of corresponding request and mask bits."
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "SAR_RANGE_INTR,SAR Range Interrupt register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RANGE,The associated RANGE(N) status is set. The associated RANGE_STATUS is also set and available for reading."
|
|
line.long 0x4 "SAR_RANGE_INTR_SET,SAR Range Interrupt request set register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RANGE_SET,Write with '1' to set corresponding bit in interrupt request register."
|
|
line.long 0x8 "SAR_RANGE_INTR_MASK,SAR Range Interrupt request mask"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RANGE_SET_MASK,Mask bit for corresponding bit in interrupt request register."
|
|
rgroup.long 0x21C++0x3
|
|
line.long 0x0 "SAR_RANGE_INTR_MASKED,SAR Range Interrupt request masked"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RANGE_SET_MASKED,Logical and of corresponding request and mask bits."
|
|
repeat 14. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x230)++0x3
|
|
line.long 0x0 "CHAN_RESULT_PACKED[$1],Channel result register packed with 2 results per register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESULT_ODD,Odd numbered channel results. (e.g. 1 3 5 ... 27)"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RESULT_EVEN,Even numbered channel results (e.g. 0 2 4 ... 26)"
|
|
repeat.end
|
|
group.long 0x300++0xB
|
|
line.long 0x0 "AROUTE_CTRL_MODE,AROUTE control mode"
|
|
bitfld.long 0x0 31. "AROUTE_ENABLED,Global AROUTE Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 30. "TEMPSENSE_ENABLED,NOTE: This register field has been depricated and no longer in use. It may be left at the default value of '1' or it may be cleared to '0'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MUX3_CTRL,The associated AROUTE MUX is controlled by the SAR sequencer or by FW or AC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "MUX2_CTRL,The associated AROUTE MUX is controlled by the SAR sequencer or by FW or AC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MUX1_CTRL,The associated AROUTE MUX is controlled by the SAR sequencer or by FW or AC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "MUX0_CTRL,The associated AROUTE MUX is controlled by the SAR sequencer by static FW setting or AC" "0,1,2,3"
|
|
line.long 0x4 "AROUTE_FW_CTRL,AROUTE firmware switch control set (individual)"
|
|
bitfld.long 0x4 15. "MUX3_SW3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "MUX3_SW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MUX3_SW1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "MUX3_SW0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MUX2_SW3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "MUX2_SW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MUX2_SW1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "MUX2_SW0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MUX1_SW3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "MUX1_SW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MUX1_SW1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MUX1_SW0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MUX0_SW3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MUX0_SW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MUX0_SW1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MUX0_SW0,Firmware control: 0=open 1=close switch. Write with '1' to set bit." "0: open,1: close switch"
|
|
line.long 0x8 "AROUTE_FW_CTRL_CLR,AROUTE firmware switch control clear (individual)"
|
|
bitfld.long 0x8 15. "MUX3_SW3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "MUX3_SW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "MUX3_SW1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "MUX3_SW0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "MUX2_SW3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MUX2_SW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "MUX2_SW1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "MUX2_SW0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "MUX1_SW3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "MUX1_SW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "MUX1_SW1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MUX1_SW0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "MUX0_SW3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "MUX0_SW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "MUX0_SW1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "MUX0_SW0,Write '1' to clear corresponding bit in AROUTE_FW_CTRL. A read of this register returns the values of AROUTE_FW_CTRL." "0,1"
|
|
rgroup.long 0x30C++0x3
|
|
line.long 0x0 "AROUTE_STATUS,AROUTE switch status"
|
|
bitfld.long 0x0 15. "MUX3_SW3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "MUX3_SW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MUX3_SW1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MUX3_SW0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MUX2_SW3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MUX2_SW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MUX2_SW1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MUX2_SW0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MUX1_SW3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MUX1_SW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MUX1_SW1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MUX1_SW0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MUX0_SW3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MUX0_SW2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MUX0_SW1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MUX0_SW0,Read back the current state of the associated switch control (regardless of mode)" "0,1"
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "TEMPSENSE_CTRL,Temperture Sensor Control"
|
|
bitfld.long 0x0 0. "TEMPSENSE_CURRENT_SEL,Used for Delta Vbe Temperature Sensor Algoritm (see BROS for full details)" "0: BJT current is 1uA,1: Add 8uA to BJT current"
|
|
tree.end
|
|
repeat 2. (list 0x0 0x1)(list ad:0x42B80800 ad:0x42B80880)
|
|
tree "FIR[$1]"
|
|
base $2
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "FIR_COEFS[$1],FIR Coeffecients"
|
|
hexmask.long.word 0x0 0.--15. 1. "COEF,FIR Coefficient Value"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "FIR_TAPS[$1],FIR Taps"
|
|
hexmask.long.word 0x0 0.--15. 1. "TAP,FIR Tap Value"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SARADC (SAR ADC Core (Calibration and Test))"
|
|
base ad:0x42B70000
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "CALOFFST[$1],SARADC Offset Calibration Values"
|
|
hexmask.long.byte 0x0 24.--30. 1. "OFFSET_4N_3,7-bit signed offset calibration value for sampler 4n + 3"
|
|
hexmask.long.byte 0x0 16.--22. 1. "OFFSET_4N_2,7-bit signed offset calibration value for sampler 4n + 2"
|
|
hexmask.long.byte 0x0 8.--14. 1. "OFFSET_4N_1,7-bit signed offset calibration value for sampler 4n + 1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "OFFSET_4N_0,7-bit signed offset calibration value for sampler 4n + 0"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "CALLIN[$1],SARADC Linearity Calibration Values"
|
|
hexmask.long.byte 0x0 24.--30. 1. "LIN12,7 bit signed linearity calibration value for bit 12 of this sampler"
|
|
hexmask.long.byte 0x0 16.--22. 1. "LIN11,7 bit signed linearity calibration value for bit 11 of this sampler"
|
|
hexmask.long.byte 0x0 8.--14. 1. "LIIN10,7 bit signed linearity calibration value for bit 10 of this sampler"
|
|
hexmask.long.byte 0x0 0.--6. 1. "LIN9,7 bit signed linearity calibration value for bit 9 of this sampler"
|
|
repeat.end
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "CALGAINC,SARADC Coarse-grained Gain Calibration Values"
|
|
hexmask.long.byte 0x0 16.--19. 1. "GAINC12,Coarse-grained gain calibration value for gain=12 setting"
|
|
hexmask.long.byte 0x0 8.--11. 1. "GAINC6,Coarse-grained gain calibration value for gain=6 setting"
|
|
hexmask.long.byte 0x0 0.--3. 1. "GAINC3,Coarse-grained gain calibration value for gain=3 setting"
|
|
line.long 0x4 "CALGAINF,SARADC Fine-grained Gain Calibration Values"
|
|
hexmask.long.byte 0x4 16.--22. 1. "GAINF12,7-bit signed fine-grained gain calibration value for gain=12 setting"
|
|
hexmask.long.byte 0x4 8.--14. 1. "GAINF6,7-bit signed fine-grained gain calibration value for gain=6 setting"
|
|
hexmask.long.byte 0x4 0.--6. 1. "GAINF3,7-bit signed fine-grained gain calibration value for gain=3 setting"
|
|
tree.end
|
|
tree.end
|
|
tree "HSIOM (High-Speed I/O Matrix)"
|
|
base ad:0x42400000
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x42400000 ad:0x42400010 ad:0x42400020 ad:0x42400030 ad:0x42400040 ad:0x42400050 ad:0x42400060 ad:0x42400070 ad:0x42400080 ad:0x42400090)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PORT_SEL0,Port selection 0"
|
|
hexmask.long.byte 0x0 24.--28. 1. "IO3_SEL,Selects connection for IO pin 3 route."
|
|
hexmask.long.byte 0x0 16.--20. 1. "IO2_SEL,Selects connection for IO pin 2 route."
|
|
hexmask.long.byte 0x0 8.--12. 1. "IO1_SEL,Selects connection for IO pin 1 route."
|
|
hexmask.long.byte 0x0 0.--4. 1. "IO0_SEL,Selects connection for IO pin 0 route."
|
|
line.long 0x4 "PORT_SEL1,Port selection 1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "IO7_SEL,Selects connection for IO pin 7 route."
|
|
hexmask.long.byte 0x4 16.--20. 1. "IO6_SEL,Selects connection for IO pin 6 route."
|
|
hexmask.long.byte 0x4 8.--12. 1. "IO5_SEL,Selects connection for IO pin 5 route."
|
|
hexmask.long.byte 0x4 0.--4. 1. "IO4_SEL,Selects connection for IO pin 4 route."
|
|
tree.end
|
|
repeat.end
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x42401000 ad:0x42401010 ad:0x42401020 ad:0x42401030 ad:0x42401040 ad:0x42401050 ad:0x42401060 ad:0x42401070 ad:0x42401080 ad:0x42401090)
|
|
tree "SECURE_PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "NONSECURE_MASK,Non-Secure Mask"
|
|
bitfld.long 0x0 7. "NONSECURE7,Non-secure attribute for IO7." "0,1"
|
|
bitfld.long 0x0 6. "NONSECURE6,Non-secure attribute for IO6." "0,1"
|
|
bitfld.long 0x0 5. "NONSECURE5,Non-secure attribute for IO5." "0,1"
|
|
bitfld.long 0x0 4. "NONSECURE4,Non-secure attribute for IO4." "0,1"
|
|
bitfld.long 0x0 3. "NONSECURE3,Non-secure attribute for IO3." "0,1"
|
|
bitfld.long 0x0 2. "NONSECURE2,Non-secure attribute for IO2." "0,1"
|
|
bitfld.long 0x0 1. "NONSECURE1,Non-secure attribute for IO1." "0,1"
|
|
bitfld.long 0x0 0. "NONSECURE0,Non-secure attribute for IO0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x42400000
|
|
newline
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2000)++0x3
|
|
line.long 0x0 "AMUX_SPLIT_CTL[$1],AMUX splitter cell control"
|
|
bitfld.long 0x0 6. "SWITCH_BB_S0,T-switch control for AMUXBUSB vssa/ground switch." "0,1"
|
|
bitfld.long 0x0 5. "SWITCH_BB_SR,T-switch control for Right AMUXBUSB switch." "0,1"
|
|
bitfld.long 0x0 4. "SWITCH_BB_SL,T-switch control for Left AMUXBUSB switch." "0,1"
|
|
bitfld.long 0x0 2. "SWITCH_AA_S0,T-switch control for AMUXBUSA vssa/ground switch:" "0: switch open,1: switch closed"
|
|
newline
|
|
bitfld.long 0x0 1. "SWITCH_AA_SR,T-switch control for Right AMUXBUSA switch:" "0: switch open,1: switch closed"
|
|
bitfld.long 0x0 0. "SWITCH_AA_SL,T-switch control for Left AMUXBUSA switch:" "0: switch open,1: switch closed"
|
|
repeat.end
|
|
group.long 0x2200++0xF
|
|
line.long 0x0 "MONITOR_CTL_0,Power/Ground Monitor cell control 0"
|
|
hexmask.long 0x0 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0x4 "MONITOR_CTL_1,Power/Ground Monitor cell control 1"
|
|
hexmask.long 0x4 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0x8 "MONITOR_CTL_2,Power/Ground Monitor cell control 2"
|
|
hexmask.long 0x8 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0xC "MONITOR_CTL_3,Power/Ground Monitor cell control 3"
|
|
hexmask.long 0xC 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
tree.end
|
|
tree "ICACHE (Instruction Cache)"
|
|
base ad:0x42103000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Cache control"
|
|
bitfld.long 0x0 31. "CA_EN,Cache enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 30. "PREF_EN,Prefetch enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SET_ADDR,Specifies the cache set for which cache information is provided in STATUS0/1/2."
|
|
bitfld.long 0x0 16.--17. "WAY,Specifies the cache way for which cache information is provided in STATUS0/1/2." "0,1,2,3"
|
|
bitfld.long 0x0 1. "ECC_INJ_EN,Enable error injection for cache." "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,Enable ECC checking for cache accesses:" "0: Disabled,1: Enabled"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD,Cache command"
|
|
bitfld.long 0x0 1. "BUFF_INV,Invalidation of buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed." "0,1"
|
|
bitfld.long 0x0 0. "INV,Invalidation of cahce and buffer. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The caches' LRU structures are also reset to their default state." "0,1"
|
|
rgroup.long 0x80++0xB
|
|
line.long 0x0 "STATUS0,Cache status 0"
|
|
hexmask.long 0x0 0.--31. 1. "VALID32,Sixteen valid bits of the cache line specified by CTL.WAY and CTL.SET_ADDR."
|
|
line.long 0x4 "STATUS1,Cache status 1"
|
|
hexmask.long 0x4 0.--31. 1. "TAG,Cache line address of the cache line specified by CTL.WAY and CTL.SET_ADDR."
|
|
line.long 0x8 "STATUS2,Cache status 2"
|
|
hexmask.long.byte 0x8 0.--5. 1. "LRU,Six bit LRU representation of the cache set specified by CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y):"
|
|
tree.end
|
|
tree "IPC (Inter-Processor Communication)"
|
|
base ad:0x421D0000
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x421D0000 ad:0x421D0020 ad:0x421D0040 ad:0x421D0060)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "ACQUIRE,IPC acquire"
|
|
bitfld.long 0x0 31. "SUCCESS,N/A" "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,N/A"
|
|
bitfld.long 0x0 1. "NS,N/A" "0,1"
|
|
bitfld.long 0x0 0. "P,N/A" "0,1"
|
|
wgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "RELEASE,IPC release"
|
|
hexmask.long.word 0x0 0.--15. 1. "INTR_RELEASE,Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC.."
|
|
line.long 0x4 "NOTIFY,IPC notification"
|
|
hexmask.long.word 0x4 0.--15. 1. "INTR_NOTIFY,This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1' but only for those IPC interrupt structures for which the.."
|
|
group.long ($2+0xC)++0x7
|
|
line.long 0x0 "DATA0,IPC data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
line.long 0x4 "DATA1,IPC data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "LOCK_STATUS,IPC lock status"
|
|
bitfld.long 0x0 31. "ACQUIRED,N/A" "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,N/A"
|
|
bitfld.long 0x0 1. "NS,N/A" "0,1"
|
|
bitfld.long 0x0 0. "P,N/A" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list ad:0x421D1000 ad:0x421D1020)
|
|
tree "INTR_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
hexmask.long.word 0x4 16.--31. 1. "NOTIFY,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
hexmask.long.word 0x4 0.--15. 1. "RELEASE,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
hexmask.long.word 0x8 16.--31. 1. "NOTIFY,Mask bit for corresponding field in the INTR register."
|
|
hexmask.long.word 0x8 0.--15. 1. "RELEASE,Mask bit for corresponding field in the INTR register."
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,Logical and of corresponding INTR and INTR_MASK fields."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,Logical and of corresponding request and mask bits."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LPCOMP (Low Power Comparator)"
|
|
base ad:0x42430000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CONFIG,LPCOMP Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLED,- 0: LPCOMP disabled (puts analog in power down opens all switches all clocks turned off)" "0: LPCOMP disabled,1: LPCOMP enabled"
|
|
bitfld.long 0x0 30. "LPREF_EN,Enable the local reference generator circuit to generate the local Vref and Ibias. Ibias current is an alternative to the reference current IREF generated by SRSS. This bit must be set for System Deep Sleep and System Hibernate operation." "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,LPCOMP Status Register"
|
|
bitfld.long 0x0 16. "OUT1,Current output value of the comparator 1." "0,1"
|
|
bitfld.long 0x0 0. "OUT0,Current output value of the comparator 0." "0,1"
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "INTR,LPCOMP Interrupt request register"
|
|
bitfld.long 0x0 1. "COMP1,Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit." "0,1"
|
|
bitfld.long 0x0 0. "COMP0,Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit." "0,1"
|
|
line.long 0x4 "INTR_SET,LPCOMP Interrupt set register"
|
|
bitfld.long 0x4 1. "COMP1,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "COMP0,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,LPCOMP Interrupt request mask"
|
|
bitfld.long 0x8 1. "COMP1_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "COMP0_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "INTR_MASKED,LPCOMP Interrupt request masked"
|
|
bitfld.long 0x0 1. "COMP1_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "COMP0_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CMP0_CTRL,Comparator 0 control Register"
|
|
bitfld.long 0x0 11. "DSI_LEVEL0,Synchronous comparator output (trigger):" "0: pulse,1: level"
|
|
bitfld.long 0x0 10. "DSI_BYPASS0,Asynchronous: bypass comparator output synchronization:" "0: synchronize,1: bypass"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "INTTYPE0,N/A" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
bitfld.long 0x0 5. "HYST0,Add hysteresis to the comparator" "0: Disable Hysteresis,1: Enable Hysteresis"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "MODE0,N/A" "0: Off,1: Ultra lowpower operating mode (uses less power <..,2: Low Power operating mode (uses more power <10uA..,3: Normal full speed power operating mode (uses.."
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "CMP0_SW,Comparator 0 switch control"
|
|
bitfld.long 0x0 7. "CMP0_VN0,Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set)" "0,1"
|
|
bitfld.long 0x0 6. "CMP0_BN0,Comparator 0 negative terminal switch to amuxbusB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CMP0_AN0,Comparator 0 negative terminal switch to amuxbusA" "0,1"
|
|
bitfld.long 0x0 4. "CMP0_IN0,Comparator 0 negative terminal isolation switch to GPIO" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CMP0_BP0,Comparator 0 positive terminal switch to amuxbusB" "0,1"
|
|
bitfld.long 0x0 1. "CMP0_AP0,Comparator 0 positive terminal switch to amuxbusA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMP0_IP0,Comparator 0 positive terminal isolation switch to GPIO" "0,1"
|
|
line.long 0x4 "CMP0_SW_CLEAR,Comparator 0 switch control clear"
|
|
bitfld.long 0x4 7. "CMP0_VN0,see corresponding bit in CMP0_SW" "0,1"
|
|
bitfld.long 0x4 6. "CMP0_BN0,see corresponding bit in CMP0_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CMP0_AN0,see corresponding bit in CMP0_SW" "0,1"
|
|
bitfld.long 0x4 4. "CMP0_IN0,see corresponding bit in CMP0_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CMP0_BP0,see corresponding bit in CMP0_SW" "0,1"
|
|
bitfld.long 0x4 1. "CMP0_AP0,see corresponding bit in CMP0_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMP0_IP0,see corresponding bit in CMP0_SW" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "CMP1_CTRL,Comparator 1 control Register"
|
|
bitfld.long 0x0 11. "DSI_LEVEL1,Synchronous comparator output (trigger):" "0: pulse,1: level"
|
|
bitfld.long 0x0 10. "DSI_BYPASS1,Asynchronous: bypass comparator output synchronization:" "0: synchronize,1: bypass"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "INTTYPE1,N/A" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
bitfld.long 0x0 5. "HYST1,Add hysteresis to the comparator" "0: Disable Hysteresis,1: Enable Hysteresis"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "MODE1,N/A" "0: Off,1: Ultra lowpower operating mode (uses less power <..,2: Low Power operating mode (uses more power <10uA..,3: Normal full speed power operating mode (uses.."
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "CMP1_SW,Comparator 1 switch control"
|
|
bitfld.long 0x0 7. "CMP1_VN1,Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set)" "0,1"
|
|
bitfld.long 0x0 6. "CMP1_BN1,Comparator 1 negative terminal switch to amuxbusB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CMP1_AN1,Comparator 1 negative terminal switch to amuxbusA" "0,1"
|
|
bitfld.long 0x0 4. "CMP1_IN1,Comparator 1 negative terminal isolation switch to GPIO" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CMP1_BP1,Comparator 1 positive terminal switch to amuxbusB" "0,1"
|
|
bitfld.long 0x0 1. "CMP1_AP1,Comparator 1 positive terminal switch to amuxbusA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMP1_IP1,Comparator 1 positive terminal isolation switch to GPIO" "0,1"
|
|
line.long 0x4 "CMP1_SW_CLEAR,Comparator 1 switch control clear"
|
|
bitfld.long 0x4 7. "CMP1_VN1,see corresponding bit in CMP1_SW" "0,1"
|
|
bitfld.long 0x4 6. "CMP1_BN1,see corresponding bit in CMP1_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CMP1_AN1,see corresponding bit in CMP1_SW" "0,1"
|
|
bitfld.long 0x4 4. "CMP1_IN1,see corresponding bit in CMP1_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CMP1_BP1,see corresponding bit in CMP1_SW" "0,1"
|
|
bitfld.long 0x4 1. "CMP1_AP1,see corresponding bit in CMP1_SW" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CMP1_IP1,see corresponding bit in CMP1_SW" "0,1"
|
|
tree.end
|
|
tree "MS_CTL (Master Control Registers)"
|
|
base ad:0x421C4000
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x421C4000 ad:0x421C4010 ad:0x421C4020 ad:0x421C4030 ad:0x421C4040 ad:0x421C4050 ad:0x421C4060 ad:0x421C4070 ad:0x421C4080 ad:0x421C4090 ad:0x421C40A0 ad:0x421C40B0 ad:0x421C40C0 ad:0x421C40D0 ad:0x421C40E0 ad:0x421C40F0)
|
|
tree "MS[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Master 'x' protection context control"
|
|
hexmask.long.word 0x0 16.--31. 1. "PC_MASK,Protection context mask for protection contexts '15' down to '0'. Bit PC_MASK[i] indicates if the MS_PC_STRUCT[x].PC[3:0] protection context field can be set to the value 'i':"
|
|
bitfld.long 0x0 1. "NS,Master security controller configuration." "0: Bus master is secure,1: Bus master is non-secure"
|
|
bitfld.long 0x0 0. "P,Privileged setting ('0': user mode; '1': privileged mode)." "0: user mode,1: privileged mode"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x421C4100 ad:0x421C4110 ad:0x421C4120 ad:0x421C4130 ad:0x421C4140 ad:0x421C4150 ad:0x421C4160 ad:0x421C4170 ad:0x421C4180 ad:0x421C4190 ad:0x421C41A0 ad:0x421C41B0 ad:0x421C41C0 ad:0x421C41D0 ad:0x421C41E0 ad:0x421C41F0)
|
|
tree "MS[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Master 'x' protection context control"
|
|
hexmask.long.word 0x0 16.--31. 1. "PC_MASK,Protection context mask for protection contexts '15' down to '0'. Bit PC_MASK[i] indicates if the MS_PC_STRUCT[x].PC[3:0] protection context field can be set to the value 'i':"
|
|
bitfld.long 0x0 1. "NS,Master security controller configuration." "0: Bus master is secure,1: Bus master is non-secure"
|
|
bitfld.long 0x0 0. "P,Privileged setting ('0': user mode; '1': privileged mode)." "0: user mode,1: privileged mode"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x421C5000 ad:0x421C5010 ad:0x421C5020 ad:0x421C5030 ad:0x421C5040 ad:0x421C5050 ad:0x421C5060 ad:0x421C5070 ad:0x421C5080 ad:0x421C5090 ad:0x421C50A0 ad:0x421C50B0 ad:0x421C50C0 ad:0x421C50D0 ad:0x421C50E0 ad:0x421C50F0)
|
|
tree "MS_PC[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "PC,Master 'x' protection context value"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,N/A"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Active protection context (PC). Modifications to this field are constrained by the associated MS_CTL_STRUCT[x].CTL.PC_MASK value. PC[3:0] can be set to 'i' only if the corresponding mask bit (PC_MASK[i]) is '1'."
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "PC_READ_MIR,Master 'x' protection context value read mirror register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Read-only mirror of PC.PC_SAVED"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Read-only mirror of PC.PC"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x421C5100 ad:0x421C5110 ad:0x421C5120 ad:0x421C5130 ad:0x421C5140 ad:0x421C5150 ad:0x421C5160 ad:0x421C5170 ad:0x421C5180 ad:0x421C5190 ad:0x421C51A0 ad:0x421C51B0 ad:0x421C51C0 ad:0x421C51D0 ad:0x421C51E0 ad:0x421C51F0)
|
|
tree "MS_PC[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "PC,Master 'x' protection context value"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,N/A"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Active protection context (PC). Modifications to this field are constrained by the associated MS_CTL_STRUCT[x].CTL.PC_MASK value. PC[3:0] can be set to 'i' only if the corresponding mask bit (PC_MASK[i]) is '1'."
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "PC_READ_MIR,Master 'x' protection context value read mirror register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Read-only mirror of PC.PC_SAVED"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Read-only mirror of PC.PC"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x421C4000
|
|
newline
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "CODE_MS0_MSC_ACG_CTL,CODE_MS0 master security Controller & ACG configuration"
|
|
bitfld.long 0x0 1. "SEC_RESP,Reseponse type when transfers are not allowed by MSC." "0: Read as zero,1: Error response"
|
|
bitfld.long 0x0 0. "CFG_GATE_RESP,Response type when the ACG is blocking the incoming transfers:" "0: Waited transfer,1: Error response"
|
|
group.long 0x2010++0x7
|
|
line.long 0x0 "SYS_MS0_MSC_ACG_CTL,SYS_MS0 master security Controller & ACG configuration"
|
|
bitfld.long 0x0 1. "SEC_RESP,Reseponse type when transfers are not allowed by MSC." "0: Read as zero,1: Error response"
|
|
bitfld.long 0x0 0. "CFG_GATE_RESP,Response type when the ACG is blocking the incoming transfers:" "0: Waited transfer,1: Error response"
|
|
line.long 0x4 "SYS_MS1_MSC_ACG_CTL,SYS_MS1 master security Controller & ACG configuration"
|
|
bitfld.long 0x4 1. "SEC_RESP,Reseponse type when transfers are not allowed by MSC." "0: Read as zero,1: Error response"
|
|
bitfld.long 0x4 0. "CFG_GATE_RESP,Response type when the ACG is blocking the incoming transfers:" "0: Waited transfer,1: Error response"
|
|
group.long 0x2020++0x3
|
|
line.long 0x0 "EXP_MS_MSC_ACG_CTL,EXP_MS master security Controller & ACG configuration"
|
|
bitfld.long 0x0 1. "SEC_RESP,Reseponse type when transfers are not allowed by MSC." "0: Read as zero,1: Error response"
|
|
bitfld.long 0x0 0. "CFG_GATE_RESP,Response type when the ACG is blocking the incoming transfers:" "0: Waited transfer,1: Error response"
|
|
group.long 0x2030++0x3
|
|
line.long 0x0 "DMAC0_MSC_ACG_CTL,DMAC-0 master security Controller & ACG configuration"
|
|
bitfld.long 0x0 1. "SEC_RESP,Reseponse type when transfers are not allowed by MSC." "0: Read as zero,1: Error response"
|
|
bitfld.long 0x0 0. "CFG_GATE_RESP,Response type when the ACG is blocking the incoming transfers:" "0: Waited transfer,1: Error response"
|
|
group.long 0x2040++0x3
|
|
line.long 0x0 "DMAC1_MSC_ACG_CTL,DMAC-1 master security Controller & ACG configuration"
|
|
bitfld.long 0x0 1. "SEC_RESP,Reseponse type when transfers are not allowed by MSC." "0: Read as zero,1: Error response"
|
|
bitfld.long 0x0 0. "CFG_GATE_RESP,Response type when the ACG is blocking the incoming transfers:" "0: Waited transfer,1: Error response"
|
|
tree.end
|
|
tree "MXCM33"
|
|
base ad:0x42160000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CM33_CTL,Control"
|
|
bitfld.long 0x0 31. "IDC_MASK,N/A" "0,1"
|
|
bitfld.long 0x0 28. "IXC_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "UFC_MASK,N/A" "0,1"
|
|
bitfld.long 0x0 26. "OFC_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DZC_MASK,N/A" "0,1"
|
|
bitfld.long 0x0 24. "IOC_MASK,CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition:" "0: The CPU's exception condition does NOT activate..,1: the CPU's exception condition activates the.."
|
|
newline
|
|
bitfld.long 0x0 12. "LOCKSAU,N/A" "0,1"
|
|
bitfld.long 0x0 11. "LOCKNSMPU,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "LOCKSMPU,N/A" "0,1"
|
|
bitfld.long 0x0 9. "LOCKSVTAIRCR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LOCKNSVTOR,N/A" "0,1"
|
|
bitfld.long 0x0 4. "CPU_WAIT,N/A" "0,1"
|
|
line.long 0x4 "CM33_CMD,Command"
|
|
hexmask.long.word 0x4 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x4 1. "ENABLED,Processor enable:" "0: Disabled,1: Enabled"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "CM33_STATUS,Status"
|
|
bitfld.long 0x0 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
bitfld.long 0x0 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "CM33_INT_STATUS[$1],CM33 interrupt status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,Valid indication for SYSTEM_INT_IDX. When '0' no system interrupt for CPU interrupt 0 is valid/activated." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM33 activated system interrupt index for given CPU interrupt."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "CM33_NMI_CTL[$1],CM33 NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
repeat.end
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "CM33_EVENT_CTL,CM33 event control"
|
|
hexmask.long.byte 0x0 0.--4. 1. "MASK,One mask bit for each CPU (other than itself)."
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CM33_S_VECTOR_TABLE_BASE,CM33 secure vector table base"
|
|
hexmask.long 0x0 7.--31. 1. "ADDR25,Address of CM33 secure vector table to be used at reset."
|
|
line.long 0x4 "CM33_NS_VECTOR_TABLE_BASE,CM33 non-secure vector table base"
|
|
hexmask.long 0x4 7.--31. 1. "ADDR25,Address of CM33 non-secure vector table to be used at reset. Default value:"
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "CM33_PC_CTL,CM33 protection context control"
|
|
hexmask.long.byte 0x0 0.--3. 1. "VALID,Valid fields for the protection context handler CM33_PCi_HANDLER registers:"
|
|
group.long 0x2040++0x3
|
|
line.long 0x0 "CM33_PC0_HANDLER,CM33 protection context 0 handler"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt."
|
|
group.long 0x2100++0x3
|
|
line.long 0x0 "CM33_PC1_HANDLER,CM33 protection context 1 handler"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address of the protection context 1 handler."
|
|
group.long 0x2140++0x3
|
|
line.long 0x0 "CM33_PC2_HANDLER,CM33 protection context 2 handler"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address of the protection context 2 handler."
|
|
group.long 0x2180++0x3
|
|
line.long 0x0 "CM33_PC3_HANDLER,CM33 protection context 3 handler"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address of the protection context 3 handler."
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8000)++0x3
|
|
line.long 0x0 "CM33_SYSTEM_INT_CTL[$1],CM33 system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,Interrupt enable:" "0: Disabled,1: Enabled"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CPU_INT_IDX,CPU interrupt index (legal range [0 15]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g. if CPU_INT_IDX is '6' the system interrupt is mapped to CPU interrupt '6'."
|
|
repeat.end
|
|
tree.end
|
|
tree "MXCORDIC (Coordinate Rotation Digital Computer)"
|
|
base ad:0x42240000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,N/A"
|
|
bitfld.long 0x0 31. "ENABLED,Enables/Disables IP" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ID,Module Identification Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "MOD_NUMBER,Module Number Value - MOD_NUMBER"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MOD_TYPE,Module Type - MOD_TYPE"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MOD_REV,Module Revision Number - MOD_REV"
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "INTR,Interrupt Cause Register"
|
|
bitfld.long 0x0 3. "CDERR,CORDIC Error Event Flag - CDERR" "0,1"
|
|
bitfld.long 0x0 2. "CDEOC,CORDIC End of Calculation Event Flag - CDEOC" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt Set Register"
|
|
bitfld.long 0x4 3. "CDERR,CORDIC Error Event Flag Set - CDERR" "0,1"
|
|
bitfld.long 0x4 2. "CDEOC,CORDIC Event Flag Set - CDEOC" "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x8 3. "CDERR,CORDIC Error Interrupt Mask - CDERR" "0,1"
|
|
bitfld.long 0x8 2. "CDEOC,CORDIC End of Calculation Interrupt Mask- CDEOC" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt Masked Register"
|
|
bitfld.long 0x0 3. "CDERR,CORDIC Error Interrupt Masked - CDERR" "0,1"
|
|
bitfld.long 0x0 2. "CDEOC,CORDIC End of Calculation Interrupt Masked- CDEOC" "0,1"
|
|
group.long 0x40++0x13
|
|
line.long 0x0 "KEEP,CORDIC Keep Register"
|
|
bitfld.long 0x0 7. "KEEPZ,Last Z Result as Initial Data for New Calculation - KEEPZ" "0,1"
|
|
bitfld.long 0x0 6. "KEEPY,Last Y Result as Initial Data for New Calculation - KEEPY" "0,1"
|
|
bitfld.long 0x0 5. "KEEPX,Last X Result as Initial Data for New Calculation - KEEPX" "0,1"
|
|
line.long 0x4 "CON,CORDIC Control Register"
|
|
bitfld.long 0x4 8.--10. "N_ITER,Number of CORDIC iterations divided by 4" "?,1: N/A,2: N/A,3: N/A,4: N/A,5: N/A,6: N/A,7: N/A"
|
|
bitfld.long 0x4 6.--7. "MPS,X and Y Magnitude Prescaler - MPS" "0: N/A,1: N/A,2: N/A,3: N/A"
|
|
bitfld.long 0x4 5. "X_USIGN,Result Data Format for X in Circular Vectoring Mode - X_USIGN" "0: N/A,1: N/A"
|
|
bitfld.long 0x4 4. "ST_MODE,Start Method - ST_MODE" "0: Operation starts with write into CORDZ register,1: Operation starts with write into START_CMD.."
|
|
newline
|
|
bitfld.long 0x4 3. "ROTVEC,Rotation Vectoring Selection - ROTVEC" "0: N/A,1: N/A"
|
|
bitfld.long 0x4 1.--2. "MODE,Operating Mode - MODE" "0: N/A,1: N/A,2: N/A,3: N/A"
|
|
line.long 0x8 "CORDX,CORDIC X Data Register"
|
|
hexmask.long.tbyte 0x8 8.--31. 1. "DATA,Initial X Parameter Data - DATA"
|
|
line.long 0xC "CORDY,CORDIC Y Data Register"
|
|
hexmask.long.tbyte 0xC 8.--31. 1. "DATA,Initial Y Parameter Data - DATA"
|
|
line.long 0x10 "CORDZ,CORDIC Z Data Register"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "DATA,Initial Z Parameter Data - DATA"
|
|
rgroup.long 0x54++0xF
|
|
line.long 0x0 "CORRX,CORDIC X Result Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RESULT,X Calculation Result - RESULT"
|
|
line.long 0x4 "CORRY,CORDIC Y Result Register"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RESULT,Y Calculation Result - RESULT"
|
|
line.long 0x8 "CORRZ,CORDIC Z Result Register"
|
|
hexmask.long.tbyte 0x8 8.--31. 1. "RESULT,Z Calculation Result - RESULT"
|
|
line.long 0xC "STAT,CORDIC Status Register"
|
|
bitfld.long 0xC 0. "BSY,Busy Indication - BSY" "0,1"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "START_CMD,CORDIC Start Command Register"
|
|
bitfld.long 0x0 0. "ST,Start Calculation Set - ST" "0,1"
|
|
tree.end
|
|
tree "PERI (Peripheral Interconnect)"
|
|
base ad:0x42000000
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TIMEOUT_CTL,Timeout control"
|
|
bitfld.long 0x0 31. "HWRST_DISABLE,This field provides control for HW to reset the slave that is causing the timeout to occur." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,This field specifies a number of peripheral group root undivided (clk_group_root[i]) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection) the bus transfer is terminated with an AHB5 bus.."
|
|
group.long 0x2000++0x7
|
|
line.long 0x0 "TR_CMD,Trigger command"
|
|
bitfld.long 0x0 31. "ACTIVATE,SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles." "0,1"
|
|
bitfld.long 0x0 30. "OUT_SEL,Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger will result in activation of all output triggers that have the specific input trigger selected.." "0: TR_SEL selection and trigger activation is for..,1: TR_SEL selection and trigger activation is for.."
|
|
bitfld.long 0x0 29. "TR_EDGE,Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "GROUP_SEL,Specifies the trigger group:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present the trigger activation has no effect."
|
|
line.long 0x4 "INFRA_CLK_FORCE,Infrastructure clock force enable"
|
|
bitfld.long 0x4 0. "ENABLED,Infrastructure clock force enable." "0: Disabled,1: Enabled"
|
|
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x42004000 ad:0x42004040 ad:0x42004080 ad:0x420040C0 ad:0x42004100 ad:0x42004140)
|
|
tree "GR[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[1/2/3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]."
|
|
group.long ($2+0x10)++0x7
|
|
line.long 0x0 "SL_CTL,Slave control"
|
|
hexmask.long 0x0 0.--31. 1. "ENABLED,Slave Enable. Each bit indicates whether the respective slave is enabled. If the slave is disabled its clock is gated off (constant '0')."
|
|
line.long 0x4 "SL_CTL2,Slave control2"
|
|
hexmask.long 0x4 0.--31. 1. "RST,Slave reset. Each bit indicates whether the respective slave is enabled. If the slave is under reset its clock is gated off (constant '0') and its resets are activated."
|
|
rgroup.long ($2+0x18)++0x3
|
|
line.long 0x0 "SL_CTL3,Slave control3"
|
|
hexmask.long 0x0 0.--31. 1. "SS_POWERSTATE,Slave status to represent subsystem (SS) IP current power status. Each bit represents the respective IP power state (Note that separate mxsperi peripheral group should be defined for type4 peripheral should not be mixed with type1/2/3 and.."
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "SL_WOUND,Slave wounding"
|
|
hexmask.long 0x0 0.--31. 1. "DISABLED,Slave disabled. Each bit indicates whether the respective slave is disabled. Setting this bit to 1 has the same effect as setting SL_CTL.ENABLED_0 to 0. However once set to 1 this bit cannot be changed back to 0 anymore."
|
|
tree.end
|
|
repeat.end
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0x42008000 ad:0x42008400 ad:0x42008800 ad:0x42008C00 ad:0x42009000 ad:0x42009400 ad:0x42009800 ad:0x42009C00 ad:0x4200A000 ad:0x4200A400 ad:0x4200A800 ad:0x4200AC00 ad:0x4200B000 ad:0x4200B400 ad:0x4200B800)
|
|
tree "TR_GR[$1]"
|
|
base $2
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation." "0,1"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0.."
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x4200C000 ad:0x4200C400 ad:0x4200C800)
|
|
tree "TR_1TO1_GR[$1]"
|
|
base $2
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation." "0,1"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0: level sensitive,1: edge sensitive trigger"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
bitfld.long 0x0 0. "TR_SEL,Specifies input trigger:" "0: constant signal level '0',1: input trigger"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PERI_PCLK (Peripheral PCLK groups)"
|
|
base ad:0x42040000
|
|
repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x42040000 ad:0x42042000 ad:0x42044000 ad:0x42046000 ad:0x42048000 ad:0x4204A000 ad:0x4204C000)
|
|
tree "GR[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "DIV_CMD,Divider command"
|
|
bitfld.long 0x0 31. "ENABLE,Clock divider enable command (mutually exclusive with DISABLE). Typically SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled its integer and.." "0: Disable the divider using the DIV_CMD,1: Configure the divider's DIV_XXX_CTL register"
|
|
bitfld.long 0x0 30. "DISABLE,Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'." "0,1"
|
|
bitfld.long 0x0 24.--25. "PA_TYPE_SEL,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:" "0: 8,1: 16,2: 16,3: 24"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PA_DIV_SEL,(PA_TYPE_SEL PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other even when they are.."
|
|
bitfld.long 0x0 8.--9. "TYPE_SEL,Specifies the divider type of the divider on which the command is performed:" "0: 8,1: 16,2: 16,3: 24"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_SEL,(TYPE_SEL DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed."
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC00)++0x3
|
|
line.long 0x0 "CLOCK_CTL[$1],Clock control"
|
|
bitfld.long 0x0 8.--9. "TYPE_SEL,Specifies divider type:" "0: 8,1: 16,2: 16,3: 24"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL."
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "DIV_8_CTL[$1],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1400)++0x3
|
|
line.long 0x0 "DIV_16_CTL[$1],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1800)++0x3
|
|
line.long 0x0 "DIV_16_5_CTL[$1],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: combined with fractional division this divider type allows for a division in the range [1 65 536 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root[i]' cycle longer than other clock periods."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 255. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1C00)++0x3
|
|
line.long 0x0 "DIV_24_5_CTL[$1],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1 16 777 216]. Note: combined with fractional division this divider type allows for a division in the range [1 16 777 216 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root[i]' cycle longer than other clock periods."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PPC (Peripheral Protection Controller)"
|
|
base ad:0x42020000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,PPC Control Registers"
|
|
bitfld.long 0x0 0. "RESP_CFG,Response Configuration. This field configures the security violation response." "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "LOCK_MASK,Locked Mask"
|
|
hexmask.long 0x0 0.--31. 1. "LOCK_MASK,A mask that indicates which protection contexts are 'locked'. Once locked a protection context cannot be unlocked until the next reset or power cycle. Bit i specifies the locked status for protection context i."
|
|
repeat 1024. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "PC_MASK[$1],Protection Context Mask"
|
|
hexmask.long 0x0 0.--31. 1. "PC_MASK,A mask that indicates which protection contexts have access to a peripheral region. Bit i specifies the access for protection context i."
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2000)++0x3
|
|
line.long 0x0 "NS_ATT[$1],Non-secure attribute"
|
|
hexmask.long 0x0 0.--31. 1. "NS,Non-Secure. Each bit indicates whether access to a peripheral region must be secure or non-secure:"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2400)++0x3
|
|
line.long 0x0 "S_P_ATT[$1],Secure Privilege Attribute"
|
|
hexmask.long 0x0 0.--31. 1. "S_P,Secure Privilege. Each bit indicates whether access to a secure peripheral region requires privilege:"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x4000)++0x3
|
|
line.long 0x0 "NS_P_ATT[$1],Non-secure Privilege Attribute"
|
|
hexmask.long 0x0 0.--31. 1. "NS_P,Non-Secure Privilege. Each bit indicates whether access to a non-secure peripheral region requires privilege:"
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x42025000 ad:0x42025004 ad:0x42025008 ad:0x4202500C ad:0x42025010 ad:0x42025014 ad:0x42025018 ad:0x4202501C ad:0x42025020 ad:0x42025024 ad:0x42025028 ad:0x4202502C ad:0x42025030 ad:0x42025034 ad:0x42025038 ad:0x4202503C)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x42025040 ad:0x42025044 ad:0x42025048 ad:0x4202504C ad:0x42025050 ad:0x42025054 ad:0x42025058 ad:0x4202505C ad:0x42025060 ad:0x42025064 ad:0x42025068 ad:0x4202506C ad:0x42025070 ad:0x42025074 ad:0x42025078 ad:0x4202507C)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list ad:0x42025080 ad:0x42025084 ad:0x42025088 ad:0x4202508C ad:0x42025090 ad:0x42025094 ad:0x42025098 ad:0x4202509C ad:0x420250A0 ad:0x420250A4 ad:0x420250A8 ad:0x420250AC ad:0x420250B0 ad:0x420250B4 ad:0x420250B8 ad:0x420250BC)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list ad:0x420250C0 ad:0x420250C4 ad:0x420250C8 ad:0x420250CC ad:0x420250D0 ad:0x420250D4 ad:0x420250D8 ad:0x420250DC ad:0x420250E0 ad:0x420250E4 ad:0x420250E8 ad:0x420250EC ad:0x420250F0 ad:0x420250F4 ad:0x420250F8 ad:0x420250FC)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list ad:0x42025100 ad:0x42025104 ad:0x42025108 ad:0x4202510C ad:0x42025110 ad:0x42025114 ad:0x42025118 ad:0x4202511C ad:0x42025120 ad:0x42025124 ad:0x42025128 ad:0x4202512C ad:0x42025130 ad:0x42025134 ad:0x42025138 ad:0x4202513C)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F)(list ad:0x42025140 ad:0x42025144 ad:0x42025148 ad:0x4202514C ad:0x42025150 ad:0x42025154 ad:0x42025158 ad:0x4202515C ad:0x42025160 ad:0x42025164 ad:0x42025168 ad:0x4202516C ad:0x42025170 ad:0x42025174 ad:0x42025178 ad:0x4202517C)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F)(list ad:0x42025180 ad:0x42025184 ad:0x42025188 ad:0x4202518C ad:0x42025190 ad:0x42025194 ad:0x42025198 ad:0x4202519C ad:0x420251A0 ad:0x420251A4 ad:0x420251A8 ad:0x420251AC ad:0x420251B0 ad:0x420251B4 ad:0x420251B8 ad:0x420251BC)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F)(list ad:0x420251C0 ad:0x420251C4 ad:0x420251C8 ad:0x420251CC ad:0x420251D0 ad:0x420251D4 ad:0x420251D8 ad:0x420251DC ad:0x420251E0 ad:0x420251E4 ad:0x420251E8 ad:0x420251EC ad:0x420251F0 ad:0x420251F4 ad:0x420251F8 ad:0x420251FC)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F)(list ad:0x42025200 ad:0x42025204 ad:0x42025208 ad:0x4202520C ad:0x42025210 ad:0x42025214 ad:0x42025218 ad:0x4202521C ad:0x42025220 ad:0x42025224 ad:0x42025228 ad:0x4202522C ad:0x42025230 ad:0x42025234 ad:0x42025238 ad:0x4202523C)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F)(list ad:0x42025240 ad:0x42025244 ad:0x42025248 ad:0x4202524C ad:0x42025250 ad:0x42025254 ad:0x42025258 ad:0x4202525C ad:0x42025260 ad:0x42025264 ad:0x42025268 ad:0x4202526C ad:0x42025270 ad:0x42025274 ad:0x42025278 ad:0x4202527C)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF)(list ad:0x42025280 ad:0x42025284 ad:0x42025288 ad:0x4202528C ad:0x42025290 ad:0x42025294 ad:0x42025298 ad:0x4202529C ad:0x420252A0 ad:0x420252A4 ad:0x420252A8 ad:0x420252AC ad:0x420252B0 ad:0x420252B4 ad:0x420252B8 ad:0x420252BC)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF)(list ad:0x420252C0 ad:0x420252C4 ad:0x420252C8 ad:0x420252CC ad:0x420252D0 ad:0x420252D4 ad:0x420252D8 ad:0x420252DC ad:0x420252E0 ad:0x420252E4 ad:0x420252E8 ad:0x420252EC ad:0x420252F0 ad:0x420252F4 ad:0x420252F8 ad:0x420252FC)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF)(list ad:0x42025300 ad:0x42025304 ad:0x42025308 ad:0x4202530C ad:0x42025310 ad:0x42025314 ad:0x42025318 ad:0x4202531C ad:0x42025320 ad:0x42025324 ad:0x42025328 ad:0x4202532C ad:0x42025330 ad:0x42025334 ad:0x42025338 ad:0x4202533C)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 14. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD)(list ad:0x42025340 ad:0x42025344 ad:0x42025348 ad:0x4202534C ad:0x42025350 ad:0x42025354 ad:0x42025358 ad:0x4202535C ad:0x42025360 ad:0x42025364 ad:0x42025368 ad:0x4202536C ad:0x42025370 ad:0x42025374)
|
|
tree "R_ADDR[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ADDR,Region Address"
|
|
hexmask.long 0x0 2.--31. 1. "R_ADDR,This field specifies the base address of the peripheral region. The region size is defined by R_ATTR.R_SIZE. A region of n Bytes mus be n Byte aligned. Therefore some of the lesser significant address bits of ADDR must be '0's. E.g. a 64KB.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x42026000 ad:0x42026004 ad:0x42026008 ad:0x4202600C ad:0x42026010 ad:0x42026014 ad:0x42026018 ad:0x4202601C ad:0x42026020 ad:0x42026024 ad:0x42026028 ad:0x4202602C ad:0x42026030 ad:0x42026034 ad:0x42026038 ad:0x4202603C)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x42026040 ad:0x42026044 ad:0x42026048 ad:0x4202604C ad:0x42026050 ad:0x42026054 ad:0x42026058 ad:0x4202605C ad:0x42026060 ad:0x42026064 ad:0x42026068 ad:0x4202606C ad:0x42026070 ad:0x42026074 ad:0x42026078 ad:0x4202607C)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list ad:0x42026080 ad:0x42026084 ad:0x42026088 ad:0x4202608C ad:0x42026090 ad:0x42026094 ad:0x42026098 ad:0x4202609C ad:0x420260A0 ad:0x420260A4 ad:0x420260A8 ad:0x420260AC ad:0x420260B0 ad:0x420260B4 ad:0x420260B8 ad:0x420260BC)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list ad:0x420260C0 ad:0x420260C4 ad:0x420260C8 ad:0x420260CC ad:0x420260D0 ad:0x420260D4 ad:0x420260D8 ad:0x420260DC ad:0x420260E0 ad:0x420260E4 ad:0x420260E8 ad:0x420260EC ad:0x420260F0 ad:0x420260F4 ad:0x420260F8 ad:0x420260FC)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list ad:0x42026100 ad:0x42026104 ad:0x42026108 ad:0x4202610C ad:0x42026110 ad:0x42026114 ad:0x42026118 ad:0x4202611C ad:0x42026120 ad:0x42026124 ad:0x42026128 ad:0x4202612C ad:0x42026130 ad:0x42026134 ad:0x42026138 ad:0x4202613C)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F)(list ad:0x42026140 ad:0x42026144 ad:0x42026148 ad:0x4202614C ad:0x42026150 ad:0x42026154 ad:0x42026158 ad:0x4202615C ad:0x42026160 ad:0x42026164 ad:0x42026168 ad:0x4202616C ad:0x42026170 ad:0x42026174 ad:0x42026178 ad:0x4202617C)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F)(list ad:0x42026180 ad:0x42026184 ad:0x42026188 ad:0x4202618C ad:0x42026190 ad:0x42026194 ad:0x42026198 ad:0x4202619C ad:0x420261A0 ad:0x420261A4 ad:0x420261A8 ad:0x420261AC ad:0x420261B0 ad:0x420261B4 ad:0x420261B8 ad:0x420261BC)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F)(list ad:0x420261C0 ad:0x420261C4 ad:0x420261C8 ad:0x420261CC ad:0x420261D0 ad:0x420261D4 ad:0x420261D8 ad:0x420261DC ad:0x420261E0 ad:0x420261E4 ad:0x420261E8 ad:0x420261EC ad:0x420261F0 ad:0x420261F4 ad:0x420261F8 ad:0x420261FC)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F)(list ad:0x42026200 ad:0x42026204 ad:0x42026208 ad:0x4202620C ad:0x42026210 ad:0x42026214 ad:0x42026218 ad:0x4202621C ad:0x42026220 ad:0x42026224 ad:0x42026228 ad:0x4202622C ad:0x42026230 ad:0x42026234 ad:0x42026238 ad:0x4202623C)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F)(list ad:0x42026240 ad:0x42026244 ad:0x42026248 ad:0x4202624C ad:0x42026250 ad:0x42026254 ad:0x42026258 ad:0x4202625C ad:0x42026260 ad:0x42026264 ad:0x42026268 ad:0x4202626C ad:0x42026270 ad:0x42026274 ad:0x42026278 ad:0x4202627C)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF)(list ad:0x42026280 ad:0x42026284 ad:0x42026288 ad:0x4202628C ad:0x42026290 ad:0x42026294 ad:0x42026298 ad:0x4202629C ad:0x420262A0 ad:0x420262A4 ad:0x420262A8 ad:0x420262AC ad:0x420262B0 ad:0x420262B4 ad:0x420262B8 ad:0x420262BC)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF)(list ad:0x420262C0 ad:0x420262C4 ad:0x420262C8 ad:0x420262CC ad:0x420262D0 ad:0x420262D4 ad:0x420262D8 ad:0x420262DC ad:0x420262E0 ad:0x420262E4 ad:0x420262E8 ad:0x420262EC ad:0x420262F0 ad:0x420262F4 ad:0x420262F8 ad:0x420262FC)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF)(list ad:0x42026300 ad:0x42026304 ad:0x42026308 ad:0x4202630C ad:0x42026310 ad:0x42026314 ad:0x42026318 ad:0x4202631C ad:0x42026320 ad:0x42026324 ad:0x42026328 ad:0x4202632C ad:0x42026330 ad:0x42026334 ad:0x42026338 ad:0x4202633C)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
repeat 14. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD)(list ad:0x42026340 ad:0x42026344 ad:0x42026348 ad:0x4202634C ad:0x42026350 ad:0x42026354 ad:0x42026358 ad:0x4202635C ad:0x42026360 ad:0x42026364 ad:0x42026368 ad:0x4202636C ad:0x42026370 ad:0x42026374)
|
|
tree "R_ATT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "R_ATT,Region Attribute"
|
|
hexmask.long.byte 0x0 24.--28. 1. "R_SIZE,This field specifies the size of the peripheral region:"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PROMC (Patchable ROM Controller)"
|
|
base ad:0x42140000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 0.--1. "ROM_WS,Wait states." "0: N/A,1: N/A,2: N/A,3: N/A"
|
|
tree "MPC (MPC Memory Protection Controller registers)"
|
|
base ad:0x42141000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CFG,Config register with error response. RegionID PPC_MPC_MAIN is the security owner PC. The error response configuration is located in CFG.RESPONSE. only one such configuration exists applying to all protection contexts in the system."
|
|
bitfld.long 0x0 4. "RESPONSE,Response Configuration for Security and PC violations" "0: Read-Zero Write Ignore,1: Bus Error"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CTRL,Control register with lock bit and auto-increment only (Separate CTRL for each PC depends on access_pc)"
|
|
bitfld.long 0x0 31. "LOCK,Security lockdown for this protection context. Software can set this bit but not clear it once set. When set write operations to BLK_LUT are not possible from this protection context. Setting LOCK also blocks writes to CTRL itself (for that PC.." "0,1"
|
|
bitfld.long 0x0 8. "AUTO_INC,Auto-increment BLK_IDX by 1 for this protection context as a side effect of each read/write access to BLK_LUT" "0,1"
|
|
rgroup.long 0x104++0x7
|
|
line.long 0x0 "BLK_MAX,Max value of block-based index register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Maximum value of block-based index register. The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; See product datasheet for details on protection of.."
|
|
line.long 0x4 "BLK_CFG,Block size & initialization in progress"
|
|
bitfld.long 0x4 31. "INIT_IN_PROGRESS,During initialization INIT_IN_PROGRESS is '1' and MMIO register accesses to BLK_LUT is blocked (BLK_IDX increment is also ignored). The block attributes are retained in DeepSleep (and obviously Active) power mode. Initialization is only.." "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "BLOCK_SIZE,Block size of individually protected blocks (0: 32B 1: 64B ... up to 15: 1MB)"
|
|
group.long 0x10C++0x7
|
|
line.long 0x0 "BLK_IDX,Index of 32-block group accessed through BLK_LUT (Separate IDX for each PC depending on access_pc)"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Index value for accessing block-based lookup table using BLK_LUT. Programming out of LUT range is an user error and it loops back to '0' once overflow occurs."
|
|
line.long 0x4 "BLK_LUT,NS status for 32 blocks at BLK_IDX with PC=<access_pc>"
|
|
bitfld.long 0x4 31. "ATTR_NS31,NS bit for block 31 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 30. "ATTR_NS30,NS bit for block 30 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 29. "ATTR_NS29,NS bit for block 29 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 28. "ATTR_NS28,NS bit for block 28 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 27. "ATTR_NS27,NS bit for block 27 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "ATTR_NS26,NS bit for block 26 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 25. "ATTR_NS25,NS bit for block 25 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 24. "ATTR_NS24,NS bit for block 24 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 23. "ATTR_NS23,NS bit for block 23 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 22. "ATTR_NS22,NS bit for block 22 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "ATTR_NS21,NS bit for block 21 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 20. "ATTR_NS20,NS bit for block 20 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 19. "ATTR_NS19,NS bit for block 19 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 18. "ATTR_NS18,NS bit for block 18 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 17. "ATTR_NS17,NS bit for block 17 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "ATTR_NS16,NS bit for block 16 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 15. "ATTR_NS15,NS bit for block 15 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 14. "ATTR_NS14,NS bit for block 14 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 13. "ATTR_NS13,NS bit for block 13 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 12. "ATTR_NS12,NS bit for block 12 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ATTR_NS11,NS bit for block 11 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 10. "ATTR_NS10,NS bit for block 10 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 9. "ATTR_NS9,NS bit for block 9 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 8. "ATTR_NS8,NS bit for block 8 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 7. "ATTR_NS7,NS bit for block 7 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ATTR_NS6,NS bit for block 6 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 5. "ATTR_NS5,NS bit for block 5 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 4. "ATTR_NS4,NS bit for block 4 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 3. "ATTR_NS3,NS bit for block 3 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 2. "ATTR_NS2,NS bit for block 2 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ATTR_NS1,NS bit for block 1 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 0. "ATTR_NS0,NS bit for block 0 based on BLK_IDX" "0,1"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "ROT_CTRL,Control register with lock bit and auto-increment only"
|
|
bitfld.long 0x0 31. "LOCK,Security lockdown for the root-of-trust configuration registers. Software can set this bit but not clear it once set. When set write operations to ROT_BLK_LUT are not possible. Write is ignored." "0,1"
|
|
bitfld.long 0x0 8. "AUTO_INC,Auto-increment BLK_IDX by 1 for each read/write of ROT_BLK_LUT" "0,1"
|
|
rgroup.long 0x208++0x7
|
|
line.long 0x0 "ROT_BLK_MAX,Max value of block-based index register for ROT"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Maximum value of block-based index register. The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of.."
|
|
line.long 0x4 "ROT_BLK_CFG,Same as BLK_CFG"
|
|
bitfld.long 0x4 31. "INIT_IN_PROGRESS,During initialization INIT_IN_PROGRESS is '1' and MMIO register accesses to ROT_BLK_LUT is RAZWI. The block attributes are retained in DeepSleep (and obviously Active) power mode. Initialization is only required from a power mode in.." "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "BLOCK_SIZE,Block size of individually protected blocks (0: 32B 1: 64B ...up to 15:1MB)"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "ROT_BLK_IDX,Index of 8-block group accessed through ROT_BLK_LUT_*"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Index value for accessing block-based lookup table using ROT_BLK_LUT. Programming out of LUT range is an user error and it loops back to '0' once overflow occurs."
|
|
line.long 0x4 "ROT_BLK_PC,Protection context of 8-block group accesses through ROT_BLK_LUT"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PC,Specify PC values for ROT_BLK_IDX and ROT_BLK_LUT"
|
|
line.long 0x8 "ROT_BLK_LUT,(R.W.NS) bits for 8 blocks at ROT_BLK_IDX for PC=ROT_BKL_PC"
|
|
bitfld.long 0x8 28.--30. "ATTR7,W/R/NS bits for block 7 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24.--26. "ATTR6,W/R/NS bits for block 6 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 20.--22. "ATTR5,W/R/NS bits for block 5 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--18. "ATTR4,W/R/NS bits for block 4 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 12.--14. "ATTR3,W/R/NS bits for block 3 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "ATTR2,W/R/NS bits for block 2 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 4.--6. "ATTR1,W/R/NS bits for block 1 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "ATTR0,W/R/NS bits for block 0 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree.end
|
|
tree "PWRMODE (Device Power Modes)"
|
|
base ad:0x42210000
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x42210000 ad:0x42210010 ad:0x42210020 ad:0x42210030 ad:0x42210040 ad:0x42210050 ad:0x42210060 ad:0x42210070 ad:0x42210080 ad:0x42210090 ad:0x422100A0 ad:0x422100B0 ad:0x422100C0 ad:0x422100D0 ad:0x422100E0 ad:0x422100F0)
|
|
tree "PD[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "PD_SENSE,Dependency Sense Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PD_ON,Each bit <i> indicates whether PD<j> is directly kept on when PD<i> is on. Indirect dependency is still possible if multiple direct dependencies work together to create a transitive relationship. For example if PD1 depends upon PD2; and PD2.."
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "PD_SPT,Dependency Support Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PD_CONFIG_ON,Each bit <i> indicates whether PD<j> can be configured on when PD<i> is on."
|
|
hexmask.long.word 0x0 0.--15. 1. "PD_FORCE_ON,Each bit <i> indicates whether PD<j> is always kept on when PD<i> is on for sense bits that are not configurable. For configurable bits this indicates the reset value of the configurable bit."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x42210000
|
|
tree "PPU_MAIN (Power Policy Unit for Active Domain)"
|
|
base ad:0x42211000
|
|
tree "PPU (Power Policy Unit Registers for the main power domain (VCCACT_PD))"
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "PWPR,Power Policy Register"
|
|
bitfld.long 0x0 24. "OP_DYN_EN,N/A" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "OP_POLICY,N/A"
|
|
bitfld.long 0x0 12. "LOCK_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PWR_DYN_EN,Power mode dynamic transition enable. For main PPU keep this bit 1." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PWR_POLICY,Power mode policy. When static power mode transitions are enabled PWR_DYN_EN is set to 0 this is the target power mode for the PPU. When dynamic power mode transitions are enabled PWR_DYN_EN is set to 1 this is the minimum power mode for.."
|
|
line.long 0x4 "PMER,Power Mode Emulation Register"
|
|
bitfld.long 0x4 0. "EMU_EN,N/A" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "PWSR,Power Status Register"
|
|
bitfld.long 0x0 24. "OP_DYN_STATUS,N/A" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "OP_STATUS,N/A"
|
|
bitfld.long 0x0 12. "LOCK_STATUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PWR_DYN_STATUS,Power mode dynamic transition status. When set to 1 power mode dynamic transitions are enabled. There might be a delay in dynamic transitions becoming active or inactive if the PPU is transitioning when PWR_DYN_EN is programmed." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PWR_STATUS,Power mode status. These bits reflect the current power mode of the PPU. See PPU_PWPR.PWR_POLICY for power mode enumeration."
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "DISR,Device Interface Input Current Status Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "OP_DEVACTIVE_STATUS,N/A"
|
|
hexmask.long.word 0x0 0.--10. 1. "PWR_DEVACTIVE_STATUS,Status of the power mode DEVACTIVE inputs."
|
|
line.long 0x4 "MISR,Miscellaneous Input Current Status Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DEVDENY_STATUS,Status of the device interface DEVDENY inputs."
|
|
hexmask.long.byte 0x4 8.--15. 1. "DEVACCEPT_STATUS,Status of the device interface DEVACCEPT inputs."
|
|
bitfld.long 0x4 0. "PCSMPACCEPT_STATUS,The status of the PCSMPACCEPT input." "0,1"
|
|
line.long 0x8 "STSR,Stored Status Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "STORED_DEVDENY,Status of the DEVDENY signals from the last device interface Q-Channel transition. For Q-Channel: There is one bit for each device interface DEVQDENY. For example bit 0 is for Q-Channel 0 DEVQDENY and bit 1 for Q-Channel 1 DEVQDENY."
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "UNLK,Unlock register"
|
|
bitfld.long 0x0 0. "UNLOCK,N/A" "0,1"
|
|
line.long 0x4 "PWCR,Power Configuration Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "OP_DEVACTIVEEN,N/A"
|
|
hexmask.long.word 0x4 8.--18. 1. "PWR_DEVACTIVEEN,These bits enable the power mode DEVACTIVE inputs. When a bit is to 1 the related DEVACTIVE input is enabled when set to 0 it is disabled. All available bits are reset to 1."
|
|
hexmask.long.byte 0x4 0.--7. 1. "DEVREQEN,When set to 1 enables the device interface handshake for transitions. All available bits are reset to 1."
|
|
line.long 0x8 "PTCR,Power Mode Transition Configuration Register"
|
|
bitfld.long 0x8 1. "DBG_RECOV_PORST_EN,N/A" "0,1"
|
|
bitfld.long 0x8 0. "WARM_RST_DEVREQEN,Transition behavior between ON and WARM_RST. This bit should not be modified when the PPU is in WARM_RST or if the PPU is performing a transition otherwise PPU behavior is UNPREDICTABLE." "0: The PPU does not perform a device interface..,1: The PPU performs a device interface handshake.."
|
|
group.long 0x30++0x17
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 5. "LOCKED_IRQ_MASK,N/A" "0,1"
|
|
bitfld.long 0x0 4. "EMU_DENY_IRQ_MASK,N/A" "0,1"
|
|
bitfld.long 0x0 3. "EMU_ACCEPT_IRQ_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STA_DENY_IRQ_MASK,Static transition denial event mask." "0,1"
|
|
bitfld.long 0x0 1. "STA_ACCEPT_IRQ_MASK,Static transition acceptance event mask. For main PPU keep this bit 1 to mask the event otherwise the interrupt may trigger a wakeup." "0,1"
|
|
bitfld.long 0x0 0. "STA_POLICY_TRN_IRQ_MASK,Static full policy transition completion event mask. For main PPU this bit has no function because no static transitions are supported (see PWPR.PWR_DYN_EN)." "0,1"
|
|
line.long 0x4 "AIMR,Additional Interrupt Mask Register"
|
|
bitfld.long 0x4 4. "STA_POLICY_OP_IRQ_MASK,N/A" "0,1"
|
|
bitfld.long 0x4 3. "STA_POLICY_PWR_IRQ_MASK,N/A" "0,1"
|
|
bitfld.long 0x4 2. "DYN_DENY_IRQ_MASK,Dynamic transition denial event mask." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DYN_ACCEPT_IRQ_MASK,Dynamic transition acceptance event mask. For main PPU keep this bit 1 to mask the event otherwise the interrupt that occurs when entering a low power mode may trigger a wakeup." "0,1"
|
|
bitfld.long 0x4 0. "UNSPT_POLICY_IRQ_MASK,Unsupported Policy event mask." "0,1"
|
|
line.long 0x8 "ISR,Interrupt Status Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "OP_ACTIVE_EDGE_IRQ,N/A"
|
|
hexmask.long.word 0x8 8.--18. 1. "PWR_ACTIVE_EDGE_IRQ,N/A"
|
|
rbitfld.long 0x8 7. "OTHER_IRQ,Indicates there is an interrupt event pending in the Additional Interrupt Status Register (PPU_AISR)." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "LOCKED_IRQ,N/A" "0,1"
|
|
bitfld.long 0x8 4. "EMU_DENY_IRQ,N/A" "0,1"
|
|
bitfld.long 0x8 3. "EMU_ACCEPT_IRQ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "STA_DENY_IRQ,Static transition denial event status." "0,1"
|
|
bitfld.long 0x8 1. "STA_ACCEPT_IRQ,Static transition acceptance event status." "0,1"
|
|
bitfld.long 0x8 0. "STA_POLICY_TRN_IRQ,Static full policy transition completion event status." "0,1"
|
|
line.long 0xC "AISR,Additional Interrupt Status Register"
|
|
bitfld.long 0xC 4. "STA_POLICY_OP_IRQ,N/A" "0,1"
|
|
bitfld.long 0xC 3. "STA_POLICY_PWR_IRQ,N/A" "0,1"
|
|
bitfld.long 0xC 2. "DYN_DENY_IRQ,Dynamic transition denial event status." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "DYN_ACCEPT_IRQ,Dynamic transition acceptance event status." "0,1"
|
|
bitfld.long 0xC 0. "UNSPT_POLICY_IRQ,Unsupported Policy event status." "0,1"
|
|
line.long 0x10 "IESR,Input Edge Sensitivity Register"
|
|
bitfld.long 0x10 20.--21. "DEVACTIVE10_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "DEVACTIVE09_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "DEVACTIVE08_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "DEVACTIVE07_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "DEVACTIVE06_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "DEVACTIVE05_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 8.--9. "DEVACTIVE04_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "DEVACTIVE03_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "DEVACTIVE02_EDGE,DEVACTIVE 2 edge sensitivity." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 2.--3. "DEVACTIVE01_EDGE,DEVACTIVE 1 edge sensitivity." "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "DEVACTIVE00_EDGE,DEVACTIVE 0 edge sensitivity." "0,1,2,3"
|
|
line.long 0x14 "OPSR,Operating Mode Active Edge Sensitivity Register"
|
|
bitfld.long 0x14 14.--15. "DEVACTIVE23_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. "DEVACTIVE22_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. "DEVACTIVE21_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 8.--9. "DEVACTIVE20_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "DEVACTIVE19_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. "DEVACTIVE18_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 2.--3. "DEVACTIVE17_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. "DEVACTIVE16_EDGE,N/A" "0,1,2,3"
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "FUNRR,Functional Retention RAM Configuration Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FUNC_RET_RAM_CFG,N/A"
|
|
line.long 0x4 "FULRR,Full Retention RAM Configuration Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "FULL_RET_RAM_CFG,N/A"
|
|
line.long 0x8 "MEMRR,Memory Retention RAM Configuration Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "MEM_RET_RAM_CFG,N/A"
|
|
group.long 0x160++0x7
|
|
line.long 0x0 "EDTR0,Power Mode Entry Delay Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "FULL_RET_DEL,N/A"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LOGIC_RET_DEL,N/A"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MEM_RET_DEL,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "OFF_DEL,N/A"
|
|
line.long 0x4 "EDTR1,Power Mode Entry Delay Register 1"
|
|
hexmask.long.byte 0x4 8.--15. 1. "FUNC_RET_DEL,N/A"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MEM_OFF_DEL,N/A"
|
|
rgroup.long 0x170++0x7
|
|
line.long 0x0 "DCDR0,Device Control Delay Configuration Register 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RST_HWSTAT_DLY,N/A"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ISO_CLKEN_DLY,N/A"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CLKEN_RST_DLY,N/A"
|
|
line.long 0x4 "DCDR1,Device Control Delay Configuration Register 1"
|
|
hexmask.long.byte 0x4 8.--15. 1. "CLKEN_ISO_DLY,N/A"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ISO_RST_DLY,N/A"
|
|
rgroup.long 0xFB0++0x7
|
|
line.long 0x0 "IDR0,PPU Identification Register 0"
|
|
bitfld.long 0x0 29. "DYN_WRM_RST_SPT,Dynamic WARM_RST support." "0,1"
|
|
bitfld.long 0x0 28. "DYN_ON_SPT,Dynamic ON support." "0,1"
|
|
bitfld.long 0x0 27. "DYN_FUNC_RET_SPT,Dynamic FUNC_RET support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "DYN_FULL_RET_SPT,Dynamic FULL_RET support." "0,1"
|
|
bitfld.long 0x0 25. "DYN_MEM_OFF_SPT,Dynamic MEM_OFF support." "0,1"
|
|
bitfld.long 0x0 24. "DYN_LGC_RET_SPT,Dynamic LOGIC_RET support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DYN_MEM_RET_EMU_SPT,Dynamic MEM_RET_EMU support" "0,1"
|
|
bitfld.long 0x0 22. "DYN_MEM_RET_SPT,Dynamic MEM_RET support." "0,1"
|
|
bitfld.long 0x0 21. "DYN_OFF_EMU_SPT,Dynamic OFF_EMU support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DYN_OFF_SPT,Dynamic OFF support." "0,1"
|
|
bitfld.long 0x0 18. "STA_DBG_RECOV_SPT,DBG_RECOV support." "0,1"
|
|
bitfld.long 0x0 17. "STA_WRM_RST_SPT,WARM_RST support. Ignore this bit. Do not use WARM_RST." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "STA_ON_SPT,ON support." "0,1"
|
|
bitfld.long 0x0 15. "STA_FUNC_RET_SPT,FUNC_RET support." "0,1"
|
|
bitfld.long 0x0 14. "STA_FULL_RET_SPT,FULL_RET support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "STA_MEM_OFF_SPT,MEM_OFF support." "0,1"
|
|
bitfld.long 0x0 12. "STA_LGC_RET_SPT,LOGIC_RET support." "0,1"
|
|
bitfld.long 0x0 11. "STA_MEM_RET_EMU_SPT,MEM_RET_EMU support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STA_MEM_RET_SPT,MEM_RET support." "0,1"
|
|
bitfld.long 0x0 9. "STA_OFF_EMU_SPT,OFF_EMU support." "0,1"
|
|
bitfld.long 0x0 8. "STA_OFF_SPT,OFF support." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "NUM_OPMODE,No. of operating modes supported is NUM_OPMODE + 1."
|
|
hexmask.long.byte 0x0 0.--3. 1. "DEVCHAN,No. of Device Interface Channels."
|
|
line.long 0x4 "IDR1,PPU Identification Register 1"
|
|
bitfld.long 0x4 12. "OFF_MEM_RET_TRANS,OFF to MEM_RET direct transition. Indicates if direct transitions from OFF to MEM_RET and from OFF_EMU to MEM_RET_EMU are supported." "0,1"
|
|
bitfld.long 0x4 10. "OP_ACTIVE,N/A" "0,1"
|
|
bitfld.long 0x4 9. "STA_POLICY_OP_IRQ_SPT,Operating policy transition completion event status." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "STA_POLICY_PWR_IRQ_SPT,Power policy transition completion event status." "0,1"
|
|
bitfld.long 0x4 6. "FUNC_RET_RAM_REG,N/A" "0,1"
|
|
bitfld.long 0x4 5. "FULL_RET_RAM_REG,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MEM_RET_RAM_REG,N/A" "0,1"
|
|
bitfld.long 0x4 2. "LOCK_SPT,Lock and the lock interrupt event are supported." "0,1"
|
|
bitfld.long 0x4 1. "SW_DEV_DEL_SPT,Software device delay control configuration support." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PWR_MODE_ENTRY_DEL_SPT,Power mode entry delay support." "0,1"
|
|
rgroup.long 0xFC8++0x7
|
|
line.long 0x0 "IIDR,Implementation Identification Register"
|
|
hexmask.long.word 0x0 20.--31. 1. "PRODUCT_ID,PPU part identification."
|
|
hexmask.long.byte 0x0 16.--19. 1. "VARIANT,Major revision of the product."
|
|
hexmask.long.byte 0x0 12.--15. 1. "REVISION,Minor revision of the product."
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "IMPLEMENTER,Implementer identification. [11:8] The JEP106 continuation code of the implementer. [7] Always 0. [6:0] The JEP106 identity code of the implementer. For an Arm implementation bits [11:0] are 0x43B."
|
|
line.long 0x4 "AIDR,Architecture Identification Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "ARCH_REV_MAJOR,N/A"
|
|
hexmask.long.byte 0x4 0.--3. 1. "ARCH_REV_MINOR,N/A"
|
|
tree.end
|
|
tree.end
|
|
base ad:0x42210000
|
|
newline
|
|
group.long 0x2000++0x3
|
|
newline
|
|
line.long 0x0 "CLK_SELECT,Clock Selection for Power Mode Components"
|
|
bitfld.long 0x0 16.--17. "CLK_PWR_MUX,Selects a source for the clock used by power control components. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally.." "0: IMO - Internal R/C Oscillator,1: IHO - Internal High-speed Oscillator,2: N/A,?"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CLK_PWR_DIV,clk_pwr is generated by dividing the CLK_PWR_MUX selection by (CLK_PWR_DIV+1)."
|
|
tree.end
|
|
tree "RAMC (SRAM Controller)"
|
|
base ad:0x42110000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 16. "CLOCK_FORCE,Force EAM clock gating to be always ON." "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0.--1. "SRAM_WS,Wait states." "0: N/A,1: N/A,2: N/A,3: N/A"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 4. "PWR_DONE,After a PWR_MACRO_CTL.OFF change this flag indicates if the new power mode has taken effect or not." "0: Indicates change is in progress,1: Indicates change is effective"
|
|
bitfld.long 0x0 0. "WB_EMPTY,Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode." "0: Write buffer NOT empty,1: Write buffer empty"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 16.--22. 1. "PARITY,Injected parity."
|
|
bitfld.long 0x0 3. "CHECK_EN,ECC checking enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 2. "INJ_EN,ECC parity injection:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_CORRECT,ECC auto correction:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "EN,ECC enable:" "0: Disabled,1: Enabled"
|
|
rgroup.long 0x24++0x7
|
|
line.long 0x0 "ECC_STATUS0,ECC status 0"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,ECC error address. This register captures the address location when ECC error happens."
|
|
line.long 0x4 "ECC_STATUS1,ECC status 1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "SYNDROME,This register captures the ECC syndrome when ECC error happens."
|
|
group.long 0x104++0x3
|
|
line.long 0x0 "ECC_MATCH,ECC match"
|
|
hexmask.long 0x0 0.--24. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "PWR_MACRO_CTL,SRAM power partition power control"
|
|
hexmask.long 0x0 0.--31. 1. "OFF,Each bit represent the individual RAM power partition power state. One bit for each macro of RAM controller when all 32 bits are populated as 32 independent power partitions."
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "PWR_MACRO_CTL_LOCK,SRAM power partition power control Lock"
|
|
bitfld.long 0x0 0.--1. "PWR_MACRO_CTL_LOCK,Prohibits Read/Write access to PWR_MACRO_CTL register when this field is not equal to 0. Requires at least two different writes to unlock." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "PWR_DELAY_CTL,SRAM power switch power up & sequence delay"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SEQ1_DELAY,Number of IMO clock cycles delay needed for sequence-1 of SRAM power transition"
|
|
hexmask.long.byte 0x0 16.--23. 1. "SEQ0_DELAY,Number of IMO clock cycles delay needed for sequence-0 of SRAM power transition"
|
|
hexmask.long.word 0x0 0.--9. 1. "UP,Number of IMO clock cycles delay needed after power domain power up"
|
|
tree "MPC (MPC Memory Protection Controller registers)"
|
|
base ad:0x42114000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CFG,Config register with error response. RegionID PPC_MPC_MAIN is the security owner PC. The error response configuration is located in CFG.RESPONSE. only one such configuration exists applying to all protection contexts in the system."
|
|
bitfld.long 0x0 4. "RESPONSE,Response Configuration for Security and PC violations" "0: Read-Zero Write Ignore,1: Bus Error"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CTRL,Control register with lock bit and auto-increment only (Separate CTRL for each PC depends on access_pc)"
|
|
bitfld.long 0x0 31. "LOCK,Security lockdown for this protection context. Software can set this bit but not clear it once set. When set write operations to BLK_LUT are not possible from this protection context. Setting LOCK also blocks writes to CTRL itself (for that PC.." "0,1"
|
|
bitfld.long 0x0 8. "AUTO_INC,Auto-increment BLK_IDX by 1 for this protection context as a side effect of each read/write access to BLK_LUT" "0,1"
|
|
rgroup.long 0x104++0x7
|
|
line.long 0x0 "BLK_MAX,Max value of block-based index register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Maximum value of block-based index register. The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; See product datasheet for details on protection of.."
|
|
line.long 0x4 "BLK_CFG,Block size & initialization in progress"
|
|
bitfld.long 0x4 31. "INIT_IN_PROGRESS,During initialization INIT_IN_PROGRESS is '1' and MMIO register accesses to BLK_LUT is blocked (BLK_IDX increment is also ignored). The block attributes are retained in DeepSleep (and obviously Active) power mode. Initialization is only.." "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "BLOCK_SIZE,Block size of individually protected blocks (0: 32B 1: 64B ... up to 15: 1MB)"
|
|
group.long 0x10C++0x7
|
|
line.long 0x0 "BLK_IDX,Index of 32-block group accessed through BLK_LUT (Separate IDX for each PC depending on access_pc)"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Index value for accessing block-based lookup table using BLK_LUT. Programming out of LUT range is an user error and it loops back to '0' once overflow occurs."
|
|
line.long 0x4 "BLK_LUT,NS status for 32 blocks at BLK_IDX with PC=<access_pc>"
|
|
bitfld.long 0x4 31. "ATTR_NS31,NS bit for block 31 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 30. "ATTR_NS30,NS bit for block 30 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 29. "ATTR_NS29,NS bit for block 29 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 28. "ATTR_NS28,NS bit for block 28 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 27. "ATTR_NS27,NS bit for block 27 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "ATTR_NS26,NS bit for block 26 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 25. "ATTR_NS25,NS bit for block 25 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 24. "ATTR_NS24,NS bit for block 24 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 23. "ATTR_NS23,NS bit for block 23 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 22. "ATTR_NS22,NS bit for block 22 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "ATTR_NS21,NS bit for block 21 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 20. "ATTR_NS20,NS bit for block 20 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 19. "ATTR_NS19,NS bit for block 19 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 18. "ATTR_NS18,NS bit for block 18 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 17. "ATTR_NS17,NS bit for block 17 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "ATTR_NS16,NS bit for block 16 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 15. "ATTR_NS15,NS bit for block 15 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 14. "ATTR_NS14,NS bit for block 14 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 13. "ATTR_NS13,NS bit for block 13 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 12. "ATTR_NS12,NS bit for block 12 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ATTR_NS11,NS bit for block 11 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 10. "ATTR_NS10,NS bit for block 10 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 9. "ATTR_NS9,NS bit for block 9 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 8. "ATTR_NS8,NS bit for block 8 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 7. "ATTR_NS7,NS bit for block 7 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ATTR_NS6,NS bit for block 6 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 5. "ATTR_NS5,NS bit for block 5 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 4. "ATTR_NS4,NS bit for block 4 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 3. "ATTR_NS3,NS bit for block 3 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 2. "ATTR_NS2,NS bit for block 2 based on BLK_IDX" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ATTR_NS1,NS bit for block 1 based on BLK_IDX" "0,1"
|
|
bitfld.long 0x4 0. "ATTR_NS0,NS bit for block 0 based on BLK_IDX" "0,1"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "ROT_CTRL,Control register with lock bit and auto-increment only"
|
|
bitfld.long 0x0 31. "LOCK,Security lockdown for the root-of-trust configuration registers. Software can set this bit but not clear it once set. When set write operations to ROT_BLK_LUT are not possible. Write is ignored." "0,1"
|
|
bitfld.long 0x0 8. "AUTO_INC,Auto-increment BLK_IDX by 1 for each read/write of ROT_BLK_LUT" "0,1"
|
|
rgroup.long 0x208++0x7
|
|
line.long 0x0 "ROT_BLK_MAX,Max value of block-based index register for ROT"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Maximum value of block-based index register. The number and size blocks in an MPC is design time configurable and for embedded memories defaults to covering the entire memory using 4kB blocks; see product datasheet for details on protection of.."
|
|
line.long 0x4 "ROT_BLK_CFG,Same as BLK_CFG"
|
|
bitfld.long 0x4 31. "INIT_IN_PROGRESS,During initialization INIT_IN_PROGRESS is '1' and MMIO register accesses to ROT_BLK_LUT is RAZWI. The block attributes are retained in DeepSleep (and obviously Active) power mode. Initialization is only required from a power mode in.." "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "BLOCK_SIZE,Block size of individually protected blocks (0: 32B 1: 64B ...up to 15:1MB)"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "ROT_BLK_IDX,Index of 8-block group accessed through ROT_BLK_LUT_*"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Index value for accessing block-based lookup table using ROT_BLK_LUT. Programming out of LUT range is an user error and it loops back to '0' once overflow occurs."
|
|
line.long 0x4 "ROT_BLK_PC,Protection context of 8-block group accesses through ROT_BLK_LUT"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PC,Specify PC values for ROT_BLK_IDX and ROT_BLK_LUT"
|
|
line.long 0x8 "ROT_BLK_LUT,(R.W.NS) bits for 8 blocks at ROT_BLK_IDX for PC=ROT_BKL_PC"
|
|
bitfld.long 0x8 28.--30. "ATTR7,W/R/NS bits for block 7 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24.--26. "ATTR6,W/R/NS bits for block 6 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 20.--22. "ATTR5,W/R/NS bits for block 5 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--18. "ATTR4,W/R/NS bits for block 4 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 12.--14. "ATTR3,W/R/NS bits for block 3 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "ATTR2,W/R/NS bits for block 2 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 4.--6. "ATTR1,W/R/NS bits for block 1 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "ATTR0,W/R/NS bits for block 0 indicated by ROT_BLK_IDX for ROT_BLK_PC PC" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree.end
|
|
tree "RAMC_PPU (Power Policy Unit Registers for System RAM)"
|
|
base ad:0x42100000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "PWPR,Power Policy Register"
|
|
bitfld.long 0x0 24. "OP_DYN_EN,N/A" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "OP_POLICY,N/A"
|
|
bitfld.long 0x0 12. "LOCK_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PWR_DYN_EN,Power mode dynamic transition enable. When this bit is set to 1 dynamic transitions are enabled for power modes allowing transitions to be initiated by changes on power mode DEVACTIVE inputs." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PWR_POLICY,Power mode policy. When static power mode transitions are enabled PWR_DYN_EN is set to 0 this is the target power mode for the PPU. When dynamic power mode transitions are enabled PWR_DYN_EN is set to 1 this is the minimum power mode for.."
|
|
line.long 0x4 "PMER,Power Mode Emulation Register"
|
|
bitfld.long 0x4 0. "EMU_EN,N/A" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "PWSR,Power Status Register"
|
|
bitfld.long 0x0 24. "OP_DYN_STATUS,N/A" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "OP_STATUS,N/A"
|
|
bitfld.long 0x0 12. "LOCK_STATUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PWR_DYN_STATUS,Power mode dynamic transition status. When set to 1 power mode dynamic transitions are enabled. There might be a delay in dynamic transitions becoming active or inactive if the PPU is transitioning when PWR_DYN_EN is programmed." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PWR_STATUS,Power mode status. These bits reflect the current power mode of the PPU. See PPU_PWPR.PWR_POLICY for power mode enumeration."
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "DISR,Device Interface Input Current Status Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "OP_DEVACTIVE_STATUS,N/A"
|
|
hexmask.long.word 0x0 0.--10. 1. "PWR_DEVACTIVE_STATUS,Status of the power mode DEVACTIVE inputs."
|
|
line.long 0x4 "MISR,Miscellaneous Input Current Status Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DEVDENY_STATUS,Status of the device interface DEVDENY inputs."
|
|
hexmask.long.byte 0x4 8.--15. 1. "DEVACCEPT_STATUS,Status of the device interface DEVACCEPT inputs."
|
|
bitfld.long 0x4 0. "PCSMPACCEPT_STATUS,The status of the PCSMPACCEPT input." "0,1"
|
|
line.long 0x8 "STSR,Stored Status Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "STORED_DEVDENY,N/A"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "UNLK,Unlock register"
|
|
bitfld.long 0x0 0. "UNLOCK,N/A" "0,1"
|
|
line.long 0x4 "PWCR,Power Configuration Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "OP_DEVACTIVEEN,N/A"
|
|
hexmask.long.word 0x4 8.--18. 1. "PWR_DEVACTIVEEN,These bits enable the power mode DEVACTIVE inputs. When a bit is to 1 the related DEVACTIVE input is enabled when set to 0 it is disabled. All available bits are reset to 1."
|
|
hexmask.long.byte 0x4 0.--7. 1. "DEVREQEN,When set to 1 enables the device interface handshake for transitions. All available bits are reset to 1."
|
|
line.long 0x8 "PTCR,Power Mode Transition Configuration Register"
|
|
bitfld.long 0x8 1. "DBG_RECOV_PORST_EN,N/A" "0,1"
|
|
bitfld.long 0x8 0. "WARM_RST_DEVREQEN,Transition behavior between ON and WARM_RST. This bit should not be modified when the PPU is in WARM_RST or if the PPU is performing a transition otherwise PPU behavior is UNPREDICTABLE." "0: The PPU does not perform a device interface..,1: The PPU performs a device interface handshake.."
|
|
group.long 0x30++0x17
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 5. "LOCKED_IRQ_MASK,N/A" "0,1"
|
|
bitfld.long 0x0 4. "EMU_DENY_IRQ_MASK,N/A" "0,1"
|
|
bitfld.long 0x0 3. "EMU_ACCEPT_IRQ_MASK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "STA_DENY_IRQ_MASK,Static transition denial event mask." "0,1"
|
|
bitfld.long 0x0 1. "STA_ACCEPT_IRQ_MASK,Static transition acceptance event mask." "0,1"
|
|
bitfld.long 0x0 0. "STA_POLICY_TRN_IRQ_MASK,Static full policy transition completion event mask." "0,1"
|
|
line.long 0x4 "AIMR,Additional Interrupt Mask Register"
|
|
bitfld.long 0x4 4. "STA_POLICY_OP_IRQ_MASK,N/A" "0,1"
|
|
bitfld.long 0x4 3. "STA_POLICY_PWR_IRQ_MASK,N/A" "0,1"
|
|
bitfld.long 0x4 2. "DYN_DENY_IRQ_MASK,Dynamic transition denial event mask." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DYN_ACCEPT_IRQ_MASK,Dynamic transition acceptance event mask." "0,1"
|
|
bitfld.long 0x4 0. "UNSPT_POLICY_IRQ_MASK,Unsupported Policy event mask." "0,1"
|
|
line.long 0x8 "ISR,Interrupt Status Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "OP_ACTIVE_EDGE_IRQ,N/A"
|
|
hexmask.long.word 0x8 8.--18. 1. "PWR_ACTIVE_EDGE_IRQ,N/A"
|
|
rbitfld.long 0x8 7. "OTHER_IRQ,Indicates there is an interrupt event pending in the Additional Interrupt Status Register (PPU_AISR)." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "LOCKED_IRQ,N/A" "0,1"
|
|
bitfld.long 0x8 4. "EMU_DENY_IRQ,N/A" "0,1"
|
|
bitfld.long 0x8 3. "EMU_ACCEPT_IRQ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "STA_DENY_IRQ,Static transition denial event status." "0,1"
|
|
bitfld.long 0x8 1. "STA_ACCEPT_IRQ,Static transition acceptance event status." "0,1"
|
|
bitfld.long 0x8 0. "STA_POLICY_TRN_IRQ,Static full policy transition completion event status." "0,1"
|
|
line.long 0xC "AISR,Additional Interrupt Status Register"
|
|
bitfld.long 0xC 4. "STA_POLICY_OP_IRQ,N/A" "0,1"
|
|
bitfld.long 0xC 3. "STA_POLICY_PWR_IRQ,N/A" "0,1"
|
|
bitfld.long 0xC 2. "DYN_DENY_IRQ,Dynamic transition denial event status." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "DYN_ACCEPT_IRQ,Dynamic transition acceptance event status." "0,1"
|
|
bitfld.long 0xC 0. "UNSPT_POLICY_IRQ,Unsupported Policy event status." "0,1"
|
|
line.long 0x10 "IESR,Input Edge Sensitivity Register"
|
|
bitfld.long 0x10 20.--21. "DEVACTIVE10_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 18.--19. "DEVACTIVE09_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "DEVACTIVE08_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "DEVACTIVE07_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 12.--13. "DEVACTIVE06_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 10.--11. "DEVACTIVE05_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 8.--9. "DEVACTIVE04_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. "DEVACTIVE03_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 4.--5. "DEVACTIVE02_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 2.--3. "DEVACTIVE01_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "DEVACTIVE00_EDGE,DEVACTIVE 0 edge sensitivity." "0,1,2,3"
|
|
line.long 0x14 "OPSR,Operating Mode Active Edge Sensitivity Register"
|
|
bitfld.long 0x14 14.--15. "DEVACTIVE23_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. "DEVACTIVE22_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. "DEVACTIVE21_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 8.--9. "DEVACTIVE20_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. "DEVACTIVE19_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. "DEVACTIVE18_EDGE,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 2.--3. "DEVACTIVE17_EDGE,N/A" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. "DEVACTIVE16_EDGE,N/A" "0,1,2,3"
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "FUNRR,Functional Retention RAM Configuration Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FUNC_RET_RAM_CFG,N/A"
|
|
line.long 0x4 "FULRR,Full Retention RAM Configuration Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "FULL_RET_RAM_CFG,N/A"
|
|
line.long 0x8 "MEMRR,Memory Retention RAM Configuration Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "MEM_RET_RAM_CFG,N/A"
|
|
group.long 0x160++0x7
|
|
line.long 0x0 "EDTR0,Power Mode Entry Delay Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "FULL_RET_DEL,N/A"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LOGIC_RET_DEL,N/A"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MEM_RET_DEL,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "OFF_DEL,N/A"
|
|
line.long 0x4 "EDTR1,Power Mode Entry Delay Register 1"
|
|
hexmask.long.byte 0x4 8.--15. 1. "FUNC_RET_DEL,N/A"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MEM_OFF_DEL,N/A"
|
|
rgroup.long 0x170++0x7
|
|
line.long 0x0 "DCDR0,Device Control Delay Configuration Register 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RST_HWSTAT_DLY,N/A"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ISO_CLKEN_DLY,N/A"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CLKEN_RST_DLY,N/A"
|
|
line.long 0x4 "DCDR1,Device Control Delay Configuration Register 1"
|
|
hexmask.long.byte 0x4 8.--15. 1. "CLKEN_ISO_DLY,N/A"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ISO_RST_DLY,N/A"
|
|
rgroup.long 0xFB0++0x7
|
|
line.long 0x0 "IDR0,PPU Identification Register 0"
|
|
bitfld.long 0x0 29. "DYN_WRM_RST_SPT,Dynamic WARM_RST support." "0,1"
|
|
bitfld.long 0x0 28. "DYN_ON_SPT,Dynamic ON support." "0,1"
|
|
bitfld.long 0x0 27. "DYN_FUNC_RET_SPT,Dynamic FUNC_RET support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "DYN_FULL_RET_SPT,Dynamic FULL_RET support." "0,1"
|
|
bitfld.long 0x0 25. "DYN_MEM_OFF_SPT,Dynamic MEM_OFF support." "0,1"
|
|
bitfld.long 0x0 24. "DYN_LGC_RET_SPT,Dynamic LOGIC_RET support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DYN_MEM_RET_EMU_SPT,Dynamic MEM_RET_EMU support" "0,1"
|
|
bitfld.long 0x0 22. "DYN_MEM_RET_SPT,Dynamic MEM_RET support." "0,1"
|
|
bitfld.long 0x0 21. "DYN_OFF_EMU_SPT,Dynamic OFF_EMU support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DYN_OFF_SPT,Dynamic OFF support." "0,1"
|
|
bitfld.long 0x0 18. "STA_DBG_RECOV_SPT,DBG_RECOV support." "0,1"
|
|
bitfld.long 0x0 17. "STA_WRM_RST_SPT,WARM_RST support. Ignore this bit. Do not use WARM_RST." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "STA_ON_SPT,ON support." "0,1"
|
|
bitfld.long 0x0 15. "STA_FUNC_RET_SPT,FUNC_RET support." "0,1"
|
|
bitfld.long 0x0 14. "STA_FULL_RET_SPT,FULL_RET support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "STA_MEM_OFF_SPT,MEM_OFF support." "0,1"
|
|
bitfld.long 0x0 12. "STA_LGC_RET_SPT,LOGIC_RET support." "0,1"
|
|
bitfld.long 0x0 11. "STA_MEM_RET_EMU_SPT,MEM_RET_EMU support." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STA_MEM_RET_SPT,MEM_RET support." "0,1"
|
|
bitfld.long 0x0 9. "STA_OFF_EMU_SPT,OFF_EMU support." "0,1"
|
|
bitfld.long 0x0 8. "STA_OFF_SPT,OFF support." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "NUM_OPMODE,No. of operating modes supported is NUM_OPMODE + 1."
|
|
hexmask.long.byte 0x0 0.--3. 1. "DEVCHAN,No. of Device Interface Channels. The device enumeration is:"
|
|
line.long 0x4 "IDR1,PPU Identification Register 1"
|
|
bitfld.long 0x4 12. "OFF_MEM_RET_TRANS,OFF to MEM_RET direct transition. Indicates if direct transitions from OFF to MEM_RET and from OFF_EMU to MEM_RET_EMU are supported." "0,1"
|
|
bitfld.long 0x4 10. "OP_ACTIVE,N/A" "0,1"
|
|
bitfld.long 0x4 9. "STA_POLICY_OP_IRQ_SPT,Operating policy transition completion event status." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "STA_POLICY_PWR_IRQ_SPT,Power policy transition completion event status." "0,1"
|
|
bitfld.long 0x4 6. "FUNC_RET_RAM_REG,N/A" "0,1"
|
|
bitfld.long 0x4 5. "FULL_RET_RAM_REG,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MEM_RET_RAM_REG,N/A" "0,1"
|
|
bitfld.long 0x4 2. "LOCK_SPT,Lock and the lock interrupt event are supported." "0,1"
|
|
bitfld.long 0x4 1. "SW_DEV_DEL_SPT,Software device delay control configuration support." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PWR_MODE_ENTRY_DEL_SPT,Power mode entry delay support." "0,1"
|
|
rgroup.long 0xFC8++0xB
|
|
line.long 0x0 "IIDR,Implementation Identification Register"
|
|
hexmask.long.word 0x0 20.--31. 1. "PRODUCT_ID,PPU part identification."
|
|
hexmask.long.byte 0x0 16.--19. 1. "VARIANT,Major revision of the product."
|
|
hexmask.long.byte 0x0 12.--15. 1. "REVISION,Minor revision of the product."
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "IMPLEMENTER,Implementer identification. [11:8] The JEP106 continuation code of the implementer. [7] Always 0. [6:0] The JEP106 identity code of the implementer. For an Arm implementation bits [11:0] are 0x43B."
|
|
line.long 0x4 "AIDR,Architecture Identification Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "ARCH_REV_MAJOR,N/A"
|
|
hexmask.long.byte 0x4 0.--3. 1. "ARCH_REV_MINOR,N/A"
|
|
line.long 0x8 "PID4,Implementation Defined Identification Register (PID4)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "IMPLEMENTER_11_8,The JEP106 continuation code of the implementer which is 0x4 hardcoded value."
|
|
rgroup.long 0xFE0++0x1F
|
|
line.long 0x0 "PID0,Implementation Defined Identification Register (PID0)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PRODUCT_ID_7_0,PPU part identification bits [7:0]."
|
|
line.long 0x4 "PID1,Implementation Defined Identification Register (PID1)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "IMPLEMENTER_3_0,JEP106_ID bits [3:0]"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRODUCT_ID_11_8,PPU part identification bits [11:8]"
|
|
line.long 0x8 "PID2,Implementation Defined Identification Register (PID2)"
|
|
hexmask.long.byte 0x8 4.--7. 1. "REV_CONST,Constant LOW Revision (4 bits)"
|
|
bitfld.long 0x8 3. "CONST_HIGH,Constant HIGH" "0,1"
|
|
bitfld.long 0x8 0.--2. "IMPLEMENTER_6_4,JEP106_ID bits [6:4]" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "PID3,Implementation Defined Identification Register (PID3)"
|
|
hexmask.long.byte 0xC 4.--7. 1. "PID3_REVISION,Minor revision of the product."
|
|
hexmask.long.byte 0xC 0.--3. 1. "PID3_REV_CONST,Constant LOW (4 bits)"
|
|
line.long 0x10 "ID0,Implementation Defined Identification Register (ID0)"
|
|
hexmask.long.byte 0x10 0.--7. 1. "ID0,ID0 hard coded value"
|
|
line.long 0x14 "ID1,Implementation Defined Identification Register (ID1)"
|
|
hexmask.long.byte 0x14 0.--7. 1. "ID1,ID1 hardcoded value"
|
|
line.long 0x18 "ID2,Implementation Defined Identification Register (ID2)"
|
|
hexmask.long.byte 0x18 0.--7. 1. "ID2,ID2 hardcoded value"
|
|
line.long 0x1C "ID3,Implementation Defined Identification Register (ID3)"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "ID3,ID3 hardcoded value"
|
|
tree.end
|
|
tree "SCB (Serial Communications Block (SPI/UART/I2C))"
|
|
base ad:0x0
|
|
tree "SCB0"
|
|
base ad:0x42820000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MEM_WIDTH,N/A" "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
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newline
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,N/A" "0,1"
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newline
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,N/A" "0,1"
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newline
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,N/A" "0,1"
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newline
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bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
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newline
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bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
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newline
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bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
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newline
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "LATE_SAMPLE,Changes the SCLK edge on which MISO is captured in master mode or MOSI is captured in slave mode." "0,1"
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newline
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bitfld.long 0x0 3. "CPOL,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "CPHA,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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newline
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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newline
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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group.long 0x28++0x7
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
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bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
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newline
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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newline
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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newline
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,N/A" "0,1"
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newline
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,N/A"
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newline
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bitfld.long 0x8 14. "HDRXEN,N/A" "0,1"
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bitfld.long 0x8 13. "SKIP_START,N/A" "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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newline
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bitfld.long 0x8 10. "MP_MODE,N/A" "0,1"
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newline
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
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newline
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
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newline
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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newline
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
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newline
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bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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newline
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
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newline
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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newline
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,N/A" "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,N/A" "0,1"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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bitfld.long 0x0 24. "HS_MODE,N/A" "0,1"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,N/A"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,N/A"
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newline
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "I2CS_IC_BUSY,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_EC_BUSY,N/A" "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xF
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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newline
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
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newline
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bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
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newline
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0: 0 ns,1: 50 ns,2: 100 ns,3: 150 ns"
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newline
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
|
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0: 0 ns,1: 50 ns"
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newline
|
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0: 0 ns,1: 50 ns"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
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hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,N/A"
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rgroup.long 0x78++0x3
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line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
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bitfld.long 0x0 8. "STRETCHING,N/A" "0,1"
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newline
|
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bitfld.long 0x0 5. "SYNC_DETECTED,N/A" "0,1"
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newline
|
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bitfld.long 0x0 4. "STRETCH_DETECTED,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,N/A"
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group.long 0x80++0x3
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line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
|
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bitfld.long 0x0 31. "HS_ENABLED,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,N/A"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,N/A"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
|
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bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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newline
|
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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|
rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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newline
|
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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|
wgroup.long 0x240++0x3
|
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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|
newline
|
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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newline
|
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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|
group.long 0x310++0x3
|
|
line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
|
|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
|
|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "I2C_RESTART,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "SCB1"
|
|
base ad:0x42840000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
|
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MEM_WIDTH,N/A" "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SSEL_HOLD_DEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SSEL_SETUP_DEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_SAMPLE,Changes the SCLK edge on which MISO is captured in master mode or MOSI is captured in slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
|
|
newline
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
|
|
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
|
|
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
bitfld.long 0x8 24. "BREAK_LEVEL,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,N/A"
|
|
newline
|
|
bitfld.long 0x8 14. "HDRXEN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
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|
group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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newline
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
|
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,N/A" "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,N/A" "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,N/A" "0,1"
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newline
|
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,N/A" "0,1"
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newline
|
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bitfld.long 0x0 8. "M_READY_DATA_ACK,N/A" "0,1"
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|
newline
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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bitfld.long 0x0 24. "HS_MODE,N/A" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,N/A"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,N/A"
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newline
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "I2CS_IC_BUSY,N/A" "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,N/A" "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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|
group.long 0x68++0xF
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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newline
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
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newline
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bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
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newline
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0: 0 ns,1: 50 ns,2: 100 ns,3: 150 ns"
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newline
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0: 0 ns,1: 50 ns"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0: 0 ns,1: 50 ns"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
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hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,N/A"
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rgroup.long 0x78++0x3
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line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
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bitfld.long 0x0 8. "STRETCHING,N/A" "0,1"
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newline
|
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bitfld.long 0x0 5. "SYNC_DETECTED,N/A" "0,1"
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newline
|
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bitfld.long 0x0 4. "STRETCH_DETECTED,N/A" "0,1"
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,N/A"
|
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group.long 0x80++0x3
|
|
line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
|
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bitfld.long 0x0 31. "HS_ENABLED,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,N/A"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,N/A"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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newline
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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newline
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
|
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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|
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
|
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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newline
|
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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newline
|
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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|
group.long 0x310++0x3
|
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line.long 0x0 "RX_MATCH,Slave address and mask"
|
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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|
rgroup.long 0x340++0x7
|
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
|
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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|
rgroup.long 0xE00++0x3
|
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "I2C_RESTART,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "SCB2"
|
|
base ad:0x42850000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MEM_WIDTH,N/A" "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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|
newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SSEL_SETUP_DEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_SAMPLE,Changes the SCLK edge on which MISO is captured in master mode or MOSI is captured in slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
|
|
newline
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
|
|
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
|
|
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
bitfld.long 0x8 24. "BREAK_LEVEL,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,N/A"
|
|
newline
|
|
bitfld.long 0x8 14. "HDRXEN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "S_READY_ADDR_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "S_GENERAL_IGNORE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M_READY_DATA_ACK,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
bitfld.long 0x0 24. "HS_MODE,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,N/A"
|
|
newline
|
|
bitfld.long 0x0 5. "M_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2CS_IC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
|
|
group.long 0x68++0xF
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
|
|
line.long 0x4 "I2C_S_CMD,I2C slave command"
|
|
bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
|
|
line.long 0x8 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0: 0 ns,1: 50 ns,2: 100 ns,3: 150 ns"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0: 0 ns,1: 50 ns"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0: 0 ns,1: 50 ns"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
|
|
line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
|
|
hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,N/A"
|
|
rgroup.long 0x78++0x3
|
|
line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
|
|
bitfld.long 0x0 8. "STRETCHING,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SYNC_DETECTED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "STRETCH_DETECTED,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,N/A"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
|
|
bitfld.long 0x0 31. "HS_ENABLED,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,N/A"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
|
|
newline
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
|
|
newline
|
|
bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
|
|
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
|
|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
|
|
newline
|
|
bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
|
|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
|
|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "I2C_RESTART,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "SCB3"
|
|
base ad:0x42860000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MEM_WIDTH,N/A" "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SSEL_HOLD_DEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SSEL_SETUP_DEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_SAMPLE,Changes the SCLK edge on which MISO is captured in master mode or MOSI is captured in slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
|
|
newline
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
|
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newline
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,N/A" "0,1"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,N/A"
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bitfld.long 0x8 14. "HDRXEN,N/A" "0,1"
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bitfld.long 0x8 13. "SKIP_START,N/A" "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,N/A" "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
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bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,N/A" "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,N/A" "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,N/A" "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,N/A" "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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bitfld.long 0x0 24. "HS_MODE,N/A" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,N/A"
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,N/A"
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,N/A" "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,N/A" "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xF
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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newline
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
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newline
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bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0: 0 ns,1: 50 ns,2: 100 ns,3: 150 ns"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0: 0 ns,1: 50 ns"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0: 0 ns,1: 50 ns"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
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hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,N/A"
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rgroup.long 0x78++0x3
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line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
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bitfld.long 0x0 8. "STRETCHING,N/A" "0,1"
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newline
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bitfld.long 0x0 5. "SYNC_DETECTED,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "STRETCH_DETECTED,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,N/A"
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group.long 0x80++0x3
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line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
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bitfld.long 0x0 31. "HS_ENABLED,N/A" "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,N/A"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,N/A"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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newline
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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newline
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
|
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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newline
|
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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|
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
|
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line.long 0x0 "RX_MATCH,Slave address and mask"
|
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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rgroup.long 0x340++0x7
|
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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|
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "I2C_RESTART,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "SCB4"
|
|
base ad:0x42870000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MEM_WIDTH,N/A" "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0: no ongoing bus transfer,1: ongoing bus transfer"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
|
|
newline
|
|
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SSEL_HOLD_DEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SSEL_SETUP_DEL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_SAMPLE,Changes the SCLK edge on which MISO is captured in master mode or MOSI is captured in slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
|
|
newline
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
|
|
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
|
|
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
bitfld.long 0x8 24. "BREAK_LEVEL,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,N/A"
|
|
newline
|
|
bitfld.long 0x8 14. "HDRXEN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "S_READY_ADDR_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "S_GENERAL_IGNORE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M_READY_DATA_ACK,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
bitfld.long 0x0 24. "HS_MODE,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,N/A"
|
|
newline
|
|
bitfld.long 0x0 5. "M_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "S_READ,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2CS_IC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
|
|
group.long 0x68++0xF
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
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bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0: 0 ns,1: 50 ns,2: 100 ns,3: 150 ns"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0: 0 ns,1: 50 ns"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0: 0 ns,1: 50 ns"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
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hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,N/A"
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rgroup.long 0x78++0x3
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line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
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bitfld.long 0x0 8. "STRETCHING,N/A" "0,1"
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bitfld.long 0x0 5. "SYNC_DETECTED,N/A" "0,1"
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bitfld.long 0x0 4. "STRETCH_DETECTED,N/A" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,N/A"
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group.long 0x80++0x3
|
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line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
|
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bitfld.long 0x0 31. "HS_ENABLED,N/A" "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,N/A"
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hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,N/A"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
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group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
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|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xECC++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
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|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xF00++0xB
|
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line.long 0x0 "INTR_M,Master interrupt request"
|
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bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
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bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
|
|
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|
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
|
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|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
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|
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
|
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
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|
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
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|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
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|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
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|
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bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
|
|
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|
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bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "I2C_HS_ENTER,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "I2C_RESTART,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "SCB5"
|
|
base ad:0x42C00000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MEM_WIDTH,N/A" "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0: Internally clocked mode,1: externally clocked mode"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0: Internally clocked mode,1: Externally clocked mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,N/A" "0,1"
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newline
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0: no ongoing bus transfer,1: ongoing bus transfer"
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newline
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: No local loopback,1: the SPI master MISO line is connected to the SPI.."
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newline
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,N/A" "0,1"
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newline
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,N/A" "0,1"
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newline
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,N/A" "0,1"
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newline
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bitfld.long 0x0 11. "SSEL_POLARITY3,N/A" "0,1"
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newline
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bitfld.long 0x0 10. "SSEL_POLARITY2,N/A" "0,1"
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newline
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bitfld.long 0x0 9. "SSEL_POLARITY1,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "SSEL_POLARITY0,N/A" "0,1"
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newline
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "LATE_SAMPLE,Changes the SCLK edge on which MISO is captured in master mode or MOSI is captured in slave mode." "0,1"
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newline
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bitfld.long 0x0 3. "CPOL,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "CPHA,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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newline
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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newline
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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group.long 0x28++0x7
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
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bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
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newline
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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newline
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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newline
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,N/A" "0,1"
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newline
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,N/A"
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newline
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bitfld.long 0x8 14. "HDRXEN,N/A" "0,1"
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bitfld.long 0x8 13. "SKIP_START,N/A" "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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newline
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bitfld.long 0x8 10. "MP_MODE,N/A" "0,1"
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newline
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
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newline
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
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newline
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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newline
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bitfld.long 0x8 5. "PARITY_ENABLED,N/A" "0,1"
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newline
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bitfld.long 0x8 4. "PARITY,N/A" "0,1"
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newline
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0: Disabled,1: Enabled"
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newline
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0: CTS is active low,1: CTS is active high"
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newline
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0: RTS is active low,1: RTS is active high"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 30. "SLAVE_MODE,N/A" "0,1"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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newline
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,N/A" "0,1"
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newline
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,N/A" "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,N/A" "0,1"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median filtering."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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bitfld.long 0x0 24. "HS_MODE,N/A" "0,1"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,N/A"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,N/A"
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newline
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bitfld.long 0x0 5. "M_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 4. "S_READ,N/A" "0,1"
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newline
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bitfld.long 0x0 2. "I2CS_IC_BUSY,N/A" "0,1"
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newline
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bitfld.long 0x0 1. "I2C_EC_BUSY,N/A" "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xF
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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newline
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
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newline
|
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bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
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newline
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0: 0 ns,1: 50 ns,2: 100 ns,3: 150 ns"
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newline
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
|
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0: 0 ns,1: 50 ns"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0: 0 ns,1: 50 ns"
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newline
|
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
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hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,N/A"
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rgroup.long 0x78++0x3
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line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
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bitfld.long 0x0 8. "STRETCHING,N/A" "0,1"
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newline
|
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bitfld.long 0x0 5. "SYNC_DETECTED,N/A" "0,1"
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newline
|
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bitfld.long 0x0 4. "STRETCH_DETECTED,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,N/A"
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group.long 0x80++0x3
|
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line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
|
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bitfld.long 0x0 31. "HS_ENABLED,N/A" "0,1"
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newline
|
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hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,N/A"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,N/A"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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newline
|
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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|
wgroup.long 0x240++0x3
|
|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
|
|
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
|
|
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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|
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|
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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|
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|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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|
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
|
|
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|
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
|
|
group.long 0x310++0x3
|
|
line.long 0x0 "RX_MATCH,Slave address and mask"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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|
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,N/A"
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|
rgroup.long 0x340++0x7
|
|
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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|
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|
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
|
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|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
|
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|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
|
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|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
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|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
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|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
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|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
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|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
|
group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
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|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
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line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
|
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|
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bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
|
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|
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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|
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|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
|
|
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|
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
|
|
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|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
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|
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
|
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
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bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
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bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "I2C_HS_ENTER,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "I2C_RESTART,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "SPI_BUS_ERROR,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,N/A" "0,1"
|
|
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|
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bitfld.long 0x0 7. "I2C_GENERAL,N/A" "0,1"
|
|
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|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,N/A" "0,1"
|
|
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|
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bitfld.long 0x0 5. "I2C_START,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,N/A" "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "SMARTIO (Smart I/O)"
|
|
base ad:0x42420000
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x42420000 ad:0x42420100 ad:0x42420200 ad:0x42420300 ad:0x42420400 ad:0x42420500 ad:0x42420600 ad:0x42420700 ad:0x42420800 ad:0x42420900)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 31. "ENABLED,Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 25. "PIPELINE_EN,Enable for pipeline register:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "HLD_OVR,IO cell hold override functionality. In DeepSleep power mode the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep.." "0: The HSIOM controls the IO cell hold override..,1: The SMARTIO controls the IO cel hold override.."
|
|
hexmask.long.byte 0x0 8.--12. 1. "CLOCK_SRC,Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "BYPASS,Bypass of the programmable IO one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1' this field is used. When ENABLED is '0' this field is NOT used and SMARTIO fabric is always bypassed."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SYNC_CTL,Synchronization control register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHIP_SYNC_EN,Synchronization of the chip input signals to 'clk_fabric' one bit for each input: CHIP_SYNC_EN[i] is for input i."
|
|
hexmask.long.byte 0x0 0.--7. 1. "IO_SYNC_EN,Synchronization of the IO pin input signals to 'clk_fabric' one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "LUT_SEL[$1],LUT component input selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection:"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection:"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "LUT_CTL[$1],LUT component control register"
|
|
bitfld.long 0x0 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation:" "0: Combinatoral output,1: Combinatorial output,2: Sequential output,3: Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LUT,LUT configuration. Depending on the LUT opcode LUT_OPC the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in tr1_in tr2_in the LUT configuration is used to determine the LUT output signal and the next sequential.."
|
|
repeat.end
|
|
group.long ($2+0xC0)++0x7
|
|
line.long 0x0 "DU_SEL,Data unit component input selection"
|
|
bitfld.long 0x0 28.--29. "DU_DATA1_SEL,Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL." "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "DU_DATA0_SEL,Data unit input data 'data0_in' source selection:" "0: Constant '0',1: chip_data[7:0],2: io_data_in[7:0],3: DATA"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "DU_TR2_SEL,Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "DU_TR1_SEL,Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU_TR0_SEL,Data unit input signal 'tr0_in' source selection:"
|
|
line.long 0x4 "DU_CTL,Data unit component control register"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DU_OPC,Data unit opcode specifies the data unit operation:"
|
|
bitfld.long 0x4 0.--2. "DU_SIZE,Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g. if DU_SIZE is 7 the width is 8 bits." "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data unit input data source."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SRSS (System Resources Subsystem)"
|
|
base ad:0x42200000
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "PWR_LVD_STATUS,High Voltage / Low Voltage Detector (HVLVD) Status Register"
|
|
bitfld.long 0x0 0. "HVLVD1_OK,HVLVD1 output." "0: below voltage threshold,1: above voltage threshold"
|
|
line.long 0x4 "PWR_LVD_STATUS2,High Voltage / Low Voltage Detector (HVLVD) Status Register #2"
|
|
bitfld.long 0x4 0. "HVLVD2_OUT,HVLVD2 output." "0: below voltage threshold,1: above voltage threshold"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "CLK_DSI_SELECT[$1],Clock DSI Select Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DSI_MUX,Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It.."
|
|
repeat.end
|
|
group.long 0x140++0xB
|
|
line.long 0x0 "CLK_OUTPUT_FAST,Fast Clock Output Select Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HFCLK_SEL1,Selects a HFCLK tree for use in fast clock output #1 logic"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PATH_SEL1,Selects a clock path to use in fast clock output #1 logic."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "FAST_SEL1,Select signal for fast clock output #1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HFCLK_SEL0,Selects a HFCLK tree for use in fast clock output #0"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PATH_SEL0,Selects a clock path to use in fast clock output #0 logic."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "FAST_SEL0,Select signal for fast clock output #0"
|
|
line.long 0x4 "CLK_OUTPUT_SLOW,Slow Clock Output Select Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SLOW_SEL1,Select signal for slow clock output #1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "SLOW_SEL0,Select signal for slow clock output #0"
|
|
line.long 0x8 "CLK_CAL_CNT1,Clock Calibration Counter 1"
|
|
rbitfld.long 0x8 31. "CAL_COUNTER_DONE,Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 30. "CAL_CLK1_PRESENT,Status bit indicating that a posedge was detected by counter #1. If this bit never asserts there is no clock on counter #1 and CAL_COUNTER_DONE will stay low indefinitely. This can be recovered with CAL_RESET." "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "CAL_RESET,Reset clock calibration logic for window mode. This can be used to recover from unexpected conditions such as no clock present on counter #1." "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "CAL_COUNTER1,Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that.."
|
|
rgroup.long 0x14C++0x3
|
|
line.long 0x0 "CLK_CAL_CNT2,Clock Calibration Counter 2"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CAL_COUNTER2,Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1 the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related.."
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "SRSS_INTR,SRSS Interrupt Register"
|
|
rbitfld.long 0x0 31. "AINTR,See additional interrupts in SRSS_AINTR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CLK_CAL,Clock calibration counter is done. This field is reset during DEEPSLEEP mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WDT_MATCH,WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization it takes 2 SYSCLK cycles to update after a W1C." "0,1"
|
|
line.long 0x4 "SRSS_INTR_SET,SRSS Interrupt Set Register"
|
|
bitfld.long 0x4 5. "CLK_CAL,Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "WDT_MATCH,Set interrupt for low voltage detector WDT_MATCH" "0,1"
|
|
line.long 0x8 "SRSS_INTR_MASK,SRSS Interrupt Mask Register"
|
|
bitfld.long 0x8 5. "CLK_CAL,Mask for clock calibration done" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "WDT_MATCH,Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not however disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip it also internally pends an interrupt that.." "0,1"
|
|
rgroup.long 0x20C++0x3
|
|
line.long 0x0 "SRSS_INTR_MASKED,SRSS Interrupt Masked Register"
|
|
bitfld.long 0x0 31. "AINTR,See additional MASKED bits in SRSS_AINTR_MASKED.ADDITIONAL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CLK_CAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WDT_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x300++0xB
|
|
line.long 0x0 "SRSS_AINTR,SRSS Additional Interrupt Register"
|
|
bitfld.long 0x0 2. "HVLVD2,Interrupt for low voltage detector HVLVD2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "HVLVD1,Interrupt for low voltage detector HVLVD1" "0,1"
|
|
line.long 0x4 "SRSS_AINTR_SET,SRSS Additional Interrupt Set Register"
|
|
bitfld.long 0x4 2. "HVLVD2,Set interrupt for low voltage detector HVLVD2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "HVLVD1,Set interrupt for low voltage detector HVLVD1" "0,1"
|
|
line.long 0x8 "SRSS_AINTR_MASK,SRSS Additional Interrupt Mask Register"
|
|
bitfld.long 0x8 2. "HVLVD2,Mask for low voltage detector HVLVD2" "0,1"
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newline
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bitfld.long 0x8 1. "HVLVD1,Mask for low voltage detector HVLVD1" "0,1"
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rgroup.long 0x30C++0x3
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line.long 0x0 "SRSS_AINTR_MASKED,SRSS Additional Interrupt Masked Register"
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bitfld.long 0x0 2. "HVLVD2,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "HVLVD1,Logical and of corresponding request and mask bits." "0,1"
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group.long 0x404++0xF
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line.long 0x0 "BOOT_DLM_CTL,Debug Control Register"
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bitfld.long 0x0 31. "WFA,Wait for Action. Set by BootROM when it waits for application or debug certificate to be loaded into the RAM. The bit must be cleared to continue BootROM operation. It is used by the Sys-AP." "0,1"
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newline
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bitfld.long 0x0 30. "RESET,Request the device reset after RAM application complete input parameters processing. This bit is analyzed with APP_INPUT_AVAIL so to take effect write both." "0,1"
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newline
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bitfld.long 0x0 29. "INPUT_AVAIL,Notify RAM application that input parameters are valid for processing:" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "REQUEST,A request to ROM_BOOT FW to execute particular code."
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line.long 0x4 "BOOT_DLM_CTL2,Debug Control Register 2"
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hexmask.long 0x4 0.--31. 1. "APP_CTL,Address of application descriptor or debug certificate depends on DEBUG_TST_CTL.REQUEST. The application descriptor provides info about RAM application and its parameters layout in the staging area to BootROM and RAM application itself"
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line.long 0x8 "BOOT_DLM_STATUS,Debug Status Register"
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hexmask.long 0x8 0.--31. 1. "DEBUG_STATUS,RAM application execution status. This status can be read by the debugger using Sys-AP or user application when RAM application completes with system reset. This field survives some resets including a system reset."
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line.long 0xC "RES_SOFT_CTL,Soft Reset Trigger Register"
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bitfld.long 0xC 0. "TRIGGER_SOFT,Triggers a soft reset. The reset clears this bit." "0,1"
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group.long 0x418++0x3
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line.long 0x0 "BOOT_STATUS,Boot Execution Status Register"
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hexmask.long 0x0 0.--31. 1. "DEBUG_STATUS,Boot execution status. This status register can be used for communication between ROM_BOOT and User Application. This status can be read by the debugger using Sys-AP or User Application. This field survives some resets including a system.."
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group.long 0x430++0x3
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line.long 0x0 "BOOT_ENTRY,Warm Boot Entry Address"
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hexmask.long 0x0 0.--31. 1. "WARM_BOOT_ENTRY,Warm boot entry point. This status register can be used for communication between 2 software application before/after DS-RAM or soft reset. This field survives low voltage resets including a system reset."
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repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x800)++0x3
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line.long 0x0 "PWR_HIB_DATA[$1],HIBERNATE Data Register"
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hexmask.long 0x0 0.--31. 1. "HIB_DATA,Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register."
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repeat.end
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group.long 0x8A0++0x7
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line.long 0x0 "PWR_HIB_WAKE_CTL,Hibernate Wakeup Mask Register"
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bitfld.long 0x0 31. "HIB_WAKE_WDT,When set HIBERNATE will wakeup for a pending WDT interrupt." "0,1"
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newline
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bitfld.long 0x0 30. "HIB_WAKE_RTC,When set HIBERNATE will wakeup for a pending RTC interrupt." "0,1"
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newline
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bitfld.long 0x0 29. "HIB_WAKE_CSV_BAK,When set HIBERNATE will wakeup for CSV_BAK detection." "0,1"
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newline
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hexmask.long.tbyte 0x0 0.--23. 1. "HIB_WAKE_SRC,When set HIBERNATE will wakeup for the assigned source."
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line.long 0x4 "PWR_HIB_WAKE_CTL2,Hibernate Wakeup Polarity Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "HIB_WAKE_SRC,Each bit selects the polarity for the corresponding HIBERNATE wakeup source. 0: Wakes when unmasked input is 0."
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group.long 0x8AC++0x3
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line.long 0x0 "PWR_HIB_WAKE_CAUSE,Hibernate Wakeup Cause Register"
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bitfld.long 0x0 31. "HIB_WAKE_WDT,Indicates WDT wakeup cause. The WDT interrupt must be cleared before this bit can be cleared." "0,1"
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newline
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bitfld.long 0x0 30. "HIB_WAKE_RTC,Indicates RTC wakeup cause. The RTC interrupt must be cleared before this bit can be cleared." "0,1"
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newline
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bitfld.long 0x0 29. "HIB_WAKE_CSV_BAK,Indicates CSV_BAK wakeup cause. The related fault must be handled before this bit can be cleared." "0,1"
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newline
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hexmask.long.tbyte 0x0 0.--23. 1. "HIB_WAKE_SRC,Each bit indicates a HIBERNATE wakeup cause. For each bit writing a 1 clears the cause flag."
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rgroup.long 0x1000++0x3
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line.long 0x0 "PWR_CTL,Power Mode Control"
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bitfld.long 0x0 5. "LPM_READY,Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES HIBERNATE wakeup or supply supervision reset wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless.." "0: If a low power circuit operation is requested,1: Normal operation"
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newline
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bitfld.long 0x0 4. "DEBUG_SESSION,Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)" "0: No debug session active,1: Debug session is active. Power modes behave.."
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newline
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bitfld.long 0x0 0.--1. "POWER_MODE,Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon." "0: System is resetting.,1: At least one CPU is running.,2: No CPUs are running. Peripherals may be running.,3: Main high-frequency clock is off; low speed.."
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group.long 0x1004++0x7
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line.long 0x0 "PWR_CTL2,Power Mode Control 2"
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bitfld.long 0x0 31. "PLL_LS_BYPASS,Bypass level shifter inside the PLL. Unused if no PLL is present in the product. Note that this only applies to PLL200M." "0: Do not bypass the level shifter,1: Bypass the level shifter"
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newline
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bitfld.long 0x0 30. "FREEZE_DPSLP,Controls whether mode and state of GPIOs and SIOs in the system are frozen. This is intended to be used as part of the DEEPSLEEP-RAM and DEEPSLEEP-OFF entry and exit sequences. It is set by HW while entering DEEPSLEEP-RAM and DEEPSLEEP-OFF.." "0,1"
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newline
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bitfld.long 0x0 28. "BGREF_LPMODE,Control the circuit-level power mode of the Bandgap Reference circuits for higher operating modes than DEEPSLEEP. This selects a second set of bandgap voltage and current generation circuits that are optimized for low current consumption." "0: Bandgap Reference uses the normal settings,1: Bandgap Reference uses the low power DeepSleep.."
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newline
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bitfld.long 0x0 27. "PORBOD_LPMODE,Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: POR/BOD circuits operate in normal mode,1: POR/BOD circuits operate in low power mode"
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newline
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bitfld.long 0x0 26. "REFI_LPMODE,Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Current reference generator operates in normal..,1: Current reference generator operates in low.."
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newline
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rbitfld.long 0x0 25. "REFI_OK,Indicates that the current reference is ready. Due to synchronization delays it may take two IMO clock cycles for hardware to clear this bit after asserting REFI_DIS=1." "0,1"
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newline
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bitfld.long 0x0 24. "REFI_DIS,N/A" "0,1"
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newline
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rbitfld.long 0x0 21. "REFVBUF_OK,Indicates that the voltage reference buffer is ready. Due to synchronization delays it may take two IMO clock cycles for hardware to clear this bit after asserting REFVBUF_DIS=1." "0,1"
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newline
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bitfld.long 0x0 20. "REFVBUF_DIS,Disable the voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS.." "0,1"
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newline
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rbitfld.long 0x0 17. "REFV_OK,Indicates that the normal mode of the voltage reference is ready." "0,1"
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newline
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bitfld.long 0x0 16. "REFV_DIS,N/A" "0,1"
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newline
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bitfld.long 0x0 12. "NWELL_REG_DIS,Explicitly disable the Nwell regulator. This register should normally be zero except for special sequences provided by Infineon to use a different regulator. This register is only reset by XRES HIBERNATE wakeup or supply supervision.." "0: Nwell Regulator is on,1: Nwell Regulator is explicitly disabled"
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newline
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bitfld.long 0x0 8. "RET_REG_DIS,Explicitly disable the Retention regulator. This field should normally be zero except for special sequences provided by Infineon to use a different regulator. This register is only reset by XRES HIBERNATE wakeup or supply supervision.." "0: Retention Regulator is not explicitly disabled,1: Retention Regulator is explicitly disabled"
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newline
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bitfld.long 0x0 4. "DPSLP_REG_DIS,Explicity disable the DeepSleep regulator including circuits shared with the Active Regulator. This register must not be set except as part of an Infineon-provided sequence or API. This register is only reset by XRES HIBERNATE wakeup .." "0: DeepSleep Regulator is not explicitly disabled,1: DeepSleep Regulator is explicitly disabled"
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newline
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bitfld.long 0x0 2. "LINREG_LPMODE,Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Linear Regulator operates in normal mode,1: Linear Regulator operates in low power mode"
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newline
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rbitfld.long 0x0 1. "LINREG_OK,Status of the linear Core Regulator." "0,1"
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newline
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bitfld.long 0x0 0. "LINREG_DIS,Explicitly disable the linear Core Regulator. Write zero for Traveo II devices. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Linear Core Regulator is not explicitly disabled,1: Linear Core Regulator is explicitly disabled"
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line.long 0x4 "PWR_HIBERNATE,HIBERNATE Mode Register"
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bitfld.long 0x4 31. "HIBERNATE,Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP. Both UNLOCK and FREEZE must have been set correctly in a previous.." "0,1"
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newline
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bitfld.long 0x4 30. "HIBERNATE_DISABLE,Hibernate disable bit." "0: Normal operation,1: Further writes to this register are ignored"
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newline
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bitfld.long 0x4 29. "SENSE_MODE,Power mode when wakeups are sensitive. The default of this field is 0 for software compatibility with other products. It is recommended to set this field to 1 for new/updated software." "0: Wakeups are sensitive only during HIBERNATE mode,1: Wakeups are sensitive in HIBERNATE and higher.."
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newline
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hexmask.long.byte 0x4 24.--27. 1. "MASK_HIBPIN,N/A"
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newline
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hexmask.long.byte 0x4 20.--23. 1. "POLARITY_HIBPIN,N/A"
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newline
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bitfld.long 0x4 19. "MASK_HIBWDT,N/A" "0,1"
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newline
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bitfld.long 0x4 18. "MASK_HIBALARM,N/A" "0,1"
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newline
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bitfld.long 0x4 17. "FREEZE,Controls whether mode and state of GPIOs and SIOs in the system are frozen. This is intended to be used as part of the HIBERNATE entry and exit sequences. When entering HIBERNATE mode the first write instructs DEEPSLEEP peripherals that they.." "0,1"
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newline
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hexmask.long.byte 0x4 8.--15. 1. "UNLOCK,This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect except as noted in the FREEZE description."
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TOKEN,Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register."
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group.long 0x1010++0xB
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line.long 0x0 "PWR_BUCK_CTL,Buck Control Register"
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bitfld.long 0x0 31. "BUCK_OUT1_EN,Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset. The regulator takes up to 600us to charge the external.." "0,1"
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newline
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bitfld.long 0x0 30. "BUCK_EN,Master enable for buck converter. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0,1"
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newline
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bitfld.long 0x0 0.--2. "BUCK_OUT1_SEL,Voltage output selection for vccbuck1 output. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset. When increasing the voltage it can take up to 200us for the output voltage to settle. When decreasing the.." "0: 0,1: 0,2: 0,3: 1,4: 1,5: 1,6: 1,7: 1"
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line.long 0x4 "PWR_BUCK_CTL2,Buck Control Register 2"
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bitfld.long 0x4 31. "BUCK_OUT2_EN,Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging this will increase the.." "0,1"
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newline
|
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bitfld.long 0x4 30. "BUCK_OUT2_HW_SEL,Hardware control for vccbuck2 output. When this bit is set the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware it can directly control the enable signal for vccbuck2." "0,1"
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newline
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bitfld.long 0x4 0.--2. "BUCK_OUT2_SEL,Voltage output selection for vccbuck2 output. When increasing the voltage it can take up to 200us for the output voltage to settle. When decreasing the voltage the settling time depends on the load current." "0: 1,1: 1,2: 1,3: 1,4: 1,5: 1,6: 1,7: 1"
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line.long 0x8 "PWR_SSV_CTL,Supply Supervision Control Register"
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bitfld.long 0x8 27. "OVDVCCD_ENABLE,Enable for OVD on vccd. This cannot be disabled during normal operation." "0,1"
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newline
|
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bitfld.long 0x8 24. "OVDVDDA_ENABLE,Enable for OVD on vdda." "0,1"
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|
newline
|
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bitfld.long 0x8 22.--23. "OVDVDDA_ACTION,Action taken when the OVD on vdda triggers." "0: No action,1: Generate a fault,2: Reset the chip,?"
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newline
|
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bitfld.long 0x8 20. "OVDVDDA_VSEL,Selects the voltage threshold for OVD on vdda. Ensure OVDVDDA_ENABLE==0 before changing this setting to prevent false triggers" "0: vddd>5,1: vddd>5"
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newline
|
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bitfld.long 0x8 19. "OVDVDDD_ENABLE,Enable for OVD on vddd. This cannot be disabled during normal operation." "0,1"
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|
newline
|
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bitfld.long 0x8 16. "OVDVDDD_VSEL,Selects the voltage threshold for OVD on vddd. The OVD does not reliably monitor the supply during the transition." "0: vddd>5,1: vddd>5"
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newline
|
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bitfld.long 0x8 11. "BODVCCD_ENABLE,Enable for BOD on vccd. This cannot be disabled during normal operation." "0,1"
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|
newline
|
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bitfld.long 0x8 8. "BODVDDA_ENABLE,Enable for BOD on vdda. BODVDDA_ACTION will be triggered when the BOD is disabled. If no action is desired when disabling firmware must first write BODVDDA_ACTION=NOTHING in a separate write cycle." "0,1"
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newline
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bitfld.long 0x8 6.--7. "BODVDDA_ACTION,Action taken when the BOD on vdda triggers." "0: No action,1: Generate a fault,2: Reset the chip,?"
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newline
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bitfld.long 0x8 4. "BODVDDA_VSEL,Selects the voltage threshold for BOD on vdda. Ensure BODVDDA_ENABLE==0 before changing this setting to prevent false triggers." "0: vdda<2,1: vdda<3"
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newline
|
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bitfld.long 0x8 3. "BODVDDD_ENABLE,Enable for BOD on vddd. This cannot be disabled during normal operation." "0,1"
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|
newline
|
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bitfld.long 0x8 0. "BODVDDD_VSEL,Selects the voltage threshold for BOD on vddd. The BOD does not reliably monitor the supply during the transition." "0: vddd<2,1: vddd<3"
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|
rgroup.long 0x101C++0x3
|
|
line.long 0x0 "PWR_SSV_STATUS,Supply Supervision Status Register"
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|
bitfld.long 0x0 17. "OCD_DPSLP_REG_OK,OCD indicates the current drawn from the linear DeepSleep Regulator is ok. This will always read 1 because a detected over-current condition will reset the chip." "0,1"
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|
newline
|
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bitfld.long 0x0 16. "OCD_ACT_LINREG_OK,OCD indicates the current drawn from the linear Active Regulator is ok. This will always read 1 because a detected over-current condition will reset the chip." "0,1"
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newline
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bitfld.long 0x0 10. "OVDVCCD_OK,OVD indicates vccd is ok. This will always read 1 because a detected over-over-voltage condition will reset the chip." "0,1"
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newline
|
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bitfld.long 0x0 9. "OVDVDDA_OK,OVD indicates vdda is ok." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "OVDVDDD_OK,OVD indicates vddd is ok. This will always read 1 because a detected over-voltage condition will reset the chip." "0,1"
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newline
|
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bitfld.long 0x0 2. "BODVCCD_OK,BOD indicates vccd is ok. This will always read 1 because a detected brownout will reset the chip." "0,1"
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newline
|
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bitfld.long 0x0 1. "BODVDDA_OK,BOD indicates vdda is ok." "0,1"
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newline
|
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bitfld.long 0x0 0. "BODVDDD_OK,BOD indicates vddd is ok. This will always read 1 because a detected brownout will reset the chip." "0,1"
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group.long 0x1020++0xB
|
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line.long 0x0 "PWR_LVD_CTL,High Voltage / Low Voltage Detector (HVLVD) Configuration Register"
|
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bitfld.long 0x0 18. "HVLVD1_ACTION,Action taken when the threshold is crossed in the programmed directions(s)" "0: Generate an interrupt,1: Generate a fault"
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|
newline
|
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bitfld.long 0x0 16.--17. "HVLVD1_EDGE_SEL,Sets which edge(s) will trigger an action when the threshold is crossed." "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
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newline
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bitfld.long 0x0 15. "HVLVD1_EN_HT,Enable HVLVD1 voltage monitor. This detector monitors vddd only. Do not change other HVLVD1 settings when enabled." "0,1"
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newline
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bitfld.long 0x0 14. "HVLVD1_DPSLP_EN_HT,Keep HVLVD1 voltage monitor enabled during DEEPSLEEP mode. This field is only used when HVLVD1_EN_HT==1." "0,1"
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newline
|
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hexmask.long.byte 0x0 8.--12. 1. "HVLVD1_TRIPSEL_HT,N/A"
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newline
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bitfld.long 0x0 7. "HVLVD1_EN,Enable HVLVD1 voltage monitor. HVLVD1 does not function during DEEPSLEEP but it automatically returns to its configured setting after DEEPSLEEP wakeup. Do not change other HVLVD1 settings when enabled." "0,1"
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newline
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bitfld.long 0x0 4.--6. "HVLVD1_SRCSEL,Source selection for HVLVD1" "0: Select VDDD,1: Select AMUXBUSA (VDDD branch),2: N/A,3: N/A,4: Select AMUXBUSB (VDDD branch),?,?,?"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HVLVD1_TRIPSEL,Threshold selection for HVLVD1. Disable the detector (HVLVD1_EN=0) before changing the threshold."
|
|
line.long 0x4 "PWR_LVD_CTL2,High Voltage / Low Voltage Detector (HVLVD) Configuration Register #2"
|
|
bitfld.long 0x4 18. "HVLVD2_ACTION,Action taken when the threshold is crossed in the programmed directions(s)" "0: Generate an interrupt,1: Generate a fault"
|
|
newline
|
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bitfld.long 0x4 16.--17. "HVLVD2_EDGE_SEL,Sets which edge(s) will trigger an action when the threshold is crossed." "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
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newline
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bitfld.long 0x4 15. "HVLVD2_EN_HT,Enable HVLVD2 voltage monitor. This detector monitors vddd only. Do not change other HVLVD2 settings when enabled." "0,1"
|
|
newline
|
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bitfld.long 0x4 14. "HVLVD2_DPSLP_EN_HT,Keep HVLVD2 voltage monitor enabled during DEEPSLEEP mode. This field is only used when HVLVD1_EN_HT==1." "0,1"
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newline
|
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hexmask.long.byte 0x4 8.--12. 1. "HVLVD2_TRIPSEL_HT,N/A"
|
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line.long 0x8 "PWR_REGHC_CTL,REGHC Control Register"
|
|
bitfld.long 0x8 31. "REGHC_CONFIGURED,Indicates the REGHC has been configured. This is used to know if REGHC should be enabled in response to a debug power up request. Do not change REGHC settings after this bit is set high." "0,1"
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newline
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bitfld.long 0x8 30. "REGHC_TRANS_USE_OCD,N/A" "0,1"
|
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newline
|
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hexmask.long.word 0x8 20.--29. 1. "REGHC_PMIC_STATUS_WAIT,Wait count in 4us steps after PMIC status ok. This is used by the hardware sequencer to allow additional settling time before disabling the internal regulator. The LSB is 32 IMO periods which results in a nominal LSB step of 4us."
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newline
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bitfld.long 0x8 19. "REGHC_PMIC_STATUS_POLARITY,The polarity used to trigger a reset action based on the PMIC status input. The reset system triggers a reset when the unmasked PMIC status matches this value." "0,1"
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newline
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bitfld.long 0x8 18. "REGHC_PMIC_STATUS_INEN,Input buffer enable for PMIC status input. Set this bit high to enable the input receiver." "0,1"
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newline
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bitfld.long 0x8 17. "REGHC_PMIC_CTL_POLARITY,Polarity used to enable the PMIC. The sequencer uses REGHC_PMIC_CTL_POLARITY to enable the PMIC and it uses the complement to disable the PMIC." "0,1"
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newline
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bitfld.long 0x8 16. "REGHC_PMIC_CTL_OUTEN,Output enable for PMIC enable pin. Set this bit high to enable the driver on this pin." "0,1"
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newline
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bitfld.long 0x8 12.--14. "REGHC_PMIC_RADJ,Reset voltage adjustment for PMIC as a factor (Vfbk/Vref) where Vfbk is the feedback voltage and Vref is the PMIC internal reference. The reset voltage adjustment circuit is enabled by the hardware sequencer if REGHC_PMIC_USE_RADJ=1." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x8 11. "REGHC_PMIC_USE_RADJ,Controls whether hardware sequencer enables reset voltage adjustment circuit when enabling a PMIC." "0,1"
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|
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bitfld.long 0x8 10. "REGHC_PMIC_USE_LINREG,For REGHC external PMIC mode controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd. When using this feature if the PMIC fails to keep vccd above the internal.." "0: Internal Active Linear Regulator disabled after..,1: Internal Active Linear Regulator kept enabled"
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|
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hexmask.long.byte 0x8 4.--8. 1. "REGHC_VADJ,Regulator output trim according to the formula vadj=(1.020V + REGHC_VADJ*0.005V). The default is 1.1V. For transistor mode REGHC will dynamically adjust DRV_VOUT so the supply targets the vadj voltage. For PMIC mode see REGHC_PMIC_DRV_VOUT."
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bitfld.long 0x8 2.--3. "REGHC_PMIC_DRV_VOUT,Setting for DRV_VOUT pin for PMIC mode. See REGHC_VADJ for calculation of vadj." "0,1,2,3"
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bitfld.long 0x8 0. "REGHC_MODE,REGHC control mode:" "0: external transistor connected,1: external PMIC connected"
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|
rgroup.long 0x102C++0x3
|
|
line.long 0x0 "PWR_REGHC_STATUS,REGHC Status Register"
|
|
bitfld.long 0x0 31. "REGHC_SEQ_BUSY,Indicates the REGHC enable/disable sequencer is busy transitioning to/from REGHC." "0: Sequencer is not busy,1: Sequencer is busy either enabling or disabling.."
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bitfld.long 0x0 12. "REGHC_PMIC_STATUS_OK,Indicates the PMIC status is ok. This includes polarity adjustment according to REGHC_PMIC_STATUS_POLARITY." "0: PMIC status is not ok or PMIC input buffer is..,1: PMIC status input buffer is enabled and.."
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|
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bitfld.long 0x0 9. "REGHC_OV_OUT,N/A" "0,1"
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newline
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bitfld.long 0x0 8. "REGHC_UV_OUT,N/A" "0,1"
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bitfld.long 0x0 2. "REGHC_CKT_OK,Indicates the REGHC circuit is enabled and operating. It does not indicate that the voltage and current are within required limits for robust operation." "0: REGHC circuit is not ready,1: REGHC circuit is enabled and operating"
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bitfld.long 0x0 1. "REGHC_OCD_OK,Indicates the over-current detector is operating and the current drawn from REGHC is within limits. OCD is only a choice for transistor mode and it is disabled for PMIC mode." "0: Current measurement exceeds limit or detector is..,1: Current measurement within limit"
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bitfld.long 0x0 0. "REGHC_ENABLED,Indicates the state of the REGHC enable/disable sequencer. This bit is only valid when REGHC_SEQ_BUSY==0." "0: REGHC sequencer indicates REGHC is disabled,1: REGHC sequencer indicates REGHC is enabled"
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group.long 0x1030++0x3
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line.long 0x0 "PWR_REGHC_CTL2,REGHC Control Register 2"
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|
bitfld.long 0x0 31. "REGHC_EN,Enable REGHC. This bit will not set if REGHC_CONFIGURED==0. Use PWR_REGHC_STATUS.ENABLED to know the actual status of REGHC. It will differ from this bit in the following cases:" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "REGHC_PMIC_STATUS_TIMEOUT,Timeout while waiting for REGHC_PMIC_STATUS_OK==1 when switching to PMIC."
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|
group.long 0x10C0++0x3
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|
line.long 0x0 "PWR_PMIC_CTL,PMIC Control Register"
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|
bitfld.long 0x0 31. "PMIC_CONFIGURED,Indicates the PMIC has been configured. This is used to know if PMIC should be enabled in response to a debug power up request. Do not change PMIC settings after this bit is set high." "0,1"
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|
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hexmask.long.word 0x0 20.--29. 1. "PMIC_STATUS_WAIT,Wait count in 4us steps after PMIC status ok. This is used by the hardware sequencer to allow additional settling time before disabling the internal regulator. The LSB is 32 IMO periods which results in a nominal LSB step of 4us."
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bitfld.long 0x0 19. "PMIC_STATUS_POLARITY,The polarity used to trigger a reset action based on the PMIC status input. The reset system triggers a reset when the unmasked PMIC status matches this value." "0,1"
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newline
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bitfld.long 0x0 18. "PMIC_STATUS_INEN,Input buffer enable for PMIC status input. Set this bit high to enable the input receiver." "0,1"
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bitfld.long 0x0 17. "PMIC_CTL_POLARITY,Polarity used to enable the PMIC. The sequencer uses PMIC_CTL_POLARITY to enable the PMIC and it uses the complement to disable the PMIC." "0,1"
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bitfld.long 0x0 16. "PMIC_CTL_OUTEN,Output enable for PMIC enable pin. Set this bit high to enable the driver on this pin." "0,1"
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bitfld.long 0x0 15. "PMIC_VADJ_BUF_EN,Analog buffer enable on voltage adjust output. Write this bit depending on the type of PMIC connected:" "0: Bypass buffer,1: Use analog buffer"
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bitfld.long 0x0 10. "PMIC_USE_LINREG,Controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd. When using this feature if the PMIC fails to keep vccd above the internal regulator target then the internal.." "0: Internal Active Linear Regulator disabled after..,1: Internal Active Linear Regulator kept enabled"
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hexmask.long.byte 0x0 4.--8. 1. "PMIC_VADJ,Voltage adjustment output setting. The lookup table in this field requires the proper setting in PMIC_VREF for the chosen PMIC. This field has no effect when PMIC_VREF selects no scaling. The feedback tap point is at a vccd pad inside the.."
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bitfld.long 0x0 2.--3. "PMIC_VREF,PMIC reference voltage setting. This selects the scaling factor used to generate the output voltage (vout) given the feedback voltage (vfb) for the chosen PMIC. For a PMIC that compares vfb to an internal reference voltage (vref) according to.." "0,1,2,3"
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rgroup.long 0x10C4++0x3
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line.long 0x0 "PWR_PMIC_STATUS,PMIC Status Register"
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bitfld.long 0x0 31. "PMIC_SEQ_BUSY,Indicates the PMIC enable/disable sequencer is busy transitioning to/from PMIC." "0: Sequencer is not busy,1: Sequencer is busy either enabling or disabling.."
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bitfld.long 0x0 12. "PMIC_STATUS_OK,Indicates the PMIC status is ok. This includes polarity adjustment according to PMIC_STATUS_POLARITY." "0: PMIC status is not ok or PMIC input buffer is..,1: PMIC status input buffer is enabled and.."
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bitfld.long 0x0 0. "PMIC_ENABLED,Indicates the state of the PMIC enable/disable sequencer. This bit is only valid when PMIC_SEQ_BUSY==0." "0: PMIC sequencer indicates PMIC is disabled,1: PMIC sequencer indicates PMIC is enabled"
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group.long 0x10C8++0x3
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line.long 0x0 "PWR_PMIC_CTL2,PMIC Control Register 2"
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bitfld.long 0x0 31. "PMIC_EN,Enable PMIC. This bit will not set if PMIC_CONFIGURED==0. Use PWR_PMIC_STATUS.ENABLED to know the actual status of PMIC. It will differ from this bit in the following cases:" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "PMIC_STATUS_TIMEOUT,Timeout while waiting for PMIC_STATUS_OK==1 when switching to PMIC."
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|
group.long 0x10D0++0x3
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line.long 0x0 "PWR_PMIC_CTL4,PMIC Control Register 4"
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bitfld.long 0x0 31. "PMIC_DPSLP,Configures PMIC behavior during DEEPSLEEP." "0: Device operates from internal regulators during..,1: DEEPSLEEP transition does not change PMIC enable"
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bitfld.long 0x0 30. "PMIC_VADJ_DIS,Disables the VADJ circuitry. This can be used to decrease current consumption if the entire feedback network is outside the device." "0: Device generates VADJ when PMIC is enabled,1: Device does not generate VADJ"
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repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
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|
group.long ($2+0x1200)++0x3
|
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line.long 0x0 "CLK_PATH_SELECT[$1],Clock Path Select Register"
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bitfld.long 0x0 0.--2. "PATH_MUX,Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch away.." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator,3: ALTHF - Alternate High-Frequency clock input..,4: DSI_MUX - Output of DSI mux for this path. Using..,5: LPECO - Low-Power External-Crystal Oscillator,6: IHO - Internal High-speed Oscillator,?"
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repeat.end
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repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
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|
group.long ($2+0x1240)++0x3
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line.long 0x0 "CLK_ROOT_SELECT[$1],Clock Root Select Register"
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bitfld.long 0x0 31. "ENABLE,Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0 which cannot be disabled." "0,1"
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newline
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hexmask.long.byte 0x0 8.--11. 1. "ROOT_DIV_INT,Selects predivider value for this clock root and DSI input. This divider is after DIRECT_MUX. For products with DSI the output of this mux is routed to DSI for use as a signal. For products with clock supervision the output of this mux.."
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newline
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bitfld.long 0x0 4.--5. "ROOT_DIV,Obsolete. Do not use in new designs." "0,1,2,3"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "ROOT_MUX,Selects a clock path for HFCLK<k> and SRSS DSI input <k>. The output of this mux goes to the direct mux (see CLK_DIRECT_SELECT). Use CLK_SELECT_PATH[i] to configure the desired path. The number of clock paths is product-specific and.."
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repeat.end
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repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
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|
group.long ($2+0x1280)++0x3
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line.long 0x0 "CLK_DIRECT_SELECT[$1],Clock Root Direct Select Register"
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bitfld.long 0x0 8. "DIRECT_MUX,Direct selection mux that allows IMO to bypass most of the clock mux structure. For products with multiple regulators this mux can be used to reduce current without requiring significant reconfiguration of the clocking network. The.." "0: Select IMO,1: Select ROOT_MUX selection"
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repeat.end
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tree "CSV_HF (Clock Supervisor (CSV) registers for Root clocks)"
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base ad:0x42201400
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repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x42201400 ad:0x42201410 ad:0x42201420 ad:0x42201430 ad:0x42201440 ad:0x42201450 ad:0x42201460)
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tree "CSV[$1]"
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base $2
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group.long ($2)++0xB
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line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
|
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bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
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bitfld.long 0x0 30. "CSV_ACTION,Specifies the action taken when an anomaly is detected on the monitored clock. CSV in DeepSleep domain always do a Fault report (which also wakes up the system)." "0: Generate a fault,1: Cause a power reset. This should only be used.."
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hexmask.long.word 0x0 0.--15. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable or DeepSleep wakeup from reference clock start to monitored clock start."
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line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
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hexmask.long.word 0x4 16.--31. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
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hexmask.long.word 0x4 0.--15. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
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line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
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hexmask.long.word 0x8 0.--15. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
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tree.end
|
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repeat.end
|
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tree.end
|
|
base ad:0x42200000
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newline
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group.long 0x1500++0x3
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newline
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line.long 0x0 "CLK_SELECT,Clock selection register"
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bitfld.long 0x0 15. "PUMP_ENABLE,Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings do the following:" "0,1"
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newline
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bitfld.long 0x0 12.--14. "PUMP_DIV,Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source." "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8,4: Divide selected clock source by 16,?,?,?"
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newline
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hexmask.long.byte 0x0 8.--11. 1. "PUMP_SEL,Selects clock PATH<k> where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined.."
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newline
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bitfld.long 0x0 0.--2. "LFCLK_SEL,Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK.." "0: ILO - Internal Low-speed Oscillator,1: WCO - Watch-Crystal Oscillator. Requires Backup..,2: ALTLF - Alternate Low-Frequency Clock.,3: PILO - Precision ILO if present.,4: ILO1 - Internal Low-speed Oscillator #1 if..,5: ECO_PRESCALER - External-Crystal Oscillator..,6: LPECO_PRESCALER - Low-Power External-Crystal..,?"
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group.long 0x1508++0x7
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line.long 0x0 "CLK_ILO0_CONFIG,ILO0 Configuration"
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bitfld.long 0x0 31. "ENABLE,Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register." "0,1"
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newline
|
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bitfld.long 0x0 30. "ILO0_MON_ENABLE,N/A" "0,1"
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newline
|
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bitfld.long 0x0 0. "ILO0_BACKUP,This register indicates that ILO0 should stay enabled during XRES and HIBERNATE modes. If backup voltage domain is implemented on the product this bit also indicates if ILO0 should stay enabled through power-related resets on other.." "0: ILO0 turns off during XRES,1: ILO0 stays enabled"
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line.long 0x4 "CLK_ILO1_CONFIG,ILO1 Configuration"
|
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bitfld.long 0x4 31. "ENABLE,Master enable for ILO1." "0,1"
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newline
|
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bitfld.long 0x4 30. "ILO1_MON_ENABLE,N/A" "0,1"
|
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group.long 0x1518++0xB
|
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line.long 0x0 "CLK_IMO_CONFIG,IMO Configuration"
|
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bitfld.long 0x0 31. "ENABLE,Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if DPSLP_ENABLE==0." "0,1"
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newline
|
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bitfld.long 0x0 30. "DPSLP_ENABLE,Enable for IMO during DEEPSLEEP. This bit configures IMO behavior during DEEPSLEEP:" "0: IMO is automatically disabled during DEEPSLEEP..,1: IMO is kept enabled throughout DEEPSLEEP"
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line.long 0x4 "CLK_ECO_CONFIG,ECO Configuration Register"
|
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bitfld.long 0x4 31. "ECO_EN,Master enable for ECO oscillator. Configure the settings in CLK_ECO_CONFIG2 to work with the selected crystal before enabling ECO." "0,1"
|
|
newline
|
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bitfld.long 0x4 28. "ECO_DIV_ENABLE,ECO prescaler enable command (mutually exclusive with ECO_DIV_DISABLE). ECO Prescaler only works in ACTIVE and SLEEP modes. SW sets this field to '1' to enable the divider and HW sets this field to '0' to indicate that divider enabling.." "0: Disable the divider using the ECO_DIV_DISABLE..,1: Configure CLK_ECO_PRESCALE registers"
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newline
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bitfld.long 0x4 27. "ECO_DIV_DISABLE,ECO prescaler disable command (mutually exclusive with ECO_DIV_ENABLE). SW sets this field to '1' and HW sets this field to '0'." "0,1"
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newline
|
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bitfld.long 0x4 1. "AGC_EN,Automatic Gain Control (AGC) enable. When set the oscillation amplitude is controlled to the level selected by CLK_ECO_CONFIG2.ATRIM. When low the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care.." "0,1"
|
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line.long 0x8 "CLK_ECO_PRESCALE,ECO Prescaler Configuration Register"
|
|
hexmask.long.word 0x8 16.--25. 1. "ECO_INT_DIV,10-bit integer value allows for ECO frequencies up to 33.55MHz. Subtract one from the desired divide value when writing this field. For example to divide by 1 write ECO_INT_DIV=0. Do not change this setting when ECO Prescaler is enabled."
|
|
newline
|
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hexmask.long.byte 0x8 8.--15. 1. "ECO_FRAC_DIV,8-bit fractional value sufficient to get prescaler output within the +/-65ppm calibration range. Do not change this setting when ECO Prescaler is enabled."
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newline
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rbitfld.long 0x8 0. "ECO_DIV_ENABLED,ECO prescaler enabled. HW sets this field to '1' as a result of an CLK_ECO_CONFIG.ECO_DIV_ENABLE command. HW sets this field to '0' as a result on a CLK_ECO_CONFIG.ECO_DIV_DISABLE command. ECO prescaler is incompatible with DEEPSLEEP.." "0,1"
|
|
rgroup.long 0x1524++0x3
|
|
line.long 0x0 "CLK_ECO_STATUS,ECO Status Register"
|
|
bitfld.long 0x0 1. "ECO_READY,Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled and it does not check the ECO output. It is recommended to also confirm ECO_OK==1." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "ECO_OK,Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec." "0,1"
|
|
group.long 0x1528++0x3
|
|
line.long 0x0 "CLK_PILO_CONFIG,Precision ILO Configuration Register"
|
|
bitfld.long 0x0 31. "PILO_EN,Enable PILO. If the PILO is the selected source for WDT writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register." "0,1"
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newline
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bitfld.long 0x0 16. "PILO_TCSC_EN,PILO second order temperature curvature correction enable. If the PILO is the selected source for WDT writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register." "0: Disable second order temperature curvature..,1: Enable second order temperature curvature.."
|
|
newline
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bitfld.long 0x0 0. "PILO_BACKUP,If backup domain is present on this product this register indicates that PILO should stay enabled for use by backup domain during XRES and HIBERNATE mode. If backup voltage domain is implemented on the product PILO should stay enabled.." "0: PILO turns off at XRES/BOD events,1: PILO remains on if backup domain is present and.."
|
|
group.long 0x1530++0x2B
|
|
line.long 0x0 "CLK_FLL_CONFIG,FLL Configuration Register"
|
|
bitfld.long 0x0 31. "FLL_ENABLE,Master enable for FLL. The FLL requires firmware sequencing when enabling and disabling. Hardware handles sequencing automatically when entering/exiting DEEPSLEEP." "0: Block is powered off,1: Block is powered on"
|
|
newline
|
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bitfld.long 0x0 24. "FLL_OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the FLL and do not change it while FLL is enabled." "0: no division,1: divide by 2"
|
|
newline
|
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hexmask.long.tbyte 0x0 0.--17. 1. "FLL_MULT,Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref)."
|
|
line.long 0x4 "CLK_FLL_CONFIG2,FLL Configuration Register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "UPDATE_TOL,Update tolerance sets the error threshold for when the FLL will update the CCO frequency settings. The update tolerance is the allowed difference between the count value for the ideal formula and the measured value. UPDATE_TOL should be less.."
|
|
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|
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hexmask.long.byte 0x4 16.--23. 1. "LOCK_TOL,Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or allow less accuracy. The tolerance is the allowed difference between the count.."
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|
newline
|
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hexmask.long.word 0x4 0.--12. 1. "FLL_REF_DIV,Control bits for reference divider. Set the divide value before enabling the FLL and do not change it while FLL is enabled."
|
|
line.long 0x8 "CLK_FLL_CONFIG3,FLL Configuration Register 3"
|
|
bitfld.long 0x8 28.--29. "BYPASS_SEL,Bypass mux located just after FLL output. This register can be written while the FLL is enabled. When changing BYPASS_SEL do not turn off the reference clock or CCO clock for five cycles (whichever is slower). Whenever BYPASS_SEL is.." "0: Automatic using lock indicator. When unlocked..,1: Similar to AUTO except the clock is gated off..,2: Select FLL reference input (bypass mode).,3: Select FLL output. Ignores lock indicator."
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|
newline
|
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hexmask.long.word 0x8 8.--20. 1. "SETTLING_COUNT,Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference.."
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|
newline
|
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hexmask.long.byte 0x8 4.--7. 1. "FLL_LF_PGAIN,FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN."
|
|
newline
|
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hexmask.long.byte 0x8 0.--3. 1. "FLL_LF_IGAIN,FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN."
|
|
line.long 0xC "CLK_FLL_CONFIG4,FLL Configuration Register 4"
|
|
bitfld.long 0xC 31. "CCO_ENABLE,Enable the CCO. It is required to enable the CCO before using the FLL." "0: Block is powered off,1: Block is powered on"
|
|
newline
|
|
bitfld.long 0xC 30. "CCO_HW_UPDATE_DIS,Disable CCO frequency update by FLL hardware" "0: Hardware update of CCO settings is allowed,1: Hardware update of CCO settings is disabled"
|
|
newline
|
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hexmask.long.word 0xC 16.--24. 1. "CCO_FREQ,CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range."
|
|
newline
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bitfld.long 0xC 8.--10. "CCO_RANGE,Frequency range of CCO" "0: Target frequency is in range [48 64) MHz,1: Target frequency is in range [64 85) MHz,2: Target frequency is in range [85 113) MHz,3: Target frequency is in range [113 150) MHz,4: Target frequency is in range [150 200] MHz,?,?,?"
|
|
newline
|
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hexmask.long.byte 0xC 0.--7. 1. "CCO_LIMIT,Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)"
|
|
line.long 0x10 "CLK_FLL_STATUS,FLL Status Register"
|
|
rbitfld.long 0x10 2. "CCO_READY,This indicates that the CCO is internally settled and ready to use." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "UNLOCK_OCCURRED,This bit sets whenever the FLL is enabled and goes out of lock. This bit stays set until cleared by firmware." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 0. "LOCKED,FLL Lock Indicator" "0,1"
|
|
line.long 0x14 "CLK_ECO_CONFIG2,ECO Configuration Register 2"
|
|
bitfld.long 0x14 12.--14. "GTRIM,Gain Trim - Startup time." "0,1,2,3,4,5,6,7"
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|
newline
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|
bitfld.long 0x14 10.--11. "RTRIM,Feedback resistor Trim" "0,1,2,3"
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|
newline
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|
bitfld.long 0x14 8.--9. "FTRIM,Filter Trim - 3rd harmonic oscillation" "0,1,2,3"
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|
newline
|
|
hexmask.long.byte 0x14 4.--7. 1. "ATRIM,Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal."
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|
newline
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|
bitfld.long 0x14 0.--2. "WDTRIM,Watch Dog Trim - Delta voltage below steady state level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CLK_ILO_CONFIG,ILO Configuration"
|
|
bitfld.long 0x18 31. "ENABLE,Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling it takes at most two cycles to reach the accuracy spec." "0,1"
|
|
newline
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|
bitfld.long 0x18 0. "ILO_BACKUP,If backup domain is present on this product this register indicates that ILO should stay enabled for use by backup domain during XRES HIBERNATE mode and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored.." "0: ILO turns off at XRES/BOD event or HIBERNATE entry,1: ILO remains on if backup domain is present and.."
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|
line.long 0x1C "CLK_TRIM_ILO_CTL,ILO Trim Register"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "ILO_FTRIM,IL0 frequency trims. LSB step size is 1.5 percent (typical) of the frequency."
|
|
line.long 0x20 "CLK_TRIM_ILO0_CTL,ILO0 Trim Register"
|
|
hexmask.long.byte 0x20 8.--11. 1. "ILO0_MONTRIM,ILO0 internal monitor trim."
|
|
newline
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|
hexmask.long.byte 0x20 0.--5. 1. "ILO0_FTRIM,ILO0 frequency trims. LSB step size is 1.5 percent (typical) of the frequency."
|
|
line.long 0x24 "CLK_MF_SELECT,Medium Frequency Clock Select Register"
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|
bitfld.long 0x24 31. "ENABLE,Enable for MFCLK (clk_mf). When disabling clk_mf do not disable the source until after 5 clk_mf periods. clk_mf continues to operate in DEEPSLEEP for compatible sources. Firmware must disable clk_mf before entering DEEPSLEEP if the source is.." "0,1"
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|
newline
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|
hexmask.long.byte 0x24 8.--15. 1. "MFCLK_DIV,Divide selected clock source by (1+MFCLK_DIV). The output of this divider is MFCLK (clk_mf). Allows for integer divisions in the range [1 256]. Do not change this setting while ENABLE==1."
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|
newline
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bitfld.long 0x24 0.--2. "MFCLK_SEL,Select source for MFCLK (clk_mf). Note that not all products support all clock sources. Selecting a clock source that is not supported results in undefined behavior." "0: MFO - Medium Frequency Oscillator. DEEPSLEEP..,1: ILO - Internal Low-speed Oscillator.,2: WCO - Watch-Crystal Oscillator if present.,3: ALTLF - Alternate Low-Frequency Clock.,4: PILO - Precision ILO if present.,5: ILO1 - Internal Low-speed Oscillator #1 if..,6: ECO_PRESCALER - External-Crystal Oscillator if..,7: LPECO - Low Power External Crystal Oscillator if.."
|
|
line.long 0x28 "CLK_MFO_CONFIG,MFO Configuration Register"
|
|
bitfld.long 0x28 31. "ENABLE,Enable for Medium Frequency Oscillator (MFO) to generate clk_mf. It is product-specific whether this is a separate component or implemented as a divided version of another clock (eg. IMO)." "0,1"
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|
newline
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bitfld.long 0x28 30. "DPSLP_ENABLE,Enable for MFO during DEEPSLEEP. This bit is ignored when ENABLE==0. When ENABLE==1:" "0: MFO is automatically disabled during DEEPSLEEP..,1: MFO is kept enabled throughout DEEPSLEEP"
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|
group.long 0x1560++0x7
|
|
line.long 0x0 "CLK_IHO_CONFIG,IHO Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable for Internal High-speed Oscillator (IHO) to generate clk_iho." "0,1"
|
|
line.long 0x4 "CLK_ALTHF_CTL,Alternate High Frequency Clock Control Register"
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|
bitfld.long 0x4 31. "ALTHF_ENABLE,Enable for ALTHF clock when used by SRSS. There may be independent control of ALTHF by another subsystem and this bit prevents ALTHF from being disabled when SRSS needs it. SRSS automatically removes its enable request during DEEPSLEEP.." "0,1"
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|
newline
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rbitfld.long 0x4 0. "ALTHF_ENABLED,Indicates that ALTHF is actually enabled. The delay between a transition on ALTHF_ENABLE and ALTHF_ENABLED is product specific." "0,1"
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|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1600)++0x3
|
|
line.long 0x0 "CLK_PLL_CONFIG[$1],PLL Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for PLL. Setup FEEDBACK_DIV REFERENCE_DIV and OUTPUT_DIV at least one cycle before setting ENABLE=1." "0: Block is disabled,1: Block is enabled"
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|
newline
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bitfld.long 0x0 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL do not turn off the reference clock or PLL clock for five cycles (whichever is slower)." "0: Automatic using lock indicator. When unlocked..,1: Similar to AUTO except the clock is gated off..,2: Select PLL reference input (bypass mode).,3: Select PLL output. Ignores lock indicator. If.."
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newline
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bitfld.long 0x0 27. "PLL_LF_MODE,VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled." "0: VCO frequency is [200MHz,1: VCO frequency is [170MHz"
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|
newline
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bitfld.long 0x0 25.--26. "LOCK_DELAY,N/A" "0,1,2,3"
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|
newline
|
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hexmask.long.byte 0x0 16.--20. 1. "OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
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|
newline
|
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hexmask.long.byte 0x0 8.--12. 1. "REFERENCE_DIV,Control bits for reference divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
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|
newline
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hexmask.long.byte 0x0 0.--6. 1. "FEEDBACK_DIV,Control bits for feedback divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
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|
repeat.end
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1640)++0x3
|
|
line.long 0x0 "CLK_PLL_STATUS[$1],PLL Status Register"
|
|
bitfld.long 0x0 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware." "0,1"
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|
newline
|
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rbitfld.long 0x0 0. "LOCKED,PLL Lock Indicator" "0,1"
|
|
repeat.end
|
|
group.long 0x1700++0x3
|
|
line.long 0x0 "CSV_REF_SEL,Select CSV Reference clock for Active domain"
|
|
bitfld.long 0x0 0.--2. "REF_MUX,Selects a source for clock clk_ref_hf. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch.." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator,3: ALTHF - Alternate High-Frequency clock input..,4: IHO - Internal High-speed Oscillator,?,?,?"
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|
tree "CSV_ILO (CSV registers for ILO clock)"
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|
base ad:0x42201730
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tree "CSV (HVILO clock DeepSleep domain Clock Supervisor registers)"
|
|
group.long 0x0++0xB
|
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line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable from reference clock start to monitored clock start."
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|
line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
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|
hexmask.long.byte 0x4 16.--23. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
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|
hexmask.long.byte 0x4 0.--7. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
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|
line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
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|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
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|
tree.end
|
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tree.end
|
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tree "CSV_LF (CSV registers for LF clock)"
|
|
base ad:0x42201720
|
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tree "CSV (LF clock Clock Supervisor registers)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
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|
hexmask.long.byte 0x0 0.--7. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable from reference clock start to monitored clock start."
|
|
line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
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hexmask.long.byte 0x4 16.--23. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
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hexmask.long.byte 0x4 0.--7. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
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line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
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hexmask.long.byte 0x8 0.--7. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
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|
tree.end
|
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tree.end
|
|
tree "CSV_REF (CSV registers for the CSV Reference clock)"
|
|
base ad:0x42201710
|
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tree "CSV (Active domain Clock Supervisor (CSV) registers for CSV Reference clock)"
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group.long 0x0++0xB
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line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
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bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
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bitfld.long 0x0 30. "CSV_ACTION,Specifies the action taken when an anomaly is detected on the monitored clock. CSV in DeepSleep domain always do a Fault report (which also wakes up the system)." "0: Generate a fault,1: Cause a power reset. This should only be used.."
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hexmask.long.word 0x0 0.--15. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable or DeepSleep wakeup from reference clock start to monitored clock start."
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line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
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hexmask.long.word 0x4 16.--31. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
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hexmask.long.word 0x4 0.--15. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
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|
line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
|
|
tree.end
|
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tree.end
|
|
base ad:0x42200000
|
|
newline
|
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group.long 0x1800++0xB
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newline
|
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line.long 0x0 "RES_CAUSE,Reset Cause Observation Register"
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bitfld.long 0x0 8. "RESET_MCWDT3,Multi-Counter Watchdog timer reset #3. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). This bit is only valid when parameter NUM_MCWDT>3" "0,1"
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newline
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bitfld.long 0x0 7. "RESET_MCWDT2,Multi-Counter Watchdog timer reset #2. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). This bit is only valid when parameter NUM_MCWDT>2" "0,1"
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newline
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bitfld.long 0x0 6. "RESET_MCWDT1,Multi-Counter Watchdog timer reset #1. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). This bit is only valid when parameter NUM_MCWDT>1" "0,1"
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newline
|
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bitfld.long 0x0 5. "RESET_MCWDT0,Multi-Counter Watchdog timer reset #0. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). This bit is only valid when parameter NUM_MCWDT>0" "0,1"
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newline
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bitfld.long 0x0 4. "RESET_SOFT,A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
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newline
|
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bitfld.long 0x0 3. "RESET_TC_DBGRESET,Test controller or debugger asserted reset. Only resets debug domain. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "RESET_DPSLP_FAULT,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "RESET_ACT_FAULT,N/A" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "RESET_WDT,A basic WatchDog Timer (WDT) reset has occurred since last power cycle. ULP products: This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
line.long 0x4 "RES_CAUSE2,Reset Cause Observation Register 2"
|
|
bitfld.long 0x4 16. "RESET_CSV_REF,Clock supervision logic requested a reset due to loss or frequency violation of the reference clock source that is used to monitor the other HF clock sources. This bit is only valid when parameter CSV_PRESENT is set." "0,1"
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|
newline
|
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hexmask.long.word 0x4 0.--15. 1. "RESET_CSV_HF,Clock supervision logic requested a reset due to loss or frequency violation of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero. Each bit is only valid when the corresponding bit in.."
|
|
line.long 0x8 "RES_CAUSE_EXTEND,Extended Reset Cause Observation Register"
|
|
bitfld.long 0x8 30. "RESET_PORVDDD,Indicator that a POR occurred. This is a high-voltage cause bit and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "RESET_STRUCT_XRES,Structural reset was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits." "0,1"
|
|
newline
|
|
bitfld.long 0x8 28. "RESET_PXRES,PXRES triggered. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits." "0,1"
|
|
newline
|
|
bitfld.long 0x8 26. "RESET_PMIC,PMIC status triggered a reset. If PMIC control is not present hardware will never set this bit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "RESET_OCD_REGHC,Overcurrent detection from REGHC (if present). If REGHC is not present hardware will never set this bit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "RESET_OCD_DPSLP_LINREG,Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "RESET_OCD_ACT_LINREG,Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "RESET_OVDVCCD,Overvoltage detection on the internal core VCCD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR." "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "RESET_OVDVDDA,Overvoltage detection on the external VDDA supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "RESET_OVDVDDD,Overvoltage detection on the external VDDD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR." "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "RESET_BODVCCD,Internal VCCD core supply crossed the brown-out limit. Note that this detector will detect gross issues with the internal core supply but may not catch all brown-out conditions. Functional and timing supervision (CSV WDT) is provided to.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "RESET_BODVDDA,External VDDA supply crossed the brown-out limit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "RESET_BODVDDD,External VDDD supply crossed brown-out limit. Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit. Below this limit it is not possible to reliably retain.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "RESET_XRES,External XRES pin was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits." "0,1"
|
|
wgroup.long 0x1814++0x3
|
|
line.long 0x0 "RES_PXRES_CTL,Programmable XRES Control Register"
|
|
bitfld.long 0x0 0. "PXRES_TRIGGER,Triggers PXRES. This causes a full-scope reset and reboot." "0,1"
|
|
repeat 2. (list 0x0 0x1)(list ad:0x42201A00 ad:0x42201A20)
|
|
tree "CLK_DPLL_LP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "CONFIG,DPLL_LP Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for PLL. Setup FEEDBACK_DIV REFERENCE_DIV and OUTPUT_DIV at least one cycle before setting ENABLE=1." "0: Block is disabled,1: Block is enabled"
|
|
bitfld.long 0x0 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL do not turn off the reference clock or PLL clock for five cycles (whichever is slower)." "0: Automatic using lock indicator. When unlocked..,1: Similar to AUTO except the clock is gated off..,2: Select PLL reference input (bypass mode).,3: Select PLL output. Ignores lock indicator. If.."
|
|
newline
|
|
bitfld.long 0x0 27. "PLL_DCO_CODE_MULT,DCO code coefficient during SAR operation; this trim bit is Fpfd frequency dependent" "0: multilply by 16,1: mulitply by 28"
|
|
hexmask.long.byte 0x0 16.--20. 1. "OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "REFERENCE_DIV,Control bits for reference divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
hexmask.long.byte 0x0 0.--7. 1. "FEEDBACK_DIV,Control bits for feedback divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
line.long 0x4 "CONFIG2,DPLL_LP Configuration Register 2"
|
|
bitfld.long 0x4 31. "FRAC_EN,Enables fractional division mode." "0,1"
|
|
bitfld.long 0x4 28.--30. "FRAC_DITHER_EN,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "FRAC_DIV,Control bits for fractional divider. This value is interpreted as a fraction of the PFD frequency i.e. fPFD * (FRAC_DIV/2^24). This field can be dynamically updated within the 1000ppm control limit. It takes up to 115 AHB cycles to transfer.."
|
|
line.long 0x8 "CONFIG3,DPLL_LP Configuration Register 3"
|
|
bitfld.long 0x8 31. "SSCG_EN,Enables spreading mode." "0,1"
|
|
bitfld.long 0x8 28. "SSCG_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "SSCG_DITHER_EN,N/A" "0,1"
|
|
bitfld.long 0x8 16.--18. "SSCG_RATE,N/A" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "SSCG_DEPTH,N/A"
|
|
line.long 0xC "CONFIG4,DPLL_LP Configuration Register 4"
|
|
bitfld.long 0xC 24. "ACC_CNT_LOCK,Control signal for switching to stable filter coefficients (PLL_KP_TRIM/PLL_KI_TRIM)" "0: PLL_ACC_PHASE_CNT_DONE,1: PLL_LOCK"
|
|
bitfld.long 0xC 20.--21. "PLL_TG,This value is a number of PFD clocks in relation to the DCO count. Can change the number of counts set by p_div in integer mode by the values of -1 +1 or +2." "0: 0,1: -1,2: +1,3: +2"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "TDC_MODE,N/A" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "ACC_MODE,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0xC 0.--10. 1. "DCO_CODE,Initial DCO code. It is recommended to leave this at the default setting. This setting only has effect in open loop mode. See DPLL BROS regarding test modes."
|
|
line.long 0x10 "CONFIG5,DPLL_LP Configuration Register 5"
|
|
hexmask.long.byte 0x10 24.--30. 1. "KP_ACC_INT,Gain of P/I loop filter integrator path during cold start for INT operation. Gain coefficient is 2^KP eg. 0=>1 15=>32768."
|
|
hexmask.long.byte 0x10 16.--22. 1. "KI_ACC_INT,Gain of P/I loop filter integrator path during cold start for INT operation. Gain coefficient is 2^KI eg. 0=>1 15=>32768."
|
|
newline
|
|
hexmask.long.byte 0x10 8.--14. 1. "KP_INT,Gain of P/I loop filter integrator path for INT operation. Gain coefficient is 2^KP eg. 0=>1 15=>32768."
|
|
hexmask.long.byte 0x10 0.--6. 1. "KI_INT,Gain of P/I loop filter integrator path for INT operation. Gain coefficient is 2^KI eg. 0=>1 15=>32768."
|
|
line.long 0x14 "CONFIG6,DPLL_LP Configuration Register 6"
|
|
hexmask.long.byte 0x14 24.--30. 1. "KP_ACC_FRACT,Gain of P/I loop filter integrator path during cold start for FRACT operation. Gain coefficient is 2^KP eg. 0=>1 15=>32768."
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hexmask.long.byte 0x14 16.--22. 1. "KI_ACC_FRACT,Gain of P/I loop filter integrator path during cold start for FRACT operation. Gain coefficient is 2^KI eg. 0=>1 15=>32768."
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|
newline
|
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hexmask.long.byte 0x14 8.--14. 1. "KP_FRACT,Gain of P/I loop filter proportional path for FRACT operation. Gain coefficient is 2^KP eg. 0=>1 15=>32768."
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|
hexmask.long.byte 0x14 0.--6. 1. "KI_FRACT,Gain of P/I loop filter proportional path for FRACT operation. Gain coefficient is 2^KI eg. 0=>1 15=>32768."
|
|
line.long 0x18 "CONFIG7,DPLL_LP Configuration Register 7"
|
|
hexmask.long.byte 0x18 24.--30. 1. "KP_ACC_SSCG,Gain of P/I loop filter integrator path during cold start for SSCG operation. Gain coefficient is 2^KP eg. 0=>1 15=>32768."
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|
hexmask.long.byte 0x18 16.--22. 1. "KI_ACC_SSCG,Gain of P/I loop filter integrator path during cold start for SSCG operation. Gain coefficient is 2^KI eg. 0=>1 15=>32768."
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|
newline
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hexmask.long.byte 0x18 8.--14. 1. "KP_SSCG,Gain of P/I loop filter proportional path for SSCG operation. Gain coefficient is 2^KP eg. 0=>1 15=>32768."
|
|
hexmask.long.byte 0x18 0.--6. 1. "KI_SSCG,Gain of P/I loop filter proportional path for SSCG operation. Gain coefficient is 2^KI eg. 0=>1 15=>32768."
|
|
line.long 0x1C "STATUS,DPLL_LP Status Register"
|
|
bitfld.long 0x1C 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware." "0,1"
|
|
rbitfld.long 0x1C 0. "LOCKED,PLL Lock Indicator" "0,1"
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|
tree.end
|
|
repeat.end
|
|
base ad:0x42200000
|
|
newline
|
|
group.long 0x1C00++0xB
|
|
line.long 0x0 "PWR_CBUCK_CTL,Core Buck Control Register"
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|
hexmask.long.byte 0x0 8.--12. 1. "CBUCK_MODE,CBUCK mode. Low ripple (high power) modes are intended for analog that needs low ripple. Low power mode is suitable for digital processing."
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|
newline
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hexmask.long.byte 0x0 0.--4. 1. "CBUCK_VSEL,Voltage output selection. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset. The actual CBUCK voltage is the maximum of this setting the settings for all enabled step-down regulators (see PWR_SDR*_CTL) and.."
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|
line.long 0x4 "PWR_CBUCK_CTL2,Core Buck Control Register 2"
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bitfld.long 0x4 31. "CBUCK_USE_SETTINGS,Causes the settings in PWR_CBUCK_CTL register to be included in the CBUCK setting decision. Can be used to override the normal hardware voltage behavior. Regardless of this bit the extra settings in PWR_CBUCK_CTL register are not.." "0,1"
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newline
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bitfld.long 0x4 30. "CBUCK_COPY_SETTINGS,Copies the current CBUCK composite state to the fields in PWR_CBUCK_CTL register (CBUCK_VSEL and CBUCK_MODE). It is recommended to pause transitions using CBUCK_PAUSE to ensure the state does not change near the copy. After it is.." "0: no change,1: copy settings"
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newline
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bitfld.long 0x4 29. "CBUCK_PAUSE,Pauses new dynamic CBUCK transitions. An already started transition will complete but new dynamic transitions are paused. This can be used as part of a firmware sequence to change the voltage setting of an enabled stepdown regulator." "0,1"
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newline
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bitfld.long 0x4 28. "CBUCK_OVERRIDE,Forces the CBUCK to use the settings in PWR_CBUCK_CTL register ignoring the other hardware requests. This can be used as part of a firmware algorithm to change the voltage of an enabled stepdown regulator. This bit is cleared by any.." "0,1"
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|
line.long 0x8 "PWR_CBUCK_CTL3,Core Buck Control Register 3"
|
|
bitfld.long 0x8 31. "CBUCK_INRUSH_SEL,CBUCK inrush limit selection." "0: 10mA limit,1: 100mA limit"
|
|
rgroup.long 0x1C0C++0x3
|
|
line.long 0x0 "PWR_CBUCK_STATUS,Core Buck Status Register"
|
|
bitfld.long 0x0 31. "PMU_DONE,Indicates the power management unit is finished with a transition." "0: PMU busy,1: PMU done"
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|
group.long 0x1C10++0x7
|
|
line.long 0x0 "PWR_SDR0_CTL,Step Down Regulator 0 Control Register"
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|
bitfld.long 0x0 31. "SDR0_ALLOW_BYPASS,SDR0 bypass control." "0: Force SDR0 to regulate,1: Allow SDR0 to bypass if the actual CBUCK voltage.."
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|
newline
|
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hexmask.long.byte 0x0 26.--29. 1. "SDR0_DPSLP_VSEL,SDR0 output voltage during DeepSleep. (See SDR0_VSEL for voltage table)."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SDR0_VSEL,SDR0 output voltage."
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|
newline
|
|
hexmask.long.byte 0x0 15.--19. 1. "SDR0_CBUCK_DPSLP_MODE,DeepSleep CBUCK mode when using SDR0 (see PWR_CBUCK_CTL for mode table)."
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|
newline
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hexmask.long.byte 0x0 10.--14. 1. "SDR0_CBUCK_DPSLP_VSEL,DeepSleep voltage selection of CBUCK (see PWR_CBUCK_CTL for voltage table). The voltage must be 60mV higher than the SDR output or the regulator output may bypass."
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newline
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hexmask.long.byte 0x0 5.--9. 1. "SDR0_CBUCK_MODE,Minimum CBUCK mode when using SDR0 (see PWR_CBUCK_CTL for mode table)."
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newline
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hexmask.long.byte 0x0 0.--4. 1. "SDR0_CBUCK_VSEL,Minimum voltage selection of CBUCK when using this SDR0 (see PWR_CBUCK_CTL for voltage table). The voltage must be 60mV higher than the SDR output or the regulator output may bypass."
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|
line.long 0x4 "PWR_SDR1_CTL,Step Down Regulator 1 Control Register"
|
|
bitfld.long 0x4 31. "SDR1_ENABLE,Enable for SDR1." "0,1"
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|
newline
|
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bitfld.long 0x4 30. "SDR1_HW_SEL,Selects hardware control for SDR1." "0: SDR1_ENABLE controls SDR1,1: SDR1_ENABLE is ignored and a hardware signal is.."
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|
newline
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hexmask.long.byte 0x4 16.--19. 1. "SDR1_VSEL,SDR1 output voltage."
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|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "SDR1_CBUCK_MODE,Minimum CBUCK mode when using SDR1 (see PWR_CBUCK_CTL for mode table)."
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|
newline
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hexmask.long.byte 0x4 0.--4. 1. "SDR1_CBUCK_VSEL,Minimum voltage selection of CBUCK when using this SDR1 (see PWR_CBUCK_CTL for voltage table). The voltage must be 60mV higher than the SDR output or the regulator output may bypass."
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|
group.long 0x1C30++0x3
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|
line.long 0x0 "PWR_HVLDO0_CTL,HVLDO0 Control Register"
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|
bitfld.long 0x0 31. "HVLDO0_ENABLE,HVLDO0 enable" "0,1"
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|
newline
|
|
bitfld.long 0x0 30. "HVLDO0_HW_SEL,Selects hardware control for HVLDO0." "0: HVLDO0_ENABLE controls SDR1,1: HVLDO0_ENABLE is ignored and a hardware signal.."
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|
newline
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hexmask.long.byte 0x0 0.--3. 1. "HVLDO0_VSEL,HVLDO0 output voltage."
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|
group.long 0x2054++0x3
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|
line.long 0x0 "TST_XRES_SECURE,SECURE TEST and FIRMWARE TEST Key control register"
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bitfld.long 0x0 31. "SECURE_DISABLE,Disables the SECURE TEST key entry capability until next reset. Must not be set in the same write when any of the above *_WR bits are set or toggling." "0,1"
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newline
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rbitfld.long 0x0 30. "SECURE_KEY_OK,Indicates that the 32-bit SECURE TEST key is observing the correct key. Secure key is not reset but it will establish low after a deep power cycle that causes it to lose its written state." "0,1"
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newline
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rbitfld.long 0x0 29. "FW_KEY_OK,Indicates that the 32-bit FIRMWARE TEST key is observing the correct key. Firmware key is reset by (A)XRES and STRUCT_XRES." "0,1"
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newline
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hexmask.long.byte 0x0 16.--19. 1. "SECURE_WR,Latch enables for each of the 4 bytes in the 32-bit SECURE TEST key. Must be toggled high and then low while keeping DATA8 to the correct value."
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newline
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hexmask.long.byte 0x0 8.--11. 1. "FW_WR,Latch enables for each of the 4 bytes in the 32-bit FIRMWARE TEST key. Must be toggled high and then low while keeping DATA8 to the correct value."
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|
newline
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hexmask.long.byte 0x0 0.--7. 1. "DATA8,Data byte to be set into either SECURE TEST or FIRMWARE TEST key. Must not be changed in the same write that is toggling any of the *_WR bits below "
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group.long 0x20AC++0x3
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|
line.long 0x0 "PWR_TRIM_CBUCK_CTL,CBUCK Trim Register"
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|
hexmask.long.byte 0x0 8.--12. 1. "CBUCK_DPSLP_MODE,The CBUCK mode setting to use during DEEPSLEEP."
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|
newline
|
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hexmask.long.byte 0x0 0.--4. 1. "CBUCK_DPSLP_VSEL,The CBUCK voltage setting to use during DEEPSLEEP."
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|
group.long 0x20E0++0x7
|
|
line.long 0x0 "PWR_TRIM_PWRSYS_CTL,Power System Trim Register"
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|
bitfld.long 0x0 30.--31. "ACT_REG_BOOST,Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation but an application may limit its maximum current to less than that." "0,1,2,3"
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|
newline
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hexmask.long.byte 0x0 0.--4. 1. "ACT_REG_TRIM,Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset. The nominal output voltage is vccd=850mV + ACT_REG_TRIM*12.5mV. The actual output.."
|
|
line.long 0x4 "PWR_TRIM_PWRSYS_CTL2,Power System Trim Register 2"
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|
bitfld.long 0x4 24.--26. "RET_REG_ACT_TRIM,Trim for the Retention-Regulator (if present) applied during (LP)ACTIVE/(LP)SLEEP modes. These are expected to be constant but provided as registers for risk mitigation. This register is only reset by XRES HIBERNATE wakeup or supply.." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4 20.--22. "DPSLP_REG_ACT_TRIM,Trim for the DeepSleep-Regulator applied during (LP)ACTIVE/(LP)SLEEP modes. These are expected to be constant but provided as registers for risk mitigation. This register is only reset by XRES HIBERNATE wakeup or supply supervision.." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4 16.--18. "NWELL_REG_TRIM,Trim for the Nwell-Regulator (if present) applied during DEEPSLEEP mode. Nwell trim is always forced to zero during (LP)ACTIVE/(LP)SLEEP modes. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x4 12.--14. "RET_REG_TRIM,Trim for the Retention-Regulator (if present) applied during DEEPSLEEP mode. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4 8.--10. "DPSLP_REG_TRIM,Trim for the DeepSleep-Regulator applied during DEEPSLEEP mode. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: 0,1: 0,2: 0,3: 0,4: 0,5: 1,6: 1,7: 1"
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group.long 0x301C++0x3
|
|
line.long 0x0 "CLK_TRIM_ECO_CTL,ECO Trim Register"
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|
hexmask.long.byte 0x0 16.--21. 1. "ITRIM,Current Trim"
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|
group.long 0x3220++0x3
|
|
line.long 0x0 "CLK_TRIM_ILO1_CTL,ILO1 Trim Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "ILO1_MONTRIM,ILO1 internal monitor trim."
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|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "ILO1_FTRIM,ILO1 frequency trims. LSB step size is 1.5 percent (typical) of the frequency."
|
|
tree "RAM_TRIM (SRAM Trim registers)"
|
|
base ad:0x42204000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TRIM_RAM_CTL,Trim Register for RAM Type 0"
|
|
hexmask.long 0x0 0.--31. 1. "TRIM,N/A"
|
|
line.long 0x4 "TRIM_ROM_CTL,Trim Register for ROM"
|
|
hexmask.long 0x4 0.--31. 1. "TRIM,N/A"
|
|
tree.end
|
|
repeat 2. (list 0x0 0x1)(list ad:0x42204200 ad:0x42204220)
|
|
tree "CLK_TRIM_DPLL_LP[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "DPLL_LP_CTL,DPLL LP Trim Register"
|
|
bitfld.long 0x0 31. "ENABLE_CNT,Enable for the PLL hardware sequencer." "0: Disables the hardware sequencer,1: Enables the hardware sequencer"
|
|
hexmask.long.byte 0x0 24.--29. 1. "ISOLATE_CNT,Terminal count for the stabilization counter handles PLL_ISOLATE_N"
|
|
newline
|
|
bitfld.long 0x0 23. "ISOLATE_N,Manual isolation control for PLL . This field is ignored when ENABLE_CNT==1. When controlling manually de-assert >= 3us after ENABLE=1. Assertion can happen in cycle just before ENABLE=0." "0: Isolate outputs,1: Do not isolate outputs"
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|
bitfld.long 0x0 22. "PLL_FRAC_ORDER,Order of the delta-sigma modulator used for fractional mode." "0: 2nd order,1: 1st order"
|
|
newline
|
|
bitfld.long 0x0 19.--21. "LDO_PERI_TRIM,pll ldo peripheri voltage trim (scan mode - can be '0' or '1' - not High Z)" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x0 16.--17. "PLL_DCO_SD_SEL,00': disable '01' first order SigmaDelta enabled;'10' third order SigmaDelta enabled;'11' RSVD" "0: disable,?,?,?"
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|
newline
|
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bitfld.long 0x0 12.--14. "LDO_DCO_TRIM,Trim for PLL local regulator for DCO" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x0 9. "PLL_SAR_FSM_EN,SAR FSM enable. Always set to 1 for functional mode. This register was kept in the design (and moved to hidden trim register) to increase coverage on the hard IP and could be removed once the hard IP input is removed." "0,1"
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|
newline
|
|
bitfld.long 0x0 8. "SAR_DIS,Disable Successive Approximation Register during locking." "0: Use SAR,1: Disable SAR"
|
|
hexmask.long.byte 0x0 4.--7. 1. "SAR_CYCLE_STOP,Successive Approximation Register (SAR) configuration. Ignored when SAR_DIS==1."
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "DPLL_LP_CTL3,DPLL LP Trim Register 3"
|
|
hexmask.long.word 0x0 16.--25. 1. "PHASE_ACC_CNT_SSCG,counter for phase accelerate cycles during PLL wakeup SSCG mode"
|
|
hexmask.long.word 0x0 0.--9. 1. "PHASE_ACC_CNT,counter for phase accelerate cycles during PLL wakeup for INT and FRAC modes"
|
|
line.long 0x4 "DPLL_LP_CTL4,DPLL LP Trim Register 4"
|
|
hexmask.long.word 0x4 4.--13. 1. "LOCK_WAIT_RISE,Wait time from when static phase error is within the lock window until lock signal asserts."
|
|
bitfld.long 0x4 0.--1. "LOCK_WAIT_FALL,Wait time from when static phase error is within the lock window until lock signal asserts." "0: 0 PFD clocks,1: 2 PFD clocks,2: 3 PFD clocks,3: 4 PFD clocks"
|
|
group.long ($2+0x1C)++0x3
|
|
line.long 0x0 "DPLL_LP_TEST4,DPLL LP Test Register 4"
|
|
hexmask.long.byte 0x0 23.--29. 1. "PHASE_ACC_USER_WRITE_FRACT,reduce KI KP coefficient during PLL deepsleep wakeup fract."
|
|
hexmask.long.byte 0x0 16.--22. 1. "PHASE_ACC_USER_WRITE_INT,Reduce KI KP coefficient during PLL deepsleep wakeup integer."
|
|
newline
|
|
bitfld.long 0x0 15. "PLL_READ_EN,This bit is a self clear bit. The FW writes 1 to get an updated value in PLL_USER_DCO_CODE.HW will self clear this bit to indicate that the PLL_USER_DCO_CODE be read." "0,1"
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|
bitfld.long 0x0 14. "PLL_DIS_FAST_LOCK,0: Enables DPLL Fast Lock" "0: Enables DPLL Fast Lock,1: Disables DPLL Fast Lock"
|
|
newline
|
|
hexmask.long.word 0x0 0.--13. 1. "PLL_USER_DCO_CODE,FW can read the code saved by the DPLL before deepsleep.Use PLL_READ_EN to get updated DCO_CODE from the DPLL: To read properly please refer to PLL_USER_DCO_CODE_RD_EN/PLL_READ_EN."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x42200000
|
|
newline
|
|
group.long 0xC000++0xF
|
|
line.long 0x0 "WDT_CTL,Watchdog Counter Control Register (Type A)"
|
|
bitfld.long 0x0 30.--31. "WDT_LOCK,Prohibits writing to WDT_* CLK_ILO_CONFIG CLK_SELECT.LFCLK_SEL and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
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|
newline
|
|
bitfld.long 0x0 4.--5. "WDT_CLK_SEL,Select source for WDT. Not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlock using WDT_LOCK register. It.." "0: ILO - Internal Low-speed Oscillator,1: PILO - Precision ILO. If present if present,2: BAK - Selected clk_bak source if present. See..,?"
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|
newline
|
|
bitfld.long 0x0 0. "WDT_EN,Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes." "0,1"
|
|
line.long 0x4 "WDT_CNT,Watchdog Counter Count Register (Type A)"
|
|
hexmask.long 0x4 0.--31. 1. "COUNTER,Current value of WDT Counter. The write feature of this register is for engineering use (DfV) have no synchronization and can only be applied when the WDT is fully off. When writing the value is updated immediately in the WDT counter but it.."
|
|
line.long 0x8 "WDT_MATCH,Watchdog Counter Match Register (Type A)"
|
|
hexmask.long 0x8 0.--31. 1. "MATCH,Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match)."
|
|
line.long 0xC "WDT_MATCH2,Watchdog Counter Match Register 2 (Type A)"
|
|
hexmask.long.byte 0xC 0.--4. 1. "IGNORE_BITS_ABOVE,The bit index to be considered the MSB for matching. Bit indices above this setting are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). The.."
|
|
tree "MCWDT_STRUCT (Multi-Counter Watchdog Timer (Type A))"
|
|
base ad:0x4220D000
|
|
group.long 0x4++0x1F
|
|
line.long 0x0 "MCWDT_CNTLOW,Multi-Counter Watchdog Sub-counters 0/1"
|
|
hexmask.long.word 0x0 16.--31. 1. "WDT_CTR1,Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "WDT_CTR0,Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled."
|
|
line.long 0x4 "MCWDT_CNTHIGH,Multi-Counter Watchdog Sub-counter 2"
|
|
hexmask.long 0x4 0.--31. 1. "WDT_CTR2,Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled"
|
|
line.long 0x8 "MCWDT_MATCH,Multi-Counter Watchdog Counter Match Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "WDT_MATCH1,Match value for sub-counter 1 of this MCWDT"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "WDT_MATCH0,Match value for sub-counter 0 of this MCWDT"
|
|
line.long 0xC "MCWDT_CONFIG,Multi-Counter Watchdog Counter Configuration"
|
|
hexmask.long.byte 0xC 24.--28. 1. "WDT_BITS2,Bit to observe for WDT_INT2:"
|
|
newline
|
|
bitfld.long 0xC 16. "WDT_MODE2,Watchdog Counter 2 Mode." "0: Free running counter with no interrupt requests,1: Free running counter with interrupt request that.."
|
|
newline
|
|
bitfld.long 0xC 15. "WDT_MATCH1_2,Specifies matching behavior when WDT_CASCADE1_2==1. When WDT_CASCADE1_2==0 this bit is not used and match is based on counter 2 alone." "0: Match based on counter 2 alone,1: Match based on counter 2 and counter 1 matching.."
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|
newline
|
|
bitfld.long 0xC 14. "WDT_CARRY1_2,Carry out behavior that applies when WDT_CASCADE1_2==1. This bit is not used when WDT_CASCADE1_2==0." "0: carry out on counter 1 match,1: carry out on counter 1 roll-over"
|
|
newline
|
|
bitfld.long 0xC 12.--13. "WDT_LOWER_MODE1,Watchdog Counter Action on service before lower limit." "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset,?"
|
|
newline
|
|
bitfld.long 0xC 11. "WDT_CASCADE1_2,Cascade Watchdog Counters 1 2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters." "0: Independent counters,1: Cascaded counters"
|
|
newline
|
|
bitfld.long 0xC 10. "WDT_CLEAR1,Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1)." "0: Free running counter,1: Clear on match"
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|
newline
|
|
bitfld.long 0xC 8.--9. "WDT_MODE1,Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1)." "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset,3: Assert WDT_INTx assert WDT Reset after 3rd.."
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|
newline
|
|
bitfld.long 0xC 7. "WDT_MATCH0_1,Specifies matching behavior when WDT_CASCADE0_1==1. When WDT_CASCADE0_1==0 this bit is not used and match is based on counter 1 alone." "0: Match based on counter 1 alone,1: Match based on counter 1 and counter 0 matching.."
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|
newline
|
|
bitfld.long 0xC 6. "WDT_CARRY0_1,Carry out behavior that applies when WDT_CASCADE0_1==1. This bit is not used when WDT_CASCADE0_1==0." "0: carry out on counter 0 match,1: carry out on counter 0 roll-over"
|
|
newline
|
|
bitfld.long 0xC 4.--5. "WDT_LOWER_MODE0,Watchdog Counter Action on service before lower limit." "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset,?"
|
|
newline
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bitfld.long 0xC 3. "WDT_CASCADE0_1,Cascade Watchdog Counters 0 1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0." "0: Independent counters,1: Cascaded counters"
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bitfld.long 0xC 2. "WDT_CLEAR0,Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1)." "0: Free running counter,1: Clear on match"
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bitfld.long 0xC 0.--1. "WDT_MODE0,Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0)." "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset,3: Assert WDT_INTx assert WDT Reset after 3rd.."
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line.long 0x10 "MCWDT_CTL,Multi-Counter Watchdog Counter Control"
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bitfld.long 0x10 19. "WDT_RESET2,Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
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rbitfld.long 0x10 17. "WDT_ENABLED2,Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles." "0,1"
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bitfld.long 0x10 16. "WDT_ENABLE2,Enable subcounter 2. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
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bitfld.long 0x10 11. "WDT_RESET1,Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
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rbitfld.long 0x10 9. "WDT_ENABLED1,Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles." "0,1"
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bitfld.long 0x10 8. "WDT_ENABLE1,Enable subcounter 1. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
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bitfld.long 0x10 3. "WDT_RESET0,Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect." "0,1"
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rbitfld.long 0x10 1. "WDT_ENABLED0,Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles." "0,1"
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bitfld.long 0x10 0. "WDT_ENABLE0,Enable subcounter 0. May take up to 2 LFCLK cycles to take effect." "0: Counter is disabled,1: Counter is enabled"
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line.long 0x14 "MCWDT_INTR,Multi-Counter Watchdog Counter Interrupt Register"
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bitfld.long 0x14 2. "MCWDT_INT2,MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3." "0,1"
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bitfld.long 0x14 1. "MCWDT_INT1,MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3." "0,1"
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bitfld.long 0x14 0. "MCWDT_INT0,MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3." "0,1"
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line.long 0x18 "MCWDT_INTR_SET,Multi-Counter Watchdog Counter Interrupt Set Register"
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bitfld.long 0x18 2. "MCWDT_INT2,Set interrupt for MCWDT_INT2" "0,1"
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bitfld.long 0x18 1. "MCWDT_INT1,Set interrupt for MCWDT_INT1" "0,1"
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bitfld.long 0x18 0. "MCWDT_INT0,Set interrupt for MCWDT_INT0" "0,1"
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line.long 0x1C "MCWDT_INTR_MASK,Multi-Counter Watchdog Counter Interrupt Mask Register"
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bitfld.long 0x1C 2. "MCWDT_INT2,Mask for sub-counter 2. This controls if the interrupt is forwarded to the CPU." "0: Interrupt is masked,1: Interrupt is forwarded"
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bitfld.long 0x1C 1. "MCWDT_INT1,Mask for sub-counter 1. This controls if the interrupt is forwarded to the CPU." "0: Interrupt is masked,1: Interrupt is forwarded"
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bitfld.long 0x1C 0. "MCWDT_INT0,Mask for sub-counter 0. This controls if the interrupt is forwarded to the CPU." "0: Interrupt is masked,1: Interrupt is forwarded"
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rgroup.long 0x24++0x3
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line.long 0x0 "MCWDT_INTR_MASKED,Multi-Counter Watchdog Counter Interrupt Masked Register"
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bitfld.long 0x0 2. "MCWDT_INT2,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "MCWDT_INT1,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "MCWDT_INT0,Logical and of corresponding request and mask bits." "0,1"
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group.long 0x28++0x7
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line.long 0x0 "MCWDT_LOCK,Multi-Counter Watchdog Counter Lock Register"
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bitfld.long 0x0 30.--31. "MCWDT_LOCK,Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
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line.long 0x4 "MCWDT_LOWER_LIMIT,Multi-Counter Watchdog Counter Lower Limit Register"
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hexmask.long.word 0x4 16.--31. 1. "WDT_LOWER_LIMIT1,Lower limit for sub-counter 1 of this MCWDT"
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hexmask.long.word 0x4 0.--15. 1. "WDT_LOWER_LIMIT0,Lower limit for sub-counter 0 of this MCWDT"
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tree.end
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tree.end
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tree "TCPWM (Timer/Counter Pulse-Width Modulator)"
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base ad:0x42A00000
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repeat 3. (list 0x0 0x1 0x2)(list ad:0x42A00000 ad:0x42A10000 ad:0x42A20000)
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tree "GRP[$1]"
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base $2
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repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x100 0x200 0x300 0x400 0x500 0x600 0x700)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0: counter disabled,1: counter enabled"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0: The counter operation depends on DBG_SUS_EN value,1: The counter operation freezes in debug mode.."
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bitfld.long 0x0 29. "DBG_SUS_EN,Specifies the counter behavior in debug mode when suspend is enabled" "0: The counter operation continues in debug mode as..,1: The counter operation freezes in debug mode.."
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bitfld.long 0x0 27.--28. "KILL_LINE_POLARITY,In PWM and PWM_DT modes these two bits can be used to invert 'line_out' and 'line_compl_out' during kill mode" "?,1: When bit 0 is '1' inverts the suppressed..,2: When bit 1 is '1' inverts the suppressed..,?"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode. HRPWM feature..,5: PWM with deadtime insertion mode. HRPWM feature..,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 22.--23. "DITHEREN,When '0' dithering is disabled" "?,1: Period dithering is enabled,2: Duty dithering is enabled,3: Period and Duty dithering is enabled"
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 15. "PWM_SYNC_KILL_DT,Specifies synchronous DT kill behavior:" "0: synchronous DT kill mode: Disable,1: synchronous DT kill mode: the kill event.."
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bitfld.long 0x0 14. "PWM_TC_SYNC_KILL_DT,Specifies TC synchronour DT kill behavior:" "0: TC synchronous DT kill mode: Disable,1: TC synchronous DT kill mode: the kill event.."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTRL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 11. "SWAP_ENABLE,Specifies whether swapping mechanism between CC0 and buffered CC0 CC1 and buffered CC1 PERIOD and buffered PERIOD DT and buffered DT are disabled" "0: swap is disable,1: swap is enable"
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0: asynchronous kill mode: the kill event only..,1: synchronous kill mode: the kill event disables.."
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0: kill event does NOT stop counter,1: kill event stops counter"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'line_out' and 'line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0: synchronous kill activation,1: immediate kill activation"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0: compare match 1 event generation disabled when..,1: compare match 1 event generation enabled when.."
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0: compare match 1 event generation disabled when..,1: compare match 1 event generation enabled when.."
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0: compare match 0 event generation disabled when..,1: compare match 0 event generation enabled when.."
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0: compare match 0 event generation disabled when..,1: compare match 0 event generation enabled when.."
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0: never switch,1: switch on a terminal count event with and.."
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0: Captures on index,1: Captures when COUNTER equals 0 or 0xffff"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with an.."
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with an.."
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 3. "KILL_STATUS,When '0' There is no kill event in pwm pwm_dt pwm_pr sr operation" "0,1"
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bitfld.long 0x0 2. "CC1_READ_MISS,When '0' CPU did not miss reading capture1 event information" "0,1"
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bitfld.long 0x0 1. "CC0_READ_MISS,When '0' CPU did not miss reading capture0 event information" "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x2B
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value. In compare mode 6 LSBs is used for HRPWM generation when HRPWM is enabled."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register. In compare mode 6 LSBs is used for HRPWM generation when HRPWM is enabled."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value. In compare mode 6 LSBs is used for HRPWM generation when HRPWM is enabled."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register. In compare mode 6 LSBs is used for HRPWM generation when HRPWM is enabled."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1. In PWM and PWM_DT mode 6 LSBs given by are used for HRPWM generation when HRPWM is enabled."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: The source for PWM signal conditioning comes..,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: The source for PWM signal conditioning comes..,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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line.long 0x24 "DT_BUFF,Counter buffered PWM dead time register"
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hexmask.long.word 0x24 16.--31. 1. "DT_LINE_COMPL_OUT,Buffer for DT.DT_LINE_COMPL_OUT register"
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hexmask.long.byte 0x24 8.--15. 1. "DT_LINE_OUT_H,Buffer for DT.DT_LINE_OUT_H register"
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hexmask.long.byte 0x24 0.--7. 1. "DT_LINE_OUT_L,Buffer for DT.DT_LINE_OUT_L register"
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line.long 0x28 "PS,Counter prescalar register"
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bitfld.long 0x28 0.--2. "PS_DIV,Select the pre-scaling of the selected counter clock. If HRPWM is intended to be used for the counter output this value shall be set to default '0' else the HRPWM feature will not work." "0: Pre-scaling of the selected counter clock.,1: Pre-scaling of the selected counter clock.,2: Pre-scaling of the selected counter clock.,3: Pre-scaling of the selected counter clock.,4: Pre-scaling of the selected counter clock.,5: Pre-scaling of the selected counter clock.,6: Pre-scaling of the selected counter clock.,7: Pre-scaling of the selected counter clock."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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|
newline
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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|
newline
|
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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|
newline
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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|
line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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|
newline
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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|
newline
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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|
newline
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: Compare match 0 event or Compare match 1 event,7: Output trigger disabled."
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|
newline
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: Compare match 0 event or Compare match 1 event,7: Output trigger disabled."
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|
group.long ($2+0x70)++0xB
|
|
line.long 0x0 "INTR,Interrupt request register"
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|
bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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|
newline
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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|
newline
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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|
line.long 0x4 "INTR_SET,Interrupt set request register"
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|
bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
line.long 0x8 "INTR_MASK,Interrupt mask register"
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|
bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
rgroup.long ($2+0x7C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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|
newline
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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|
newline
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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|
group.long ($2+0x80)++0x3
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line.long 0x0 "LFSR,LFSR register"
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|
bitfld.long 0x0 16.--18. "LIMITER,Limiter register." "?,1: When Limit_1 is '1' the PLFSR[0]/DLFSR[0] is..,2: When Limit_2 is '1' the PLFSR[1:0]/DLFSR[1:0] is..,3: When Limit_3 is '1' the PLFSR[2:0]/DLFSR[2:0] is..,4: When Limit_4 is '1' the PLFSR[3:0]/DLFSR[3:0] is..,5: When Limit_5 is '1' the PLFSR[4:0]/DLFSR[4:0] is..,6: When Limit_6 is '1' the PLFSR[5:0]/DLFSR[5:0] is..,7: When Limit_7 is '1' the PLFSR[6:0]/DLFSR[6:0] is.."
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|
newline
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hexmask.long.byte 0x0 8.--15. 1. "DLFSR,DLFSR register."
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|
newline
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hexmask.long.byte 0x0 0.--7. 1. "PLFSR,PLFSR register."
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|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
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|
group.long ($2+0x84)++0x3
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|
line.long 0x0 "ONE_GF[$1],Glitch filter register for one to one trigger"
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|
bitfld.long 0x0 3.--4. "GFPS_DIV,Select the glitch filter pre-scaling of the selected counter clock" "0: Glitch filter pre-scaling of the selected..,1: Glitch filter pre-scaling of the selected..,2: Glitch filter pre-scaling of the selected..,3: Glitch filter pre-scaling of the selected.."
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newline
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bitfld.long 0x0 0.--2. "GF_DEPTH,Select the glitch filter depth" "0: Glitch filter is turned off,1: Glitch filter depth is set to 1 x GFPS_DIVBYx of..,2: Glitch filter depth is set to 2 x GFPS_DIVBYx of..,3: Glitch filter depth is set to 4 x GFPS_DIVBYx of..,4: Glitch filter depth is set to 8 x GFPS_DIVBYx of..,5: Glitch filter depth is set to 16 x GFPS_DIVBYx..,6: Glitch filter depth is set to 32 x GFPS_DIVBYx..,7: Glitch filter depth is set to 64 x GFPS_DIVBYx.."
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|
repeat.end
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|
group.long ($2+0xA4)++0x3
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line.long 0x0 "TR_ONE_SYNC_BYPASS,Sync bypass register for one to one trigger"
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|
hexmask.long.byte 0x0 0.--7. 1. "SYNC_BYPASS,When set='1' bypass the sync stage for the corresponding one to one trigger"
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|
group.long ($2+0xB0)++0x3
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line.long 0x0 "HRPWM_CTRL,Counter control register for HRPWM feature"
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bitfld.long 0x0 5.--6. "FREQ_SEL,Selects the frequency of operation of HRPWM feature. Microtick is adjusted based on this information. These bits specifies the frequency of CLK_OUT from TCPWM counter. CLK_OUT = CLK_PERI = CLK_HF3" "0: CLK_OUT = 160MHz,1: CLK_OUT = 200 MHz,2: CLK_OUT = 240 MHz,3: N/A"
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|
newline
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bitfld.long 0x0 4. "DATA_IN_CC1_EN,When '1' parallel data path to register CC1 is active and bypass CC1 and CC1_BUFF register." "0,1"
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|
newline
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bitfld.long 0x0 3. "DATA_IN_CC0_EN,When '1' parallel data path to register CC0 is active and bypass CC0 and CC0_BUFF register." "0,1"
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newline
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bitfld.long 0x0 0. "HRPWM_EN,When '0' HRPWM feature is bypass when '1' HRPWM feature is enabled. When enabled HRPWM feature is only available in PWM and PWM_DT mode. In other modes this bit will have no effect and HRPWM feature remain bypass" "0,1"
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tree.end
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repeat.end
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tree.end
|
|
repeat.end
|
|
base ad:0x42A00000
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tree "TR_ALL_GF (Glitch filter module for group trigger)"
|
|
base ad:0x42A80000
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repeat 254. (increment 0x0 0x1)(increment 0x0 0x4)
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|
group.long ($2)++0x3
|
|
line.long 0x0 "ALL_GF[$1],Glitch filter register for All Group Triggers"
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|
bitfld.long 0x0 3.--4. "GFPS_DIV,Select the glitch filter pre-scaling of the selected counter clock" "0: Glitch filter pre-scaling of the selected..,1: Glitch filter pre-scaling of the selected..,2: Glitch filter pre-scaling of the selected..,3: Glitch filter pre-scaling of the selected.."
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bitfld.long 0x0 0.--2. "GF_DEPTH,Select the glitch filter depth" "0: Glitch filter is turned off,1: Glitch filter depth is set to 1 x GFPS_DIVBYx of..,2: Glitch filter depth is set to 2 x GFPS_DIVBYx of..,3: Glitch filter depth is set to 4 x GFPS_DIVBYx of..,4: Glitch filter depth is set to 8 x GFPS_DIVBYx of..,5: Glitch filter depth is set to 16 x GFPS_DIVBYx..,6: Glitch filter depth is set to 32 x GFPS_DIVBYx..,7: Glitch filter depth is set to 64 x GFPS_DIVBYx.."
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|
repeat.end
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tree.end
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tree "TR_ALL_SYNC_BYPASS (Glitch filter module for group trigger)"
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|
base ad:0x42A90000
|
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repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
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|
group.long ($2)++0x3
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line.long 0x0 "TR_ALL_SYNC_BYPASS[$1],Trigger Sync bypass for group trigger"
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hexmask.long 0x0 0.--31. 1. "SYNC_BYPASS,When set='1' bypass the sync stage for the corresponding group trigger"
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|
repeat.end
|
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tree.end
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x42AA0000 ad:0x42AA4000 ad:0x42AA8000)
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|
tree "MOTIF_GRP[$1]"
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base $2
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tree "MOTIF (MOTIF Module)"
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|
group.long ($2)++0xB
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line.long 0x0 "PCONF,Global control register"
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hexmask.long.byte 0x0 28.--31. 1. "LPC,Low Pass Filters Configuration"
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bitfld.long 0x0 27. "EWIL,External Wrong Hall Event active level" "0,1"
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newline
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bitfld.long 0x0 26. "EWIE,External Wrong Hall Event enable" "0,1"
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|
bitfld.long 0x0 22. "MSYES,Multi-Channel pattern update msync trigger edge" "0,1"
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|
newline
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bitfld.long 0x0 21. "MSES,Multi-Channel pattern update mset trigger edge" "0,1"
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bitfld.long 0x0 17. "SPES,Edge selector for the sampling trigger" "0,1"
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|
newline
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bitfld.long 0x0 14.--15. "CHEC,Correct Hall Event Clear selection" "0: OR between wrong hall event and module pin..,1: Wrong Hall Event,2: Module Pin - MOTIFx.EWHE,3: N/A"
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bitfld.long 0x0 6.--7. "FTS,Fault Hall event Selection" "0: OR between wrong hall event and module pin..,1: Wrong Hall Event,2: Module Pin - MOTIFx.EWHE,3: N/A"
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newline
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bitfld.long 0x0 5. "MCUE,Multi-Channel Pattern SW update enable" "0,1"
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|
bitfld.long 0x0 4. "HIDG,Idle generation enable" "0,1"
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newline
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bitfld.long 0x0 3. "QDCM,Position Decoder Mode selection" "0,1"
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|
bitfld.long 0x0 1.--2. "FSEL,Function Selector" "0: Hall Sensor Mode enabled,1: Quadrature Decoder Mode enabled,2: stand-alone Multi-Channel Mode enabled,3: Quadrature Decoder and stand-alone.."
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newline
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bitfld.long 0x0 0. "ENABLE,MOTIF enable" "0,1"
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|
line.long 0x4 "PSUS,Suspend Configuration"
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|
bitfld.long 0x4 0.--2. "SUS,MOTIF Mode Suspend Config" "0: Suspend request ignored,1: Stop immediately,2: In quad mode and quad with stand-alone mode..,3: In quad mode and quad with stand-alone mode..,4: Stop immediately. Multi-Channel pattern is set..,5: Suspend with the synchronization of the PWM..,6: N/A,7: N/A"
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line.long 0x8 "PRUNS,MOTIF run bit set"
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bitfld.long 0x8 0. "SRB,Set Run bit" "0,1"
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|
rgroup.long ($2+0x10)++0x3
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line.long 0x0 "PRUN,MOTIF run bit status"
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|
bitfld.long 0x0 0. "RB,Run Bit" "0,1"
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|
wgroup.long ($2+0x24)++0x3
|
|
line.long 0x0 "HIST,Hall Inputs Sample Trigger"
|
|
bitfld.long 0x0 0. "HIS,Hall Inputs Sample" "0,1"
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|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "HMEC,Hall Mode Extra Config"
|
|
bitfld.long 0x0 1. "HPPE,Previous Pattern Compare Enable" "0,1"
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|
bitfld.long 0x0 0. "HDBP,Hall Sensor Debounce Stage Bypass" "0,1"
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|
rgroup.long ($2+0x30)++0x3
|
|
line.long 0x0 "HALP,Hall Current and Expected patterns"
|
|
bitfld.long 0x0 8.--10. "HPP,Hall Previous Pattern" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3.--5. "HEP,Hall Expected Pattern" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x0 0.--2. "HCP,Hall Current Pattern" "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x34)++0x7
|
|
line.long 0x0 "HALPS,Hall Current and Expected shadow patterns"
|
|
bitfld.long 0x0 24.--26. "HLUT5,Hall LUT data position 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 19.--21. "HLUT4,Hall LUT data position 4" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x0 16.--18. "HLUT3,Hall LUT data position 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "HPPS2,Shadow Hall Previous Pattern - HLUT2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "HEPS1,Shadow Hall expected Pattern - HLUT1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "HCPS0,Shadow Hall Current Pattern - HLUT0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "HOSC,Hall Sensor Output Config"
|
|
bitfld.long 0x4 24.--26. "PPN,Previous Pattern Match Event Output Node" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 20.--22. "CPN,Current Pattern Match Event Output Node" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x4 16.--18. "SPN,Stop Counters/Pattern Mismatch Event Output Node" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "HSTN,Start Event Output Node" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x4 8.--10. "IDN,Idle/Wrong Hall Event Output Node" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "CHN,Correct Hall Event Output Node" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x4 0.--2. "EDN,Edge Detection Event Output Node" "0: Signal is not forward to any output,1: Forward to MOTIFx.OUT0,2: Forward to MOTIFx.OUT1,3: Forward to MOTIFx.OUT2,4: Forward to MOTIFx.OUT3,5: Forward to MOTIFx.OUT4,6: Forward to MOTIFx.OUT5,7: Forward to MOTIFx.OUT6"
|
|
rgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "MCM,Multi-Channel Mode Pattern"
|
|
hexmask.long 0x0 0.--31. 1. "MCMP,Multi-Channel Pattern"
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "MCSM,Multi-Channel Mode shadow Pattern LUT0"
|
|
hexmask.long 0x0 0.--31. 1. "MCMPS,Shadow Multi-Channel Pattern"
|
|
wgroup.long ($2+0x48)++0x7
|
|
line.long 0x0 "MCMS,Multi-Channel Mode Control set"
|
|
bitfld.long 0x0 2. "STMR,Multi-Channel Shadow Transfer Request" "0,1"
|
|
bitfld.long 0x0 1. "STHR,Hall Pattern Shadow Transfer Request" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "MNPS,Multi-Channel Pattern Update Enable Set" "0,1"
|
|
line.long 0x4 "MCMC,Multi-Channel Mode Control clear"
|
|
bitfld.long 0x4 1. "MPC,Multi-Channel Pattern clear" "0,1"
|
|
bitfld.long 0x4 0. "MNPC,Multi-Channel Pattern Update Enable Clear" "0,1"
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "MCMF,Multi-Channel Mode flag status"
|
|
bitfld.long 0x0 0. "MSS,Multi-Channel Pattern update status" "0,1"
|
|
group.long ($2+0x54)++0x7
|
|
line.long 0x0 "MCPF,Multi-Channel Pattern Fault"
|
|
hexmask.long 0x0 0.--31. 1. "MCFV,Multi-Channel Fault Value"
|
|
line.long 0x4 "MOSC,Multi-Channel Output Config"
|
|
bitfld.long 0x4 8.--10. "MSTN,Start Event Output Node" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "SHN,Update Sync Event Output Node" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "PUN,Pattern Update Event Output Node" "0: Signal is not forward to any output,1: Forward to MOTIFx.OUT0,2: Forward to MOTIFx.OUT1,3: Forward to MOTIFx.OUT2,4: Forward to MOTIFx.OUT3,5: Forward to MOTIFx.OUT4,6: Forward to MOTIFx.OUT5,7: Forward to MOTIFx.OUT6"
|
|
group.long ($2+0x60)++0xB
|
|
line.long 0x0 "QDC,Quadrature Decoder Configuration"
|
|
bitfld.long 0x0 24.--25. "IDS,Index Selector" "0: Disabled,1: POSI0,2: POSI1,3: POSI2"
|
|
bitfld.long 0x0 20.--21. "PBDS,Phase B or Direction Selector" "0: Disabled,1: POSI0,2: POSI1,3: POSI2"
|
|
newline
|
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bitfld.long 0x0 16.--17. "PACS,Phase A or Clock Selector" "0: Disabled,1: POSI0,2: POSI1,3: POSI2"
|
|
bitfld.long 0x0 14.--15. "PBEM,Phase B Edge Mode" "0: clock is decoded on rising and falling edges of..,1: clock is decoded on rising edge of the Phase B..,2: clock is decoded on falling edge of the Phase B..,3: Clock is not decoded for PHASE B"
|
|
newline
|
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bitfld.long 0x0 12.--13. "PAEM,Phase A Edge Mode" "0: clock is decoded on rising and falling edges of..,1: clock is decoded on rising edge of the Phase A..,2: clock is decoded on falling edge of the Phase A..,3: Clock is not decoded for PHASE A"
|
|
rbitfld.long 0x0 8. "DVAL,Current rotation direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ICM,Index Marker generations control" "0: No index marker generation,1: Only first index occurrence generated,2: All index occurrences generated,3: N/A"
|
|
bitfld.long 0x0 3. "INDS,Index Signal Level selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "PHS,Phase signals swap" "0,1"
|
|
bitfld.long 0x0 1. "PBLS,Phase B Level selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PALS,Phase A Level selector" "0,1"
|
|
line.long 0x4 "QOSC,Quadrature Output Config"
|
|
bitfld.long 0x4 20.--22. "QSTN,Start Event Output Node" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "IXN,Index Event Output Node" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "CCN,Clear/Capture Event Output Node" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "PCN,Period Clock Event Output Node" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "DON,Direction Event Output Node" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "QCN,Quadrature Clock Event Output Node" "0: Signal is not forward to any output,1: Forward to MOTIFx.OUT0,2: Forward to MOTIFx.OUT1,3: Forward to MOTIFx.OUT2,4: Forward to MOTIFx.OUT3,5: Forward to MOTIFx.OUT4,6: Forward to MOTIFx.OUT5,7: Forward to MOTIFx.OUT6"
|
|
line.long 0x8 "MCMEC,Multi-Channel Extra Config"
|
|
bitfld.long 0x8 4. "MFCE,Multi-Channel Fault Clear Enable" "0,1"
|
|
bitfld.long 0x8 1. "MEBP,Multi-Channel Pattern Enable Delay Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "MSBP,Multi-Channel Mode Sync Bypass" "0,1"
|
|
rgroup.long ($2+0x70)++0x3
|
|
line.long 0x0 "PFLG,MOTIF interrupt status"
|
|
bitfld.long 0x0 14. "PPES,Previous Pattern Match Status" "0,1"
|
|
bitfld.long 0x0 13. "CPES,Current Pattern Match Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PCLKS,Quadrature Period Clk Status" "0,1"
|
|
bitfld.long 0x0 11. "DIRS,Quadrature Direction Change" "0,1"
|
|
newline
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bitfld.long 0x0 10. "CNTS,Quadrature CLK Status" "0,1"
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bitfld.long 0x0 9. "ERRS,Quadrature Phase Error Status" "0,1"
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newline
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bitfld.long 0x0 8. "INDXS,Quadrature Index Status" "0,1"
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bitfld.long 0x0 4. "MSTS,Multi-Channel pattern shadow transfer status" "0,1"
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newline
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bitfld.long 0x0 2. "HIES,Hall Inputs Update Status" "0,1"
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bitfld.long 0x0 1. "WHES,Wrong Hall Event Status" "0,1"
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newline
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bitfld.long 0x0 0. "CHES,Correct Hall Event Status" "0,1"
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group.long ($2+0x74)++0x3
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line.long 0x0 "PFLGE,MOTIF interrupt enable"
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bitfld.long 0x0 30. "PPSEL,Previous Pattern Match Event Service Request Selector" "0,1"
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bitfld.long 0x0 29. "CPSEL,Current Pattern Match Event Service Request Selector" "0,1"
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newline
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bitfld.long 0x0 28. "PCLSEL,Quadrature Period clock Event Service Request Selector" "0,1"
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bitfld.long 0x0 27. "DIRSEL,Quadrature Direction Update Event Service Request Selector" "0,1"
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newline
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bitfld.long 0x0 26. "CNTSEL,Quadrature Clock Event Service Request Selector" "0,1"
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bitfld.long 0x0 25. "ERRSEL,Quadrature Phase Error Event Service Request Selector" "0,1"
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newline
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bitfld.long 0x0 24. "INDSEL,Quadrature Index Event Service Request Selector" "0,1"
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bitfld.long 0x0 20. "MSTSEL,Multi-Channel pattern Update Event Service Request Selector" "0,1"
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newline
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bitfld.long 0x0 18. "HIESEL,Hall Inputs Update Event Service Request Selector" "0,1"
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bitfld.long 0x0 17. "WHESEL,Wrong Hall Event Service Request Selector" "0,1"
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newline
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bitfld.long 0x0 16. "CHESEL,Correct Hall Event Service Request Selector" "0,1"
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bitfld.long 0x0 14. "EPPE,Previous Pattern Match interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "ECPE,Current Pattern Match interrupt Enable" "0,1"
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bitfld.long 0x0 12. "EPCLK,Quadrature Period CLK interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 11. "EDIR,Quadrature direction change interrupt Enable" "0,1"
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bitfld.long 0x0 10. "ECNT,Quadrature CLK interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "EERR,Quadrature Phase Error Enable" "0,1"
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bitfld.long 0x0 8. "EINDX,Quadrature Index Event Enable" "0,1"
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newline
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bitfld.long 0x0 4. "EMST,Multi-Channel pattern shadow transfer enable" "0,1"
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bitfld.long 0x0 2. "EHIE,Hall Input Update Enable" "0,1"
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newline
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bitfld.long 0x0 1. "EWHE,Wrong Hall Event Enable" "0,1"
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bitfld.long 0x0 0. "ECHE,Correct Hall Event Enable" "0,1"
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wgroup.long ($2+0x78)++0x7
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line.long 0x0 "SPFLG,Interrupt set register"
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bitfld.long 0x0 14. "SPP,Previous Pattern Match flag set" "0,1"
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bitfld.long 0x0 13. "SCP,Current Pattern Match flag set" "0,1"
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newline
|
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bitfld.long 0x0 12. "SPCLK,Quadrature period clock flag set" "0,1"
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bitfld.long 0x0 11. "SDIR,Quadrature Direction flag set" "0,1"
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newline
|
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bitfld.long 0x0 10. "SCNT,Quadrature CLK flag set" "0,1"
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bitfld.long 0x0 9. "SERR,Quadrature Phase Error flag set" "0,1"
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newline
|
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bitfld.long 0x0 8. "SINDX,Quadrature Index flag set" "0,1"
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bitfld.long 0x0 4. "SMST,Multi-Channel Pattern shadow transfer flag set" "0,1"
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newline
|
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bitfld.long 0x0 2. "SHIE,Hall Inputs Update Event flag set" "0,1"
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bitfld.long 0x0 1. "SWHE,Wrong Hall Event flag set" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "SCHE,Correct Hall Event flag set" "0,1"
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line.long 0x4 "RPFLG,Interrupt clear register"
|
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bitfld.long 0x4 14. "RPP,Previous Pattern Match flag clear" "0,1"
|
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bitfld.long 0x4 13. "RCP,Current Pattern Match flag clear" "0,1"
|
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newline
|
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bitfld.long 0x4 12. "RPCLK,Quadrature period clock flag clear" "0,1"
|
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bitfld.long 0x4 11. "RDIR,Quadrature Direction flag clear" "0,1"
|
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newline
|
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bitfld.long 0x4 10. "RCNT,Quadrature CLK flag clear" "0,1"
|
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bitfld.long 0x4 9. "RERR,Quadrature Phase Error flag clear" "0,1"
|
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newline
|
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bitfld.long 0x4 8. "RINDX,Quadrature Index flag clear" "0,1"
|
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bitfld.long 0x4 4. "RMST,Multi-Channel Pattern shadow transfer flag clear" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "RHIE,Hall Inputs Update Event flag clear" "0,1"
|
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bitfld.long 0x4 1. "RWHE,Wrong Hall Event flag clear" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "RCHE,Correct Hall Event flag clear" "0,1"
|
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group.long ($2+0x80)++0x17
|
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line.long 0x0 "MCSM1,Multi-Channel Mode shadow pattern LUT1"
|
|
hexmask.long 0x0 0.--31. 1. "MLUT1,Multi-Channel LUT 1"
|
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line.long 0x4 "MCSM2,Multi-Channel Mode shadow pattern LUT2"
|
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hexmask.long 0x4 0.--31. 1. "MLUT2,Multi-Channel LUT 2"
|
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line.long 0x8 "MCSM3,Multi-Channel Mode shadow pattern LUT3"
|
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hexmask.long 0x8 0.--31. 1. "MLUT3,Multi-Channel LUT 3"
|
|
line.long 0xC "MCSM4,Multi-Channel Mode shadow pattern LUT4"
|
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hexmask.long 0xC 0.--31. 1. "MLUT4,Multi-Channel LUT 4"
|
|
line.long 0x10 "MCSM5,Multi-Channel Mode shadow pattern LUT5"
|
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hexmask.long 0x10 0.--31. 1. "MLUT5,Multi-Channel LUT 5"
|
|
line.long 0x14 "CLUT,Hall Mode LUT config"
|
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bitfld.long 0x14 0. "LUTEN,HALL LUT enable" "0,1"
|
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rgroup.long ($2+0x98)++0x3
|
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line.long 0x0 "SLUT,Hall Mode LUT status"
|
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bitfld.long 0x0 0.--2. "PTR,HALL LUT Pointer status" "0,1,2,3,4,5,6,7"
|
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rgroup.long ($2+0x100)++0xF
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line.long 0x0 "PDBG,MOTIF Debug Register"
|
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bitfld.long 0x0 14. "LPF2V,Low Pass filter 2 valid state" "0,1"
|
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bitfld.long 0x0 13. "LPF1V,Low Pass filter 1 valid state" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "LPF0V,Low Pass filter 0 valid state" "0,1"
|
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bitfld.long 0x0 8.--10. "HSP,Hall Current Sampled Pattern" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x0 6. "IVAL,Current Index Value" "0,1"
|
|
bitfld.long 0x0 3.--5. "QPSV,Quadrature Decoder Previous state" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "QCSV,Quadrature Decoder Current state" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "PLP0S,MOTIF Low Pass 0 Status"
|
|
hexmask.long.word 0x4 0.--9. 1. "LPP0,Actual count of the Low Pass Filter"
|
|
line.long 0x8 "PLP1S,MOTIF Low Pass 1 Status"
|
|
hexmask.long.word 0x8 0.--9. 1. "LPP1,Actual count of the Low Pass Filter"
|
|
line.long 0xC "PLP2S,MOTIF Low Pass 2 Status"
|
|
hexmask.long.word 0xC 0.--9. 1. "LPP2,Actual count of the Low Pass Filter"
|
|
tree.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
newline
|
|
AUTOINDENT.OFF
|