34717 lines
1.5 MiB
34717 lines
1.5 MiB
; --------------------------------------------------------------------------------
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; @Title: SAM9X6 On-Chip Peripherals
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; @Props: Released
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; @Author: KRZ
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; @Changelog: 2025-06-18 KRZ
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; @Manufacturer: MICROCHIP - Microchip Technology Inc.
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; @Doc: Generated (TRACE32, build: 180698.), based on:
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; SAM9X60.svd (SAM9X6_DFP 1.12.231, 2025-02-26)
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; @Core: ARM926EJ-S
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; @Chip: SAM9X60*
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; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: persam9x6.per 19643 2025-06-18 11:51:38Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree "Core Registers (ARM926EJ-S)"
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AUTOINDENT.PUSH
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AUTOINDENT.ON CENTER TREE
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width 8.
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tree "ID Registers"
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group c15:0x0000--0x0000
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line.long 0x0 "MIDR,Identity Code"
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hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer"
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hexmask.long.byte 0x0 20.--23. 0x1 "SPEC,Specification Revision"
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hexmask.long.byte 0x0 16.--19. 0x1 "ARCH,Architecture Version"
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hexmask.long.word 0x0 4.--15. 0x1 "PARTNUM,Part Number"
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hexmask.long.byte 0x0 0.--3. 0x01 "REV,Layout Revision"
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group c15:0x0100--0x0100
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line.long 0x0 "CTR,Cache Type"
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bitfld.long 0x0 25.--28. "CLASS,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
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bitfld.long 0x0 24. "H,Cache Havardness" "no,yes"
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newline
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bitfld.long 0x0 18.--21. "DSIZE,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 15.--17. "DASS,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 14. "DM,Data Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 12.--13. "DLENGTH,Data Cache Line Length" "2,4,8,16"
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newline
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bitfld.long 0x0 6.--9. "ISIZE,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 3.--5. "IASS,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 2. "IM,Instruction Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 0.--1. "ILENGTH,Instruction Cache Line Length" "2,4,8,16"
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group c15:0x0200--0x0200
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line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register"
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bitfld.long 0x0 16. "DP,Data TCM Present" "no,yes"
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bitfld.long 0x0 0. "IP,Instruction TCM Present" "no,yes"
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tree.end
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tree "MMU Control and Configuration"
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width 8.
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group c15:0x0001--0x0001
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 15. "L4,Configure Loading TBIT" "Enable,Disable"
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bitfld.long 0x0 14. "RR,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin"
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bitfld.long 0x0 13. "V,Location of Exception Vectors" "0x00000000,0xFFFF0000"
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newline
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bitfld.long 0x0 12. "I,Instruction Cache" "Disable,Enable"
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bitfld.long 0x0 9. "R,ROM Protection" "Disable,Enable"
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bitfld.long 0x0 8. "S,System Protection" "Disable,Enable"
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bitfld.long 0x0 7. "B,Endianism" "Little,Big"
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newline
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bitfld.long 0x0 2. "C,Data Cache" "Disable,Enable"
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bitfld.long 0x0 1. "A,Alignment Fault Checking" "Disable,Enable"
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bitfld.long 0x0 0. "M,MMU" "Disable,Enable"
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newline
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group c15:0x0002--0x0002
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line.long 0x0 "TTBR,Translation Table Base Register"
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hexmask.long 0x0 14.--31. 0x4000 "TTBA,Translation Table Base Address"
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newline
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group c15:0x3--0x3
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line.long 0x0 "DACR,Domain Access Control Register"
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bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
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newline
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bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
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newline
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bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
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newline
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bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
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newline
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group c15:0x0005--0x0005
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line.long 0x0 "DFSR,Data Fault Status Register"
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bitfld.long 0x0 0x4--0x7 "DOMAIN,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 "STATUS,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0105--0x0105
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line.long 0x0 "IFSR,Instruction Fault Status Register"
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bitfld.long 0x0 0x4--0x7 "DOMAIN,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 "STATUS,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0006--0x0006
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line.long 0x0 "DFAR,Data Fault Address Register"
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newline
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group c15:0x000a--0x000a
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line.long 0x0 "TLBR,TLB Lockdown Register"
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bitfld.long 0x0 26.--28. "VICTIM,Victim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. "P,P bit" "0,1"
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newline
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group c15:0x000d--0x000d
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line.long 0x0 "FCSEPID,FCSE Process ID"
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group c15:0x010d--0x010d
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line.long 0x0 "CONTEXT,Context ID"
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tree.end
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tree "Cache Control and Configuration"
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group c15:0x0009--0x0009
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line.long 0x0 "DCACHE,Data Cache Lockdown"
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bitfld.long 0x0 3. "LWAY3,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. "LWAY2,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. "LWAY1,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. "LWAY0,L bit for WAY 0" "0,1"
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group c15:0x0109--0x0109
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line.long 0x0 "ICACHE,Instruction Cache Lockdown"
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bitfld.long 0x0 3. "LWAY3,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. "LWAY2,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. "LWAY1,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. "LWAY0,L bit for WAY 0" "0,1"
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tree.end
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tree "TCM Control and Configuration"
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group c15:0x0019--0x0019
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line.long 0x0 "DTCM,Data TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 "BASE,Base Address"
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bitfld.long 0x0 2.--5. "SIZE,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. "ENABLE,Enable Bit" "disable,enable"
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group c15:0x0119--0x0119
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line.long 0x0 "ITCM,Instruction TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 "BASE,Base Address"
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bitfld.long 0x0 2.--5. "SIZE,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. "ENABLE,Enable Bit" "disable,enable"
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tree.end
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tree "Test and Debug"
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group c15:0x000f--0x000f
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line.long 0x0 "DOVRR,Debug Override Register"
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bitfld.long 0x0 19. "TCALL,Test and clean all" "disable,enable"
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bitfld.long 0x0 18. "DTLBMISS,Abort Data TLB Miss" "no abort,abort"
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bitfld.long 0x0 17. "ITLBMISS,Abort Instruction TLB Miss" "no abort,abort"
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newline
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bitfld.long 0x0 16. "PREFETCH,NC Instruction Prefetching" "enable,disable"
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bitfld.long 0x0 15. "CLOCKGATE,Block Level Clock Gating" "enable,disable"
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bitfld.long 0x0 14. "NCBSTORE,NCB Stores" "disable,enable"
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bitfld.long 0x0 13. "MMU/DC,MMU disable DCache Enabled Behaviour" "NCNB,WT"
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group c15:0x001f--0x001f
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line.long 0x0 "ADDRESS,Debug/Test Address"
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;wgroup c15:0x402f--0x402f
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; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry"
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;wgroup c15:0x403f--0x403f
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; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry"
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;wgroup c15:0x404f--0x404f
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; line.long 0x0 "RMTLBPA,Read PA in main TLB entry"
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;wgroup c15:0x405f--0x405f
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; line.long 0x0 "WMTLBPA,Write PA in main TLB entry"
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;wgroup c15:0x407f--0x407f
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; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM"
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;wgroup c15:0x412f--0x412f
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; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry"
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;wgroup c15:0x413f--0x413f
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; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry"
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;wgroup c15:0x414f--0x414f
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; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry"
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;wgroup c15:0x415f--0x415f
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; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry"
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;wgroup c15:0x417f--0x417f
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; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM"
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group c15:0x101f--0x101f
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line.long 0x0 "TRACE,Trace Control"
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bitfld.long 0x0 2. "FIQ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall"
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bitfld.long 0x0 1. "IRQ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall"
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group c15:0x700f--0x700f
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line.long 0x0 "CACHE,Cache Debug Control"
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bitfld.long 0x0 2. "DWT,Disable Writeback (force WT)" "writeback,write-through"
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bitfld.long 0x0 1. "DIL,Disable ICache Linefill" "enable,disable"
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bitfld.long 0x0 0. "DDL,Disable DCache Linefill" "enable,disable"
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group c15:0x701f--0x701f
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line.long 0x0 "MMU,MMU Debug Control"
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bitfld.long 0x0 7. "TLBMI,Disable Main TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 6. "TLBMD,Disable Main TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 5. "TLBLI,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 4. "TLBLD,Disable Main TLB Load Due to Data Access Miss" "enable,disable"
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newline
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bitfld.long 0x0 3. "TLBMMI,Disable Micro TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 2. "TLBMMD,Disable Micro TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 1. "TLBMLI,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 0. "TLBMLD,Disable Micro TLB Load Due to Data Access Miss" "enable,disable"
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group c15:0x002f--0x002f
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line.long 0x0 "REMAP,Memory Region Remap"
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bitfld.long 0x0 14.--15. "IWB," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 12.--13. "IWT," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 10.--11. "INCB," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 8.--9. "INCNB," "NCNB,NCB,WT,WB"
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newline
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bitfld.long 0x0 6.--7. "DWB," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 4.--5. "DWT," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 2.--3. "DNCB," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 0.--1. "DNCNB," "NCNB,NCB,WT,WB"
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tree.end
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tree "ICEbreaker"
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width 8.
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group ice:0x0--0x5 "Debug Control"
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line.long 0x0 "DBGCTRL,Debug Control Register"
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bitfld.long 0x0 0x5 "ICE,EmbeddedICE Disable" "enabled,disabled"
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bitfld.long 0x0 0x4 "MONITOR,Monitor Mode Enable" "disabled,enabled"
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newline
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bitfld.long 0x0 0x3 "STEP,Single Step" "disabled,enabled"
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bitfld.long 0x0 0x2 "INTDIS,Interrupts Disable" "enabled,disabled"
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bitfld.long 0x0 0x1 "DBGRQ,Debug Request" "no,yes"
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bitfld.long 0x0 0x0 "DBGACK,Debug Acknowledge" "no,yes"
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line.long 0x4 "DBGSTAT,Debug Status Register"
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bitfld.long 0x4 0x6--0x9 "MOE,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res"
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bitfld.long 0x4 0x5 "IJBIT,IJBIT" "0,java"
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bitfld.long 0x4 0x4 "ITBIT,ITBIT" "0,thumb"
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bitfld.long 0x4 0x3 "SYSCOMP,SYSCOMP" "0,1"
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bitfld.long 0x4 0x2 "IFEN,Interrupts Enable" "disabled,enabled"
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bitfld.long 0x4 0x1 "DBGRQ,Debug Request" "no,yes"
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bitfld.long 0x4 0x0 "DBGACK,Debug Acknowledge" "no,yes"
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line.long 0x8 "VECTOR,Vector Catch Register"
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bitfld.long 0x8 0x7 "FIQ,FIQ" "dis,ena"
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bitfld.long 0x8 0x6 "IRQ,IRQ" "dis,ena"
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bitfld.long 0x8 0x4 "D_ABO,D_ABORT" "dis,ena"
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bitfld.long 0x8 0x3 "P_ABO,P_ABORT" "dis,ena"
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bitfld.long 0x8 0x2 "SWI,SWI" "dis,ena"
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bitfld.long 0x8 0x1 "UND,UNDEF" "dis,ena"
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bitfld.long 0x8 0x0 "RES,RESET" "dis,ena"
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line.long 0x10 "COMCTRL,Debug Communication Control Register"
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bitfld.long 0x10 28.--31. "VERSION,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
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bitfld.long 0x10 0x1 "WRITE,Write Register Free" "idle,pend"
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bitfld.long 0x10 0x0 "READ,Read Register Free" "idle,pend"
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line.long 0x14 "COMDATA,Debug Communication Data Register"
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group ice:0x8--0x0d "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 "ENABLE,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 "RANGE,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 "CHAIN,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 "EXTERN,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 "nTRANS,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 "nOPC,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 "MAS,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 "nRW,Read/Write" "R ,W"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 "RANGE,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 "CHAIN,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 "EXTERN,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 "nTRANS,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 "nOPC,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 "MAS,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 "nRW,Read/Write" "ENA,DIS"
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group ice:0x10--0x15 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 "ENABLE,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 "RANGE,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 "CHAIN,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 "EXTERN,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 "nTRANS,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 "nOPC,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 "MAS,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 "nRW,Read/Write" "R ,w"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 "RANGE,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 "CHAIN,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 "EXTERN,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 "nTRANS,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 "nOPC,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 "MAS,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 "nRW,Read/Write" "ENA,DIS"
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tree.end
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AUTOINDENT.POP
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tree.end
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tree "ADC (Analog-to-Digital Converter)"
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base ad:0xF804C000
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wgroup.long 0x0++0x3
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 4. "CMPRST,Comparison Restart" "0,1"
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bitfld.long 0x0 2. "TSCALIB,Touchscreen Calibration" "0,1"
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newline
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bitfld.long 0x0 1. "START,Start Conversion" "0,1"
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bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
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group.long 0x4++0xB
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line.long 0x0 "MR,Mode Register"
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bitfld.long 0x0 31. "USEQ,User Sequence Enable" "0: Normal mode: The controller converts channels in..,1: User Sequence mode: The sequence respects what.."
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bitfld.long 0x0 30. "MAXSPEED,Maximum Sampling Rate Enable in Freerun Mode" "0,1"
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newline
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bitfld.long 0x0 28.--29. "TRANSFER,Transfer Time" "0,1,2,3"
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hexmask.long.byte 0x0 24.--27. 1. "TRACKTIM,Tracking Time"
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newline
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bitfld.long 0x0 23. "ANACH,Analog Change" "0: No analog change on channel switching: DIFF0 is..,1: Allows different analog settings for each.."
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hexmask.long.byte 0x0 16.--19. 1. "STARTUP,Startup Time"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "PRESCAL,Prescaler Rate Selection"
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bitfld.long 0x0 6. "FWUP,Fast Wakeup" "0: If SLEEP is 1 then both ADC core and reference..,1: If SLEEP is 1 then Fast Wakeup Sleep mode: The.."
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newline
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bitfld.long 0x0 5. "SLEEP,Sleep Mode" "0: Normal Mode: The ADC core and reference voltage..,1: Sleep Mode: The wakeup time can be modified by.."
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bitfld.long 0x0 1.--3. "TRGSEL,Trigger Selection" "0: ADTRG,1: TIOA0,2: TIOA1,3: TIOA2,?,?,?,?"
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line.long 0x4 "SEQR1,Channel Sequence Register 1"
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hexmask.long.byte 0x4 28.--31. 1. "USCH8,User Sequence Number 8"
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hexmask.long.byte 0x4 24.--27. 1. "USCH7,User Sequence Number 7"
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newline
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hexmask.long.byte 0x4 20.--23. 1. "USCH6,User Sequence Number 6"
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hexmask.long.byte 0x4 16.--19. 1. "USCH5,User Sequence Number 5"
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newline
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hexmask.long.byte 0x4 12.--15. 1. "USCH4,User Sequence Number 4"
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hexmask.long.byte 0x4 8.--11. 1. "USCH3,User Sequence Number 3"
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newline
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hexmask.long.byte 0x4 4.--7. 1. "USCH2,User Sequence Number 2"
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hexmask.long.byte 0x4 0.--3. 1. "USCH1,User Sequence Number 1"
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line.long 0x8 "SEQR2,Channel Sequence Register 2"
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hexmask.long.byte 0x8 8.--11. 1. "USCH11,User Sequence Number 11"
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hexmask.long.byte 0x8 4.--7. 1. "USCH10,User Sequence Number 10"
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newline
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hexmask.long.byte 0x8 0.--3. 1. "USCH9,User Sequence Number 9"
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wgroup.long 0x10++0x7
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line.long 0x0 "CHER,Channel Enable Register"
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bitfld.long 0x0 11. "CH11,Channel 11 Enable" "0,1"
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bitfld.long 0x0 10. "CH10,Channel 10 Enable" "0,1"
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newline
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bitfld.long 0x0 9. "CH9,Channel 9 Enable" "0,1"
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bitfld.long 0x0 8. "CH8,Channel 8 Enable" "0,1"
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newline
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bitfld.long 0x0 7. "CH7,Channel 7 Enable" "0,1"
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bitfld.long 0x0 6. "CH6,Channel 6 Enable" "0,1"
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newline
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bitfld.long 0x0 5. "CH5,Channel 5 Enable" "0,1"
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bitfld.long 0x0 4. "CH4,Channel 4 Enable" "0,1"
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newline
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bitfld.long 0x0 3. "CH3,Channel 3 Enable" "0,1"
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bitfld.long 0x0 2. "CH2,Channel 2 Enable" "0,1"
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newline
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bitfld.long 0x0 1. "CH1,Channel 1 Enable" "0,1"
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bitfld.long 0x0 0. "CH0,Channel 0 Enable" "0,1"
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line.long 0x4 "CHDR,Channel Disable Register"
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bitfld.long 0x4 11. "CH11,Channel 11 Disable" "0,1"
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bitfld.long 0x4 10. "CH10,Channel 10 Disable" "0,1"
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newline
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bitfld.long 0x4 9. "CH9,Channel 9 Disable" "0,1"
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bitfld.long 0x4 8. "CH8,Channel 8 Disable" "0,1"
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newline
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bitfld.long 0x4 7. "CH7,Channel 7 Disable" "0,1"
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bitfld.long 0x4 6. "CH6,Channel 6 Disable" "0,1"
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newline
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bitfld.long 0x4 5. "CH5,Channel 5 Disable" "0,1"
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bitfld.long 0x4 4. "CH4,Channel 4 Disable" "0,1"
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newline
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bitfld.long 0x4 3. "CH3,Channel 3 Disable" "0,1"
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bitfld.long 0x4 2. "CH2,Channel 2 Disable" "0,1"
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newline
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bitfld.long 0x4 1. "CH1,Channel 1 Disable" "0,1"
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bitfld.long 0x4 0. "CH0,Channel 0 Disable" "0,1"
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rgroup.long 0x18++0x3
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line.long 0x0 "CHSR,Channel Status Register"
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bitfld.long 0x0 11. "CH11,Channel 11 Status" "0,1"
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bitfld.long 0x0 10. "CH10,Channel 10 Status" "0,1"
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newline
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bitfld.long 0x0 9. "CH9,Channel 9 Status" "0,1"
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bitfld.long 0x0 8. "CH8,Channel 8 Status" "0,1"
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newline
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bitfld.long 0x0 7. "CH7,Channel 7 Status" "0,1"
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bitfld.long 0x0 6. "CH6,Channel 6 Status" "0,1"
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newline
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bitfld.long 0x0 5. "CH5,Channel 5 Status" "0,1"
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bitfld.long 0x0 4. "CH4,Channel 4 Status" "0,1"
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newline
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bitfld.long 0x0 3. "CH3,Channel 3 Status" "0,1"
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bitfld.long 0x0 2. "CH2,Channel 2 Status" "0,1"
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newline
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bitfld.long 0x0 1. "CH1,Channel 1 Status" "0,1"
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bitfld.long 0x0 0. "CH0,Channel 0 Status" "0,1"
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rgroup.long 0x20++0x3
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line.long 0x0 "LCDR,Last Converted Data Register"
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hexmask.long.byte 0x0 24.--28. 1. "CHNBOSR,Channel Number in Oversampling Mode"
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hexmask.long.word 0x0 0.--15. 1. "LDATA,Last Data Converted"
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wgroup.long 0x24++0x7
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line.long 0x0 "IER,Interrupt Enable Register"
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bitfld.long 0x0 30. "NOPEN,No Pen Contact Interrupt Enable" "0,1"
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bitfld.long 0x0 29. "PEN,Pen Contact Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "COMPE,Comparison Event Interrupt Enable" "0,1"
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bitfld.long 0x0 25. "GOVRE,General Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 24. "DRDY,Data Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 22. "PRDY,Touchscreen Measure Pressure Ready Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 21. "YRDY,Touchscreen Measure YPOS Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "XRDY,Touchscreen Measure XPOS Ready Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "LCCHG,Last Channel Change Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "EOC11,End of Conversion Interrupt Enable 11" "0,1"
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newline
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bitfld.long 0x0 10. "EOC10,End of Conversion Interrupt Enable 10" "0,1"
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bitfld.long 0x0 9. "EOC9,End of Conversion Interrupt Enable 9" "0,1"
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newline
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bitfld.long 0x0 8. "EOC8,End of Conversion Interrupt Enable 8" "0,1"
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bitfld.long 0x0 7. "EOC7,End of Conversion Interrupt Enable 7" "0,1"
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newline
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bitfld.long 0x0 6. "EOC6,End of Conversion Interrupt Enable 6" "0,1"
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bitfld.long 0x0 5. "EOC5,End of Conversion Interrupt Enable 5" "0,1"
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newline
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bitfld.long 0x0 4. "EOC4,End of Conversion Interrupt Enable 4" "0,1"
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bitfld.long 0x0 3. "EOC3,End of Conversion Interrupt Enable 3" "0,1"
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newline
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bitfld.long 0x0 2. "EOC2,End of Conversion Interrupt Enable 2" "0,1"
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bitfld.long 0x0 1. "EOC1,End of Conversion Interrupt Enable 1" "0,1"
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newline
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bitfld.long 0x0 0. "EOC0,End of Conversion Interrupt Enable 0" "0,1"
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line.long 0x4 "IDR,Interrupt Disable Register"
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bitfld.long 0x4 30. "NOPEN,No Pen Contact Interrupt Disable" "0,1"
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bitfld.long 0x4 29. "PEN,Pen Contact Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 26. "COMPE,Comparison Event Interrupt Disable" "0,1"
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bitfld.long 0x4 25. "GOVRE,General Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 24. "DRDY,Data Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 22. "PRDY,Touchscreen Measure Pressure Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 21. "YRDY,Touchscreen Measure YPOS Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "XRDY,Touchscreen Measure XPOS Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 19. "LCCHG,Last Channel Change Interrupt Disable" "0,1"
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bitfld.long 0x4 11. "EOC11,End of Conversion Interrupt Disable 11" "0,1"
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newline
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bitfld.long 0x4 10. "EOC10,End of Conversion Interrupt Disable 10" "0,1"
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bitfld.long 0x4 9. "EOC9,End of Conversion Interrupt Disable 9" "0,1"
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newline
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bitfld.long 0x4 8. "EOC8,End of Conversion Interrupt Disable 8" "0,1"
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bitfld.long 0x4 7. "EOC7,End of Conversion Interrupt Disable 7" "0,1"
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newline
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bitfld.long 0x4 6. "EOC6,End of Conversion Interrupt Disable 6" "0,1"
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bitfld.long 0x4 5. "EOC5,End of Conversion Interrupt Disable 5" "0,1"
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newline
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bitfld.long 0x4 4. "EOC4,End of Conversion Interrupt Disable 4" "0,1"
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bitfld.long 0x4 3. "EOC3,End of Conversion Interrupt Disable 3" "0,1"
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newline
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bitfld.long 0x4 2. "EOC2,End of Conversion Interrupt Disable 2" "0,1"
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bitfld.long 0x4 1. "EOC1,End of Conversion Interrupt Disable 1" "0,1"
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newline
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bitfld.long 0x4 0. "EOC0,End of Conversion Interrupt Disable 0" "0,1"
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rgroup.long 0x2C++0x7
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line.long 0x0 "IMR,Interrupt Mask Register"
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bitfld.long 0x0 30. "NOPEN,No Pen Contact Interrupt Mask" "0,1"
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bitfld.long 0x0 29. "PEN,Pen Contact Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "COMPE,Comparison Event Interrupt Mask" "0,1"
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bitfld.long 0x0 25. "GOVRE,General Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 24. "DRDY,Data Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 22. "PRDY,Touchscreen Measure Pressure Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 21. "YRDY,Touchscreen Measure YPOS Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "XRDY,Touchscreen Measure XPOS Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 19. "LCCHG,Last Channel Change Interrupt Disable" "0,1"
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bitfld.long 0x0 11. "EOC11,End of Conversion Interrupt Mask 11" "0,1"
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newline
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bitfld.long 0x0 10. "EOC10,End of Conversion Interrupt Mask 10" "0,1"
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bitfld.long 0x0 9. "EOC9,End of Conversion Interrupt Mask 9" "0,1"
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newline
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bitfld.long 0x0 8. "EOC8,End of Conversion Interrupt Mask 8" "0,1"
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bitfld.long 0x0 7. "EOC7,End of Conversion Interrupt Mask 7" "0,1"
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newline
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bitfld.long 0x0 6. "EOC6,End of Conversion Interrupt Mask 6" "0,1"
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bitfld.long 0x0 5. "EOC5,End of Conversion Interrupt Mask 5" "0,1"
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newline
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bitfld.long 0x0 4. "EOC4,End of Conversion Interrupt Mask 4" "0,1"
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bitfld.long 0x0 3. "EOC3,End of Conversion Interrupt Mask 3" "0,1"
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newline
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bitfld.long 0x0 2. "EOC2,End of Conversion Interrupt Mask 2" "0,1"
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bitfld.long 0x0 1. "EOC1,End of Conversion Interrupt Mask 1" "0,1"
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newline
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bitfld.long 0x0 0. "EOC0,End of Conversion Interrupt Mask 0" "0,1"
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line.long 0x4 "ISR,Interrupt Status Register"
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bitfld.long 0x4 31. "PENS,Pen Detect Status" "0,1"
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bitfld.long 0x4 30. "NOPEN,No Pen Contact (cleared on read)" "0,1"
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newline
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bitfld.long 0x4 29. "PEN,Pen contact (cleared on read)" "0,1"
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bitfld.long 0x4 26. "COMPE,Comparison Event (cleared on read)" "0,1"
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newline
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bitfld.long 0x4 25. "GOVRE,General Overrun Error (cleared on read)" "0,1"
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bitfld.long 0x4 24. "DRDY,Data Ready (automatically set / cleared)" "0,1"
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newline
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bitfld.long 0x4 22. "PRDY,Touchscreen Pressure Measure Ready (cleared on read)" "0,1"
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bitfld.long 0x4 21. "YRDY,Touchscreen YPOS Measure Ready (cleared on read)" "0,1"
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newline
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bitfld.long 0x4 20. "XRDY,Touchscreen XPOS Measure Ready (cleared on read)" "0,1"
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bitfld.long 0x4 19. "LCCHG,Last Channel Change (cleared on read)" "0,1"
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newline
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bitfld.long 0x4 11. "EOC11,End of Conversion 11 (automatically set / cleared)" "0,1"
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bitfld.long 0x4 10. "EOC10,End of Conversion 10 (automatically set / cleared)" "0,1"
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newline
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bitfld.long 0x4 9. "EOC9,End of Conversion 9 (automatically set / cleared)" "0,1"
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bitfld.long 0x4 8. "EOC8,End of Conversion 8 (automatically set / cleared)" "0,1"
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newline
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bitfld.long 0x4 7. "EOC7,End of Conversion 7 (automatically set / cleared)" "0,1"
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bitfld.long 0x4 6. "EOC6,End of Conversion 6 (automatically set / cleared)" "0,1"
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newline
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bitfld.long 0x4 5. "EOC5,End of Conversion 5 (automatically set / cleared)" "0,1"
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bitfld.long 0x4 4. "EOC4,End of Conversion 4 (automatically set / cleared)" "0,1"
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newline
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bitfld.long 0x4 3. "EOC3,End of Conversion 3 (automatically set / cleared)" "0,1"
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bitfld.long 0x4 2. "EOC2,End of Conversion 2 (automatically set / cleared)" "0,1"
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newline
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bitfld.long 0x4 1. "EOC1,End of Conversion 1 (automatically set / cleared)" "0,1"
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bitfld.long 0x4 0. "EOC0,End of Conversion 0 (automatically set / cleared)" "0,1"
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group.long 0x34++0x7
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line.long 0x0 "LCTMR,Last Channel Trigger Mode Register"
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bitfld.long 0x0 4.--5. "CMPMOD,Last Channel Comparison Mode" "0: Generates the ADC_ISR.LCCHG flag when the..,1: Generates the ADC_ISR.LCCHG flag when the..,2: Generates the ADC_ISR.LCCHG flag when the..,3: Generates the ADC_ISR.LCCHG flag when the.."
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bitfld.long 0x0 0. "DUALTRIG,Dual Trigger ON" "0,1"
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line.long 0x4 "LCCWR,Last Channel Compare Window Register"
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hexmask.long.word 0x4 16.--27. 1. "HIGHTHRES,High Threshold"
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hexmask.long.word 0x4 0.--11. 1. "LOWTHRES,Low Threshold"
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rgroup.long 0x3C++0x3
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line.long 0x0 "OVER,Overrun Status Register"
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bitfld.long 0x0 11. "OVRE11,Overrun Error 11" "0,1"
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bitfld.long 0x0 10. "OVRE10,Overrun Error 10" "0,1"
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newline
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bitfld.long 0x0 9. "OVRE9,Overrun Error 9" "0,1"
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bitfld.long 0x0 8. "OVRE8,Overrun Error 8" "0,1"
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newline
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bitfld.long 0x0 7. "OVRE7,Overrun Error 7" "0,1"
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bitfld.long 0x0 6. "OVRE6,Overrun Error 6" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE5,Overrun Error 5" "0,1"
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bitfld.long 0x0 4. "OVRE4,Overrun Error 4" "0,1"
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newline
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bitfld.long 0x0 3. "OVRE3,Overrun Error 3" "0,1"
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bitfld.long 0x0 2. "OVRE2,Overrun Error 2" "0,1"
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newline
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bitfld.long 0x0 1. "OVRE1,Overrun Error 1" "0,1"
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bitfld.long 0x0 0. "OVRE0,Overrun Error 0" "0,1"
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group.long 0x40++0x7
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line.long 0x0 "EMR,Extended Mode Register"
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bitfld.long 0x0 28.--29. "ADCMODE,ADC Running Mode" "0: Normal mode of operation.,1: Offset Error mode to measure the offset error.,2: Gain Error mode to measure the gain error. See..,3: Gain Error mode to measure the gain error. See.."
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bitfld.long 0x0 25.--26. "SIGNMODE,Sign Mode" "0: Single-Ended channels: Unsigned conversions.,1: Single-Ended channels: Signed conversions.,2: All channels: Unsigned conversions.,3: All channels: Signed conversions."
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newline
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bitfld.long 0x0 24. "TAG,Tag of ADC_LCDR" "0,1"
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bitfld.long 0x0 22. "TRACKX4,Tracking Time x4" "0,1"
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newline
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bitfld.long 0x0 21. "SRCCLK,External Clock Selection" "0: The peripheral clock is the source for the ADC..,1: GCLK is the source clock for the ADC prescaler.."
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bitfld.long 0x0 20. "ASTE,Averaging on Single Trigger Event" "0: The average requests several trigger events.,1: The average requests only one trigger event."
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newline
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bitfld.long 0x0 16.--18. "OSR,Over Sampling Rate" "0: No averaging. ADC sample rate is maximum.,1: 1-bit enhanced resolution by averaging. ADC..,2: 2-bit enhanced resolution by averaging. ADC..,3: 3-bit enhanced resolution by averaging. ADC..,4: 4-bit enhanced resolution by averaging. ADC..,?,?,?"
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bitfld.long 0x0 12.--13. "CMPFILTER,Compare Event Filtering" "0,1,2,3"
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newline
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bitfld.long 0x0 9. "CMPALL,Compare All Channels" "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "CMPSEL,Comparison Selected Channel"
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newline
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bitfld.long 0x0 2. "CMPTYPE,Comparison Type" "0: Any conversion is performed and comparison..,1: Comparison conditions must be met to start the.."
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bitfld.long 0x0 0.--1. "CMPMODE,Comparison Mode" "0: When the converted data is lower than the low..,1: When the converted data is higher than the high..,2: When the converted data is in the comparison..,3: When the converted data is out of the comparison.."
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line.long 0x4 "CWR,Compare Window Register"
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hexmask.long.word 0x4 16.--31. 1. "HIGHTHRES,High Threshold"
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hexmask.long.word 0x4 0.--15. 1. "LOWTHRES,Low Threshold"
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group.long 0x4C++0x3
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line.long 0x0 "CCR,Channel Configuration Register"
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bitfld.long 0x0 27. "DIFF11,Differential Inputs for Channel 11" "0,1"
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bitfld.long 0x0 26. "DIFF10,Differential Inputs for Channel 10" "0,1"
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newline
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bitfld.long 0x0 25. "DIFF9,Differential Inputs for Channel 9" "0,1"
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bitfld.long 0x0 24. "DIFF8,Differential Inputs for Channel 8" "0,1"
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newline
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bitfld.long 0x0 23. "DIFF7,Differential Inputs for Channel 7" "0,1"
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bitfld.long 0x0 22. "DIFF6,Differential Inputs for Channel 6" "0,1"
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newline
|
|
bitfld.long 0x0 21. "DIFF5,Differential Inputs for Channel 5" "0,1"
|
|
bitfld.long 0x0 20. "DIFF4,Differential Inputs for Channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DIFF3,Differential Inputs for Channel 3" "0,1"
|
|
bitfld.long 0x0 18. "DIFF2,Differential Inputs for Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DIFF1,Differential Inputs for Channel 1" "0,1"
|
|
bitfld.long 0x0 16. "DIFF0,Differential Inputs for Channel 0" "0,1"
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "CDR[$1],Channel Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted Data"
|
|
repeat.end
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "ACR,Analog Control Register"
|
|
bitfld.long 0x0 8.--9. "IBCTL,ADC Bias Current Control" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PENDETSENS,Pen Detection Sensitivity" "0,1,2,3"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "PDR,Pseudo-Differential Register"
|
|
bitfld.long 0x0 15. "PDIFF15,Pseudo-Differential Inputs for Channel 15" "0,1"
|
|
bitfld.long 0x0 14. "PDIFF14,Pseudo-Differential Inputs for Channel 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PDIFF13,Pseudo-Differential Inputs for Channel 13" "0,1"
|
|
bitfld.long 0x0 12. "PDIFF12,Pseudo-Differential Inputs for Channel 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PDIFF11,Pseudo-Differential Inputs for Channel 11" "0,1"
|
|
bitfld.long 0x0 10. "PDIFF10,Pseudo-Differential Inputs for Channel 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PDIFF9,Pseudo-Differential Inputs for Channel 9" "0,1"
|
|
bitfld.long 0x0 8. "PDIFF8,Pseudo-Differential Inputs for Channel 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PDIFF7,Pseudo-Differential Inputs for Channel 7" "0,1"
|
|
bitfld.long 0x0 6. "PDIFF6,Pseudo-Differential Inputs for Channel 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PDIFF5,Pseudo-Differential Inputs for Channel 5" "0,1"
|
|
bitfld.long 0x0 4. "PDIFF4,Pseudo-Differential Inputs for Channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PDIFF3,Pseudo-Differential Inputs for Channel 3" "0,1"
|
|
bitfld.long 0x0 2. "PDIFF2,Pseudo-Differential Inputs for Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PDIFF1,Pseudo-Differential Inputs for Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "PDIFF0,Pseudo-Differential Inputs for Channel 0" "0,1"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "TSMR,Touchscreen Mode Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PENDBC,Pen Detect Debouncing Period"
|
|
bitfld.long 0x0 24. "PENDET,Pen Contact Detection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "NOTSDMA,No TouchScreen DMA" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TSSCTIM,Touchscreen Switches Closure Time"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "TSFREQ,Touchscreen Frequency"
|
|
bitfld.long 0x0 4.--5. "TSAV,Touchscreen Average" "0: No Filtering. Only one ADC conversion per measure,1: Averages 2 ADC conversions,2: Averages 4 ADC conversions,3: Averages 8 ADC conversions"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TSMODE,Touchscreen Mode" "0: No Touchscreen,1: 4-wire Touchscreen without pressure measurement,2: 4-wire Touchscreen with pressure measurement,3: 5-wire Touchscreen"
|
|
rgroup.long 0xB4++0xB
|
|
line.long 0x0 "XPOSR,Touchscreen X Position Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "XSCALE,Scale of XPOS"
|
|
hexmask.long.word 0x0 0.--11. 1. "XPOS,X Position"
|
|
line.long 0x4 "YPOSR,Touchscreen Y Position Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "YSCALE,Scale of YPOS"
|
|
hexmask.long.word 0x4 0.--11. 1. "YPOS,Y Position"
|
|
line.long 0x8 "PRESSR,Touchscreen Pressure Register"
|
|
hexmask.long.word 0x8 16.--27. 1. "Z2,Data of Z2 Measurement"
|
|
hexmask.long.word 0x8 0.--11. 1. "Z1,Data of Z1 Measurement"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "TRGR,Trigger Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TRGPER,Trigger Period"
|
|
bitfld.long 0x0 0.--2. "TRGMOD,Trigger Mode" "0: No hardware trigger enabled only software..,1: Rising edge of the selected hardware trigger..,2: Falling edge of the selected hardware trigger..,3: Any edge of the selected hardware trigger event,4: Pen Detect Trigger (shall be selected only if..,5: ADC internal hardware periodic trigger (see..,6: Continuous mode,?"
|
|
group.long 0xD4++0xB
|
|
line.long 0x0 "CVR,Correction Values Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "GAINCORR,Gain Correction"
|
|
hexmask.long.word 0x0 0.--15. 1. "OFFSETCORR,Offset Correction"
|
|
line.long 0x4 "CECR,Channel Error Correction Register"
|
|
bitfld.long 0x4 11. "ECORR11,Error Correction Enable for channel 11" "0,1"
|
|
bitfld.long 0x4 10. "ECORR10,Error Correction Enable for channel 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ECORR9,Error Correction Enable for channel 9" "0,1"
|
|
bitfld.long 0x4 8. "ECORR8,Error Correction Enable for channel 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ECORR7,Error Correction Enable for channel 7" "0,1"
|
|
bitfld.long 0x4 6. "ECORR6,Error Correction Enable for channel 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ECORR5,Error Correction Enable for channel 5" "0,1"
|
|
bitfld.long 0x4 4. "ECORR4,Error Correction Enable for channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ECORR3,Error Correction Enable for channel 3" "0,1"
|
|
bitfld.long 0x4 2. "ECORR2,Error Correction Enable for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ECORR1,Error Correction Enable for channel 1" "0,1"
|
|
bitfld.long 0x4 0. "ECORR0,Error Correction Enable for channel 0" "0,1"
|
|
line.long 0x8 "TSCVR,Touchscreen Correction Values Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "TSGAINCORR,Touchscreen Gain Correction"
|
|
hexmask.long.word 0x8 0.--15. 1. "TSOFFSETCORR,Touchscreen Offset Correction"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCTEN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "AES (Advanced Encryption Standard)"
|
|
base ad:0xF0034000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "UNLOCK,Unlock Processing" "0,1"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Start Processing" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 31. "TAMPCLR,Tamper Clear Enable" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CKEY,Key"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "CFBS,Cipher Feedback Data Size" "0: 128-bit,1: 64-bit,2: 32-bit,3: 16-bit,4: 8-bit,?,?,?"
|
|
bitfld.long 0x0 15. "LOD,Last Output Data Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "OPMOD,Operating Mode" "0: ECB: Electronic Codebook mode,1: CBC: Cipher Block Chaining mode,2: OFB: Output Feedback mode,3: CFB: Cipher Feedback mode,4: CTR: Counter mode (16-bit internal counter),5: GCM: Galois/Counter mode,6: XTS: XEX-based tweaked-codebook mode,?"
|
|
bitfld.long 0x0 10.--11. "KEYSIZE,Key Size" "0: AES Key Size is 128 bits,1: AES Key Size is 192 bits,2: AES Key Size is 256 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "SMOD,Start Mode" "0: Manual Mode,1: Auto Mode,2: AES_IDATAR0 access only Auto Mode (DMA),?"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PROCDLY,Processing Delay"
|
|
newline
|
|
bitfld.long 0x0 3. "DUALBUFF,Dual Input Buffer" "0: AES_IDATARx cannot be written during processing..,1: AES_IDATARx can be written during processing of.."
|
|
bitfld.long 0x0 1. "GTAGEN,GCM Automatic Tag Generation Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CIPHER,Processing Mode" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 19. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "PLENERR,Padding Length Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "EOPAD,End of Padding Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "TAGRDY,GCM Tag Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 19. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "PLENERR,Padding Length Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "EOPAD,End of Padding Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "TAGRDY,GCM Tag Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 19. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "PLENERR,Padding Length Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "EOPAD,End of Padding Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "TAGRDY,GCM Tag Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 19. "SECE,Security and/or Safety Event (cleared on read)" "0,1"
|
|
bitfld.long 0x4 18. "PLENERR,Padding Length Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "EOPAD,End of Padding" "0,1"
|
|
bitfld.long 0x4 16. "TAGRDY,GCM Tag Ready" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "URAT,Unspecified Register Access (cleared by writing SWRST in AES_CR)"
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)" "0,1"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "KEYWR[$1],Key Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEYW,Key Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "ODATAR[$1],Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "IVR[$1],Initialization Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "IV,Initialization Vector"
|
|
repeat.end
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "AADLENR,Additional Authenticated Data Length Register"
|
|
hexmask.long 0x0 0.--31. 1. "AADLEN,Additional Authenticated Data Length"
|
|
line.long 0x4 "CLENR,Plaintext/Ciphertext Length Register"
|
|
hexmask.long 0x4 0.--31. 1. "CLEN,Plaintext/Ciphertext Length"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x78)++0x3
|
|
line.long 0x0 "GHASHR[$1],GCM Intermediate Hash Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "GHASH,Intermediate GCM Hash Word x"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x88)++0x3
|
|
line.long 0x0 "TAGR[$1],GCM Authentication Tag Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "TAG,GCM Authentication Tag x"
|
|
repeat.end
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "CTRR,GCM Encryption Counter Value Register"
|
|
hexmask.long 0x0 0.--31. 1. "CTR,GCM Encryption Counter"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x9C)++0x3
|
|
line.long 0x0 "GCMHR[$1],GCM H Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "H,GCM H Word x"
|
|
repeat.end
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 31. "BPE,Block Processing End" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NHEAD,IPSEC Next Header"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "PADLEN,Auto Padding Length"
|
|
bitfld.long 0x0 7. "PKRS,Private Key Internal Register Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PLIPD,Protocol Layer Improved Performance Decipher" "0,1"
|
|
bitfld.long 0x0 4. "PLIPEN,Protocol Layer Improved Performance Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "APM,Auto Padding Mode" "0,1"
|
|
bitfld.long 0x0 0. "APEN,Auto Padding Enable" "0,1"
|
|
line.long 0x4 "BCNT,Byte Counter Register"
|
|
hexmask.long 0x4 0.--31. 1. "BCNT,Auto Padding Byte Counter"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC0)++0x3
|
|
line.long 0x0 "TWR[$1],Tweak Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "TWEAK,Tweak Word x"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0xD0)++0x3
|
|
line.long 0x0 "ALPHAR[$1],Alpha Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "ALPHA,Alpha Word x"
|
|
repeat.end
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 5.--7. "ACTION,Action on Abnormal Event Detection" "0: No action (stop or clear key) is performed when..,1: If a processing is in progress when the..,2: If a processing is in progress when the..,3: If a processing is in progress when the..,4: If a processing is in progress when the..,5: If a processing is in progress when the..,6: If a processing is in progress when the..,?"
|
|
newline
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Configuration Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: An access is performed into key input data.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 4. "PKRPVS,Private Key Internal Register Protection Violation Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "AIC (Advanced Interrupt Controller)"
|
|
base ad:0xFFFFF100
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "SSR,Source Select Register"
|
|
hexmask.long.byte 0x0 0.--6. 1. "INTSEL,Interrupt Line Selection"
|
|
line.long 0x4 "SMR,Source Mode Register"
|
|
bitfld.long 0x4 5.--6. "SRCTYPE,Interrupt Source Type" "0: High-level sensitive for internal source.,1: Negative-edge triggered for external source,2: High-level sensitive for internal source.,3: Positive-edge triggered for external source"
|
|
bitfld.long 0x4 0.--2. "PRIOR,Priority Level" "0: Minimum priority,1: Very low priority,2: Low priority,3: Medium priority,4: Medium-high priority,5: High priority,6: Very high priority,7: Maximum priority"
|
|
line.long 0x8 "SVR,Source Vector Register"
|
|
hexmask.long 0x8 0.--31. 1. "VECTOR,Source Vector"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "IVR,Interrupt Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "IRQV,Interrupt Vector Register"
|
|
line.long 0x4 "FVR,FIQ Vector Register"
|
|
hexmask.long 0x4 0.--31. 1. "FIQV,FIQ Vector Register"
|
|
line.long 0x8 "ISR,Interrupt Status Register"
|
|
hexmask.long.byte 0x8 0.--6. 1. "IRQID,Current Interrupt Identifier"
|
|
rgroup.long 0x20++0x17
|
|
line.long 0x0 "IPR0,Interrupt Pending Register 0"
|
|
bitfld.long 0x0 31. "PID31,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 30. "PID30,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 29. "PID29,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 28. "PID28,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 27. "PID27,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 26. "PID26,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 25. "PID25,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "PID24,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 23. "PID23,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 22. "PID22,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 21. "PID21,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 20. "PID20,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 19. "PID19,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 18. "PID18,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PID17,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 16. "PID16,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 15. "PID15,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 14. "PID14,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 13. "PID13,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 12. "PID12,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 11. "PID11,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PID10,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 9. "PID9,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 8. "PID8,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 7. "PID7,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 6. "PID6,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 5. "PID5,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 4. "PID4,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PID3,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 2. "PID2,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 1. "SYS,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 0. "FIQ,Interrupt Pending" "0,1"
|
|
line.long 0x4 "IPR1,Interrupt Pending Register 1"
|
|
bitfld.long 0x4 31. "PID63,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 30. "PID62,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 29. "PID61,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 28. "PID60,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 27. "PID59,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 26. "PID58,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 25. "PID57,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "PID56,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 23. "PID55,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 22. "PID54,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 21. "PID53,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 20. "PID52,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 19. "PID51,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 18. "PID50,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PID49,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 16. "PID48,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 15. "PID47,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 14. "PID46,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 13. "PID45,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 12. "PID44,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 11. "PID43,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "PID42,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 9. "PID41,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 8. "PID40,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 7. "PID39,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 6. "PID38,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 5. "PID37,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 4. "PID36,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PID35,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 2. "PID34,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 1. "PID33,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 0. "PID32,Interrupt Pending" "0,1"
|
|
line.long 0x8 "IPR2,Interrupt Pending Register 2"
|
|
bitfld.long 0x8 31. "PID95,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 30. "PID94,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 29. "PID93,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 28. "PID92,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 27. "PID91,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 26. "PID90,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 25. "PID89,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "PID88,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 23. "PID87,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 22. "PID86,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 21. "PID85,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 20. "PID84,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 19. "PID83,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 18. "PID82,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PID81,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 16. "PID80,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 15. "PID79,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 14. "PID78,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 13. "PID77,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 12. "PID76,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 11. "PID75,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "PID74,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 9. "PID73,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 8. "PID72,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 7. "PID71,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 6. "PID70,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 5. "PID69,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 4. "PID68,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PID67,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 2. "PID66,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 1. "PID65,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 0. "PID64,Interrupt Pending" "0,1"
|
|
line.long 0xC "IPR3,Interrupt Pending Register 3"
|
|
bitfld.long 0xC 31. "PID127,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 30. "PID126,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 29. "PID125,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 28. "PID124,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 27. "PID123,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 26. "PID122,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 25. "PID121,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 24. "PID120,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 23. "PID119,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 22. "PID118,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 21. "PID117,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 20. "PID116,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 19. "PID115,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 18. "PID114,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PID113,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 16. "PID112,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 15. "PID111,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 14. "PID110,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 13. "PID109,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 12. "PID108,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 11. "PID107,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "PID106,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 9. "PID105,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 8. "PID104,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 7. "PID103,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 6. "PID102,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 5. "PID101,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 4. "PID100,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PID99,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 2. "PID98,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 1. "PID97,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 0. "PID96,Interrupt Pending" "0,1"
|
|
line.long 0x10 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x10 0. "INTM,Interrupt Mask" "0,1"
|
|
line.long 0x14 "CISR,Core Interrupt Status Register"
|
|
bitfld.long 0x14 1. "NIRQ,NIRQ Status" "0,1"
|
|
bitfld.long 0x14 0. "NFIQ,NFIQ Status" "0,1"
|
|
wgroup.long 0x38++0x3
|
|
line.long 0x0 "EOICR,End of Interrupt Command Register"
|
|
bitfld.long 0x0 0. "ENDIT,Interrupt Processing Complete Command" "0,1"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "SPU,Spurious Interrupt Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "SIVR,Spurious Interrupt Vector Register"
|
|
wgroup.long 0x40++0x17
|
|
line.long 0x0 "IECR,Interrupt Enable Command Register"
|
|
bitfld.long 0x0 0. "INTEN,Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDCR,Interrupt Disable Command Register"
|
|
bitfld.long 0x4 0. "INTD,Interrupt Disable" "0,1"
|
|
line.long 0x8 "ICCR,Interrupt Clear Command Register"
|
|
bitfld.long 0x8 0. "INTCLR,Interrupt Clear" "0,1"
|
|
line.long 0xC "ISCR,Interrupt Set Command Register"
|
|
bitfld.long 0xC 0. "INTSET,Interrupt Set" "0,1"
|
|
line.long 0x10 "FFER,Fast Forcing Enable Register"
|
|
bitfld.long 0x10 0. "FFEN,Fast Forcing Enable" "0,1"
|
|
line.long 0x14 "FFDR,Fast Forcing Disable Register"
|
|
bitfld.long 0x14 0. "FFDIS,Fast Forcing Disable" "0,1"
|
|
rgroup.long 0x58++0x3
|
|
line.long 0x0 "FFSR,Fast Forcing Status Register"
|
|
bitfld.long 0x0 0. "FFS,Fast Forcing Status" "0,1"
|
|
wgroup.long 0x60++0x7
|
|
line.long 0x0 "SVRRER,SVR Return Enable Register"
|
|
bitfld.long 0x0 0. "SVRREN,SVR Return Enable" "0,1"
|
|
line.long 0x4 "SVRRDR,SVR Return Disable Register"
|
|
bitfld.long 0x4 0. "SVRRDIS,SVR Return Disable" "0,1"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "SVRRSR,SVR Return Status Register"
|
|
bitfld.long 0x0 0. "SVRRS,SVR Return Status" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "DCR,Debug Control Register"
|
|
bitfld.long 0x0 1. "GMSK,General Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "PROT,Protection Mode" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "BSC (Boot Sequence Controller)"
|
|
base ad:0xFFFFFE54
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,Boot Sequence Controller Configuration Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WPKEY,Write Protection Key (Write-only)"
|
|
bitfld.long 0x0 0.--2. "BOOT,Boot Media Sequence" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "CAN (Controller Area Network)"
|
|
base ad:0x0
|
|
tree "CAN0"
|
|
base ad:0xF8000000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 24.--26. "RXSYNC,Reception Synchronization Stage (not readable)" "0: Rx Signal with Double Synchro Stages (2 Positive..,1: Rx Signal with Double Synchro Stages (One..,2: Rx Signal with Single Synchro Stage (Positive..,3: Rx Signal with No Synchro Stage,?,?,?,?"
|
|
bitfld.long 0x0 7. "DRPT,Disable Repeat" "0,1"
|
|
bitfld.long 0x0 6. "TIMFRZ,Enable Timer Freeze" "0,1"
|
|
bitfld.long 0x0 5. "TTM,Disable/Enable Time-Triggered Mode" "0,1"
|
|
bitfld.long 0x0 4. "TEOF,Timestamp messages at each end of Frame" "0,1"
|
|
bitfld.long 0x0 3. "OVL,Disable/Enable Overload Frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ABM,Disable/Enable Autobaud/Listen mode" "0,1"
|
|
bitfld.long 0x0 1. "LPM,Disable/Enable Low-power Mode" "0,1"
|
|
bitfld.long 0x0 0. "CANEN,CAN Controller Enable" "0,1"
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "BERR,Bit Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 27. "FERR,Form Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "AERR,Acknowledgment Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 25. "SERR,Stuffing Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "CERR,CRC Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 23. "TSTP,TimeStamp Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "TOVF,Timer Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "WAKEUP,Wakeup Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "SLEEP,Sleep Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 19. "BOFF,Bus Off Mode Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "ERRP,Error Passive Mode Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "WARN,Warning Limit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ERRA,Error Active Mode Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "MB7,Mailbox 7 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "MB6,Mailbox 6 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "MB5,Mailbox 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "MB4,Mailbox 4 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "MB3,Mailbox 3 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MB2,Mailbox 2 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "MB1,Mailbox 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "MB0,Mailbox 0 Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 28. "BERR,Bit Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 27. "FERR,Form Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "AERR,Acknowledgment Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 25. "SERR,Stuffing Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "CERR,CRC Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 23. "TSTP,TimeStamp Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "TOVF,Timer Overflow Interrupt" "0,1"
|
|
bitfld.long 0x4 21. "WAKEUP,Wakeup Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "SLEEP,Sleep Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 19. "BOFF,Bus Off Mode Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "ERRP,Error Passive Mode Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "WARN,Warning Limit Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "ERRA,Error Active Mode Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "MB7,Mailbox 7 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "MB6,Mailbox 6 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "MB5,Mailbox 5 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "MB4,Mailbox 4 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "MB3,Mailbox 3 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MB2,Mailbox 2 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "MB1,Mailbox 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "MB0,Mailbox 0 Interrupt Disable" "0,1"
|
|
rgroup.long 0xC++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "BERR,Bit Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 27. "FERR,Form Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "AERR,Acknowledgment Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 25. "SERR,Stuffing Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "CERR,CRC Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 23. "TSTP,Timestamp Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "TOVF,Timer Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 21. "WAKEUP,Wakeup Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "SLEEP,Sleep Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 19. "BOFF,Bus Off Mode Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "ERRP,Error Passive Mode Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 17. "WARN,Warning Limit Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ERRA,Error Active Mode Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "MB7,Mailbox 7 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "MB6,Mailbox 6 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "MB5,Mailbox 5 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "MB4,Mailbox 4 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "MB3,Mailbox 3 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MB2,Mailbox 2 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "MB1,Mailbox 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "MB0,Mailbox 0 Interrupt Mask" "0,1"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 31. "OVLSY,Overload busy" "0,1"
|
|
bitfld.long 0x4 30. "TBSY,Transmitter Busy" "0,1"
|
|
bitfld.long 0x4 29. "RBSY,Receiver Busy" "0,1"
|
|
bitfld.long 0x4 28. "BERR,Bit Error (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 27. "FERR,Form Error (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 26. "AERR,Acknowledgment Error (automatically cleared by reading CAN_SR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "SERR,Mailbox Stuffing Error (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 24. "CERR,Mailbox CRC Error (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 23. "TSTP,Timestamp (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 22. "TOVF,Timer Overflow (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 21. "WAKEUP,CAN Controller is not in Low-power Mode" "0,1"
|
|
bitfld.long 0x4 20. "SLEEP,CAN Controller in Low-power Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "BOFF,Bus Off Mode (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 18. "ERRP,Error Passive Mode (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 17. "WARN,Warning Limit (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 16. "ERRA,Error Active Mode (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 7. "MB7,Mailbox 7 Event" "0,1"
|
|
bitfld.long 0x4 6. "MB6,Mailbox 6 Event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MB5,Mailbox 5 Event" "0,1"
|
|
bitfld.long 0x4 4. "MB4,Mailbox 4 Event" "0,1"
|
|
bitfld.long 0x4 3. "MB3,Mailbox 3 Event" "0,1"
|
|
bitfld.long 0x4 2. "MB2,Mailbox 2 Event" "0,1"
|
|
bitfld.long 0x4 1. "MB1,Mailbox 1 Event" "0,1"
|
|
bitfld.long 0x4 0. "MB0,Mailbox 0 Event" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "BR,Baudrate Register"
|
|
bitfld.long 0x0 24. "SMP,Sampling Mode" "0: The incoming bit stream is sampled once at..,1: The incoming bit stream is sampled three times.."
|
|
hexmask.long.byte 0x0 16.--22. 1. "BRP,Baudrate Prescaler"
|
|
bitfld.long 0x0 12.--13. "SJW,Re-synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x0 8.--10. "PROPAG,Programming Time Segment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PHASE1,Phase 1 Segment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "PHASE2,Phase 2 Segment" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "TIM,Timer Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TIMER,Timer"
|
|
line.long 0x4 "TIMESTP,Timestamp Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MTIMESTAMP,Timestamp"
|
|
line.long 0x8 "ECR,Error Counter Register"
|
|
hexmask.long.word 0x8 16.--24. 1. "TEC,Transmit Error Counter"
|
|
hexmask.long.byte 0x8 0.--7. 1. "REC,Receive Error Counter"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x0 "TCR,Transfer Command Register"
|
|
bitfld.long 0x0 31. "TIMRST,Timer Reset" "0,1"
|
|
bitfld.long 0x0 7. "MB7,Transfer Request for Mailbox 7" "0,1"
|
|
bitfld.long 0x0 6. "MB6,Transfer Request for Mailbox 6" "0,1"
|
|
bitfld.long 0x0 5. "MB5,Transfer Request for Mailbox 5" "0,1"
|
|
bitfld.long 0x0 4. "MB4,Transfer Request for Mailbox 4" "0,1"
|
|
bitfld.long 0x0 3. "MB3,Transfer Request for Mailbox 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MB2,Transfer Request for Mailbox 2" "0,1"
|
|
bitfld.long 0x0 1. "MB1,Transfer Request for Mailbox 1" "0,1"
|
|
bitfld.long 0x0 0. "MB0,Transfer Request for Mailbox 0" "0,1"
|
|
line.long 0x4 "ACR,Abort Command Register"
|
|
bitfld.long 0x4 7. "MB7,Abort Request for Mailbox 7" "0,1"
|
|
bitfld.long 0x4 6. "MB6,Abort Request for Mailbox 6" "0,1"
|
|
bitfld.long 0x4 5. "MB5,Abort Request for Mailbox 5" "0,1"
|
|
bitfld.long 0x4 4. "MB4,Abort Request for Mailbox 4" "0,1"
|
|
bitfld.long 0x4 3. "MB3,Abort Request for Mailbox 3" "0,1"
|
|
bitfld.long 0x4 2. "MB2,Abort Request for Mailbox 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MB1,Abort Request for Mailbox 1" "0,1"
|
|
bitfld.long 0x4 0. "MB0,Abort Request for Mailbox 0" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key Password"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0xF8000200 ad:0xF8000220 ad:0xF8000240 ad:0xF8000260 ad:0xF8000280 ad:0xF80002A0 ad:0xF80002C0 ad:0xF80002E0)
|
|
tree "CAN_MB[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "MMR,Mailbox Mode Register"
|
|
bitfld.long 0x0 24.--26. "MOT,Mailbox Object Type" "0: Mailbox is disabled. This prevents receiving or..,1: Reception Mailbox. Mailbox is configured for..,2: Reception mailbox with overwrite. Mailbox is..,3: Transmit mailbox. Mailbox is configured for..,4: Consumer Mailbox. Mailbox is configured in..,5: Producer Mailbox. Mailbox is configured in..,?,?"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PRIOR,Mailbox Priority"
|
|
hexmask.long.word 0x0 0.--15. 1. "MTIMEMARK,Mailbox Timemark"
|
|
line.long 0x4 "MAM,Mailbox Acceptance Mask Register"
|
|
bitfld.long 0x4 29. "MIDE,Identifier Version" "0,1"
|
|
hexmask.long.word 0x4 18.--28. 1. "MIDvA,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "MIDvB,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x8 "MID,Mailbox ID Register"
|
|
bitfld.long 0x8 29. "MIDE,Identifier Version" "0,1"
|
|
hexmask.long.word 0x8 18.--28. 1. "MIDvA,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x8 0.--17. 1. "MIDvB,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long ($2+0xC)++0x7
|
|
line.long 0x0 "MFID,Mailbox Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. "MFID,Family ID"
|
|
line.long 0x4 "MSR,Mailbox Status Register"
|
|
bitfld.long 0x4 24. "MMI,Mailbox Message Ignored (cleared by reading CAN_MSRx)" "0,1"
|
|
bitfld.long 0x4 23. "MRDY,Mailbox Ready (cleared by writing MTCR or MACR in the CAN_MCRx)" "0,1"
|
|
bitfld.long 0x4 22. "MABT,Mailbox Message Abort (cleared by writing MTCR or MACR in the CAN_MCRx)" "0,1"
|
|
bitfld.long 0x4 20. "MRTR,Mailbox Remote Transmission Request" "0,1"
|
|
hexmask.long.byte 0x4 16.--19. 1. "MDLC,Mailbox Data Length Code"
|
|
hexmask.long.word 0x4 0.--15. 1. "MTIMESTAMP,Timer Value"
|
|
group.long ($2+0x14)++0x7
|
|
line.long 0x0 "MDL,Mailbox Data Low Register"
|
|
hexmask.long 0x0 0.--31. 1. "MDL,Message Data Low Value"
|
|
line.long 0x4 "MDH,Mailbox Data High Register"
|
|
hexmask.long 0x4 0.--31. 1. "MDH,Message Data High Value"
|
|
wgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "MCR,Mailbox Control Register"
|
|
bitfld.long 0x0 23. "MTCR,Mailbox Transfer Command" "0,1"
|
|
bitfld.long 0x0 22. "MACR,Abort Request for Mailbox 0" "0,1"
|
|
bitfld.long 0x0 20. "MRTR,Mailbox Remote Transmission Request" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "MDLC,Mailbox Data Length Code"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "CAN1"
|
|
base ad:0xF8004000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 24.--26. "RXSYNC,Reception Synchronization Stage (not readable)" "0: Rx Signal with Double Synchro Stages (2 Positive..,1: Rx Signal with Double Synchro Stages (One..,2: Rx Signal with Single Synchro Stage (Positive..,3: Rx Signal with No Synchro Stage,?,?,?,?"
|
|
bitfld.long 0x0 7. "DRPT,Disable Repeat" "0,1"
|
|
bitfld.long 0x0 6. "TIMFRZ,Enable Timer Freeze" "0,1"
|
|
bitfld.long 0x0 5. "TTM,Disable/Enable Time-Triggered Mode" "0,1"
|
|
bitfld.long 0x0 4. "TEOF,Timestamp messages at each end of Frame" "0,1"
|
|
bitfld.long 0x0 3. "OVL,Disable/Enable Overload Frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ABM,Disable/Enable Autobaud/Listen mode" "0,1"
|
|
bitfld.long 0x0 1. "LPM,Disable/Enable Low-power Mode" "0,1"
|
|
bitfld.long 0x0 0. "CANEN,CAN Controller Enable" "0,1"
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "BERR,Bit Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 27. "FERR,Form Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "AERR,Acknowledgment Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 25. "SERR,Stuffing Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "CERR,CRC Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 23. "TSTP,TimeStamp Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "TOVF,Timer Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "WAKEUP,Wakeup Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "SLEEP,Sleep Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 19. "BOFF,Bus Off Mode Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "ERRP,Error Passive Mode Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "WARN,Warning Limit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ERRA,Error Active Mode Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "MB7,Mailbox 7 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "MB6,Mailbox 6 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "MB5,Mailbox 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "MB4,Mailbox 4 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "MB3,Mailbox 3 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MB2,Mailbox 2 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "MB1,Mailbox 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "MB0,Mailbox 0 Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 28. "BERR,Bit Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 27. "FERR,Form Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "AERR,Acknowledgment Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 25. "SERR,Stuffing Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "CERR,CRC Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 23. "TSTP,TimeStamp Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "TOVF,Timer Overflow Interrupt" "0,1"
|
|
bitfld.long 0x4 21. "WAKEUP,Wakeup Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "SLEEP,Sleep Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 19. "BOFF,Bus Off Mode Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "ERRP,Error Passive Mode Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "WARN,Warning Limit Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "ERRA,Error Active Mode Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "MB7,Mailbox 7 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "MB6,Mailbox 6 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "MB5,Mailbox 5 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "MB4,Mailbox 4 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "MB3,Mailbox 3 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MB2,Mailbox 2 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "MB1,Mailbox 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "MB0,Mailbox 0 Interrupt Disable" "0,1"
|
|
rgroup.long 0xC++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "BERR,Bit Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 27. "FERR,Form Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "AERR,Acknowledgment Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 25. "SERR,Stuffing Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "CERR,CRC Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 23. "TSTP,Timestamp Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "TOVF,Timer Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 21. "WAKEUP,Wakeup Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "SLEEP,Sleep Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 19. "BOFF,Bus Off Mode Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "ERRP,Error Passive Mode Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 17. "WARN,Warning Limit Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ERRA,Error Active Mode Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "MB7,Mailbox 7 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "MB6,Mailbox 6 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "MB5,Mailbox 5 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "MB4,Mailbox 4 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "MB3,Mailbox 3 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MB2,Mailbox 2 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "MB1,Mailbox 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "MB0,Mailbox 0 Interrupt Mask" "0,1"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 31. "OVLSY,Overload busy" "0,1"
|
|
bitfld.long 0x4 30. "TBSY,Transmitter Busy" "0,1"
|
|
bitfld.long 0x4 29. "RBSY,Receiver Busy" "0,1"
|
|
bitfld.long 0x4 28. "BERR,Bit Error (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 27. "FERR,Form Error (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 26. "AERR,Acknowledgment Error (automatically cleared by reading CAN_SR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "SERR,Mailbox Stuffing Error (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 24. "CERR,Mailbox CRC Error (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 23. "TSTP,Timestamp (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 22. "TOVF,Timer Overflow (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 21. "WAKEUP,CAN Controller is not in Low-power Mode" "0,1"
|
|
bitfld.long 0x4 20. "SLEEP,CAN Controller in Low-power Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "BOFF,Bus Off Mode (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 18. "ERRP,Error Passive Mode (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 17. "WARN,Warning Limit (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 16. "ERRA,Error Active Mode (automatically cleared by reading CAN_SR)" "0,1"
|
|
bitfld.long 0x4 7. "MB7,Mailbox 7 Event" "0,1"
|
|
bitfld.long 0x4 6. "MB6,Mailbox 6 Event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MB5,Mailbox 5 Event" "0,1"
|
|
bitfld.long 0x4 4. "MB4,Mailbox 4 Event" "0,1"
|
|
bitfld.long 0x4 3. "MB3,Mailbox 3 Event" "0,1"
|
|
bitfld.long 0x4 2. "MB2,Mailbox 2 Event" "0,1"
|
|
bitfld.long 0x4 1. "MB1,Mailbox 1 Event" "0,1"
|
|
bitfld.long 0x4 0. "MB0,Mailbox 0 Event" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "BR,Baudrate Register"
|
|
bitfld.long 0x0 24. "SMP,Sampling Mode" "0: The incoming bit stream is sampled once at..,1: The incoming bit stream is sampled three times.."
|
|
hexmask.long.byte 0x0 16.--22. 1. "BRP,Baudrate Prescaler"
|
|
bitfld.long 0x0 12.--13. "SJW,Re-synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x0 8.--10. "PROPAG,Programming Time Segment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PHASE1,Phase 1 Segment" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "PHASE2,Phase 2 Segment" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "TIM,Timer Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TIMER,Timer"
|
|
line.long 0x4 "TIMESTP,Timestamp Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "MTIMESTAMP,Timestamp"
|
|
line.long 0x8 "ECR,Error Counter Register"
|
|
hexmask.long.word 0x8 16.--24. 1. "TEC,Transmit Error Counter"
|
|
hexmask.long.byte 0x8 0.--7. 1. "REC,Receive Error Counter"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x0 "TCR,Transfer Command Register"
|
|
bitfld.long 0x0 31. "TIMRST,Timer Reset" "0,1"
|
|
bitfld.long 0x0 7. "MB7,Transfer Request for Mailbox 7" "0,1"
|
|
bitfld.long 0x0 6. "MB6,Transfer Request for Mailbox 6" "0,1"
|
|
bitfld.long 0x0 5. "MB5,Transfer Request for Mailbox 5" "0,1"
|
|
bitfld.long 0x0 4. "MB4,Transfer Request for Mailbox 4" "0,1"
|
|
bitfld.long 0x0 3. "MB3,Transfer Request for Mailbox 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MB2,Transfer Request for Mailbox 2" "0,1"
|
|
bitfld.long 0x0 1. "MB1,Transfer Request for Mailbox 1" "0,1"
|
|
bitfld.long 0x0 0. "MB0,Transfer Request for Mailbox 0" "0,1"
|
|
line.long 0x4 "ACR,Abort Command Register"
|
|
bitfld.long 0x4 7. "MB7,Abort Request for Mailbox 7" "0,1"
|
|
bitfld.long 0x4 6. "MB6,Abort Request for Mailbox 6" "0,1"
|
|
bitfld.long 0x4 5. "MB5,Abort Request for Mailbox 5" "0,1"
|
|
bitfld.long 0x4 4. "MB4,Abort Request for Mailbox 4" "0,1"
|
|
bitfld.long 0x4 3. "MB3,Abort Request for Mailbox 3" "0,1"
|
|
bitfld.long 0x4 2. "MB2,Abort Request for Mailbox 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MB1,Abort Request for Mailbox 1" "0,1"
|
|
bitfld.long 0x4 0. "MB0,Abort Request for Mailbox 0" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key Password"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0xF8004200 ad:0xF8004220 ad:0xF8004240 ad:0xF8004260 ad:0xF8004280 ad:0xF80042A0 ad:0xF80042C0 ad:0xF80042E0)
|
|
tree "CAN_MB[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "MMR,Mailbox Mode Register"
|
|
bitfld.long 0x0 24.--26. "MOT,Mailbox Object Type" "0: Mailbox is disabled. This prevents receiving or..,1: Reception Mailbox. Mailbox is configured for..,2: Reception mailbox with overwrite. Mailbox is..,3: Transmit mailbox. Mailbox is configured for..,4: Consumer Mailbox. Mailbox is configured in..,5: Producer Mailbox. Mailbox is configured in..,?,?"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PRIOR,Mailbox Priority"
|
|
hexmask.long.word 0x0 0.--15. 1. "MTIMEMARK,Mailbox Timemark"
|
|
line.long 0x4 "MAM,Mailbox Acceptance Mask Register"
|
|
bitfld.long 0x4 29. "MIDE,Identifier Version" "0,1"
|
|
hexmask.long.word 0x4 18.--28. 1. "MIDvA,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "MIDvB,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x8 "MID,Mailbox ID Register"
|
|
bitfld.long 0x8 29. "MIDE,Identifier Version" "0,1"
|
|
hexmask.long.word 0x8 18.--28. 1. "MIDvA,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x8 0.--17. 1. "MIDvB,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long ($2+0xC)++0x7
|
|
line.long 0x0 "MFID,Mailbox Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. "MFID,Family ID"
|
|
line.long 0x4 "MSR,Mailbox Status Register"
|
|
bitfld.long 0x4 24. "MMI,Mailbox Message Ignored (cleared by reading CAN_MSRx)" "0,1"
|
|
bitfld.long 0x4 23. "MRDY,Mailbox Ready (cleared by writing MTCR or MACR in the CAN_MCRx)" "0,1"
|
|
bitfld.long 0x4 22. "MABT,Mailbox Message Abort (cleared by writing MTCR or MACR in the CAN_MCRx)" "0,1"
|
|
bitfld.long 0x4 20. "MRTR,Mailbox Remote Transmission Request" "0,1"
|
|
hexmask.long.byte 0x4 16.--19. 1. "MDLC,Mailbox Data Length Code"
|
|
hexmask.long.word 0x4 0.--15. 1. "MTIMESTAMP,Timer Value"
|
|
group.long ($2+0x14)++0x7
|
|
line.long 0x0 "MDL,Mailbox Data Low Register"
|
|
hexmask.long 0x0 0.--31. 1. "MDL,Message Data Low Value"
|
|
line.long 0x4 "MDH,Mailbox Data High Register"
|
|
hexmask.long 0x4 0.--31. 1. "MDH,Message Data High Value"
|
|
wgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "MCR,Mailbox Control Register"
|
|
bitfld.long 0x0 23. "MTCR,Mailbox Transfer Command" "0,1"
|
|
bitfld.long 0x0 22. "MACR,Abort Request for Mailbox 0" "0,1"
|
|
bitfld.long 0x0 20. "MRTR,Mailbox Remote Transmission Request" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "MDLC,Mailbox Data Length Code"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "CLASSD (Audio Class D Amplifier)"
|
|
base ad:0xF003C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 20.--21. "NOVRVAL,Non-Overlapping Value" "0: Non-overlapping time is 5 ns,1: Non-overlapping time is 10 ns,2: Non-overlapping time is 15 ns,3: Non-overlapping time is 20 ns"
|
|
bitfld.long 0x0 16. "NON_OVERLAP,Non-Overlapping Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PWMTYP,PWM Modulation Type" "0: The signal is single-ended.,1: The signal is differential."
|
|
bitfld.long 0x0 5. "RMUTE,Right Channel Mute" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "REN,Right Channel Enable" "0,1"
|
|
bitfld.long 0x0 1. "LMUTE,Left Channel Mute" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LEN,Left Channel Enable" "0,1"
|
|
line.long 0x4 "INTPMR,Interpolator Mode Register"
|
|
bitfld.long 0x4 29.--30. "MONOMODE,Mono Mode Selection" "0: (left + right) / 2 is sent on both channels,1: (left + right) is sent to both channels. If the..,2: THR[15:0] is sent on both left and right channels,3: THR[31:16] is sent on both left and right channels"
|
|
bitfld.long 0x4 28. "MONO,Mono Signal" "0: The signal is sent stereo to the left and right..,1: The same signal is sent on both left and right.."
|
|
newline
|
|
hexmask.long.byte 0x4 24.--27. 1. "EQCFG,Equalization Selection"
|
|
bitfld.long 0x4 20.--22. "FRAME,CLASSD Incoming Data Sampling Frequency" "0: 8 kHz,1: 16 kHz,2: 32 kHz,3: 48 kHz,4: 96 kHz,5: 22.05 kHz,6: 44.1 kHz,7: 88.2 kHz"
|
|
newline
|
|
bitfld.long 0x4 19. "SWAP,Swap Left and Right Channels" "0: Left channel is on CLASSD_THR[15:0] right..,1: Right channel is on CLASSD_THR[15:0] left.."
|
|
bitfld.long 0x4 18. "DEEMP,Enable De-emphasis Filter" "0: De-emphasis filter is disabled.,1: De-emphasis filter is enabled."
|
|
newline
|
|
bitfld.long 0x4 16. "DSPCLKFREQ,DSP Clock Frequency" "0: DSP Clock (DSPCLK) is 12.288 MHz.,1: DSP Clock (DSPCLK) is 11.2896 MHz."
|
|
hexmask.long.byte 0x4 8.--14. 1. "ATTR,Right Channel Attenuation"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "ATTL,Left Channel Attenuation"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "INTSR,Interpolator Status Register"
|
|
bitfld.long 0x0 0. "CFGERR,Configuration Error" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RDATA,Right Channel Data"
|
|
hexmask.long.word 0x0 0.--15. 1. "LDATA,Left Channel Data"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready" "0,1"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "DBGU (Debug Unit)"
|
|
base ad:0xFFFFF200
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 11. "STTTO,Start Timeout" "0,1"
|
|
bitfld.long 0x0 10. "RETTO,Rearm Timeout" "0,1"
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic echo,2: Local loopback,3: Remote loopback"
|
|
bitfld.long 0x0 12. "BRSRCCK,Baud Rate Source Clock" "0: The baud rate is driven by the peripheral clock,1: The baud rate is driven by a PMC-programmable.."
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even Parity,1: Odd Parity,2: Space: parity forced to 0,3: Mark: parity forced to 1,4: No parity,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 4. "FILTER,Receiver Digital Filter" "0: DBGU does not filter the receive line.,1: DBGU filters the receive line using a.."
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "COMMRX,Enable COMMRX (from ARM) Interrupt" "0,1"
|
|
bitfld.long 0x0 30. "COMMTX,Enable COMMTX (from ARM) Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Enable TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Enable Timeout Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "PARE,Enable Parity Error Interrupt" "0,1"
|
|
bitfld.long 0x0 6. "FRAME,Enable Framing Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Enable Overrun Error Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "TXRDY,Enable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Enable RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "COMMRX,Disable COMMRX (from ARM) Interrupt" "0,1"
|
|
bitfld.long 0x4 30. "COMMTX,Disable COMMTX (from ARM) Interrupt" "0,1"
|
|
bitfld.long 0x4 9. "TXEMPTY,Disable TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Disable Timeout Interrupt" "0,1"
|
|
bitfld.long 0x4 7. "PARE,Disable Parity Error Interrupt" "0,1"
|
|
bitfld.long 0x4 6. "FRAME,Disable Framing Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Disable Overrun Error Interrupt" "0,1"
|
|
bitfld.long 0x4 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x4 0. "RXRDY,Disable RXRDY Interrupt" "0,1"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "COMMRX,Mask COMMRX (from ARM) Interrupt" "0,1"
|
|
bitfld.long 0x0 30. "COMMTX,Mask COMMTX (from ARM) Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Mask TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Mask Timeout Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "PARE,Mask Parity Error Interrupt" "0,1"
|
|
bitfld.long 0x0 6. "FRAME,Mask Framing Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Mask Overrun Error Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Mask RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 31. "COMMRX,Debug Communication Channel Read Status" "0,1"
|
|
bitfld.long 0x4 30. "COMMTX,Debug Communication Channel Write Status" "0,1"
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready" "0,1"
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready" "0,1"
|
|
line.long 0x8 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXCHR,Received Character"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR,Character to be Transmitted"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BRGR,Baud Rate Generator Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divisor"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TO,Timeout Value"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "CIDR,Chip ID Register"
|
|
bitfld.long 0x0 31. "EXT,Extension Flag" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CHID,Chip ID Value"
|
|
line.long 0x4 "EXID,Chip ID Extension Register"
|
|
hexmask.long 0x4 0.--31. 1. "EXID,Chip ID Extension"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "FNR,Force NTRST Register"
|
|
bitfld.long 0x0 0. "FNTRST,Force NTRST" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "EMAC (Ethernet MAC 10/100)"
|
|
base ad:0x0
|
|
tree "EMAC0"
|
|
base ad:0xF802C000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "NCR,Network Control Register"
|
|
bitfld.long 0x0 12. "TZQ,Transmit Zero Quantum Pause Frame" "0,1"
|
|
bitfld.long 0x0 11. "TPFR,Transmit Pause Frame" "0,1"
|
|
bitfld.long 0x0 10. "THALT,Transmit Halt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TSTART,Start Transmission" "0,1"
|
|
bitfld.long 0x0 8. "BP,Back Pressure" "0,1"
|
|
bitfld.long 0x0 7. "WESTAT,Write Enable for Statistics Registers" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INCSTAT,Increment Statistics Registers" "0,1"
|
|
bitfld.long 0x0 5. "CLRSTAT,Clear Statistics Registers" "0,1"
|
|
bitfld.long 0x0 4. "MPE,Management Port Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmit Enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receive Enable" "0,1"
|
|
bitfld.long 0x0 1. "LLB,Loopback Local" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LB,LoopBack" "0,1"
|
|
line.long 0x4 "NCFGR,Network Configuration Register"
|
|
bitfld.long 0x4 19. "IRXFCS,Ignore RX FCS" "0,1"
|
|
bitfld.long 0x4 18. "EFRHD,Enable Frames Received in Half Duplex" "0,1"
|
|
bitfld.long 0x4 17. "DRFCS,Discard Receive FCS" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "RLCE,Receive Length Field Checking Enable" "0,1"
|
|
bitfld.long 0x4 14.--15. "RBOF,Receive Buffer Offset" "0: No offset from start of receive buffer,1: One-byte offset from start of receive buffer,2: Two-byte offset from start of receive buffer,3: Three-byte offset from start of receive buffer"
|
|
bitfld.long 0x4 13. "PAE,Pause Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RTY,Retry Test" "0,1"
|
|
bitfld.long 0x4 10.--11. "CLK,MDC Clock Divider" "0: MCK divided by 8 (MCK up to 20 MHz),1: MCK divided by 16 (MCK up to 40 MHz),2: MCK divided by 32 (MCK up to 80 MHz),3: MCK divided by 64 (MCK up to 160 MHz)"
|
|
bitfld.long 0x4 9. "EAE,External Address Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "BIG,Receive 1536 Bytes Frames" "0,1"
|
|
bitfld.long 0x4 7. "UNI,Unicast Hash Enable" "0,1"
|
|
bitfld.long 0x4 6. "MTI,Multicast Hash Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "NBC,No Broadcast" "0,1"
|
|
bitfld.long 0x4 4. "CAF,Copy All Frames" "0,1"
|
|
bitfld.long 0x4 3. "JFRAME,Jumbo Frames" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FD,Full Duplex" "0,1"
|
|
bitfld.long 0x4 0. "SPD,Speed" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "NSR,Network Status Register"
|
|
bitfld.long 0x0 2. "IDLE,PHY Management Logic Status" "0,1"
|
|
bitfld.long 0x0 1. "MDIO,MDIO Input Status" "0,1"
|
|
bitfld.long 0x0 0. "LINKR,Link Pin Status" "0,1"
|
|
group.long 0x14++0x13
|
|
line.long 0x0 "TSR,Transmit Status Register"
|
|
bitfld.long 0x0 6. "UND,Transmit Underrun (cleared by writing a one to this bit)" "0,1"
|
|
bitfld.long 0x0 5. "COMP,Transmit Complete (cleared by writing a one to this bit)" "0,1"
|
|
bitfld.long 0x0 4. "BEX,Buffers Exhausted Mid-frame (cleared by writing a one to this bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TGO,Transmit Go" "0,1"
|
|
bitfld.long 0x0 2. "RLES,Retry Limit Exceeded (cleared by writing a one to this bit)" "0,1"
|
|
bitfld.long 0x0 1. "COL,Collision Occurred (cleared by writing a one to this bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "UBR,Used Bit Read (cleared by writing a one to this bit)" "0,1"
|
|
line.long 0x4 "RBQP,Receive Buffer Queue Pointer Register"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Receive Buffer Queue Pointer Address"
|
|
line.long 0x8 "TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Transmit Buffer Queue Pointer Address"
|
|
line.long 0xC "RSR,Receive Status Register"
|
|
bitfld.long 0xC 2. "OVR,Receive Overrun (cleared by writing a one to this bit)" "0,1"
|
|
bitfld.long 0xC 1. "REC,Frame Received (cleared by writing a one to this bit)" "0,1"
|
|
bitfld.long 0xC 0. "BNA,Buffer Not Available (cleared by writing a one to this bit)" "0,1"
|
|
line.long 0x10 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x10 14. "WOL,Wake-On-LAN (cleared on read)" "0,1"
|
|
bitfld.long 0x10 13. "PTZ,Pause Time Zero (cleared on read)" "0,1"
|
|
bitfld.long 0x10 12. "PFRE,Pause Frame Received (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "HRESP,Hresp Not OK (cleared on read)" "0,1"
|
|
bitfld.long 0x10 10. "ROVR,Receive Overrun (cleared on read)" "0,1"
|
|
bitfld.long 0x10 9. "LINK,Link Change (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "TCOMP,Transmit Complete (cleared on read)" "0,1"
|
|
bitfld.long 0x10 6. "TXERR,Transmit Error (cleared on read)" "0,1"
|
|
bitfld.long 0x10 5. "RLEX,Retry Limit Exceeded (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "TUND,Ethernet Transmit Buffer Underrun (cleared on read)" "0,1"
|
|
bitfld.long 0x10 3. "TXUBR,Transmit Used Bit Read (cleared on read)" "0,1"
|
|
bitfld.long 0x10 2. "RXUBR,Receive Used Bit Read (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "RCOMP,Receive Complete (cleared on read)" "0,1"
|
|
bitfld.long 0x10 0. "MFD,Management Frame Done (cleared on read)" "0,1"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 14. "WOL,Wake-On-LAN" "0,1"
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x0 12. "PFR,Pause Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "HRESP,Hresp Not OK" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x0 9. "LINK,Link Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TXERR,Transmit Error" "0,1"
|
|
bitfld.long 0x0 5. "RLE,Retry Limit Exceeded" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TUND,Ethernet Transmit Buffer Underrun" "0,1"
|
|
bitfld.long 0x0 3. "TXUBR,Transmit Used Bit Read" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,Receive Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x0 0. "MFD,Management Frame Done" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 14. "WOL,Wake-On-LAN" "0,1"
|
|
bitfld.long 0x4 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x4 12. "PFR,Pause Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "HRESP,Hresp Not OK" "0,1"
|
|
bitfld.long 0x4 10. "ROVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x4 9. "LINK,Link Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x4 6. "TXERR,Transmit Error" "0,1"
|
|
bitfld.long 0x4 5. "RLE,Retry Limit Exceeded" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TUND,Ethernet Transmit Buffer Underrun" "0,1"
|
|
bitfld.long 0x4 3. "TXUBR,Transmit Used Bit Read" "0,1"
|
|
bitfld.long 0x4 2. "RXUBR,Receive Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x4 0. "MFD,Management Frame Done" "0,1"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 14. "WOL,Wake-On-LAN" "0,1"
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x0 12. "PFR,Pause Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "HRESP,Hresp Not OK" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x0 9. "LINK,Link Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TXERR,Transmit Error" "0,1"
|
|
bitfld.long 0x0 5. "RLE,Retry Limit Exceeded" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TUND,Ethernet Transmit Buffer Underrun" "0,1"
|
|
bitfld.long 0x0 3. "TXUBR,Transmit Used Bit Read" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,Receive Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x0 0. "MFD,Management Frame Done" "0,1"
|
|
group.long 0x34++0x63
|
|
line.long 0x0 "MAN,PHY Maintenance Register"
|
|
bitfld.long 0x0 30.--31. "SOF,Start of Frame" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "RW,PHY Read/Write Command" "0,1,2,3"
|
|
hexmask.long.byte 0x0 23.--27. 1. "PHYA,PHY Address"
|
|
newline
|
|
hexmask.long.byte 0x0 18.--22. 1. "REGA,PHY Register Address"
|
|
bitfld.long 0x0 16.--17. "CODE,Must Be Two" "0,1,2,3"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,PHY Transmit or Receive Data"
|
|
line.long 0x4 "PTR,Pause Time Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "PTIME,Pause Time"
|
|
line.long 0x8 "PFR,Pause Frames Received Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "FROK,Pause Frames Received OK"
|
|
line.long 0xC "FTO,Frames Transmitted OK Register"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "FTOK,Frames Transmitted OK"
|
|
line.long 0x10 "SCF,Single Collision Frames Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "SCF,Single Collision Frames"
|
|
line.long 0x14 "MCF,Multiple Collision Frames Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "MCF,Multicollision Frames"
|
|
line.long 0x18 "FRO,Frames Received OK Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "FROK,Frames Received OK"
|
|
line.long 0x1C "FCSE,Frame Check Sequence Errors Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "FCSE,Frame Check Sequence Errors"
|
|
line.long 0x20 "ALE,Alignment Errors Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. "ALE,Alignment Errors"
|
|
line.long 0x24 "DTF,Deferred Transmission Frames Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "DTF,Deferred Transmission Frames"
|
|
line.long 0x28 "LCOL,Late Collisions Register"
|
|
hexmask.long.byte 0x28 0.--7. 1. "LCOL,Late Collisions"
|
|
line.long 0x2C "ECOL,Excessive Collisions Register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "EXCOL,Excessive Collisions"
|
|
line.long 0x30 "TUND,Transmit Underrun Errors Register"
|
|
hexmask.long.byte 0x30 0.--7. 1. "TUND,Transmit Underruns"
|
|
line.long 0x34 "CSE,Carrier Sense Errors Register"
|
|
hexmask.long.byte 0x34 0.--7. 1. "CSE,Carrier Sense Errors"
|
|
line.long 0x38 "RRE,Receive Resource Errors Register"
|
|
hexmask.long.word 0x38 0.--15. 1. "RRE,Receive Resource Errors"
|
|
line.long 0x3C "ROV,Receive Overrun Errors Register"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "ROVR,Receive Overrun"
|
|
line.long 0x40 "RSE,Receive Symbol Errors Register"
|
|
hexmask.long.byte 0x40 0.--7. 1. "RSE,Receive Symbol Errors"
|
|
line.long 0x44 "ELE,Excessive Length Errors Register"
|
|
hexmask.long.byte 0x44 0.--7. 1. "EXL,Excessive Length Errors"
|
|
line.long 0x48 "RJA,Receive Jabbers Register"
|
|
hexmask.long.byte 0x48 0.--7. 1. "RJB,Receive Jabbers"
|
|
line.long 0x4C "USF,Undersize Frames Register"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "USF,Undersize Frames"
|
|
line.long 0x50 "STE,SQE Test Errors Register"
|
|
hexmask.long.byte 0x50 0.--7. 1. "SQER,SQE Test Errors"
|
|
line.long 0x54 "RLE,Received Length Field Mismatch Register"
|
|
hexmask.long.byte 0x54 0.--7. 1. "RLFM,Receive Length Field Mismatch"
|
|
line.long 0x58 "TPF,Transmitted Pause Frames Register"
|
|
hexmask.long.word 0x58 0.--15. 1. "TPF,Transmitted Pause Frames"
|
|
line.long 0x5C "HRB,Hash Register Bottom [31:0] Register"
|
|
hexmask.long 0x5C 0.--31. 1. "ADDR,Hash Address Bottom"
|
|
line.long 0x60 "HRT,Hash Register Top [63:32] Register"
|
|
hexmask.long 0x60 0.--31. 1. "ADDR,Hash Address Top"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xF802C098 ad:0xF802C0A0 ad:0xF802C0A8 ad:0xF802C0B0)
|
|
tree "EMAC_SA[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "SAxB,Specific Address X Bottom Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Specific Address X Bottom"
|
|
line.long 0x4 "SAxT,Specific Address X Top Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADDR,Specific Address X Top"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF802C000
|
|
newline
|
|
group.long 0xB8++0xF
|
|
line.long 0x0 "TID,Type ID Checking Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TID,Type ID Checking"
|
|
line.long 0x4 "TPQ,Transmit Pause Quantum Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TPQ,Transmit Pause Quantum"
|
|
line.long 0x8 "USRIO,User Input/Output Register"
|
|
bitfld.long 0x8 1. "CLKEN,Clock Enable" "0,1"
|
|
bitfld.long 0x8 0. "RMII,Reduced MII" "0,1"
|
|
line.long 0xC "WOL,Wake-on-LAN Register"
|
|
bitfld.long 0xC 19. "MTI,Multicast Hash Event Enable" "0,1"
|
|
bitfld.long 0xC 18. "SA1,Specific Address Register 1 Event Enable" "0,1"
|
|
bitfld.long 0xC 17. "ARP,ARP Request Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "MAG,Magic Packet Event Enable" "0,1"
|
|
hexmask.long.word 0xC 0.--15. 1. "IP,ARP Request IP Address"
|
|
tree.end
|
|
tree "EMAC1"
|
|
base ad:0xF8030000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "NCR,Network Control Register"
|
|
bitfld.long 0x0 12. "TZQ,Transmit Zero Quantum Pause Frame" "0,1"
|
|
bitfld.long 0x0 11. "TPFR,Transmit Pause Frame" "0,1"
|
|
bitfld.long 0x0 10. "THALT,Transmit Halt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TSTART,Start Transmission" "0,1"
|
|
bitfld.long 0x0 8. "BP,Back Pressure" "0,1"
|
|
bitfld.long 0x0 7. "WESTAT,Write Enable for Statistics Registers" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "INCSTAT,Increment Statistics Registers" "0,1"
|
|
bitfld.long 0x0 5. "CLRSTAT,Clear Statistics Registers" "0,1"
|
|
bitfld.long 0x0 4. "MPE,Management Port Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmit Enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receive Enable" "0,1"
|
|
bitfld.long 0x0 1. "LLB,Loopback Local" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LB,LoopBack" "0,1"
|
|
line.long 0x4 "NCFGR,Network Configuration Register"
|
|
bitfld.long 0x4 19. "IRXFCS,Ignore RX FCS" "0,1"
|
|
bitfld.long 0x4 18. "EFRHD,Enable Frames Received in Half Duplex" "0,1"
|
|
bitfld.long 0x4 17. "DRFCS,Discard Receive FCS" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "RLCE,Receive Length Field Checking Enable" "0,1"
|
|
bitfld.long 0x4 14.--15. "RBOF,Receive Buffer Offset" "0: No offset from start of receive buffer,1: One-byte offset from start of receive buffer,2: Two-byte offset from start of receive buffer,3: Three-byte offset from start of receive buffer"
|
|
bitfld.long 0x4 13. "PAE,Pause Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RTY,Retry Test" "0,1"
|
|
bitfld.long 0x4 10.--11. "CLK,MDC Clock Divider" "0: MCK divided by 8 (MCK up to 20 MHz),1: MCK divided by 16 (MCK up to 40 MHz),2: MCK divided by 32 (MCK up to 80 MHz),3: MCK divided by 64 (MCK up to 160 MHz)"
|
|
bitfld.long 0x4 9. "EAE,External Address Match Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "BIG,Receive 1536 Bytes Frames" "0,1"
|
|
bitfld.long 0x4 7. "UNI,Unicast Hash Enable" "0,1"
|
|
bitfld.long 0x4 6. "MTI,Multicast Hash Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "NBC,No Broadcast" "0,1"
|
|
bitfld.long 0x4 4. "CAF,Copy All Frames" "0,1"
|
|
bitfld.long 0x4 3. "JFRAME,Jumbo Frames" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FD,Full Duplex" "0,1"
|
|
bitfld.long 0x4 0. "SPD,Speed" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "NSR,Network Status Register"
|
|
bitfld.long 0x0 2. "IDLE,PHY Management Logic Status" "0,1"
|
|
bitfld.long 0x0 1. "MDIO,MDIO Input Status" "0,1"
|
|
bitfld.long 0x0 0. "LINKR,Link Pin Status" "0,1"
|
|
group.long 0x14++0x13
|
|
line.long 0x0 "TSR,Transmit Status Register"
|
|
bitfld.long 0x0 6. "UND,Transmit Underrun (cleared by writing a one to this bit)" "0,1"
|
|
bitfld.long 0x0 5. "COMP,Transmit Complete (cleared by writing a one to this bit)" "0,1"
|
|
bitfld.long 0x0 4. "BEX,Buffers Exhausted Mid-frame (cleared by writing a one to this bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TGO,Transmit Go" "0,1"
|
|
bitfld.long 0x0 2. "RLES,Retry Limit Exceeded (cleared by writing a one to this bit)" "0,1"
|
|
bitfld.long 0x0 1. "COL,Collision Occurred (cleared by writing a one to this bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "UBR,Used Bit Read (cleared by writing a one to this bit)" "0,1"
|
|
line.long 0x4 "RBQP,Receive Buffer Queue Pointer Register"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Receive Buffer Queue Pointer Address"
|
|
line.long 0x8 "TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Transmit Buffer Queue Pointer Address"
|
|
line.long 0xC "RSR,Receive Status Register"
|
|
bitfld.long 0xC 2. "OVR,Receive Overrun (cleared by writing a one to this bit)" "0,1"
|
|
bitfld.long 0xC 1. "REC,Frame Received (cleared by writing a one to this bit)" "0,1"
|
|
bitfld.long 0xC 0. "BNA,Buffer Not Available (cleared by writing a one to this bit)" "0,1"
|
|
line.long 0x10 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x10 14. "WOL,Wake-On-LAN (cleared on read)" "0,1"
|
|
bitfld.long 0x10 13. "PTZ,Pause Time Zero (cleared on read)" "0,1"
|
|
bitfld.long 0x10 12. "PFRE,Pause Frame Received (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "HRESP,Hresp Not OK (cleared on read)" "0,1"
|
|
bitfld.long 0x10 10. "ROVR,Receive Overrun (cleared on read)" "0,1"
|
|
bitfld.long 0x10 9. "LINK,Link Change (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "TCOMP,Transmit Complete (cleared on read)" "0,1"
|
|
bitfld.long 0x10 6. "TXERR,Transmit Error (cleared on read)" "0,1"
|
|
bitfld.long 0x10 5. "RLEX,Retry Limit Exceeded (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "TUND,Ethernet Transmit Buffer Underrun (cleared on read)" "0,1"
|
|
bitfld.long 0x10 3. "TXUBR,Transmit Used Bit Read (cleared on read)" "0,1"
|
|
bitfld.long 0x10 2. "RXUBR,Receive Used Bit Read (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "RCOMP,Receive Complete (cleared on read)" "0,1"
|
|
bitfld.long 0x10 0. "MFD,Management Frame Done (cleared on read)" "0,1"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 14. "WOL,Wake-On-LAN" "0,1"
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x0 12. "PFR,Pause Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "HRESP,Hresp Not OK" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x0 9. "LINK,Link Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TXERR,Transmit Error" "0,1"
|
|
bitfld.long 0x0 5. "RLE,Retry Limit Exceeded" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TUND,Ethernet Transmit Buffer Underrun" "0,1"
|
|
bitfld.long 0x0 3. "TXUBR,Transmit Used Bit Read" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,Receive Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x0 0. "MFD,Management Frame Done" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 14. "WOL,Wake-On-LAN" "0,1"
|
|
bitfld.long 0x4 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x4 12. "PFR,Pause Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "HRESP,Hresp Not OK" "0,1"
|
|
bitfld.long 0x4 10. "ROVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x4 9. "LINK,Link Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x4 6. "TXERR,Transmit Error" "0,1"
|
|
bitfld.long 0x4 5. "RLE,Retry Limit Exceeded" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TUND,Ethernet Transmit Buffer Underrun" "0,1"
|
|
bitfld.long 0x4 3. "TXUBR,Transmit Used Bit Read" "0,1"
|
|
bitfld.long 0x4 2. "RXUBR,Receive Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x4 0. "MFD,Management Frame Done" "0,1"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 14. "WOL,Wake-On-LAN" "0,1"
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x0 12. "PFR,Pause Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "HRESP,Hresp Not OK" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x0 9. "LINK,Link Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TXERR,Transmit Error" "0,1"
|
|
bitfld.long 0x0 5. "RLE,Retry Limit Exceeded" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TUND,Ethernet Transmit Buffer Underrun" "0,1"
|
|
bitfld.long 0x0 3. "TXUBR,Transmit Used Bit Read" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,Receive Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x0 0. "MFD,Management Frame Done" "0,1"
|
|
group.long 0x34++0x63
|
|
line.long 0x0 "MAN,PHY Maintenance Register"
|
|
bitfld.long 0x0 30.--31. "SOF,Start of Frame" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "RW,PHY Read/Write Command" "0,1,2,3"
|
|
hexmask.long.byte 0x0 23.--27. 1. "PHYA,PHY Address"
|
|
newline
|
|
hexmask.long.byte 0x0 18.--22. 1. "REGA,PHY Register Address"
|
|
bitfld.long 0x0 16.--17. "CODE,Must Be Two" "0,1,2,3"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,PHY Transmit or Receive Data"
|
|
line.long 0x4 "PTR,Pause Time Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "PTIME,Pause Time"
|
|
line.long 0x8 "PFR,Pause Frames Received Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "FROK,Pause Frames Received OK"
|
|
line.long 0xC "FTO,Frames Transmitted OK Register"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "FTOK,Frames Transmitted OK"
|
|
line.long 0x10 "SCF,Single Collision Frames Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "SCF,Single Collision Frames"
|
|
line.long 0x14 "MCF,Multiple Collision Frames Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "MCF,Multicollision Frames"
|
|
line.long 0x18 "FRO,Frames Received OK Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "FROK,Frames Received OK"
|
|
line.long 0x1C "FCSE,Frame Check Sequence Errors Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "FCSE,Frame Check Sequence Errors"
|
|
line.long 0x20 "ALE,Alignment Errors Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. "ALE,Alignment Errors"
|
|
line.long 0x24 "DTF,Deferred Transmission Frames Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "DTF,Deferred Transmission Frames"
|
|
line.long 0x28 "LCOL,Late Collisions Register"
|
|
hexmask.long.byte 0x28 0.--7. 1. "LCOL,Late Collisions"
|
|
line.long 0x2C "ECOL,Excessive Collisions Register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "EXCOL,Excessive Collisions"
|
|
line.long 0x30 "TUND,Transmit Underrun Errors Register"
|
|
hexmask.long.byte 0x30 0.--7. 1. "TUND,Transmit Underruns"
|
|
line.long 0x34 "CSE,Carrier Sense Errors Register"
|
|
hexmask.long.byte 0x34 0.--7. 1. "CSE,Carrier Sense Errors"
|
|
line.long 0x38 "RRE,Receive Resource Errors Register"
|
|
hexmask.long.word 0x38 0.--15. 1. "RRE,Receive Resource Errors"
|
|
line.long 0x3C "ROV,Receive Overrun Errors Register"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "ROVR,Receive Overrun"
|
|
line.long 0x40 "RSE,Receive Symbol Errors Register"
|
|
hexmask.long.byte 0x40 0.--7. 1. "RSE,Receive Symbol Errors"
|
|
line.long 0x44 "ELE,Excessive Length Errors Register"
|
|
hexmask.long.byte 0x44 0.--7. 1. "EXL,Excessive Length Errors"
|
|
line.long 0x48 "RJA,Receive Jabbers Register"
|
|
hexmask.long.byte 0x48 0.--7. 1. "RJB,Receive Jabbers"
|
|
line.long 0x4C "USF,Undersize Frames Register"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "USF,Undersize Frames"
|
|
line.long 0x50 "STE,SQE Test Errors Register"
|
|
hexmask.long.byte 0x50 0.--7. 1. "SQER,SQE Test Errors"
|
|
line.long 0x54 "RLE,Received Length Field Mismatch Register"
|
|
hexmask.long.byte 0x54 0.--7. 1. "RLFM,Receive Length Field Mismatch"
|
|
line.long 0x58 "TPF,Transmitted Pause Frames Register"
|
|
hexmask.long.word 0x58 0.--15. 1. "TPF,Transmitted Pause Frames"
|
|
line.long 0x5C "HRB,Hash Register Bottom [31:0] Register"
|
|
hexmask.long 0x5C 0.--31. 1. "ADDR,Hash Address Bottom"
|
|
line.long 0x60 "HRT,Hash Register Top [63:32] Register"
|
|
hexmask.long 0x60 0.--31. 1. "ADDR,Hash Address Top"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xF8030098 ad:0xF80300A0 ad:0xF80300A8 ad:0xF80300B0)
|
|
tree "EMAC_SA[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "SAxB,Specific Address X Bottom Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Specific Address X Bottom"
|
|
line.long 0x4 "SAxT,Specific Address X Top Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADDR,Specific Address X Top"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF8030000
|
|
newline
|
|
group.long 0xB8++0xF
|
|
line.long 0x0 "TID,Type ID Checking Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TID,Type ID Checking"
|
|
line.long 0x4 "TPQ,Transmit Pause Quantum Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TPQ,Transmit Pause Quantum"
|
|
line.long 0x8 "USRIO,User Input/Output Register"
|
|
bitfld.long 0x8 1. "CLKEN,Clock Enable" "0,1"
|
|
bitfld.long 0x8 0. "RMII,Reduced MII" "0,1"
|
|
line.long 0xC "WOL,Wake-on-LAN Register"
|
|
bitfld.long 0xC 19. "MTI,Multicast Hash Event Enable" "0,1"
|
|
bitfld.long 0xC 18. "SA1,Specific Address Register 1 Event Enable" "0,1"
|
|
bitfld.long 0xC 17. "ARP,ARP Request Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "MAG,Magic Packet Event Enable" "0,1"
|
|
hexmask.long.word 0xC 0.--15. 1. "IP,ARP Request IP Address"
|
|
tree.end
|
|
tree.end
|
|
tree "FLEXCOM (Flexible Serial Communication Controller)"
|
|
base ad:0x0
|
|
tree "FLEXCOM0"
|
|
base ad:0xF801C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
|
line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
|
|
rgroup.long 0x244++0x3
|
|
line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
|
group.long 0x24C++0xF
|
|
line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
|
line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
|
rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x260++0xF
|
|
line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
|
|
newline
|
|
bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
|
|
line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
|
|
hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
|
|
line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
|
|
line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
|
|
bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
|
|
rgroup.long 0x270++0x3
|
|
line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
|
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group.long 0x274++0x17
|
|
line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
|
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line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
|
|
line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
|
|
newline
|
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hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
|
line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
|
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hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
|
|
line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
|
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hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
|
|
line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
|
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hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
|
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group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
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newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
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group.long 0x2A0++0x3
|
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
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newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
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wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
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newline
|
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
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newline
|
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
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newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
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repeat.end
|
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group.long 0x440++0x3
|
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line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
|
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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group.long 0x448++0x3
|
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
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group.long 0x4E4++0x3
|
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
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newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
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bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM1"
|
|
base ad:0xF8020000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
|
line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
|
|
rgroup.long 0x244++0x3
|
|
line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
|
group.long 0x24C++0xF
|
|
line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
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|
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
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|
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
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|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
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|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
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bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
|
line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
|
rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x260++0xF
|
|
line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
|
|
newline
|
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bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
|
|
line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
|
|
hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
|
|
line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
|
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line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
|
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bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
|
|
rgroup.long 0x270++0x3
|
|
line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
|
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group.long 0x274++0x17
|
|
line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
|
|
line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
|
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hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
|
|
line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
|
line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
|
|
line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
|
|
line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
|
|
hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
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tree.end
|
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tree "FLEXCOM2"
|
|
base ad:0xF8024000
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group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
|
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
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group.long 0x20++0x3
|
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
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wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
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newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
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|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
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newline
|
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
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|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
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|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
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|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
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bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
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newline
|
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bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
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|
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bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
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newline
|
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
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line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
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bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
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newline
|
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
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rgroup.long 0x218++0x3
|
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
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group.long 0x220++0xB
|
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
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group.long 0x228++0x3
|
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line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
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group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
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group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
|
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rgroup.long 0x244++0x3
|
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
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group.long 0x24C++0xF
|
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
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newline
|
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
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newline
|
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
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newline
|
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
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newline
|
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
|
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
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newline
|
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
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newline
|
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
|
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
|
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newline
|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
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newline
|
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
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newline
|
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
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newline
|
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
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rgroup.long 0x25C++0x3
|
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
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group.long 0x260++0xF
|
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line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
|
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hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
|
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newline
|
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bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
|
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line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
|
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hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
|
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line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
|
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line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
|
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bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
|
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newline
|
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bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
|
|
newline
|
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hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
|
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rgroup.long 0x270++0x3
|
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line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
|
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hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
|
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group.long 0x274++0x17
|
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line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
|
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line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
|
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hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
|
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line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
|
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hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
|
|
newline
|
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hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
|
line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
|
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hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
|
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line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
|
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hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
|
|
line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
|
|
hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
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bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
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newline
|
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
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newline
|
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
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newline
|
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
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newline
|
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
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bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
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wgroup.long 0x664++0x7
|
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
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rgroup.long 0x6E8++0x3
|
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
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tree.end
|
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tree "FLEXCOM3"
|
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base ad:0xF8028000
|
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group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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|
rgroup.long 0x10++0x3
|
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
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group.long 0x20++0x3
|
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
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wgroup.long 0x200++0x3
|
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line.long 0x0 "FLEX_US_CR,USART Control Register"
|
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
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newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
|
line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
|
|
rgroup.long 0x244++0x3
|
|
line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
|
group.long 0x24C++0xF
|
|
line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
|
line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
|
rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x260++0xF
|
|
line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
|
|
newline
|
|
bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
|
|
line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
|
|
hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
|
|
line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
|
|
line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
|
|
bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
|
|
rgroup.long 0x270++0x3
|
|
line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
|
|
group.long 0x274++0x17
|
|
line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
|
|
line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
|
|
line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
|
line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
|
|
line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
|
|
line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
|
|
hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
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newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
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newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
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group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
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newline
|
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
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group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
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bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM4"
|
|
base ad:0xF0000000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
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wgroup.long 0x21C++0x3
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|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
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|
newline
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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|
wgroup.long 0x21C++0x3
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|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x228++0x3
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line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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newline
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
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newline
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
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newline
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bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
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newline
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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newline
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
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|
newline
|
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
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|
newline
|
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
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newline
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
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newline
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
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newline
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
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newline
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x260++0xF
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line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
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hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
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newline
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bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
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newline
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bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
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newline
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bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
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newline
|
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bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
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newline
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bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
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newline
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bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
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line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
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hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
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line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
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hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
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line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
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bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
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newline
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bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
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|
newline
|
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hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
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rgroup.long 0x270++0x3
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line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
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hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
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group.long 0x274++0x17
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line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
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line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
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line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
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hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
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newline
|
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hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
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line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
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hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
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line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
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hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
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line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
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hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
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newline
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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newline
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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newline
|
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
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newline
|
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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group.long 0x2E4++0x3
|
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
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rgroup.long 0x2E8++0x3
|
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
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rgroup.long 0x62C++0x7
|
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
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newline
|
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
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newline
|
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
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rgroup.long 0x630++0x3
|
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
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group.long 0x638++0x3
|
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
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group.long 0x640++0x7
|
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line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
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tree "FLEXCOM5"
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base ad:0xF0004000
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group.long 0x0++0x3
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
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newline
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
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newline
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
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newline
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
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newline
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
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newline
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
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newline
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
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newline
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
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newline
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
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newline
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
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newline
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
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newline
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
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newline
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
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newline
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bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
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newline
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
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newline
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
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newline
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bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
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newline
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
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newline
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
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newline
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
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newline
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
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newline
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
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newline
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
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newline
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
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newline
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
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newline
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
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newline
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
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newline
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
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newline
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
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newline
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
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newline
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
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newline
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
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|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
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bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
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newline
|
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
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|
newline
|
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bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
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newline
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
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newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
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newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
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|
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bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
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bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
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newline
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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rgroup.long 0x214++0x3
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line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
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|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
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|
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
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|
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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rgroup.long 0x214++0x7
|
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line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
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bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
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newline
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bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
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newline
|
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
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newline
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bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
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newline
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bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
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newline
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bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
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newline
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
|
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x228++0x3
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line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
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newline
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
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newline
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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newline
|
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
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newline
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
|
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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newline
|
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
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newline
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
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newline
|
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bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
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newline
|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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newline
|
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
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newline
|
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
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newline
|
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
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newline
|
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
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newline
|
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
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newline
|
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
|
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
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group.long 0x260++0xF
|
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line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
|
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hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
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newline
|
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bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
|
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line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
|
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hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
|
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line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
|
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line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
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bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
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newline
|
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bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
|
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newline
|
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hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
|
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rgroup.long 0x270++0x3
|
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line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
|
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hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
|
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group.long 0x274++0x17
|
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line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
|
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line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
|
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hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
|
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line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
|
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hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
|
|
newline
|
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hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
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line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
|
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hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
|
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line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
|
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hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
|
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line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
|
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hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
|
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group.long 0x290++0x3
|
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
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newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
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rgroup.long 0x2A4++0x3
|
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
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newline
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bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
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newline
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
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newline
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
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newline
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
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newline
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
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newline
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
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newline
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
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newline
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
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newline
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
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newline
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
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newline
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
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newline
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
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newline
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
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newline
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
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newline
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
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newline
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bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
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newline
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
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newline
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
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newline
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
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newline
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
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newline
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
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newline
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
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newline
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bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
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group.long 0x604++0xF
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line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
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bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
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newline
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
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newline
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bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
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newline
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
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line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
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newline
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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newline
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
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newline
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
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newline
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
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newline
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
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newline
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
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newline
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
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newline
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
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line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
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line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
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hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
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newline
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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newline
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
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newline
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
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newline
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
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newline
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
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newline
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
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newline
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
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newline
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
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newline
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
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newline
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
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newline
|
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
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newline
|
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
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newline
|
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
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newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
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newline
|
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
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newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
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rgroup.long 0x62C++0x7
|
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
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newline
|
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bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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|
newline
|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
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|
wgroup.long 0x664++0x7
|
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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rgroup.long 0x66C++0x3
|
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
|
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
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newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
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tree "FLEXCOM6"
|
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base ad:0xF8010000
|
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group.long 0x0++0x3
|
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
|
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
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newline
|
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
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newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
|
line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
|
|
rgroup.long 0x244++0x3
|
|
line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
|
group.long 0x24C++0xF
|
|
line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
|
line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
|
rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x260++0xF
|
|
line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
|
|
newline
|
|
bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
|
|
line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
|
|
hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
|
|
line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
|
|
line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
|
|
bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
|
|
rgroup.long 0x270++0x3
|
|
line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
|
|
group.long 0x274++0x17
|
|
line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
|
|
line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
|
|
line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
|
|
newline
|
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hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
|
line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
|
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hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
|
|
line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
|
|
line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
|
|
hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
|
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group.long 0x290++0x3
|
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
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|
newline
|
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
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group.long 0x2A0++0x3
|
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
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newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
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rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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|
newline
|
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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|
newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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newline
|
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
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newline
|
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x3
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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group.long 0x640++0x7
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line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
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newline
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bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
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newline
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bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
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newline
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bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
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line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
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newline
|
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bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
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group.long 0x650++0x3
|
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line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
|
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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rgroup.long 0x660++0x3
|
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
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wgroup.long 0x664++0x7
|
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM7"
|
|
base ad:0xF8014000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
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|
|
hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
|
line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
|
|
rgroup.long 0x244++0x3
|
|
line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
|
group.long 0x24C++0xF
|
|
line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
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|
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
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|
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
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|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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|
newline
|
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
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bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
|
|
newline
|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
|
rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x260++0xF
|
|
line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
|
|
newline
|
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bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
|
|
line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
|
|
hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
|
|
line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
|
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line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
|
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bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
|
|
newline
|
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bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
|
|
rgroup.long 0x270++0x3
|
|
line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
|
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hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
|
|
group.long 0x274++0x17
|
|
line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
|
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line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
|
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hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
|
|
line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
|
line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
|
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hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
|
|
line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
|
|
line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
|
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hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
|
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group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
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group.long 0x2A0++0x3
|
|
line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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wgroup.long 0x2A8++0x7
|
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM8"
|
|
base ad:0xF8018000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
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newline
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
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newline
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
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newline
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
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newline
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
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newline
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
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newline
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
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newline
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
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newline
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
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newline
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
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newline
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
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newline
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
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newline
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
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newline
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bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
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newline
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
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newline
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
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newline
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bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
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newline
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
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newline
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
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newline
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
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newline
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
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newline
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
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newline
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
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newline
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
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newline
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
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newline
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
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newline
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
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newline
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
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newline
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
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newline
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
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newline
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
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newline
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
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|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
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|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
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line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
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newline
|
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
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line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
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newline
|
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
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newline
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
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group.long 0x220++0xB
|
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
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group.long 0x228++0x3
|
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line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
|
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group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
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group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
|
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rgroup.long 0x244++0x3
|
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
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group.long 0x24C++0xF
|
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
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newline
|
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
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newline
|
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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newline
|
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
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newline
|
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
|
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
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newline
|
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
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newline
|
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
|
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
|
|
newline
|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
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rgroup.long 0x25C++0x3
|
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
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group.long 0x260++0xF
|
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line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
|
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hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
|
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newline
|
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bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
|
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line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
|
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hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
|
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line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
|
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line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
|
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bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
|
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newline
|
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bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
|
|
newline
|
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hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
|
|
rgroup.long 0x270++0x3
|
|
line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
|
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hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
|
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group.long 0x274++0x17
|
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line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
|
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line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
|
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hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
|
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line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
|
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hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
|
|
newline
|
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hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
|
line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
|
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hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
|
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line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
|
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hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
|
|
line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
|
|
hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
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newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
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newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
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newline
|
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
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newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
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newline
|
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
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newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
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newline
|
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
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newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
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|
newline
|
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bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
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|
newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
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newline
|
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
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newline
|
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
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newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
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newline
|
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
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newline
|
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
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newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
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group.long 0x604++0xF
|
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line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
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newline
|
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
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newline
|
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bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
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newline
|
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
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line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
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newline
|
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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newline
|
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
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newline
|
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
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newline
|
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
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newline
|
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
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newline
|
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
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newline
|
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
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newline
|
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
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line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
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line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
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hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
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newline
|
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
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newline
|
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
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newline
|
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
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bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
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newline
|
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
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newline
|
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
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newline
|
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
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newline
|
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
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|
newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
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line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
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bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
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newline
|
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bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
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group.long 0x650++0x3
|
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line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
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newline
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
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newline
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
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wgroup.long 0x664++0x7
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
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rgroup.long 0x6E8++0x3
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
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tree.end
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tree "FLEXCOM9"
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base ad:0xF8040000
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group.long 0x0++0x3
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
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newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
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newline
|
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
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newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
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newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
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newline
|
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
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newline
|
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
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newline
|
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
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newline
|
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
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newline
|
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
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newline
|
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
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newline
|
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
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newline
|
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
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newline
|
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bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
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newline
|
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
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newline
|
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
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newline
|
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bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
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newline
|
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
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newline
|
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
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newline
|
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
|
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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|
newline
|
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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|
newline
|
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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|
newline
|
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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rgroup.long 0x210++0x3
|
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line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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rgroup.long 0x210++0x7
|
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line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
|
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bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
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newline
|
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
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bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
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newline
|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
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line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
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bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
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newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
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newline
|
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
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group.long 0x228++0x3
|
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line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
|
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group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
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group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
|
|
rgroup.long 0x244++0x3
|
|
line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
|
group.long 0x24C++0xF
|
|
line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
newline
|
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
|
line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
|
rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x260++0xF
|
|
line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
|
|
newline
|
|
bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
|
|
line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
|
|
hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
|
|
line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
|
|
line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
|
|
bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
|
|
rgroup.long 0x270++0x3
|
|
line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
|
|
group.long 0x274++0x17
|
|
line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
|
|
line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
|
|
line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
|
|
newline
|
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hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
|
line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
|
|
line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
|
|
line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
|
|
hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
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|
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
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|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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|
newline
|
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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|
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
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newline
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x3
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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group.long 0x640++0x7
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line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
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bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
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|
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hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
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newline
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bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
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newline
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bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
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line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
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newline
|
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bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
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group.long 0x650++0x3
|
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line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
|
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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rgroup.long 0x660++0x3
|
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
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wgroup.long 0x664++0x7
|
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM10"
|
|
base ad:0xF8044000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
|
line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
|
|
rgroup.long 0x244++0x3
|
|
line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
|
group.long 0x24C++0xF
|
|
line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
newline
|
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
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|
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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|
newline
|
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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|
newline
|
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
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bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
|
|
newline
|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
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rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x260++0xF
|
|
line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
|
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hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
|
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newline
|
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bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
|
|
line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
|
|
hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
|
|
line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
|
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line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
|
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bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
|
|
newline
|
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bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
|
|
rgroup.long 0x270++0x3
|
|
line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
|
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group.long 0x274++0x17
|
|
line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
|
|
line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
|
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hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
|
|
line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
|
line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
|
|
line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
|
|
line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
|
|
hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
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newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
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bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
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line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
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|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
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|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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group.long 0x448++0x3
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
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group.long 0x4E4++0x3
|
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
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rgroup.long 0x4E8++0x3
|
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
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wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
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group.long 0x638++0x3
|
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM11"
|
|
base ad:0xF0020000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
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newline
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
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newline
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
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newline
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
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newline
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
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newline
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
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newline
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
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newline
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
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newline
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
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newline
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
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newline
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
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newline
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
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newline
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
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newline
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bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
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newline
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
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newline
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
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newline
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bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
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newline
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
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newline
|
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
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newline
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
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newline
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
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newline
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
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newline
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
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newline
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
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newline
|
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
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newline
|
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
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newline
|
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
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newline
|
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
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newline
|
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
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newline
|
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
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newline
|
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
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newline
|
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
|
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
|
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
|
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
|
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
|
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
|
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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newline
|
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
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rgroup.long 0x210++0x3
|
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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rgroup.long 0x210++0x3
|
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line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
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|
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x228++0x3
|
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line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
|
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group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
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group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
|
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rgroup.long 0x244++0x3
|
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
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group.long 0x24C++0xF
|
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
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newline
|
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
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newline
|
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
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newline
|
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
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newline
|
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
|
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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newline
|
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
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newline
|
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
|
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
|
|
newline
|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
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rgroup.long 0x25C++0x3
|
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
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group.long 0x260++0xF
|
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line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
|
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hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
|
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newline
|
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bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
|
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line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
|
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hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
|
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line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
|
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line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
|
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bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
|
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newline
|
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bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
|
|
newline
|
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hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
|
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rgroup.long 0x270++0x3
|
|
line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
|
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hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
|
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group.long 0x274++0x17
|
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line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
|
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hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
|
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line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
|
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hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
|
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line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
|
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hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
|
|
newline
|
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hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
|
line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
|
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hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
|
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line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
|
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hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
|
|
line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
|
|
hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
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wgroup.long 0x664++0x7
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
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rgroup.long 0x6E8++0x3
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
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tree.end
|
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tree "FLEXCOM12"
|
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base ad:0xF0024000
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group.long 0x0++0x3
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
|
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
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wgroup.long 0x200++0x3
|
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line.long 0x0 "FLEX_US_CR,USART Control Register"
|
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
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newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
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newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
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newline
|
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
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newline
|
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
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newline
|
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
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newline
|
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
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newline
|
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
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newline
|
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
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newline
|
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
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newline
|
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
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newline
|
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bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
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newline
|
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
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newline
|
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bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
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newline
|
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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|
newline
|
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LON_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LON_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LON_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LON_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 28. "LBLOVFE,LON Backlog Overflow Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LRXD,LON Reception End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LFET,LON Frame Early Termination" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCOL,LON Collision Detected Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LTXD,LON Transmission End Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCRCE,LON CRC Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LSFE,LON Short Frame Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
|
line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "FLEX_US_TTGR_LON_MODE_MODE,USART Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "PCYCLE,LON PCYCLE Length"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI_LON_MODE_MODE,USART FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA2,LON BETA2 Length"
|
|
rgroup.long 0x244++0x3
|
|
line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
|
group.long 0x24C++0xF
|
|
line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "PDCM,DMA Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
|
line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
|
rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x260++0xF
|
|
line.long 0x0 "FLEX_US_LONMR,USART LON Mode Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EOFS,End of Frame Condition Size"
|
|
newline
|
|
bitfld.long 0x0 5. "LCDS,LON Collision Detection Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DMAM,LON DMA Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CDTAIL,LON Collision Detection on Frame Tail" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TCOL,Terminate Frame upon Collision Notification" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COLDET,LON Collision Detection Feature" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COMMT,LON comm_type Parameter Value" "0,1"
|
|
line.long 0x4 "FLEX_US_LONPR,USART LON Preamble Register"
|
|
hexmask.long.word 0x4 0.--13. 1. "LONPL,LON Preamble Length"
|
|
line.long 0x8 "FLEX_US_LONDL,USART LON Data Length Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "LONDL,LON Data Length"
|
|
line.long 0xC "FLEX_US_LONL2HDR,USART LON L2HDR Register"
|
|
bitfld.long 0xC 7. "PB,LON Priority Bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "ALTP,LON Alternate Path Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "BLI,LON Backlog Increment"
|
|
rgroup.long 0x270++0x3
|
|
line.long 0x0 "FLEX_US_LONBL,USART LON Backlog Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "LONBL,LON Node Backlog Value"
|
|
group.long 0x274++0x17
|
|
line.long 0x0 "FLEX_US_LONB1TX,USART LON Beta1 Tx Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "BETA1TX,LON Beta1 Length after Transmission"
|
|
line.long 0x4 "FLEX_US_LONB1RX,USART LON Beta1 Rx Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "BETA1RX,LON Beta1 Length after Reception"
|
|
line.long 0x8 "FLEX_US_LONPRIO,USART LON Priority Register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "NPS,LON Node Priority Slot"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "PSNB,LON Priority Slot Number"
|
|
line.long 0xC "FLEX_US_IDTTX,USART LON IDT Tx Register"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "IDTTX,LON Indeterminate Time after Transmission (comm_type = 1 mode only)"
|
|
line.long 0x10 "FLEX_US_IDTRX,USART LON IDT Rx Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "IDTRX,LON Indeterminate Time after Reception (comm_type = 1 mode only)"
|
|
line.long 0x14 "FLEX_US_ICDIFF,USART IC DIFF Register"
|
|
hexmask.long.byte 0x14 0.--3. 1. "ICDIFF,IC Differentiator Number"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
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group.long 0x2A0++0x3
|
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
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wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "GFX2D (2D Graphics Engine)"
|
|
base ad:0xF0018000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "GC,Global Configuration Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "REGQOS3,Regulation for QoS Level 3"
|
|
hexmask.long.byte 0x0 12.--15. 1. "REGQOS2,Regulation for QoS Level 2"
|
|
hexmask.long.byte 0x0 8.--11. 1. "REGQOS1,Regulation for QoS Level 1"
|
|
bitfld.long 0x0 6. "MTY,Memory Tile Access" "0,1"
|
|
bitfld.long 0x0 4. "REGEN,Outstanding Regulation Enable" "0,1"
|
|
bitfld.long 0x0 2. "CGDISFIFO,Clock Gating Disable FIFO" "0,1"
|
|
bitfld.long 0x0 1. "CGDISAXI,Clock Gating Disable AXI" "0,1"
|
|
bitfld.long 0x0 0. "CGDISCORE,Clock Gating Disable Core" "0,1"
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "GE,Global Enable Register"
|
|
bitfld.long 0x0 0. "ENABLE,GFX2D Enable" "0,1"
|
|
line.long 0x4 "GD,Global Disable Register"
|
|
bitfld.long 0x4 8. "WFERES,WFE Software Resume bit" "0,1"
|
|
bitfld.long 0x4 0. "DISABLE,GFX2D Disable Bit" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "GS,Global Status Register"
|
|
bitfld.long 0x0 8. "WFEIP,Wait For Event Status bit" "0,1"
|
|
bitfld.long 0x0 4. "BUSY,GFX2D Busy Bit" "0,1"
|
|
bitfld.long 0x0 0. "STATUS,GFX2D Status Bit" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x0 4. "IERR,Illegal Instruction Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 3. "BERR,Write Data Bus Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 2. "RERR,Read Data Bus Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 1. "EXEND,End of Execution Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 0. "RBEMPTY,Ring Buffer Empty Interrupt Enable Bit" "0,1"
|
|
line.long 0x4 "ID,Interrupt Disable Register"
|
|
bitfld.long 0x4 4. "IERR,Illegal Instruction Interrupt Disable bit" "0,1"
|
|
bitfld.long 0x4 3. "BERR,Write Access Error Interrupt Disable bit" "0,1"
|
|
bitfld.long 0x4 2. "RERR,Read Access Error Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 1. "EXEND,End of Execution Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 0. "RBEMPTY,Ring Buffer Empty Interrupt Disable Bit" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IM,Interrupt Mask Register"
|
|
bitfld.long 0x0 4. "IERR,Illegal Instruction Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 3. "BERR,Write Error Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 2. "RERR,Read Error Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 1. "EXEND,Execution Ended Empty Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 0. "RBEMPTY,Ring Buffer Empty Interrupt Mask Bit" "0,1"
|
|
line.long 0x4 "IS,Interrupt Status Register"
|
|
bitfld.long 0x4 4. "IERR,Illegal Instruction Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 3. "BERR,Write Error Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 2. "RERR,Read Error Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 1. "EXEND,End of Execution Status Bit" "0,1"
|
|
bitfld.long 0x4 0. "RBEMPTY,Ring Buffer Empty Interrupt Status Bit" "0,1"
|
|
repeat 2. (list 0x0 0x1)(list ad:0xF0018020 ad:0xF0018028)
|
|
tree "GFX2D_SUB0[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "PC,Performance Configuration 0 Register"
|
|
bitfld.long 0x0 4.--6. "FILT,Filter Configuration" "0: The filter is disabled.,1: Events are valid when input QoS is equal to 0.,2: Events are valid when input QoS is equal to 1.,3: Events are valid when input QoS is equal to 2.,4: Events are valid when input QoS is equal to 3.,?,?,?"
|
|
bitfld.long 0x0 0.--1. "SEL,Performance Metrics Selection" "0: The performance counter is disabled and reset.,1: The performance counter is incremented when a..,2: The performance counter is incremented when a..,3: Number of clock cycles"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "MC,Metrics Counter 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER,Metrics Counter"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF0018000
|
|
newline
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "BASE,Ring Buffer Base Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "BASE,Ring Buffer Base Register"
|
|
line.long 0x4 "LEN,Ring Buffer Length Register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "LEN,Ring Buffer Length Multiplier"
|
|
line.long 0x8 "HEAD,Ring Buffer Head Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "HEAD,Ring Buffer Head Pointer"
|
|
line.long 0xC "TAIL,Ring Buffer Tail Register"
|
|
hexmask.long.word 0xC 0.--9. 1. "TAIL,Ring Buffer Tail Pointer"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xF0018040 ad:0xF0018050 ad:0xF0018060 ad:0xF0018070)
|
|
tree "GFX2D_CHID[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "PA,Surface Physical Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "PA,Surface Physical Start Address"
|
|
line.long 0x4 "PITCH,Surface Pitch Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "PITCH,Surface Pitch"
|
|
line.long 0x8 "CFG,Surface Configuration Register"
|
|
bitfld.long 0x8 4. "IDXCX,Color Look-Up Table Selection" "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "PF,Pixel Format"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "GPBR (General Purpose Backup Registers)"
|
|
base ad:0xFFFFFE60
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "MR,GPBR Mode Register"
|
|
bitfld.long 0x0 31. "GPBRRP15,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 30. "GPBRRP14,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 29. "GPBRRP13,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 28. "GPBRRP12,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 27. "GPBRRP11,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 26. "GPBRRP10,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 25. "GPBRRP9,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 24. "GPBRRP8,GPBRx Read Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "GPBRRP7,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 22. "GPBRRP6,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 21. "GPBRRP5,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 20. "GPBRRP4,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 19. "GPBRRP3,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 18. "GPBRRP2,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 17. "GPBRRP1,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 16. "GPBRRP0,GPBRx Read Protection" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "GPBRWP15,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 14. "GPBRWP14,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 13. "GPBRWP13,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 12. "GPBRWP12,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 11. "GPBRWP11,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 10. "GPBRWP10,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 9. "GPBRWP9,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 8. "GPBRWP8,GPBRx Write Protection" "0,1"
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|
newline
|
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bitfld.long 0x0 7. "GPBRWP7,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 6. "GPBRWP6,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 5. "GPBRWP5,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 4. "GPBRWP4,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 3. "GPBRWP3,GPBRx Write Protection" "0,1"
|
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bitfld.long 0x0 2. "GPBRWP2,GPBRx Write Protection" "0,1"
|
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bitfld.long 0x0 1. "GPBRWP1,GPBRx Write Protection" "0,1"
|
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bitfld.long 0x0 0. "GPBRWP0,GPBRx Write Protection" "0,1"
|
|
line.long 0x4 "FCLR,GPBR Full Clear Register"
|
|
bitfld.long 0x4 0. "FCLR,Full Clear Enable" "0,1"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
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group.long ($2+0x8)++0x3
|
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line.long 0x0 "SYS_GPBR[$1],General Purpose Backup Register"
|
|
hexmask.long 0x0 0.--31. 1. "GPBR_VALUE,Value of SYS_GPBR x"
|
|
repeat.end
|
|
tree.end
|
|
tree "I2SMCC (Inter-IC Sound Multi Channel Controller)"
|
|
base ad:0xF001C000
|
|
wgroup.long 0x0++0x3
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line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 5. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TXEN,Transmitter Enable" "0,1"
|
|
bitfld.long 0x0 3. "CKDIS,Clocks Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CKEN,Clocks Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXEN,Receiver Enable" "0,1"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "MRA,Mode Register A"
|
|
bitfld.long 0x0 31. "IWS,I2SMCC_WS Slot Length" "0,1"
|
|
bitfld.long 0x0 30. "IMCKMODE,Master Clock Mode" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 24.--29. 1. "ISCKDIV,Selected Clock to I2SMCC Serial Clock Ratio"
|
|
bitfld.long 0x0 22.--23. "TDMFS,TDM Frame Synchronization" "0: I2SMCC_WS pulse is high for one time slot at..,1: I2SMCC_WS pulse is high for half the time slots..,2: I2SMCC_WS pulse is high for one bit period at..,?"
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "IMCKDIV,Selected Clock to I2SMCC Master Clock Ratio"
|
|
bitfld.long 0x0 13.--15. "NBCHAN,Number of TDM Channels-1" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x0 12. "SRCCLK,Source Clock Selection" "0,1"
|
|
bitfld.long 0x0 11. "TXSAME,Transmit Data when Underrun" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "TXMONO,Transmit Mono" "0,1"
|
|
bitfld.long 0x0 9. "RXLOOP,Loop-back Test Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RXMONO,Receive Mono" "0,1"
|
|
bitfld.long 0x0 6.--7. "FORMAT,Data Format" "0: I2S format stereo with I2SMCC_WS low for left..,1: Left-justified format stereo with I2SMCC_WS high..,2: TDM format with (NBCHAN + 1) channels I2SMCC_WS..,3: TDM format left-justified with (NBCHAN + 1).."
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newline
|
|
bitfld.long 0x0 4.--5. "ZERO,Must always be written to 0." "0,1,2,3"
|
|
bitfld.long 0x0 1.--3. "DATALENGTH,Data Word Length" "0: Data length is set to 32 bits.,1: Data length is set to 24 bits.,2: Data length is set to 20 bits.,3: Data length is set to 18 bits.,4: Data length is set to 16 bits.,5: Data length is set to 16-bit compact stereo.,6: Data length is set to 8 bits.,7: Data length is set to 8-bit compact stereo. Left.."
|
|
newline
|
|
bitfld.long 0x0 0. "MODE,Inter-IC Sound Multi Channel Controller Mode" "0: I2SMCC_CK and I2SMCC_WS pin inputs used as bit..,1: Bit clock and word select/frame synchronization.."
|
|
line.long 0x4 "MRB,Mode Register B"
|
|
bitfld.long 0x4 16. "CLKSEL,Serial Clock Selection" "0,1"
|
|
bitfld.long 0x4 8.--9. "DMACHUNK,DMA Chunk Size" "0: Each DMA transfer contains 1 word.,1: Each DMA transfer contains 2 words.,2: Each DMA transfer contains 4 words.,3: Each DMA transfer contains 8 words."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 4. "TXEN,Transmitter Enabled" "0,1"
|
|
bitfld.long 0x0 0. "RXEN,Receiver Enabled" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IERA,Interrupt Enable Register A"
|
|
bitfld.long 0x0 31. "RXROVF3,I2S Receive Right 3 (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "RXLOVF3,I2S Receive Left 3 (x=0 only) or TDM Channel 2x Overrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXROVF2,I2S Receive Right 2 (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "RXLOVF2,I2S Receive Left 2 (x=0 only) or TDM Channel 2x Overrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXROVF1,I2S Receive Right 1 (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "RXLOVF1,I2S Receive Left 1 (x=0 only) or TDM Channel 2x Overrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXROVF0,I2S Receive Right 0 (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "RXLOVF0,I2S Receive Left 0 (x=0 only) or TDM Channel 2x Overrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RXRRDY3,I2S Receive Right 3 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "RXLRDY3,I2S Receive Left 3 (x=0 only) or TDM Channel 2x Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RXRRDY2,I2S Receive Right 2 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "RXLRDY2,I2S Receive Left 2 (x=0 only) or TDM Channel 2x Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RXRRDY1,I2S Receive Right 1 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "RXLRDY1,I2S Receive Left 1 (x=0 only) or TDM Channel 2x Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXRRDY0,I2S Receive Right 0 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "RXLRDY0,I2S Receive Left 0 (x=0 only) or TDM Channel 2x Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXRUNF3,I2S Transmit Right 3 (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "TXLUNF3,I2S Transmit Left 3 (x=0 only) or TDM Channel 2x Underrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TXRUNF2,I2S Transmit Right 2 (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "TXLUNF2,I2S Transmit Left 2 (x=0 only) or TDM Channel 2x Underrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXRUNF1,I2S Transmit Right 1 (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "TXLUNF1,I2S Transmit Left 1 (x=0 only) or TDM Channel 2x Underrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXRUNF0,I2S Transmit Right 0 (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXLUNF0,I2S Transmit Left 0 (x=0 only) or TDM Channel 2x Underrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXRRDY3,I2S Transmit Right 3 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "TXLRDY3,I2S Transmit Left 3 (x=0 only) or TDM Channel 2x Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXRRDY2,I2S Transmit Right 2 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "TXLRDY2,I2S Transmit Left 2 (x=0 only) or TDM Channel 2x Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXRRDY1,I2S Transmit Right 1 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "TXLRDY1,I2S Transmit Left 1 (x=0 only) or TDM Channel 2x Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRRDY0,I2S Transmit Right 0 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "TXLRDY0,I2S Transmit Left 0 (x=0 only) or TDM Channel 2x Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDRA,Interrupt Disable Register A"
|
|
bitfld.long 0x4 31. "RXROVF3,I2S Receive Right 3 (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "RXLOVF3,I2S Receive Left 3 (x=0 only) or TDM Channel 2x Overrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXROVF2,I2S Receive Right 2 (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "RXLOVF2,I2S Receive Left 2 (x=0 only) or TDM Channel 2x Overrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXROVF1,I2S Receive Right 1 (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "RXLOVF1,I2S Receive Left 1 (x=0 only) or TDM Channel 2x Overrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "RXROVF0,I2S Receive Right 0 (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "RXLOVF0,I2S Receive Left 0 (x=0 only) or TDM Channel 2x Overrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "RXRRDY3,I2S Receive Right 3 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "RXLRDY3,I2S Receive Left 3 (x=0 only) or TDM Channel 2x Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "RXRRDY2,I2S Receive Right 2 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "RXLRDY2,I2S Receive Left 2 (x=0 only) or TDM Channel 2x Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "RXRRDY1,I2S Receive Right 1 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "RXLRDY1,I2S Receive Left 1 (x=0 only) or TDM Channel 2x Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "RXRRDY0,I2S Receive Right 0 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "RXLRDY0,I2S Receive Left 0 (x=0 only) or TDM Channel 2x Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXRUNF3,I2S Transmit Right 3 (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "TXLUNF3,I2S Transmit Left 3 (x=0 only) or TDM Channel 2x Underrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TXRUNF2,I2S Transmit Right 2 (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "TXLUNF2,I2S Transmit Left 2 (x=0 only) or TDM Channel 2x Underrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXRUNF1,I2S Transmit Right 1 (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "TXLUNF1,I2S Transmit Left 1 (x=0 only) or TDM Channel 2x Underrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXRUNF0,I2S Transmit Right 0 (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "TXLUNF0,I2S Transmit Left 0 (x=0 only) or TDM Channel 2x Underrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TXRRDY3,I2S Transmit Right 3 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "TXLRDY3,I2S Transmit Left 3 (x=0 only) or TDM Channel 2x Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TXRRDY2,I2S Transmit Right 2 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "TXLRDY2,I2S Transmit Left 2 (x=0 only) or TDM Channel 2x Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TXRRDY1,I2S Transmit Right 1 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "TXLRDY1,I2S Transmit Left 1 (x=0 only) or TDM Channel 2x Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRRDY0,I2S Transmit Right 0 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "TXLRDY0,I2S Transmit Left 0 (x=0 only) or TDM Channel 2x Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMRA,Interrupt Mask Register A"
|
|
bitfld.long 0x0 31. "RXROVF3,I2S Receive Right 3 (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "RXLOVF3,I2S Receive Left 3 (x=0 only) or TDM Channel 2x Overrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXROVF2,I2S Receive Right 2 (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "RXLOVF2,I2S Receive Left 2 (x=0 only) or TDM Channel 2x Overrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXROVF1,I2S Receive Right 1 (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "RXLOVF1,I2S Receive Left 1 (x=0 only) or TDM Channel 2x Overrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXROVF0,I2S Receive Right 0 (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "RXLOVF0,I2S Receive Left 0 (x=0 only) or TDM Channel 2x Overrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RXRRDY3,I2S Receive Right 3 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "RXLRDY3,I2S Receive Left 3 (x=0 only) or TDM Channel 2x Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RXRRDY2,I2S Receive Right 2 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "RXLRDY2,I2S Receive Left 2 (x=0 only) or TDM Channel 2x Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RXRRDY1,I2S Receive Right 1 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "RXLRDY1,I2S Receive Left 1 (x=0 only) or TDM Channel 2x Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXRRDY0,I2S Receive Right 0 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "RXLRDY0,I2S Receive Left 0 (x=0 only) or TDM Channel 2x Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXRUNF3,I2S Transmit Right 3 (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "TXLUNF3,I2S Transmit Left 3 (x=0 only) or TDM Channel 2x Underrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TXRUNF2,I2S Transmit Right 2 (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "TXLUNF2,I2S Transmit Left 2 (x=0 only) or TDM Channel 2x Underrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXRUNF1,I2S Transmit Right 1 (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "TXLUNF1,I2S Transmit Left 1 (x=0 only) or TDM Channel 2x Underrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXRUNF0,I2S Transmit Right 0 (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "TXLUNF0,I2S Transmit Left 0 (x=0 only) or TDM Channel 2x Underrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXRRDY3,I2S Transmit Right 3 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "TXLRDY3,I2S Transmit Left 3 (x=0 only) or TDM Channel 2x Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXRRDY2,I2S Transmit Right 2 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "TXLRDY2,I2S Transmit Left 2 (x=0 only) or TDM Channel 2x Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXRRDY1,I2S Transmit Right 1 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "TXLRDY1,I2S Transmit Left 1 (x=0 only) or TDM Channel 2x Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRRDY0,I2S Transmit Right 0 (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "TXLRDY0,I2S Transmit Left 0 (x=0 only) or TDM Channel 2x Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISRA,Interrupt Status Register A"
|
|
bitfld.long 0x4 31. "RXROVF3,I2S Receive Right 3 (x=0 only) or TDM Channel [2x]+1 Overrun Flag (Cleared on read)" "0,1"
|
|
bitfld.long 0x4 30. "RXLOVF3,I2S Receive Left 3 (x=0 only) or TDM Channel 2x Overrun Flag (Cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXROVF2,I2S Receive Right 2 (x=0 only) or TDM Channel [2x]+1 Overrun Flag (Cleared on read)" "0,1"
|
|
bitfld.long 0x4 28. "RXLOVF2,I2S Receive Left 2 (x=0 only) or TDM Channel 2x Overrun Flag (Cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXROVF1,I2S Receive Right 1 (x=0 only) or TDM Channel [2x]+1 Overrun Flag (Cleared on read)" "0,1"
|
|
bitfld.long 0x4 26. "RXLOVF1,I2S Receive Left 1 (x=0 only) or TDM Channel 2x Overrun Flag (Cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "RXROVF0,I2S Receive Right 0 (x=0 only) or TDM Channel [2x]+1 Overrun Flag (Cleared on read)" "0,1"
|
|
bitfld.long 0x4 24. "RXLOVF0,I2S Receive Left 0 (x=0 only) or TDM Channel 2x Overrun Flag (Cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "RXRRDY3,I2S Receive Right 3 (x=0 only) or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR)" "0,1"
|
|
bitfld.long 0x4 22. "RXLRDY3,I2S Receive Left 3 (x=0 only) or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "RXRRDY2,I2S Receive Right 2 (x=0 only) or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR)" "0,1"
|
|
bitfld.long 0x4 20. "RXLRDY2,I2S Receive Left 2 (x=0 only) or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "RXRRDY1,I2S Receive Right 1 (x=0 only) or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR)" "0,1"
|
|
bitfld.long 0x4 18. "RXLRDY1,I2S Receive Left 1 (x=0 only) or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "RXRRDY0,I2S Receive Right 0 (x=0 only) or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR)" "0,1"
|
|
bitfld.long 0x4 16. "RXLRDY0,I2S Receive Left 0 (x=0 only) or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXRUNF3,I2S Transmit Right 3 (x=0 only) or TDM Channel [2x]+1 Underrun Flag (Cleared on read)" "0,1"
|
|
bitfld.long 0x4 14. "TXLUNF3,I2S Transmit Left 3 (x=0 only) or TDM Channel 2x Underrun (Cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TXRUNF2,I2S Transmit Right 2 (x=0 only) or TDM Channel [2x]+1 Underrun Flag (Cleared on read)" "0,1"
|
|
bitfld.long 0x4 12. "TXLUNF2,I2S Transmit Left 2 (x=0 only) or TDM Channel 2x Underrun (Cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXRUNF1,I2S Transmit Right 1 (x=0 only) or TDM Channel [2x]+1 Underrun Flag (Cleared on read)" "0,1"
|
|
bitfld.long 0x4 10. "TXLUNF1,I2S Transmit Left 1 (x=0 only) or TDM Channel 2x Underrun (Cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "TXRUNF0,I2S Transmit Right 0 (x=0 only) or TDM Channel [2x]+1 Underrun Flag (Cleared on read)" "0,1"
|
|
bitfld.long 0x4 8. "TXLUNF0,I2S Transmit Left 0 (x=0 only) or TDM Channel 2x Underrun (Cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "TXRRDY3,I2S Transmit Right 3 (x=0 only) or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR)" "0,1"
|
|
bitfld.long 0x4 6. "TXLRDY3,I2S Transmit Left 3 (x=0 only) or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "TXRRDY2,I2S Transmit Right 2 (x=0 only) or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR)" "0,1"
|
|
bitfld.long 0x4 4. "TXLRDY2,I2S Transmit Left 2 (x=0 only) or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "TXRRDY1,I2S Transmit Right 1 (x=0 only) or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR)" "0,1"
|
|
bitfld.long 0x4 2. "TXLRDY1,I2S Transmit Left 1 (x=0 only) or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXRRDY0,I2S Transmit Right 0 (x=0 only) or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR)" "0,1"
|
|
bitfld.long 0x4 0. "TXLRDY0,I2S Transmit Left 0 (x=0 only) or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR)" "0,1"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "IERB,Interrupt Enable Register B"
|
|
bitfld.long 0x0 0. "WERR,Write Error Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDRB,Interrupt Disable Register B"
|
|
bitfld.long 0x4 0. "WERR,Write Error Interrupt Disable" "0,1"
|
|
rgroup.long 0x28++0xB
|
|
line.long 0x0 "IMRB,Interrupt Mask Register B"
|
|
bitfld.long 0x0 0. "WERR,Write Error Interrupt Enable" "0,1"
|
|
line.long 0x4 "ISRB,Interrupt Status Register B"
|
|
bitfld.long 0x4 0. "WERR,Write Error Flag (cleared on read)" "0,1"
|
|
line.long 0x8 "RHR,Receiver Holding Register"
|
|
hexmask.long 0x8 0.--31. 1. "RHR,Receiver Holding Register"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x0 "THR,Transmitter Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "THR,Transmitter Holding Register"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCTEN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPCFEN,Write Protection Configuration Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "ISI (Image Sensor Interface)"
|
|
base ad:0xF8048000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CFG1,ISI Configuration 1 Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SFD,Start of Frame Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. "SLD,Start of Line Delay"
|
|
newline
|
|
bitfld.long 0x0 13.--14. "THMASK,Threshold Mask" "0: Only 4 beats AHB burst allowed,1: Only 4 and 8 beats AHB burst allowed,2: 4 8 and 16 beats AHB burst allowed,?"
|
|
bitfld.long 0x0 12. "FULL,Full Mode is Allowed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DISCR,Disable Codec Request" "0,1"
|
|
bitfld.long 0x0 8.--10. "FRATE,Frame Rate [0..7]" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 7. "CRC_SYNC,Embedded Synchronization Correction" "0,1"
|
|
bitfld.long 0x0 6. "EMB_SYNC,Embedded Synchronization" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PIXCLK_POL,Pixel Clock Polarity" "0,1"
|
|
bitfld.long 0x0 3. "VSYNC_POL,Vertical Synchronization Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "HSYNC_POL,Horizontal Synchronization Polarity" "0,1"
|
|
line.long 0x4 "CFG2,ISI Configuration 2 Register"
|
|
bitfld.long 0x4 30.--31. "RGB_CFG,RGB Pixel Mapping Configuration" "0: Byte 0 R/G(MSB) Byte 1 G(LSB)/B Byte 2 R/G(MSB)..,1: Byte 0 B/G(MSB) Byte 1 G(LSB)/R Byte 2 B/G(MSB)..,2: Byte 0 G(LSB)/R Byte 1 B/G(MSB) Byte 2 G(LSB)/R..,3: Byte 0 G(LSB)/B Byte 1 R/G(MSB) Byte 2 G(LSB)/B.."
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|
bitfld.long 0x4 28.--29. "YCC_SWAP,YCrCb Format Swap Mode" "0: Byte 0 Cb(i) Byte 1 Y(i) Byte 2 Cr(i) Byte 3..,1: Byte 0 Cr(i) Byte 1 Y(i) Byte 2 Cb(i) Byte 3..,2: Byte 0 Y(i) Byte 1 Cb(i) Byte 2 Y(i+1) Byte 3..,3: Byte 0 Y(i) Byte 1 Cr(i) Byte 2 Y(i+1) Byte 3.."
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|
newline
|
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hexmask.long.word 0x4 16.--26. 1. "IM_HSIZE,Horizontal Size of the Image Sensor [0..2047]"
|
|
bitfld.long 0x4 15. "COL_SPACE,Color Space for the Image Data" "0,1"
|
|
newline
|
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bitfld.long 0x4 14. "RGB_SWAP,RGB Format Swap Mode" "0,1"
|
|
bitfld.long 0x4 13. "GRAYSCALE,Grayscale Mode Format Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RGB_MODE,RGB Input Mode" "0,1"
|
|
bitfld.long 0x4 11. "GS_MODE,Grayscale Pixel Format Mode" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--10. 1. "IM_VSIZE,Vertical Size of the Image Sensor [0..2047]"
|
|
line.long 0x8 "PSIZE,ISI Preview Size Register"
|
|
hexmask.long.word 0x8 16.--25. 1. "PREV_HSIZE,Horizontal Size for the Preview Path"
|
|
hexmask.long.word 0x8 0.--9. 1. "PREV_VSIZE,Vertical Size for the Preview Path"
|
|
line.long 0xC "PDECF,ISI Preview Decimation Factor Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "DEC_FACTOR,Decimation Factor"
|
|
line.long 0x10 "Y2R_SET0,ISI Color Space Conversion YCrCb To RGB Set 0 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "C3,Color Space Conversion Matrix Coefficient C3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "C2,Color Space Conversion Matrix Coefficient C2"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "C1,Color Space Conversion Matrix Coefficient C1"
|
|
hexmask.long.byte 0x10 0.--7. 1. "C0,Color Space Conversion Matrix Coefficient C0"
|
|
line.long 0x14 "Y2R_SET1,ISI Color Space Conversion YCrCb To RGB Set 1 Register"
|
|
bitfld.long 0x14 14. "Cboff,Color Space Conversion Blue Chrominance Default Offset" "0,1"
|
|
bitfld.long 0x14 13. "Croff,Color Space Conversion Red Chrominance Default Offset" "0,1"
|
|
newline
|
|
bitfld.long 0x14 12. "Yoff,Color Space Conversion Luminance Default Offset" "0,1"
|
|
hexmask.long.word 0x14 0.--8. 1. "C4,Color Space Conversion Matrix Coefficient C4"
|
|
line.long 0x18 "R2Y_SET0,ISI Color Space Conversion RGB To YCrCb Set 0 Register"
|
|
bitfld.long 0x18 24. "Roff,Color Space Conversion Red Component Offset" "0,1"
|
|
hexmask.long.byte 0x18 16.--22. 1. "C2,Color Space Conversion Matrix Coefficient C2"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--14. 1. "C1,Color Space Conversion Matrix Coefficient C1"
|
|
hexmask.long.byte 0x18 0.--6. 1. "C0,Color Space Conversion Matrix Coefficient C0"
|
|
line.long 0x1C "R2Y_SET1,ISI Color Space Conversion RGB To YCrCb Set 1 Register"
|
|
bitfld.long 0x1C 24. "Goff,Color Space Conversion Green Component Offset" "0,1"
|
|
hexmask.long.byte 0x1C 16.--22. 1. "C5,Color Space Conversion Matrix Coefficient C5"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--14. 1. "C4,Color Space Conversion Matrix Coefficient C4"
|
|
hexmask.long.byte 0x1C 0.--6. 1. "C3,Color Space Conversion Matrix Coefficient C3"
|
|
line.long 0x20 "R2Y_SET2,ISI Color Space Conversion RGB To YCrCb Set 2 Register"
|
|
bitfld.long 0x20 24. "Boff,Color Space Conversion Blue Component Offset" "0,1"
|
|
hexmask.long.byte 0x20 16.--22. 1. "C8,Color Space Conversion Matrix Coefficient C8"
|
|
newline
|
|
hexmask.long.byte 0x20 8.--14. 1. "C7,Color Space Conversion Matrix Coefficient C7"
|
|
hexmask.long.byte 0x20 0.--6. 1. "C6,Color Space Conversion Matrix Coefficient C6"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "CR,ISI Control Register"
|
|
bitfld.long 0x0 8. "ISI_CDC,ISI Codec Request" "0,1"
|
|
bitfld.long 0x0 2. "ISI_SRST,ISI Software Reset Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ISI_DIS,ISI Module Disable Request" "0,1"
|
|
bitfld.long 0x0 0. "ISI_EN,ISI Module Enable Request" "0,1"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "SR,ISI Status Register"
|
|
bitfld.long 0x0 27. "FR_OVR,Frame Rate Overrun (cleared on read)" "0,1"
|
|
bitfld.long 0x0 26. "CRC_ERR,CRC Synchronization Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "C_OVR,Codec Datapath Overflow (cleared on read)" "0,1"
|
|
bitfld.long 0x0 24. "P_OVR,Preview Datapath Overflow (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SIP,Synchronization in Progress" "0,1"
|
|
bitfld.long 0x0 17. "CXFR_DONE,Codec DMA Transfer has Terminated (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PXFR_DONE,Preview DMA Transfer has Terminated (cleared on read)" "0,1"
|
|
bitfld.long 0x0 10. "VSYNC,Vertical Synchronization (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CDC_PND,Pending Codec Request" "0,1"
|
|
bitfld.long 0x0 2. "SRST,Module Software Reset Request has Terminated (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DIS_DONE,Module Disable Request has Terminated (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,Module Enable" "0,1"
|
|
wgroup.long 0x2C++0x7
|
|
line.long 0x0 "IER,ISI Interrupt Enable Register"
|
|
bitfld.long 0x0 27. "FR_OVR,Frame Rate Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "CRC_ERR,Embedded Synchronization CRC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "C_OVR,Codec Datapath Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "P_OVR,Preview Datapath Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CXFR_DONE,Codec DMA Transfer Done Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "PXFR_DONE,Preview DMA Transfer Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "VSYNC,Vertical Synchronization Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "SRST,Software Reset Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DIS_DONE,Disable Done Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,ISI Interrupt Disable Register"
|
|
bitfld.long 0x4 27. "FR_OVR,Frame Rate Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "CRC_ERR,Embedded Synchronization CRC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "C_OVR,Codec Datapath Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "P_OVR,Preview Datapath Overflow Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CXFR_DONE,Codec DMA Transfer Done Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "PXFR_DONE,Preview DMA Transfer Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "VSYNC,Vertical Synchronization Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "SRST,Software Reset Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DIS_DONE,Disable Done Interrupt Disable" "0,1"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "IMR,ISI Interrupt Mask Register"
|
|
bitfld.long 0x0 27. "FR_OVR,Frame Rate Overrun" "0,1"
|
|
bitfld.long 0x0 26. "CRC_ERR,CRC Synchronization Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "C_OVR,Codec FIFO Overflow" "0,1"
|
|
bitfld.long 0x0 24. "P_OVR,Preview FIFO Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CXFR_DONE,Codec DMA Transfer Completed" "0,1"
|
|
bitfld.long 0x0 16. "PXFR_DONE,Preview DMA Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "VSYNC,Vertical Synchronization" "0,1"
|
|
bitfld.long 0x0 2. "SRST,Software Reset Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DIS_DONE,Module Disable Operation Completed" "0,1"
|
|
wgroup.long 0x38++0x7
|
|
line.long 0x0 "DMA_CHER,DMA Channel Enable Register"
|
|
bitfld.long 0x0 1. "C_CH_EN,Codec Channel Enable" "0,1"
|
|
bitfld.long 0x0 0. "P_CH_EN,Preview Channel Enable" "0,1"
|
|
line.long 0x4 "DMA_CHDR,DMA Channel Disable Register"
|
|
bitfld.long 0x4 1. "C_CH_DIS,Codec Channel Disable Request" "0,1"
|
|
bitfld.long 0x4 0. "P_CH_DIS,Preview Channel Disable Request" "0,1"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DMA_CHSR,DMA Channel Status Register"
|
|
bitfld.long 0x0 1. "C_CH_S,Code DMA Channel Status" "0,1"
|
|
bitfld.long 0x0 0. "P_CH_S,Preview DMA Channel Status" "0,1"
|
|
group.long 0x44++0x17
|
|
line.long 0x0 "DMA_P_ADDR,DMA Preview Base Address Register"
|
|
hexmask.long 0x0 2.--31. 1. "P_ADDR,Preview Image Base Address"
|
|
line.long 0x4 "DMA_P_CTRL,DMA Preview Control Register"
|
|
bitfld.long 0x4 3. "P_DONE,Preview Transfer Done" "0,1"
|
|
bitfld.long 0x4 2. "P_IEN,Transfer Done Flag Control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P_WB,Descriptor Writeback Control Bit" "0,1"
|
|
bitfld.long 0x4 0. "P_FETCH,Descriptor Fetch Control Bit" "0,1"
|
|
line.long 0x8 "DMA_P_DSCR,DMA Preview Descriptor Address Register"
|
|
hexmask.long 0x8 2.--31. 1. "P_DSCR,Preview Descriptor Base Address"
|
|
line.long 0xC "DMA_C_ADDR,DMA Codec Base Address Register"
|
|
hexmask.long 0xC 2.--31. 1. "C_ADDR,Codec Image Base Address"
|
|
line.long 0x10 "DMA_C_CTRL,DMA Codec Control Register"
|
|
bitfld.long 0x10 3. "C_DONE,Codec Transfer Done" "0,1"
|
|
bitfld.long 0x10 2. "C_IEN,Transfer Done Flag Control" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "C_WB,Descriptor Writeback Control Bit" "0,1"
|
|
bitfld.long 0x10 0. "C_FETCH,Descriptor Fetch Control Bit" "0,1"
|
|
line.long 0x14 "DMA_C_DSCR,DMA Codec Descriptor Address Register"
|
|
hexmask.long 0x14 2.--31. 1. "C_DSCR,Codec Descriptor Base Address"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key Password"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "LCDC (LCD Controller)"
|
|
base ad:0xF8038000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "LCDCFG0,LCD Controller Configuration Register 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CLKDIV,LCD Controller Clock Divider"
|
|
bitfld.long 0x0 11. "CGDISHEO,Clock Gating Disable Control for the High-End Overlay" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CGDISOVR2,Clock Gating Disable Control for the Overlay 2 Layer" "0,1"
|
|
bitfld.long 0x0 9. "CGDISOVR1,Clock Gating Disable Control for the Overlay 1 Layer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CGDISBASE,Clock Gating Disable Control for the Base Layer" "0,1"
|
|
bitfld.long 0x0 3. "CLKPWMSEL,LCD Controller PWM Clock Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKPOL,LCD Controller Clock Polarity" "0,1"
|
|
line.long 0x4 "LCDCFG1,LCD Controller Configuration Register 1"
|
|
hexmask.long.word 0x4 16.--25. 1. "VSPW,Vertical Synchronization Pulse Width"
|
|
hexmask.long.word 0x4 0.--9. 1. "HSPW,Horizontal Synchronization Pulse Width"
|
|
line.long 0x8 "LCDCFG2,LCD Controller Configuration Register 2"
|
|
hexmask.long.word 0x8 16.--25. 1. "VBPW,Vertical Back Porch Width"
|
|
hexmask.long.word 0x8 0.--9. 1. "VFPW,Vertical Front Porch Width"
|
|
line.long 0xC "LCDCFG3,LCD Controller Configuration Register 3"
|
|
hexmask.long.word 0xC 16.--25. 1. "HBPW,Horizontal Back Porch Width"
|
|
hexmask.long.word 0xC 0.--9. 1. "HFPW,Horizontal Front Porch Width"
|
|
line.long 0x10 "LCDCFG4,LCD Controller Configuration Register 4"
|
|
hexmask.long.word 0x10 16.--26. 1. "RPF,Number of Active Row Per Frame"
|
|
hexmask.long.word 0x10 0.--10. 1. "PPL,Number of Pixels Per Line"
|
|
line.long 0x14 "LCDCFG5,LCD Controller Configuration Register 5"
|
|
hexmask.long.byte 0x14 16.--23. 1. "GUARDTIME,LCD DISPLAY Guard Time"
|
|
bitfld.long 0x14 13. "VSPHO,LCD Controller Vertical synchronization Pulse Hold Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x14 12. "VSPSU,LCD Controller Vertical synchronization Pulse Setup Configuration" "0,1"
|
|
bitfld.long 0x14 8.--9. "MODE,LCD Controller Output Mode" "0: LCD Output mode is set to 12 bits per pixel,1: LCD Output mode is set to 16 bits per pixel,2: LCD Output mode is set to 18 bits per pixel,3: LCD Output mode is set to 24 bits per pixel"
|
|
newline
|
|
bitfld.long 0x14 7. "DISPDLY,LCD Controller Display Power Signal Synchronization" "0,1"
|
|
bitfld.long 0x14 6. "DITHER,LCD Controller Dithering" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "DISPPOL,Display Signal Polarity" "0,1"
|
|
bitfld.long 0x14 3. "VSPDLYE,Vertical Synchronization Pulse End" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "VSPDLYS,Vertical Synchronization Pulse Start" "0,1"
|
|
bitfld.long 0x14 1. "VSPOL,Vertical Synchronization Pulse Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "HSPOL,Horizontal Synchronization Pulse Polarity" "0,1"
|
|
line.long 0x18 "LCDCFG6,LCD Controller Configuration Register 6"
|
|
hexmask.long.byte 0x18 8.--15. 1. "PWMCVAL,LCD Controller PWM Compare Value"
|
|
bitfld.long 0x18 4. "PWMPOL,LCD Controller PWM Signal Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--2. "PWMPS,PWM Clock Prescaler" "0: The counter advances at a rate of fCOUNTER =..,1: The counter advances at a rate of fCOUNTER =..,2: The counter advances at a rate of fCOUNTER =..,3: The counter advances at a rate of fCOUNTER =..,4: The counter advances at a rate of fCOUNTER =..,5: The counter advances at a of rate fCOUNTER =..,6: The counter advances at a of rate fCOUNTER =..,?"
|
|
line.long 0x1C "LCDCFG7,LCD Controller Configuration Register 7"
|
|
hexmask.long.word 0x1C 0.--10. 1. "ROW,Row Identifier For Row Interrupt Signal"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "LCDEN,LCD Controller Enable Register"
|
|
bitfld.long 0x0 3. "PWMEN,LCD Controller Pulse Width Modulation Enable" "0,1"
|
|
bitfld.long 0x0 2. "DISPEN,LCD Controller DISP Signal Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SYNCEN,LCD Controller Horizontal and Vertical Synchronization Enable" "0,1"
|
|
bitfld.long 0x0 0. "CLKEN,LCD Controller Pixel Clock Enable" "0,1"
|
|
line.long 0x4 "LCDDIS,LCD Controller Disable Register"
|
|
bitfld.long 0x4 11. "PWMRST,LCD Controller PWM Reset" "0,1"
|
|
bitfld.long 0x4 10. "DISPRST,LCD Controller DISP Signal Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SYNCRST,LCD Controller Horizontal and Vertical Synchronization Reset" "0,1"
|
|
bitfld.long 0x4 8. "CLKRST,LCD Controller Clock Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PWMDIS,LCD Controller Pulse Width Modulation Disable" "0,1"
|
|
bitfld.long 0x4 2. "DISPDIS,LCD Controller DISP Signal Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SYNCDIS,LCD Controller Horizontal and Vertical Synchronization Disable" "0,1"
|
|
bitfld.long 0x4 0. "CLKDIS,LCD Controller Pixel Clock Disable" "0,1"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "LCDSR,LCD Controller Status Register"
|
|
bitfld.long 0x0 4. "SIPSTS,Synchronization In Progress" "0,1"
|
|
bitfld.long 0x0 3. "PWMSTS,LCD Controller PWM Signal Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DISPSTS,LCD Controller DISP Signal Status" "0,1"
|
|
bitfld.long 0x0 1. "LCDSTS,LCD Controller Synchronization status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKSTS,Clock Status" "0,1"
|
|
wgroup.long 0x2C++0x7
|
|
line.long 0x0 "LCDIER,LCD Controller Interrupt Enable Register"
|
|
bitfld.long 0x0 11. "HEOIE,High-End Overlay Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "OVR2IE,Overlay 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OVR1IE,Overlay 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "BASEIE,Base Layer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FIFOERRIE,Output FIFO Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "ROWIE,Row Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DISPIE,Powerup/Powerdown Sequence Terminated Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "DISIE,LCD Disable Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOFIE,Start of Frame Interrupt Enable" "0,1"
|
|
line.long 0x4 "LCDIDR,LCD Controller Interrupt Disable Register"
|
|
bitfld.long 0x4 11. "HEOID,High-End Overlay Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "OVR2ID,Overlay 2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "OVR1ID,Overlay 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "BASEID,Base Layer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FIFOERRID,Output FIFO Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "ROWID,Row Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DISPID,Powerup/Powerdown Sequence Terminated Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "DISID,LCD Disable Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SOFID,Start of Frame Interrupt Disable" "0,1"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x0 "LCDIMR,LCD Controller Interrupt Mask Register"
|
|
bitfld.long 0x0 11. "HEOIM,High-End Overlay Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "OVR2IM,Overlay 2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OVR1IM,Overlay 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "BASEIM,Base Layer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FIFOERRIM,Output FIFO Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "ROWIM,Row Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DISPIM,Powerup/Powerdown Sequence Terminated Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "DISIM,LCD Disable Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOFIM,Start of Frame Interrupt Mask" "0,1"
|
|
line.long 0x4 "LCDISR,LCD Controller Interrupt Status Register"
|
|
bitfld.long 0x4 11. "HEO,High-End Overlay Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "OVR2,Overlay 2 Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "OVR1,Overlay 1 Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "BASE,Base Layer Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FIFOERR,Output FIFO Error" "0,1"
|
|
bitfld.long 0x4 3. "ROW,Row Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DISP,Powerup/Powerdown Sequence Terminated Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "DIS,LCD Disable Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SOF,Start of Frame Interrupt Status" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "ATTR,LCD Controller Attribute Register"
|
|
bitfld.long 0x0 11. "HEOA2Q,High-End Overlay Update Add To Queue" "0,1"
|
|
bitfld.long 0x0 10. "OVR2A2Q,Overlay 2 Update Add to Queue" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OVR1A2Q,Overlay 1 Update Add To Queue" "0,1"
|
|
bitfld.long 0x0 8. "BASEA2Q,Base Layer Update Add To Queue" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "HEO,High-End Overlay Update Attribute" "0,1"
|
|
bitfld.long 0x0 2. "OVR2,Overlay 2 Update Attribute" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OVR1,Overlay 1 Update Attribute" "0,1"
|
|
bitfld.long 0x0 0. "BASE,Base Layer Update Attribute" "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "QOSCFG,LCD Controller QoS Configuration Register"
|
|
bitfld.long 0x0 12.--13. "QOS3CFG,Quality Of Service for 2 to 3 Transition" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "QOS2CFG,Quality Of Service for 1 to 2 Transition" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "QOS1CFG,Quality Of Service for 0 to 1 Transition" "0,1,2,3"
|
|
bitfld.long 0x0 0. "QOSLOCK,Quality Of Service Lock" "0,1"
|
|
rgroup.long 0x44++0xF
|
|
line.long 0x0 "QOS1M,LCD Controller QoS 1 Metrics Register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "MET1,Metrics QoS 1"
|
|
line.long 0x4 "QOS2M,LCD Controller QoS 2 Metrics Register"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "MET2,Metrics QoS 2"
|
|
line.long 0x8 "QOS3M,LCD Controller QoS 3 Metrics Register"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "MET3,Metrics QoS 3"
|
|
line.long 0xC "QOSMIN,LCD Controller QoS Min FIFO Level Register"
|
|
hexmask.long.word 0xC 0.--8. 1. "LEVEL,Minimum FIFO Level"
|
|
wgroup.long 0x60++0x7
|
|
line.long 0x0 "BASECHER,Base Layer Channel Enable Register"
|
|
bitfld.long 0x0 2. "A2QEN,Add To Queue Enable" "0,1"
|
|
bitfld.long 0x0 1. "UPDATEEN,Update Overlay Attributes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHEN,Channel Enable" "0,1"
|
|
line.long 0x4 "BASECHDR,Base Layer Channel Disable Register"
|
|
bitfld.long 0x4 8. "CHRST,Channel Reset" "0,1"
|
|
bitfld.long 0x4 0. "CHDIS,Channel Disable" "0,1"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "BASECHSR,Base Layer Channel Status Register"
|
|
bitfld.long 0x0 2. "A2QSR,Add To Queue Status" "0,1"
|
|
bitfld.long 0x0 1. "UPDATESR,Update Overlay Attributes In Progress Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSR,Channel Status" "0,1"
|
|
wgroup.long 0x6C++0x7
|
|
line.long 0x0 "BASEIER,Base Layer Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Enable" "0,1"
|
|
line.long 0x4 "BASEIDR,Base Layer Interrupt Disabled Register"
|
|
bitfld.long 0x4 6. "OVR,Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,Descriptor Loaded Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer Interrupt Disable" "0,1"
|
|
rgroup.long 0x74++0x7
|
|
line.long 0x0 "BASEIMR,Base Layer Interrupt Mask Register"
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Mask" "0,1"
|
|
line.long 0x4 "BASEISR,Base Layer Interrupt Status Register"
|
|
bitfld.long 0x4 6. "OVR,Overflow Detected" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,DMA Descriptor Loaded" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer" "0,1"
|
|
group.long 0x7C++0x2B
|
|
line.long 0x0 "BASEHEAD,Base DMA Head Register"
|
|
hexmask.long 0x0 2.--31. 1. "HEAD,DMA Head Pointer"
|
|
line.long 0x4 "BASEADDR,Base DMA Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,DMA Transfer Start Address"
|
|
line.long 0x8 "BASECTRL,Base DMA Control Register"
|
|
bitfld.long 0x8 5. "DONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 4. "ADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "DMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "LFETCH,Lookup Table Fetch Enable" "0,1"
|
|
bitfld.long 0x8 0. "DFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0xC "BASENEXT,Base DMA Next Register"
|
|
hexmask.long 0xC 0.--31. 1. "NEXT,DMA Descriptor Next Address"
|
|
line.long 0x10 "BASECFG0,Base Layer Configuration Register 0"
|
|
bitfld.long 0x10 8. "DLBO,defined length Burst Only For Channel Bus Transaction" "0,1"
|
|
bitfld.long 0x10 4.--5. "BLEN,System Bus Burst Length" "0: System bus access is started as soon as there is..,1: System bus access is started as soon as there is..,2: System bus access is started as soon as there is..,3: System bus access is started as soon as there is.."
|
|
line.long 0x14 "BASECFG1,Base Layer Configuration Register 1"
|
|
bitfld.long 0x14 8.--9. "CLUTMODE,Color Lookup Table Mode Input Selection" "0: Color Lookup Table mode set to 1 bit per pixel,1: Color Lookup Table mode set to 2 bits per pixel,2: Color Lookup Table mode set to 4 bits per pixel,3: Color Lookup Table mode set to 8 bits per pixel"
|
|
hexmask.long.byte 0x14 4.--7. 1. "RGBMODE,RGB Mode Input Selection"
|
|
newline
|
|
bitfld.long 0x14 0. "CLUTEN,Color Lookup Table Mode Enable" "0,1"
|
|
line.long 0x18 "BASECFG2,Base Layer Configuration Register 2"
|
|
hexmask.long 0x18 0.--31. 1. "XSTRIDE,Horizontal Stride"
|
|
line.long 0x1C "BASECFG3,Base Layer Configuration Register 3"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "RDEF,Red Default"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "GDEF,Green Default"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "BDEF,Blue Default"
|
|
line.long 0x20 "BASECFG4,Base Layer Configuration Register 4"
|
|
bitfld.long 0x20 11. "DISCEN,Discard Area Enable" "0,1"
|
|
bitfld.long 0x20 9. "REP,Use Replication logic to expand RGB color to 24 bits" "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "DMA,Use DMA Data Path" "0,1"
|
|
line.long 0x24 "BASECFG5,Base Layer Configuration Register 5"
|
|
hexmask.long.word 0x24 16.--26. 1. "DISCYPOS,Discard Area Vertical Coordinate"
|
|
hexmask.long.word 0x24 0.--10. 1. "DISCXPOS,Discard Area Horizontal Coordinate"
|
|
line.long 0x28 "BASECFG6,Base Layer Configuration Register 6"
|
|
hexmask.long.word 0x28 16.--26. 1. "DISCYSIZE,Discard Area Vertical Size"
|
|
hexmask.long.word 0x28 0.--10. 1. "DISCXSIZE,Discard Area Horizontal Size"
|
|
wgroup.long 0x160++0x7
|
|
line.long 0x0 "OVR1CHER,Overlay 1 Channel Enable Register"
|
|
bitfld.long 0x0 2. "A2QEN,Add To Queue Enable" "0,1"
|
|
bitfld.long 0x0 1. "UPDATEEN,Update Overlay Attributes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHEN,Channel Enable" "0,1"
|
|
line.long 0x4 "OVR1CHDR,Overlay 1 Channel Disable Register"
|
|
bitfld.long 0x4 8. "CHRST,Channel Reset" "0,1"
|
|
bitfld.long 0x4 0. "CHDIS,Channel Disable" "0,1"
|
|
rgroup.long 0x168++0x3
|
|
line.long 0x0 "OVR1CHSR,Overlay 1 Channel Status Register"
|
|
bitfld.long 0x0 2. "A2QSR,Add To Queue Status" "0,1"
|
|
bitfld.long 0x0 1. "UPDATESR,Update Overlay Attributes In Progress Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSR,Channel Status" "0,1"
|
|
wgroup.long 0x16C++0x7
|
|
line.long 0x0 "OVR1IER,Overlay 1 Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Enable" "0,1"
|
|
line.long 0x4 "OVR1IDR,Overlay 1 Interrupt Disable Register"
|
|
bitfld.long 0x4 6. "OVR,Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,Descriptor Loaded Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer Interrupt Disable" "0,1"
|
|
rgroup.long 0x174++0x7
|
|
line.long 0x0 "OVR1IMR,Overlay 1 Interrupt Mask Register"
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Mask" "0,1"
|
|
line.long 0x4 "OVR1ISR,Overlay 1 Interrupt Status Register"
|
|
bitfld.long 0x4 6. "OVR,Overflow Detected" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,DMA Descriptor Loaded" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer" "0,1"
|
|
group.long 0x17C++0x37
|
|
line.long 0x0 "OVR1HEAD,Overlay 1 DMA Head Register"
|
|
hexmask.long 0x0 2.--31. 1. "HEAD,DMA Head Pointer"
|
|
line.long 0x4 "OVR1ADDR,Overlay 1 DMA Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,DMA Transfer Overlay 1 Address"
|
|
line.long 0x8 "OVR1CTRL,Overlay 1 DMA Control Register"
|
|
bitfld.long 0x8 5. "DONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 4. "ADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "DMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "LFETCH,Lookup Table Fetch Enable" "0,1"
|
|
bitfld.long 0x8 0. "DFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0xC "OVR1NEXT,Overlay 1 DMA Next Register"
|
|
hexmask.long 0xC 0.--31. 1. "NEXT,DMA Descriptor Next Address"
|
|
line.long 0x10 "OVR1CFG0,Overlay 1 Configuration Register 0"
|
|
bitfld.long 0x10 13. "LOCKDIS,Hardware Rotation Lock Disable" "0,1"
|
|
bitfld.long 0x10 12. "ROTDIS,Hardware Rotation Optimization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "DLBO,defined length Burst Only for Channel Bus Transaction" "0,1"
|
|
bitfld.long 0x10 4.--5. "BLEN,System Bus Burst Length" "0: System bus access is started as soon as there is..,1: System bus access is started as soon as there is..,2: System bus access is started as soon as there is..,3: System bus access is started as soon as there is.."
|
|
line.long 0x14 "OVR1CFG1,Overlay 1 Configuration Register 1"
|
|
bitfld.long 0x14 8.--9. "CLUTMODE,Color Lookup Table Mode Input Selection" "0: Color Lookup Table mode set to 1 bit per pixel,1: Color Lookup Table mode set to 2 bits per pixel,2: Color Lookup Table mode set to 4 bits per pixel,3: Color Lookup Table mode set to 8 bits per pixel"
|
|
hexmask.long.byte 0x14 4.--7. 1. "RGBMODE,RGB Mode Input Selection"
|
|
newline
|
|
bitfld.long 0x14 0. "CLUTEN,Color Lookup Table Mode Enable" "0,1"
|
|
line.long 0x18 "OVR1CFG2,Overlay 1 Configuration Register 2"
|
|
hexmask.long.word 0x18 16.--26. 1. "YPOS,Vertical Window Position"
|
|
hexmask.long.word 0x18 0.--10. 1. "XPOS,Horizontal Window Position"
|
|
line.long 0x1C "OVR1CFG3,Overlay 1 Configuration Register 3"
|
|
hexmask.long.word 0x1C 16.--26. 1. "YSIZE,Vertical Window Size"
|
|
hexmask.long.word 0x1C 0.--10. 1. "XSIZE,Horizontal Window Size"
|
|
line.long 0x20 "OVR1CFG4,Overlay 1 Configuration Register 4"
|
|
hexmask.long 0x20 0.--31. 1. "XSTRIDE,Horizontal Stride"
|
|
line.long 0x24 "OVR1CFG5,Overlay 1 Configuration Register 5"
|
|
hexmask.long 0x24 0.--31. 1. "PSTRIDE,Pixel Stride"
|
|
line.long 0x28 "OVR1CFG6,Overlay 1 Configuration Register 6"
|
|
hexmask.long.byte 0x28 16.--23. 1. "RDEF,Red Default"
|
|
hexmask.long.byte 0x28 8.--15. 1. "GDEF,Green Default"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "BDEF,Blue Default"
|
|
line.long 0x2C "OVR1CFG7,Overlay 1 Configuration Register 7"
|
|
hexmask.long.byte 0x2C 16.--23. 1. "RKEY,Red Color Component Chroma Key"
|
|
hexmask.long.byte 0x2C 8.--15. 1. "GKEY,Green Color Component Chroma Key"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "BKEY,Blue Color Component Chroma Key"
|
|
line.long 0x30 "OVR1CFG8,Overlay 1 Configuration Register 8"
|
|
hexmask.long.byte 0x30 16.--23. 1. "RMASK,Red Color Component Chroma Key Mask"
|
|
hexmask.long.byte 0x30 8.--15. 1. "GMASK,Green Color Component Chroma Key Mask"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "BMASK,Blue Color Component Chroma Key Mask"
|
|
line.long 0x34 "OVR1CFG9,Overlay 1 Configuration Register 9"
|
|
hexmask.long.byte 0x34 16.--23. 1. "GA,Blender Global Alpha"
|
|
bitfld.long 0x34 10. "DSTKEY,Destination Chroma Keying" "0,1"
|
|
newline
|
|
bitfld.long 0x34 9. "REP,Use Replication logic to expand RGB color to 24 bits" "0,1"
|
|
bitfld.long 0x34 8. "DMA,Blender DMA Layer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 7. "OVR,Blender Overlay Layer Enable" "0,1"
|
|
bitfld.long 0x34 6. "LAEN,Blender Local Alpha Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 5. "GAEN,Blender Global Alpha Enable" "0,1"
|
|
bitfld.long 0x34 4. "REVALPHA,Blender Reverse Alpha" "0,1"
|
|
newline
|
|
bitfld.long 0x34 3. "ITER,Blender Use Iterated Color" "0,1"
|
|
bitfld.long 0x34 2. "ITER2BL,Blender Iterated Color Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 1. "INV,Blender Inverted Blender Output Enable" "0,1"
|
|
bitfld.long 0x34 0. "CRKEY,Blender Chroma Key Enable" "0,1"
|
|
wgroup.long 0x260++0x7
|
|
line.long 0x0 "OVR2CHER,Overlay 2 Channel Enable Register"
|
|
bitfld.long 0x0 2. "A2QEN,Add To Queue Enable" "0,1"
|
|
bitfld.long 0x0 1. "UPDATEEN,Update Overlay Attributes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHEN,Channel Enable" "0,1"
|
|
line.long 0x4 "OVR2CHDR,Overlay 2 Channel Disable Register"
|
|
bitfld.long 0x4 8. "CHRST,Channel Reset" "0,1"
|
|
bitfld.long 0x4 0. "CHDIS,Channel Disable" "0,1"
|
|
rgroup.long 0x268++0x3
|
|
line.long 0x0 "OVR2CHSR,Overlay 2 Channel Status Register"
|
|
bitfld.long 0x0 2. "A2QSR,Add To Queue Status" "0,1"
|
|
bitfld.long 0x0 1. "UPDATESR,Update Overlay Attributes In Progress Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSR,Channel Status" "0,1"
|
|
wgroup.long 0x26C++0x7
|
|
line.long 0x0 "OVR2IER,Overlay 2 Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Enable" "0,1"
|
|
line.long 0x4 "OVR2IDR,Overlay 2 Interrupt Disable Register"
|
|
bitfld.long 0x4 6. "OVR,Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,Descriptor Loaded Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer Interrupt Disable" "0,1"
|
|
rgroup.long 0x274++0x7
|
|
line.long 0x0 "OVR2IMR,Overlay 2 Interrupt Mask Register"
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Mask" "0,1"
|
|
line.long 0x4 "OVR2ISR,Overlay 2 Interrupt Status Register"
|
|
bitfld.long 0x4 6. "OVR,Overflow Detected" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,DMA Descriptor Loaded" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer" "0,1"
|
|
group.long 0x27C++0x37
|
|
line.long 0x0 "OVR2HEAD,Overlay 2 DMA Head Register"
|
|
hexmask.long 0x0 2.--31. 1. "HEAD,DMA Head Pointer"
|
|
line.long 0x4 "OVR2ADDR,Overlay 2 DMA Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,DMA Transfer Overlay 2 Address"
|
|
line.long 0x8 "OVR2CTRL,Overlay 2 DMA Control Register"
|
|
bitfld.long 0x8 5. "DONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 4. "ADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "DMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "LFETCH,Lookup Table Fetch Enable" "0,1"
|
|
bitfld.long 0x8 0. "DFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0xC "OVR2NEXT,Overlay 2 DMA Next Register"
|
|
hexmask.long 0xC 0.--31. 1. "NEXT,DMA Descriptor Next Address"
|
|
line.long 0x10 "OVR2CFG0,Overlay 2 Configuration Register 0"
|
|
bitfld.long 0x10 13. "LOCKDIS,Hardware Rotation Lock Disable" "0,1"
|
|
bitfld.long 0x10 12. "ROTDIS,Hardware Rotation Optimization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "DLBO,Defined Length Burst Only For Channel Bus Transaction" "0,1"
|
|
bitfld.long 0x10 4.--5. "BLEN,System Bus Burst Length" "0: System bus access is started as soon as there is..,1: System bus access is started as soon as there is..,2: System bus access is started as soon as there is..,3: System bus access is started as soon as there is.."
|
|
line.long 0x14 "OVR2CFG1,Overlay 2 Configuration Register 1"
|
|
bitfld.long 0x14 8.--9. "CLUTMODE,Color Lookup Table Mode Input Selection" "0: Color Lookup Table mode set to 1 bit per pixel,1: Color Lookup Table mode set to 2 bits per pixel,2: Color Lookup Table mode set to 4 bits per pixel,3: Color Lookup Table mode set to 8 bits per pixel"
|
|
hexmask.long.byte 0x14 4.--7. 1. "RGBMODE,RGB Mode Input Selection"
|
|
newline
|
|
bitfld.long 0x14 0. "CLUTEN,Color Lookup Table Mode Enable" "0,1"
|
|
line.long 0x18 "OVR2CFG2,Overlay 2 Configuration Register 2"
|
|
hexmask.long.word 0x18 16.--26. 1. "YPOS,Vertical Window Position"
|
|
hexmask.long.word 0x18 0.--10. 1. "XPOS,Horizontal Window Position"
|
|
line.long 0x1C "OVR2CFG3,Overlay 2 Configuration Register 3"
|
|
hexmask.long.word 0x1C 16.--26. 1. "YSIZE,Vertical Window Size"
|
|
hexmask.long.word 0x1C 0.--10. 1. "XSIZE,Horizontal Window Size"
|
|
line.long 0x20 "OVR2CFG4,Overlay 2 Configuration Register 4"
|
|
hexmask.long 0x20 0.--31. 1. "XSTRIDE,Horizontal Stride"
|
|
line.long 0x24 "OVR2CFG5,Overlay 2 Configuration Register 5"
|
|
hexmask.long 0x24 0.--31. 1. "PSTRIDE,Pixel Stride"
|
|
line.long 0x28 "OVR2CFG6,Overlay 2 Configuration Register 6"
|
|
hexmask.long.byte 0x28 16.--23. 1. "RDEF,Red Default"
|
|
hexmask.long.byte 0x28 8.--15. 1. "GDEF,Green Default"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "BDEF,Blue Default"
|
|
line.long 0x2C "OVR2CFG7,Overlay 2 Configuration Register 7"
|
|
hexmask.long.byte 0x2C 16.--23. 1. "RKEY,Red Color Component Chroma Key"
|
|
hexmask.long.byte 0x2C 8.--15. 1. "GKEY,Green Color Component Chroma Key"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "BKEY,Blue Color Component Chroma Key"
|
|
line.long 0x30 "OVR2CFG8,Overlay 2 Configuration Register 8"
|
|
hexmask.long.byte 0x30 16.--23. 1. "RMASK,Red Color Component Chroma Key Mask"
|
|
hexmask.long.byte 0x30 8.--15. 1. "GMASK,Green Color Component Chroma Key Mask"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "BMASK,Blue Color Component Chroma Key Mask"
|
|
line.long 0x34 "OVR2CFG9,Overlay 2 Configuration Register 9"
|
|
hexmask.long.byte 0x34 16.--23. 1. "GA,Blender Global Alpha"
|
|
bitfld.long 0x34 10. "DSTKEY,Destination Chroma Keying" "0,1"
|
|
newline
|
|
bitfld.long 0x34 9. "REP,Use Replication logic to expand RGB color to 24 bits" "0,1"
|
|
bitfld.long 0x34 8. "DMA,Blender DMA Layer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 7. "OVR,Blender Overlay Layer Enable" "0,1"
|
|
bitfld.long 0x34 6. "LAEN,Blender Local Alpha Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 5. "GAEN,Blender Global Alpha Enable" "0,1"
|
|
bitfld.long 0x34 4. "REVALPHA,Blender Reverse Alpha" "0,1"
|
|
newline
|
|
bitfld.long 0x34 3. "ITER,Blender Use Iterated Color" "0,1"
|
|
bitfld.long 0x34 2. "ITER2BL,Blender Iterated Color Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 1. "INV,Blender Inverted Blender Output Enable" "0,1"
|
|
bitfld.long 0x34 0. "CRKEY,Blender Chroma Key Enable" "0,1"
|
|
wgroup.long 0x360++0x7
|
|
line.long 0x0 "HEOCHER,High-End Overlay Channel Enable Register"
|
|
bitfld.long 0x0 2. "A2QEN,Add To Queue Enable" "0,1"
|
|
bitfld.long 0x0 1. "UPDATEEN,Update Overlay Attributes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHEN,Channel Enable" "0,1"
|
|
line.long 0x4 "HEOCHDR,High-End Overlay Channel Disable Register"
|
|
bitfld.long 0x4 8. "CHRST,Channel Reset" "0,1"
|
|
bitfld.long 0x4 0. "CHDIS,Channel Disable" "0,1"
|
|
rgroup.long 0x368++0x3
|
|
line.long 0x0 "HEOCHSR,High-End Overlay Channel Status Register"
|
|
bitfld.long 0x0 2. "A2QSR,Add To Queue Status" "0,1"
|
|
bitfld.long 0x0 1. "UPDATESR,Update Overlay Attributes In Progress Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSR,Channel Status" "0,1"
|
|
wgroup.long 0x36C++0x7
|
|
line.long 0x0 "HEOIER,High-End Overlay Interrupt Enable Register"
|
|
bitfld.long 0x0 22. "VOVR,Overflow for V Chrominance Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "VDONE,End of List for V Chrominance Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "VADD,Head Descriptor Loaded for V Chrominance Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 19. "VDSCR,Descriptor Loaded for V Chrominance Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "VDMA,End of DMA for V Chrominance Transfer Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "UOVR,Overflow for U or UV Chrominance Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDONE,End of List for U or UV Chrominance Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "UADD,Head Descriptor Loaded for U or UV Chrominance Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "UDSCR,Descriptor Loaded for U or UV Chrominance Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "UDMA,End of DMA Transfer for U or UV Chrominance Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Enable" "0,1"
|
|
line.long 0x4 "HEOIDR,High-End Overlay Interrupt Disable Register"
|
|
bitfld.long 0x4 22. "VOVR,Overflow for V Chrominance Component Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 21. "VDONE,End of List for V Chrominance Component Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "VADD,Head Descriptor Loaded for V Chrominance Component Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 19. "VDSCR,Descriptor Loaded for V Chrominance Component Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "VDMA,End of DMA Transfer for V Chrominance Component Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "UOVR,Overflow Interrupt for U or UV Chrominance Component Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "UDONE,End of List Interrupt for U or UV Chrominance Component Disable" "0,1"
|
|
bitfld.long 0x4 12. "UADD,Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "UDSCR,Descriptor Loaded for U or UV Chrominance Component Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "UDMA,End of DMA Transfer for U or UV Chrominance Component Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVR,Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,Descriptor Loaded Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer Interrupt Disable" "0,1"
|
|
rgroup.long 0x374++0x7
|
|
line.long 0x0 "HEOIMR,High-End Overlay Interrupt Mask Register"
|
|
bitfld.long 0x0 22. "VOVR,Overflow for V Chrominance Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 21. "VDONE,End of List for V Chrominance Component Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "VADD,Head Descriptor Loaded for V Chrominance Component Mask" "0,1"
|
|
bitfld.long 0x0 19. "VDSCR,Descriptor Loaded for V Chrominance Component Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "VDMA,End of DMA Transfer for V Chrominance Component Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "UOVR,Overflow for U Chrominance Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDONE,End of List for U or UV Chrominance Component Mask" "0,1"
|
|
bitfld.long 0x0 12. "UADD,Head Descriptor Loaded for U or UV Chrominance Component Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "UDSCR,Descriptor Loaded for U or UV Chrominance Component Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "UDMA,End of DMA Transfer for U or UV Chrominance Component Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Mask" "0,1"
|
|
line.long 0x4 "HEOISR,High-End Overlay Interrupt Status Register"
|
|
bitfld.long 0x4 22. "VOVR,Overflow Detected for V Component" "0,1"
|
|
bitfld.long 0x4 21. "VDONE,End of List Detected for V Component" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "VADD,Head Descriptor Loaded for V Component" "0,1"
|
|
bitfld.long 0x4 19. "VDSCR,DMA Descriptor Loaded for V Component" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "VDMA,End of DMA Transfer for V Component" "0,1"
|
|
bitfld.long 0x4 14. "UOVR,Overflow Detected for U Component" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "UDONE,End of List Detected for U Component" "0,1"
|
|
bitfld.long 0x4 12. "UADD,Head Descriptor Loaded for U Component" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "UDSCR,DMA Descriptor Loaded for U Component" "0,1"
|
|
bitfld.long 0x4 10. "UDMA,End of DMA Transfer for U Component" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVR,Overflow Detected" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,DMA Descriptor Loaded" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer" "0,1"
|
|
group.long 0x37C++0xD7
|
|
line.long 0x0 "HEOHEAD,High-End Overlay DMA Head Register"
|
|
hexmask.long 0x0 2.--31. 1. "HEAD,DMA Head Pointer"
|
|
line.long 0x4 "HEOADDR,High-End Overlay DMA Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,DMA Transfer Start Address"
|
|
line.long 0x8 "HEOCTRL,High-End Overlay DMA Control Register"
|
|
bitfld.long 0x8 5. "DONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 4. "ADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "DMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "LFETCH,Lookup Table Fetch Enable" "0,1"
|
|
bitfld.long 0x8 0. "DFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0xC "HEONEXT,High-End Overlay DMA Next Register"
|
|
hexmask.long 0xC 0.--31. 1. "NEXT,DMA Descriptor Next Address"
|
|
line.long 0x10 "HEOUHEAD,High-End Overlay U-UV DMA Head Register"
|
|
hexmask.long 0x10 0.--31. 1. "UHEAD,DMA Head Pointer"
|
|
line.long 0x14 "HEOUADDR,High-End Overlay U-UV DMA Address Register"
|
|
hexmask.long 0x14 0.--31. 1. "UADDR,DMA Transfer Start Address for U or UV Chrominance"
|
|
line.long 0x18 "HEOUCTRL,High-End Overlay U-UV DMA Control Register"
|
|
bitfld.long 0x18 5. "UDONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x18 4. "UADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "UDSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x18 2. "UDMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "UDFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0x1C "HEOUNEXT,High-End Overlay U-UV DMA Next Register"
|
|
hexmask.long 0x1C 0.--31. 1. "UNEXT,DMA Descriptor Next Address"
|
|
line.long 0x20 "HEOVHEAD,High-End Overlay V DMA Head Register"
|
|
hexmask.long 0x20 0.--31. 1. "VHEAD,DMA Head Pointer"
|
|
line.long 0x24 "HEOVADDR,High-End Overlay V DMA Address Register"
|
|
hexmask.long 0x24 0.--31. 1. "VADDR,DMA Transfer Start Address for V Chrominance"
|
|
line.long 0x28 "HEOVCTRL,High-End Overlay V DMA Control Register"
|
|
bitfld.long 0x28 5. "VDONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x28 4. "VADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x28 3. "VDSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x28 2. "VDMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x28 0. "VDFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0x2C "HEOVNEXT,High-End Overlay V DMA Next Register"
|
|
hexmask.long 0x2C 0.--31. 1. "VNEXT,DMA Descriptor Next Address"
|
|
line.long 0x30 "HEOCFG0,High-End Overlay Configuration Register 0"
|
|
bitfld.long 0x30 13. "LOCKDIS,Hardware Rotation Lock Disable" "0,1"
|
|
bitfld.long 0x30 12. "ROTDIS,Hardware Rotation Optimization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x30 8. "DLBO,Defined Length Burst Only For Channel Bus Transaction" "0,1"
|
|
bitfld.long 0x30 6.--7. "BLENUV,System Bus Burst Length for U-V Channel" "0: System bus access is started as soon as there is..,1: System bus access is started as soon as there is..,2: System bus access is started as soon as there is..,3: System bus access is started as soon as there is.."
|
|
newline
|
|
bitfld.long 0x30 4.--5. "BLEN,System Bus Burst Length" "0: System bus access is started as soon as there is..,1: System bus access is started as soon as there is..,2: System bus access is started as soon as there is..,3: System bus access is started as soon as there is.."
|
|
line.long 0x34 "HEOCFG1,High-End Overlay Configuration Register 1"
|
|
bitfld.long 0x34 20. "DSCALEOPT,Down Scaling Bandwidth Optimization" "0,1"
|
|
bitfld.long 0x34 17. "YUV422SWP,YUV 4:2:2 Swap" "?,?"
|
|
newline
|
|
bitfld.long 0x34 16. "YUV422ROT,YUV 4:2:2 Rotation" "?,?"
|
|
hexmask.long.byte 0x34 12.--15. 1. "YUVMODE,YUV Mode Input Selection"
|
|
newline
|
|
bitfld.long 0x34 8.--9. "CLUTMODE,Color Lookup Table Mode Input Selection" "0: Color Lookup Table mode set to 1 bit per pixel,1: Color Lookup Table mode set to 2 bits per pixel,2: Color Lookup Table mode set to 4 bits per pixel,3: Color Lookup Table mode set to 8 bits per pixel"
|
|
hexmask.long.byte 0x34 4.--7. 1. "RGBMODE,RGB Mode Input Selection"
|
|
newline
|
|
bitfld.long 0x34 1. "YUVEN,YUV Color Space Enable" "0,1"
|
|
bitfld.long 0x34 0. "CLUTEN,Color Lookup Table Mode Enable" "0,1"
|
|
line.long 0x38 "HEOCFG2,High-End Overlay Configuration Register 2"
|
|
hexmask.long.word 0x38 16.--26. 1. "YPOS,Vertical Window Position"
|
|
hexmask.long.word 0x38 0.--10. 1. "XPOS,Horizontal Window Position"
|
|
line.long 0x3C "HEOCFG3,High-End Overlay Configuration Register 3"
|
|
hexmask.long.word 0x3C 16.--26. 1. "YSIZE,Vertical Window Size"
|
|
hexmask.long.word 0x3C 0.--10. 1. "XSIZE,Horizontal Window Size"
|
|
line.long 0x40 "HEOCFG4,High-End Overlay Configuration Register 4"
|
|
hexmask.long.word 0x40 16.--26. 1. "YMEMSIZE,Vertical image Size in Memory"
|
|
hexmask.long.word 0x40 0.--10. 1. "XMEMSIZE,Horizontal image Size in Memory"
|
|
line.long 0x44 "HEOCFG5,High-End Overlay Configuration Register 5"
|
|
hexmask.long 0x44 0.--31. 1. "XSTRIDE,Horizontal Stride"
|
|
line.long 0x48 "HEOCFG6,High-End Overlay Configuration Register 6"
|
|
hexmask.long 0x48 0.--31. 1. "PSTRIDE,Pixel Stride"
|
|
line.long 0x4C "HEOCFG7,High-End Overlay Configuration Register 7"
|
|
hexmask.long 0x4C 0.--31. 1. "UVXSTRIDE,UV Horizontal Stride"
|
|
line.long 0x50 "HEOCFG8,High-End Overlay Configuration Register 8"
|
|
hexmask.long 0x50 0.--31. 1. "UVPSTRIDE,UV Pixel Stride"
|
|
line.long 0x54 "HEOCFG9,High-End Overlay Configuration Register 9"
|
|
hexmask.long.byte 0x54 16.--23. 1. "RDEF,Red Default"
|
|
hexmask.long.byte 0x54 8.--15. 1. "GDEF,Green Default"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--7. 1. "BDEF,Blue Default"
|
|
line.long 0x58 "HEOCFG10,High-End Overlay Configuration Register 10"
|
|
hexmask.long.byte 0x58 16.--23. 1. "RKEY,Red Color Component Chroma Key"
|
|
hexmask.long.byte 0x58 8.--15. 1. "GKEY,Green Color Component Chroma Key"
|
|
newline
|
|
hexmask.long.byte 0x58 0.--7. 1. "BKEY,Blue Color Component Chroma Key"
|
|
line.long 0x5C "HEOCFG11,High-End Overlay Configuration Register 11"
|
|
hexmask.long.byte 0x5C 16.--23. 1. "RMASK,Red Color Component Chroma Key Mask"
|
|
hexmask.long.byte 0x5C 8.--15. 1. "GMASK,Green Color Component Chroma Key Mask"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--7. 1. "BMASK,Blue Color Component Chroma Key Mask"
|
|
line.long 0x60 "HEOCFG12,High-End Overlay Configuration Register 12"
|
|
hexmask.long.byte 0x60 16.--23. 1. "GA,Blender Global Alpha"
|
|
bitfld.long 0x60 12. "VIDPRI,Video Priority" "0,1"
|
|
newline
|
|
bitfld.long 0x60 10. "DSTKEY,Destination Chroma Keying" "0,1"
|
|
bitfld.long 0x60 9. "REP,Use Replication logic to expand RGB color to 24 bits" "0,1"
|
|
newline
|
|
bitfld.long 0x60 8. "DMA,Blender DMA Layer Enable" "0,1"
|
|
bitfld.long 0x60 7. "OVR,Blender Overlay Layer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x60 6. "LAEN,Blender Local Alpha Enable" "0,1"
|
|
bitfld.long 0x60 5. "GAEN,Blender Global Alpha Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x60 4. "REVALPHA,Blender Reverse Alpha" "0,1"
|
|
bitfld.long 0x60 3. "ITER,Blender Use Iterated Color" "0,1"
|
|
newline
|
|
bitfld.long 0x60 2. "ITER2BL,Blender Iterated Color Enable" "0,1"
|
|
bitfld.long 0x60 1. "INV,Blender Inverted Blender Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x60 0. "CRKEY,Blender Chroma Key Enable" "0,1"
|
|
line.long 0x64 "HEOCFG13,High-End Overlay Configuration Register 13"
|
|
bitfld.long 0x64 31. "SCALEN,Hardware Scaler Enable" "0,1"
|
|
hexmask.long.word 0x64 16.--29. 1. "YFACTOR,Vertical Scaling Factor"
|
|
newline
|
|
hexmask.long.word 0x64 0.--13. 1. "XFACTOR,Horizontal Scaling Factor"
|
|
line.long 0x68 "HEOCFG14,High-End Overlay Configuration Register 14"
|
|
bitfld.long 0x68 30. "CSCYOFF,Color Space Conversion Offset" "0,1"
|
|
hexmask.long.word 0x68 20.--29. 1. "CSCRV,Color Space Conversion V coefficient for Red Component 1:2:7 format"
|
|
newline
|
|
hexmask.long.word 0x68 10.--19. 1. "CSCRU,Color Space Conversion U coefficient for Red Component 1:2:7 format"
|
|
hexmask.long.word 0x68 0.--9. 1. "CSCRY,Color Space Conversion Y coefficient for Red Component 1:2:7 format"
|
|
line.long 0x6C "HEOCFG15,High-End Overlay Configuration Register 15"
|
|
bitfld.long 0x6C 30. "CSCUOFF,Color Space Conversion Offset" "0,1"
|
|
hexmask.long.word 0x6C 20.--29. 1. "CSCGV,Color Space Conversion V coefficient for Green Component 1:2:7 format"
|
|
newline
|
|
hexmask.long.word 0x6C 10.--19. 1. "CSCGU,Color Space Conversion U coefficient for Green Component 1:2:7 format"
|
|
hexmask.long.word 0x6C 0.--9. 1. "CSCGY,Color Space Conversion Y coefficient for Green Component 1:2:7 format"
|
|
line.long 0x70 "HEOCFG16,High-End Overlay Configuration Register 16"
|
|
bitfld.long 0x70 30. "CSCVOFF,Color Space Conversion Offset" "0,1"
|
|
hexmask.long.word 0x70 20.--29. 1. "CSCBV,Color Space Conversion V coefficient for Blue Component 1:2:7 format"
|
|
newline
|
|
hexmask.long.word 0x70 10.--19. 1. "CSCBU,Color Space Conversion U coefficient for Blue Component 1:2:7 format"
|
|
hexmask.long.word 0x70 0.--9. 1. "CSCBY,Color Space Conversion Y coefficient for Blue Component 1:2:7 format"
|
|
line.long 0x74 "HEOCFG17,High-End Overlay Configuration Register 17"
|
|
hexmask.long.byte 0x74 24.--31. 1. "XPHI0COEFF3,Horizontal Coefficient for phase 0 tap 3"
|
|
hexmask.long.byte 0x74 16.--23. 1. "XPHI0COEFF2,Horizontal Coefficient for phase 0 tap 2"
|
|
newline
|
|
hexmask.long.byte 0x74 8.--15. 1. "XPHI0COEFF1,Horizontal Coefficient for phase 0 tap 1"
|
|
hexmask.long.byte 0x74 0.--7. 1. "XPHI0COEFF0,Horizontal Coefficient for phase 0 tap 0"
|
|
line.long 0x78 "HEOCFG18,High-End Overlay Configuration Register 18"
|
|
hexmask.long.byte 0x78 0.--7. 1. "XPHI0COEFF4,Horizontal Coefficient for phase 0 tap 4"
|
|
line.long 0x7C "HEOCFG19,High-End Overlay Configuration Register 19"
|
|
hexmask.long.byte 0x7C 24.--31. 1. "XPHI1COEFF3,Horizontal Coefficient for phase 1 tap 3"
|
|
hexmask.long.byte 0x7C 16.--23. 1. "XPHI1COEFF2,Horizontal Coefficient for phase 1 tap 2"
|
|
newline
|
|
hexmask.long.byte 0x7C 8.--15. 1. "XPHI1COEFF1,Horizontal Coefficient for phase 1 tap 1"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "XPHI1COEFF0,Horizontal Coefficient for phase 1 tap 0"
|
|
line.long 0x80 "HEOCFG20,High-End Overlay Configuration Register 20"
|
|
hexmask.long.byte 0x80 0.--7. 1. "XPHI1COEFF4,Horizontal Coefficient for phase 1 tap 4"
|
|
line.long 0x84 "HEOCFG21,High-End Overlay Configuration Register 21"
|
|
hexmask.long.byte 0x84 24.--31. 1. "XPHI2COEFF3,Horizontal Coefficient for phase 2 tap 3"
|
|
hexmask.long.byte 0x84 16.--23. 1. "XPHI2COEFF2,Horizontal Coefficient for phase 2 tap 2"
|
|
newline
|
|
hexmask.long.byte 0x84 8.--15. 1. "XPHI2COEFF1,Horizontal Coefficient for phase 2 tap 1"
|
|
hexmask.long.byte 0x84 0.--7. 1. "XPHI2COEFF0,Horizontal Coefficient for phase 2 tap 0"
|
|
line.long 0x88 "HEOCFG22,High-End Overlay Configuration Register 22"
|
|
hexmask.long.byte 0x88 0.--7. 1. "XPHI2COEFF4,Horizontal Coefficient for phase 2 tap 4"
|
|
line.long 0x8C "HEOCFG23,High-End Overlay Configuration Register 23"
|
|
hexmask.long.byte 0x8C 24.--31. 1. "XPHI3COEFF3,Horizontal Coefficient for phase 3 tap 3"
|
|
hexmask.long.byte 0x8C 16.--23. 1. "XPHI3COEFF2,Horizontal Coefficient for phase 3 tap 2"
|
|
newline
|
|
hexmask.long.byte 0x8C 8.--15. 1. "XPHI3COEFF1,Horizontal Coefficient for phase 3 tap 1"
|
|
hexmask.long.byte 0x8C 0.--7. 1. "XPHI3COEFF0,Horizontal Coefficient for phase 3 tap 0"
|
|
line.long 0x90 "HEOCFG24,High-End Overlay Configuration Register 24"
|
|
hexmask.long.byte 0x90 0.--7. 1. "XPHI3COEFF4,Horizontal Coefficient for phase 3 tap 4"
|
|
line.long 0x94 "HEOCFG25,High-End Overlay Configuration Register 25"
|
|
hexmask.long.byte 0x94 24.--31. 1. "XPHI4COEFF3,Horizontal Coefficient for phase 4 tap 3"
|
|
hexmask.long.byte 0x94 16.--23. 1. "XPHI4COEFF2,Horizontal Coefficient for phase 4 tap 2"
|
|
newline
|
|
hexmask.long.byte 0x94 8.--15. 1. "XPHI4COEFF1,Horizontal Coefficient for phase 4 tap 1"
|
|
hexmask.long.byte 0x94 0.--7. 1. "XPHI4COEFF0,Horizontal Coefficient for phase 4 tap 0"
|
|
line.long 0x98 "HEOCFG26,High-End Overlay Configuration Register 26"
|
|
hexmask.long.byte 0x98 0.--7. 1. "XPHI4COEFF4,Horizontal Coefficient for phase 4 tap 4"
|
|
line.long 0x9C "HEOCFG27,High-End Overlay Configuration Register 27"
|
|
hexmask.long.byte 0x9C 24.--31. 1. "XPHI5COEFF3,Horizontal Coefficient for phase 5 tap 3"
|
|
hexmask.long.byte 0x9C 16.--23. 1. "XPHI5COEFF2,Horizontal Coefficient for phase 5 tap 2"
|
|
newline
|
|
hexmask.long.byte 0x9C 8.--15. 1. "XPHI5COEFF1,Horizontal Coefficient for phase 5 tap 1"
|
|
hexmask.long.byte 0x9C 0.--7. 1. "XPHI5COEFF0,Horizontal Coefficient for phase 5 tap 0"
|
|
line.long 0xA0 "HEOCFG28,High-End Overlay Configuration Register 28"
|
|
hexmask.long.byte 0xA0 0.--7. 1. "XPHI5COEFF4,Horizontal Coefficient for phase 5 tap 4"
|
|
line.long 0xA4 "HEOCFG29,High-End Overlay Configuration Register 29"
|
|
hexmask.long.byte 0xA4 24.--31. 1. "XPHI6COEFF3,Horizontal Coefficient for phase 6 tap 3"
|
|
hexmask.long.byte 0xA4 16.--23. 1. "XPHI6COEFF2,Horizontal Coefficient for phase 6 tap 2"
|
|
newline
|
|
hexmask.long.byte 0xA4 8.--15. 1. "XPHI6COEFF1,Horizontal Coefficient for phase 6 tap 1"
|
|
hexmask.long.byte 0xA4 0.--7. 1. "XPHI6COEFF0,Horizontal Coefficient for phase 6 tap 0"
|
|
line.long 0xA8 "HEOCFG30,High-End Overlay Configuration Register 30"
|
|
hexmask.long.byte 0xA8 0.--7. 1. "XPHI6COEFF4,Horizontal Coefficient for phase 6 tap 4"
|
|
line.long 0xAC "HEOCFG31,High-End Overlay Configuration Register 31"
|
|
hexmask.long.byte 0xAC 24.--31. 1. "XPHI7COEFF3,Horizontal Coefficient for phase 7 tap 3"
|
|
hexmask.long.byte 0xAC 16.--23. 1. "XPHI7COEFF2,Horizontal Coefficient for phase 7 tap 2"
|
|
newline
|
|
hexmask.long.byte 0xAC 8.--15. 1. "XPHI7COEFF1,Horizontal Coefficient for phase 7 tap 1"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "XPHI7COEFF0,Horizontal Coefficient for phase 7 tap 0"
|
|
line.long 0xB0 "HEOCFG32,High-End Overlay Configuration Register 32"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "XPHI7COEFF4,Horizontal Coefficient for phase 7 tap 4"
|
|
line.long 0xB4 "HEOCFG33,High-End Overlay Configuration Register 33"
|
|
hexmask.long.byte 0xB4 16.--23. 1. "YPHI0COEFF2,Vertical Coefficient for phase 0 tap 2"
|
|
hexmask.long.byte 0xB4 8.--15. 1. "YPHI0COEFF1,Vertical Coefficient for phase 0 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xB4 0.--7. 1. "YPHI0COEFF0,Vertical Coefficient for phase 0 tap 0"
|
|
line.long 0xB8 "HEOCFG34,High-End Overlay Configuration Register 34"
|
|
hexmask.long.byte 0xB8 16.--23. 1. "YPHI1COEFF2,Vertical Coefficient for phase 1 tap 2"
|
|
hexmask.long.byte 0xB8 8.--15. 1. "YPHI1COEFF1,Vertical Coefficient for phase 1 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xB8 0.--7. 1. "YPHI1COEFF0,Vertical Coefficient for phase 1 tap 0"
|
|
line.long 0xBC "HEOCFG35,High-End Overlay Configuration Register 35"
|
|
hexmask.long.byte 0xBC 16.--23. 1. "YPHI2COEFF2,Vertical Coefficient for phase 2 tap 2"
|
|
hexmask.long.byte 0xBC 8.--15. 1. "YPHI2COEFF1,Vertical Coefficient for phase 2 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xBC 0.--7. 1. "YPHI2COEFF0,Vertical Coefficient for phase 2 tap 0"
|
|
line.long 0xC0 "HEOCFG36,High-End Overlay Configuration Register 36"
|
|
hexmask.long.byte 0xC0 16.--23. 1. "YPHI3COEFF2,Vertical Coefficient for phase 3 tap 2"
|
|
hexmask.long.byte 0xC0 8.--15. 1. "YPHI3COEFF1,Vertical Coefficient for phase 3 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xC0 0.--7. 1. "YPHI3COEFF0,Vertical Coefficient for phase 3 tap 0"
|
|
line.long 0xC4 "HEOCFG37,High-End Overlay Configuration Register 37"
|
|
hexmask.long.byte 0xC4 16.--23. 1. "YPHI4COEFF2,Vertical Coefficient for phase 4 tap 2"
|
|
hexmask.long.byte 0xC4 8.--15. 1. "YPHI4COEFF1,Vertical Coefficient for phase 4 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xC4 0.--7. 1. "YPHI4COEFF0,Vertical Coefficient for phase 4 tap 0"
|
|
line.long 0xC8 "HEOCFG38,High-End Overlay Configuration Register 38"
|
|
hexmask.long.byte 0xC8 16.--23. 1. "YPHI5COEFF2,Vertical Coefficient for phase 5 tap 2"
|
|
hexmask.long.byte 0xC8 8.--15. 1. "YPHI5COEFF1,Vertical Coefficient for phase 5 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xC8 0.--7. 1. "YPHI5COEFF0,Vertical Coefficient for phase 5 tap 0"
|
|
line.long 0xCC "HEOCFG39,High-End Overlay Configuration Register 39"
|
|
hexmask.long.byte 0xCC 16.--23. 1. "YPHI6COEFF2,Vertical Coefficient for phase 6 tap 2"
|
|
hexmask.long.byte 0xCC 8.--15. 1. "YPHI6COEFF1,Vertical Coefficient for phase 6 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xCC 0.--7. 1. "YPHI6COEFF0,Vertical Coefficient for phase 6 tap 0"
|
|
line.long 0xD0 "HEOCFG40,High-End Overlay Configuration Register 40"
|
|
hexmask.long.byte 0xD0 16.--23. 1. "YPHI7COEFF2,Vertical Coefficient for phase 7 tap 2"
|
|
hexmask.long.byte 0xD0 8.--15. 1. "YPHI7COEFF1,Vertical Coefficient for phase 7 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xD0 0.--7. 1. "YPHI7COEFF0,Vertical Coefficient for phase 7 tap 0"
|
|
line.long 0xD4 "HEOCFG41,High-End Overlay Configuration Register 41"
|
|
bitfld.long 0xD4 16.--18. "YPHIDEF,Vertical Filter Phase Offset" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xD4 0.--2. "XPHIDEF,Horizontal Filter Phase Offset" "0,1,2,3,4,5,6,7"
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x600)++0x3
|
|
line.long 0x0 "BASECLUT[$1],Base CLUT Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RCLUT,Red Color Entry"
|
|
hexmask.long.byte 0x0 8.--15. 1. "GCLUT,Green Color Entry"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "BCLUT,Blue Color Entry"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xA00)++0x3
|
|
line.long 0x0 "OVR1CLUT[$1],Overlay 1 CLUT Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ACLUT,Alpha Color Entry"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RCLUT,Red Color Entry"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GCLUT,Green Color Entry"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BCLUT,Blue Color Entry"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xE00)++0x3
|
|
line.long 0x0 "OVR2CLUT[$1],Overlay 2 CLUT Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ACLUT,Alpha Color Entry"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RCLUT,Red Color Entry"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GCLUT,Green Color Entry"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BCLUT,Blue Color Entry"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1200)++0x3
|
|
line.long 0x0 "HEOCLUT[$1],High-End Overlay CLUT Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ACLUT,Alpha Color Entry"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RCLUT,Red Color Entry"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GCLUT,Green Color Entry"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BCLUT,Blue Color Entry"
|
|
repeat.end
|
|
tree.end
|
|
tree "MATRIX (AHB Bus Matrix)"
|
|
base ad:0xFFFFDE00
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MCFG[$1],Master Configuration Register"
|
|
bitfld.long 0x0 0.--2. "ULBT,Undefined Length Burst Type" "0: Unlimited Length Burst-No predicted end of burst..,1: Single Access-The undefined length burst is..,2: 4-beat Burst-The undefined length burst or..,3: 8-beat Burst-The undefined length burst or..,4: 16-beat Burst-The undefined length burst or..,5: 32-beat Burst-The undefined length burst or..,6: 64-beat Burst-The undefined length burst or..,7: 128-beat Burst-The undefined length burst or.."
|
|
repeat.end
|
|
repeat 13. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SCFG[$1],Slave Configuration Register"
|
|
hexmask.long.byte 0x0 18.--21. 1. "FIXED_DEFMSTR,Fixed Default Master"
|
|
bitfld.long 0x0 16.--17. "DEFMSTR_TYPE,Default Master Type" "0: No Default Master-At the end of the current..,1: Last Default Master-At the end of the current..,2: Fixed Default Master-At the end of the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLOT_CYCLE,Maximum Bus Grant Duration for Masters"
|
|
repeat.end
|
|
repeat 13. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC)(list ad:0xFFFFDE80 ad:0xFFFFDE88 ad:0xFFFFDE90 ad:0xFFFFDE98 ad:0xFFFFDEA0 ad:0xFFFFDEA8 ad:0xFFFFDEB0 ad:0xFFFFDEB8 ad:0xFFFFDEC0 ad:0xFFFFDEC8 ad:0xFFFFDED0 ad:0xFFFFDED8 ad:0xFFFFDEE0)
|
|
tree "MATRIX_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PRAS,Priority Register A for Slave 0"
|
|
bitfld.long 0x0 30. "LQOSEN7,Latency Quality of Service Enable for Master 7" "0,1"
|
|
bitfld.long 0x0 28.--29. "M7PR,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 26. "LQOSEN6,Latency Quality of Service Enable for Master 6" "0,1"
|
|
bitfld.long 0x0 24.--25. "M6PR,Master 6 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 22. "LQOSEN5,Latency Quality of Service Enable for Master 5" "0,1"
|
|
bitfld.long 0x0 20.--21. "M5PR,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 18. "LQOSEN4,Latency Quality of Service Enable for Master 4" "0,1"
|
|
bitfld.long 0x0 16.--17. "M4PR,Master 4 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 14. "LQOSEN3,Latency Quality of Service Enable for Master 3" "0,1"
|
|
bitfld.long 0x0 12.--13. "M3PR,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 10. "LQOSEN2,Latency Quality of Service Enable for Master 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "M2PR,Master 2 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 6. "LQOSEN1,Latency Quality of Service Enable for Master 1" "0,1"
|
|
bitfld.long 0x0 4.--5. "M1PR,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 2. "LQOSEN0,Latency Quality of Service Enable for Master 0" "0,1"
|
|
bitfld.long 0x0 0.--1. "M0PR,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x4 "PRBS,Priority Register B for Slave 0"
|
|
bitfld.long 0x4 26. "LQOSEN14,Latency Quality of Service Enable for Master 14" "0,1"
|
|
bitfld.long 0x4 24.--25. "M14PR,Master 14 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 22. "LQOSEN13,Latency Quality of Service Enable for Master 13" "0,1"
|
|
bitfld.long 0x4 20.--21. "M13PR,Master 13 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 18. "LQOSEN12,Latency Quality of Service Enable for Master 12" "0,1"
|
|
bitfld.long 0x4 16.--17. "M12PR,Master 12 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 14. "LQOSEN11,Latency Quality of Service Enable for Master 11" "0,1"
|
|
bitfld.long 0x4 12.--13. "M11PR,Master 11 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 10. "LQOSEN10,Latency Quality of Service Enable for Master 10" "0,1"
|
|
bitfld.long 0x4 8.--9. "M10PR,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 6. "LQOSEN9,Latency Quality of Service Enable for Master 9" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "M9PR,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 2. "LQOSEN8,Latency Quality of Service Enable for Master 8" "0,1"
|
|
bitfld.long 0x4 0.--1. "M8PR,Master 8 Priority" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xFFFFDE00
|
|
newline
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "MRCR,Master Remap Control Register"
|
|
bitfld.long 0x0 14. "RCB14,Remap Command Bit for Master 14" "0,1"
|
|
bitfld.long 0x0 13. "RCB13,Remap Command Bit for Master 13" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RCB12,Remap Command Bit for Master 12" "0,1"
|
|
bitfld.long 0x0 11. "RCB11,Remap Command Bit for Master 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RCB10,Remap Command Bit for Master 10" "0,1"
|
|
bitfld.long 0x0 9. "RCB9,Remap Command Bit for Master 9" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RCB8,Remap Command Bit for Master 8" "0,1"
|
|
bitfld.long 0x0 7. "RCB7,Remap Command Bit for Master 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RCB6,Remap Command Bit for Master 6" "0,1"
|
|
bitfld.long 0x0 5. "RCB5,Remap Command Bit for Master 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RCB4,Remap Command Bit for Master 4" "0,1"
|
|
bitfld.long 0x0 3. "RCB3,Remap Command Bit for Master 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RCB2,Remap Command Bit for Master 2" "0,1"
|
|
bitfld.long 0x0 1. "RCB1,Remap Command Bit for Master 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RCB0,Remap Command Bit for Master 0" "0,1"
|
|
wgroup.long 0x150++0x7
|
|
line.long 0x0 "MEIER,Master Error Interrupt Enable Register"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MEIDR,Master Error Interrupt Disable Register"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
rgroup.long 0x158++0x7
|
|
line.long 0x0 "MEIMR,Master Error Interrupt Mask Register"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MESR,Master Error Status Register"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x160)++0x3
|
|
line.long 0x0 "MEAR[$1],Master 0 Error Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ERRADD,Master Error Address"
|
|
repeat.end
|
|
group.long 0x1E4++0x3
|
|
line.long 0x0 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "CFGFRZ,Configuration Freeze" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x1E8++0x3
|
|
line.long 0x0 "WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "MPDDRC (AHB Multiport DDR-SDRAM Controller)"
|
|
base ad:0xFFFFE800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 0.--2. "MODE,MPDDRC Command Mode" "0: Normal Mode. Any access to the MPDDRC is decoded..,1: The MPDDRC issues a NOP command when the..,2: The MPDDRC issues the All Banks Precharge..,3: The MPDDRC issues a Load Mode Register command..,4: The MPDDRC issues an Autorefresh command when..,5: The MPDDRC issues an Extended Load Mode Register..,6: Deep Power mode: Access to Deep Powerdown mode,?"
|
|
line.long 0x4 "RTR,Refresh Timer Register"
|
|
hexmask.long.word 0x4 0.--11. 1. "COUNT,MPDDRC Refresh Timer Count"
|
|
line.long 0x8 "CR,Configuration Register"
|
|
bitfld.long 0x8 23. "UNAL,This bit must always be written to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 22. "DECOD,Type of Decoding" "0: Method for address mapping where banks alternate..,1: Method for address mapping where banks alternate.."
|
|
newline
|
|
bitfld.long 0x8 21. "NDQS,Not DQS." "0: 'Not DQS' is enabled.,1: 'Not DQS' is disabled."
|
|
newline
|
|
bitfld.long 0x8 20. "NB,Number of Banks" "0: 4-bank memory devices,1: 8 banks. Only possible when using DDR2-SDRAM.."
|
|
newline
|
|
bitfld.long 0x8 19. "LC_LPDDR1,Low-cost Low-power DDR1" "0: Any type of memory devices except of low cost..,1: Low-cost and low-density low-power DDR1. These.."
|
|
newline
|
|
bitfld.long 0x8 16. "DQMS,Mask Data is Shared" "0: DQM is not shared with another controller,1: DQM is shared with another controller"
|
|
newline
|
|
bitfld.long 0x8 12.--14. "OCD,Off-chip Driver" "0: Exit from OCD Calibration mode and maintain..,?,?,?,?,?,?,7: OCD calibration default"
|
|
newline
|
|
bitfld.long 0x8 9. "DIS_DLL,DISABLE DLL" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DIC_DS,Output Driver Impedance Control (Drive Strength)" "0: Normal drive strength (DDR2),1: Weak drive strength (DDR2)"
|
|
newline
|
|
bitfld.long 0x8 7. "DLL,Reset DLL" "0: Disable DLL reset,1: Enable DLL reset"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "CAS,CAS Latency" "?,?,2: LPDDR1 CAS Latency 2,3: DDR2/LPDDR1 CAS Latency 3,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "NR,Number of Row Bits." "0: 11 bits to define the row number up to 2048 rows,1: 12 bits to define the row number up to 4096 rows,2: 13 bits to define the row number up to 8192 rows,3: 14 bits to define the row number up to 16384 rows"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NC,Number of Column Bits" "0: 9 bits to define the column number up to 512..,1: 10 bits to define the column number up to 1024..,2: 11 bits to define the column number up to 2048..,3: 12 bits to define the column number up to 4096.."
|
|
line.long 0xC "TPR0,Timing Parameter 0 Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "TMRD,Load Mode Register Command to Activate or Refresh Command"
|
|
newline
|
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bitfld.long 0xC 24.--26. "TWTR,Internal Write to Read Delay" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0xC 20.--23. 1. "TRRD,Active BankA to Active BankB"
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newline
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hexmask.long.byte 0xC 16.--19. 1. "TRP,Row Precharge Delay"
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|
newline
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hexmask.long.byte 0xC 12.--15. 1. "TRC,Row Cycle Delay"
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|
newline
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hexmask.long.byte 0xC 8.--11. 1. "TWR,Write Recovery Delay"
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|
newline
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hexmask.long.byte 0xC 4.--7. 1. "TRCD,Row to Column Delay"
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hexmask.long.byte 0xC 0.--3. 1. "TRAS,Active to Precharge Delay"
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line.long 0x10 "TPR1,Timing Parameter 1 Register"
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hexmask.long.byte 0x10 24.--27. 1. "TXP,Exit Powerdown Delay to First Command"
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newline
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hexmask.long.byte 0x10 16.--23. 1. "TXSRD,Exit Self-refresh Delay to Read Command"
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newline
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hexmask.long.byte 0x10 8.--15. 1. "TXSNR,Exit Self-refresh Delay to Non-Read Command"
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newline
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hexmask.long.byte 0x10 0.--6. 1. "TRFC,Row Refresh Cycle"
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line.long 0x14 "TPR2,Timing Parameter 2 Register"
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hexmask.long.byte 0x14 16.--19. 1. "TFAW,Four Active Windows"
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newline
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bitfld.long 0x14 12.--14. "TRTP,Read to Precharge" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x14 8.--11. 1. "TRPA,Row Precharge All Delay"
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newline
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hexmask.long.byte 0x14 4.--7. 1. "TXARDS,Exit Active Power Down Delay to Read Command in Mode 'Slow Exit'"
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newline
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hexmask.long.byte 0x14 0.--3. 1. "TXARD,Exit Active Power Down Delay to Read Command in Mode 'Fast Exit'"
|
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group.long 0x1C++0x7
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line.long 0x0 "LPR,Low-Power Register"
|
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bitfld.long 0x0 25. "SELF_DONE,Self-refresh is Done (read-only)" "0,1"
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bitfld.long 0x0 24. "CHG_FRQ,Change Clock Frequency During Self-refresh Mode" "0,1"
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newline
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bitfld.long 0x0 20.--21. "UPD_MR,Update Load Mode Register and Extended Mode Register" "0: Update of Load Mode and Extended Mode registers..,1: MPDDRC shares an external bus. Automatic update..,2: MPDDRC does not share an external bus. Automatic..,?"
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bitfld.long 0x0 16. "APDE,Active Power Down Exit Time" "0: Fast Exit from Power Down. DDR2-SDRAM devices..,1: Slow Exit from Power Down. DDR2-SDRAM devices.."
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bitfld.long 0x0 14. "SELFAUTO,Self-refresh Exit Autorefresh" "0,1"
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newline
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bitfld.long 0x0 12.--13. "TIMEOUT,Time Between Last Transfer and Low-Power Mode" "0: SDRAM Low-power mode is activated immediately..,1: SDRAM Low-power mode is activated 64 clock..,2: SDRAM Low-power mode is activated 128 clock..,?"
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bitfld.long 0x0 8.--10. "DS,Drive Strength" "0: Full drive strength,1: Half drive strength,2: Quarter drive strength,3: Octant drive strength,?,?,?,?"
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newline
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bitfld.long 0x0 4.--6. "PASR,Partial Array Self-refresh" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 2. "CLK_FR,Clock Frozen Command Bit" "0: Clock(s) is/are not frozen.,1: Clock(s) is/are frozen."
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newline
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bitfld.long 0x0 0.--1. "LPCB,Low-power Command Bit" "0: Low-power feature is inhibited. No Powerdown..,1: The MPDDRC issues a self-refresh command to the..,2: The MPDDRC issues a Powerdown command to the..,3: The MPDDRC issues a Deep Powerdown command to.."
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line.long 0x4 "MD,Memory Device Register"
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bitfld.long 0x4 4. "DBW,Data Bus Width" "?,1: Data bus width is 16 bits."
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newline
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bitfld.long 0x4 0.--2. "MD,Memory Device" "?,?,?,3: Low-power DDR1-SDRAM,?,?,6: DDR2-SDRAM,?"
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group.long 0x34++0x7
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line.long 0x0 "IO_CALIBR,I/O Calibration Register"
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hexmask.long.byte 0x0 20.--23. 1. "CALCODEN,Number of N-type Transistors (read-only)"
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hexmask.long.byte 0x0 16.--19. 1. "CALCODEP,Number of P-type Transistors (read-only)"
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newline
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hexmask.long.byte 0x0 8.--14. 1. "TZQIO,IO Calibration"
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newline
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bitfld.long 0x0 0.--2. "CK_F_RANGE,DDRCK Maximum Clock Frequency Range Indicator" "0,1,2,3,4,5,6,7"
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line.long 0x4 "OCMS,OCMS Register"
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bitfld.long 0x4 4. "TAMPCLR,Tamper Clear Enable" "0,1"
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newline
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bitfld.long 0x4 0. "SCR_EN,Scrambling Enable" "0,1"
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wgroup.long 0x3C++0x7
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line.long 0x0 "OCMS_KEY1,OCMS KEY1 Register"
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hexmask.long 0x0 0.--31. 1. "KEY1,Off-chip Memory Scrambling (OCMS) Key Part 1"
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line.long 0x4 "OCMS_KEY2,OCMS KEY2 Register"
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hexmask.long 0x4 0.--31. 1. "KEY2,Off-chip Memory Scrambling (OCMS) Key Part 2"
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group.long 0x44++0xB
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line.long 0x0 "CONF_ARBITER,Configuration Arbiter Register"
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bitfld.long 0x0 27. "BDW_BURST_P3,Bandwidth Arbitration Mode on Port X" "0,1"
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newline
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bitfld.long 0x0 26. "BDW_BURST_P2,Bandwidth Arbitration Mode on Port X" "0,1"
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bitfld.long 0x0 25. "BDW_BURST_P1,Bandwidth Arbitration Mode on Port X" "0,1"
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bitfld.long 0x0 24. "BDW_BURST_P0,Bandwidth Arbitration Mode on Port X" "0,1"
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bitfld.long 0x0 19. "MA_PR_P3,Master or Software Provide Information" "0,1"
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bitfld.long 0x0 18. "MA_PR_P2,Master or Software Provide Information" "0,1"
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bitfld.long 0x0 17. "MA_PR_P1,Master or Software Provide Information" "0,1"
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bitfld.long 0x0 16. "MA_PR_P0,Master or Software Provide Information" "0,1"
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newline
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bitfld.long 0x0 11. "RQ_WD_P3,Request or Word from Port X" "0,1"
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bitfld.long 0x0 10. "RQ_WD_P2,Request or Word from Port X" "0,1"
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newline
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bitfld.long 0x0 9. "RQ_WD_P1,Request or Word from Port X" "0,1"
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newline
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bitfld.long 0x0 8. "RQ_WD_P0,Request or Word from Port X" "0,1"
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newline
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bitfld.long 0x0 3. "BDW_MAX_CUR,Bandwidth Max or Current" "0,1"
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newline
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bitfld.long 0x0 0.--1. "ARB,Type of Arbitration" "0: Round-Robin Policy,1: Request Policy,2: Bandwidth Policy,3: Quality of Service Policy"
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line.long 0x4 "TIMEOUT,Timeout Register"
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hexmask.long.byte 0x4 12.--15. 1. "TIMEOUT_P3,Timeout for Ports 0 1 2 3"
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newline
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hexmask.long.byte 0x4 8.--11. 1. "TIMEOUT_P2,Timeout for Ports 0 1 2 3"
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newline
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hexmask.long.byte 0x4 4.--7. 1. "TIMEOUT_P1,Timeout for Ports 0 1 2 3"
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newline
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hexmask.long.byte 0x4 0.--3. 1. "TIMEOUT_P0,Timeout for Ports 0 1 2 3"
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line.long 0x8 "REQ_PORT_0123,Request Port 0-1-2-3 Register"
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hexmask.long.byte 0x8 24.--31. 1. "NRQ_NWD_BDW_P3,Number of Requests Number of Words or Bandwidth Allocation from Port 0-1-2-3"
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newline
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hexmask.long.byte 0x8 16.--23. 1. "NRQ_NWD_BDW_P2,Number of Requests Number of Words or Bandwidth Allocation from Port 0-1-2-3"
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newline
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hexmask.long.byte 0x8 8.--15. 1. "NRQ_NWD_BDW_P1,Number of Requests Number of Words or Bandwidth Allocation from Port 0-1-2-3"
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newline
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hexmask.long.byte 0x8 0.--7. 1. "NRQ_NWD_BDW_P0,Number of Requests Number of Words or Bandwidth Allocation from Port 0-1-2-3"
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rgroup.long 0x54++0x3
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line.long 0x0 "BDW_PORT_0123,Current/Maximum Bandwidth Port 0-1-2-3 Register"
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hexmask.long.byte 0x0 24.--30. 1. "BDW_P3,Current/Maximum Bandwidth from Port 0-1-2-3"
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newline
|
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hexmask.long.byte 0x0 16.--22. 1. "BDW_P2,Current/Maximum Bandwidth from Port 0-1-2-3"
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|
newline
|
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hexmask.long.byte 0x0 8.--14. 1. "BDW_P1,Current/Maximum Bandwidth from Port 0-1-2-3"
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|
newline
|
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hexmask.long.byte 0x0 0.--6. 1. "BDW_P0,Current/Maximum Bandwidth from Port 0-1-2-3"
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group.long 0x5C++0x17
|
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line.long 0x0 "RD_DATA_PATH,Read Data Path Register"
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bitfld.long 0x0 0.--1. "SHIFT_SAMPLING,Shift Sampling Point of Data" "0: Initial sampling point.,1: Sampling point is shifted by one cycle.,2: Sampling point is shifted by two cycles.,3: Not applicable for DDR2 and LPDDR1 devices."
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line.long 0x4 "MCFGR,Monitor Configuration Register"
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bitfld.long 0x4 11.--13. "INFO,Information Type" "0: Information concerning the transfer with the..,1: Number of transfers on the port,2: Total latency on the port,?,4: Information concerning the transfer with the..,5: Information concerning the transfer with the..,?,?"
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newline
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bitfld.long 0x4 10. "REFR_CALIB,Refresh Calibration" "0,1"
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|
newline
|
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bitfld.long 0x4 8.--9. "READ_WRITE,Read/Write Access" "0: Read and Write accesses are triggered.,1: Only Write accesses are triggered.,2: Only Read accesses are triggered.,?"
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newline
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bitfld.long 0x4 4. "RUN,Control Monitor" "0,1"
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|
newline
|
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bitfld.long 0x4 1. "SOFT_RESET,Soft Reset" "0,1"
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|
newline
|
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bitfld.long 0x4 0. "EN_MONI,Enable Monitor" "0,1"
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line.long 0x8 "MADDR0,Monitor Address High/Low Port 0 Register"
|
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hexmask.long.word 0x8 16.--31. 1. "ADDR_HIGH_PORT0,Address High on Port 0"
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newline
|
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hexmask.long.word 0x8 0.--15. 1. "ADDR_LOW_PORT0,Address Low on Port 0"
|
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line.long 0xC "MADDR1,Monitor Address High/Low Port 1 Register"
|
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hexmask.long.word 0xC 16.--31. 1. "ADDR_HIGH_PORT1,Address High on Port 1"
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|
newline
|
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hexmask.long.word 0xC 0.--15. 1. "ADDR_LOW_PORT1,Address Low on Port 1"
|
|
line.long 0x10 "MADDR2,Monitor Address High/Low Port 2 Register"
|
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hexmask.long.word 0x10 16.--31. 1. "ADDR_HIGH_PORT2,Address High on Port 2"
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newline
|
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hexmask.long.word 0x10 0.--15. 1. "ADDR_LOW_PORT2,Address Low on Port 2"
|
|
line.long 0x14 "MADDR3,Monitor Address High/Low Port 3 Register"
|
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hexmask.long.word 0x14 16.--31. 1. "ADDR_HIGH_PORT3,Address High on Port 3"
|
|
newline
|
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hexmask.long.word 0x14 0.--15. 1. "ADDR_LOW_PORT3,Address Low on Port 3"
|
|
rgroup.long 0x84++0x3
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line.long 0x0 "MINFO0_MAX_WAIT_MODE,Monitor Information Port 0 Register"
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bitfld.long 0x0 25.--26. "LQOS,Value of Quality Of Service on Port 0" "0: Background transfers,1: Bandwidth sensitive,2: Latency sensitive,3: Latency critical"
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newline
|
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bitfld.long 0x0 24. "READ_WRITE,Read or Write Access on Port 0" "0,1"
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|
newline
|
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bitfld.long 0x0 20.--22. "SIZE,Transfer Size on Port 0" "0: Byte transfer,1: Halfword transfer,2: Word transfer,3: Dword transfer,?,?,?,?"
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newline
|
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bitfld.long 0x0 16.--18. "BURST,Type of Burst on Port 0" "0: Single transfer,1: Incrementing burst of unspecified length,2: 4-beat wrapping burst,3: 4-beat incrementing burst,4: 8-beat wrapping burst,5: 8-beat incrementing burst,6: 16-beat wrapping burst,7: 16-beat incrementing burst"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "MAX_PORT0_WAITING,Address High on Port 0"
|
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rgroup.long 0x84++0x3
|
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line.long 0x0 "MINFO0_NB_TRANSFERS_MODE,Monitor Information Port 0 Register"
|
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hexmask.long 0x0 0.--31. 1. "P0_NB_TRANSFERS,Number of Transfers on Port 0"
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rgroup.long 0x84++0x3
|
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line.long 0x0 "MINFO0_TOTAL_LATENCY_MODE,Monitor Information Port 0 Register"
|
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hexmask.long 0x0 0.--31. 1. "P0_TOTAL_LATENCY,Total Latency on Port 0"
|
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rgroup.long 0x84++0x3
|
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line.long 0x0 "MINFO0_TOTAL_LATENCY_QOS01_MODE,Monitor Information Port 0 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "P0_TOTAL_LATENCY_QOS1,Total Latency on Port 1 when value of qos is 1"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "P0_TOTAL_LATENCY_QOS0,Total Latency on Port 0 when value of qos is 0"
|
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rgroup.long 0x84++0x7
|
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line.long 0x0 "MINFO0_TOTAL_LATENCY_QOS23_MODE,Monitor Information Port 0 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "P0_TOTAL_LATENCY_QOS3,Total Latency on Port 3 when value of qos is 3"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "P0_TOTAL_LATENCY_QOS2,Total Latency on Port 2 when value of qos is 2"
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line.long 0x4 "MINFO1_MAX_WAIT_MODE,Monitor Information Port 1 Register"
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bitfld.long 0x4 25.--26. "LQOS,Value of Quality Of Service on Port 1" "0: Background transfers,1: Bandwidth sensitive,2: Latency sensitive,3: Latency critical"
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|
newline
|
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bitfld.long 0x4 24. "READ_WRITE,Read or Write Access on Port 1" "0,1"
|
|
newline
|
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bitfld.long 0x4 20.--22. "SIZE,Transfer Size on Port 1" "0: Byte transfer,1: Halfword transfer,2: Word transfer,3: Dword transfer,?,?,?,?"
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newline
|
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bitfld.long 0x4 16.--18. "BURST,Type of Burst on Port 1" "0: Single transfer,1: Incrementing burst of unspecified length,2: 4-beat wrapping burst,3: 4-beat incrementing burst,4: 8-beat wrapping burst,5: 8-beat incrementing burst,6: 16-beat wrapping burst,7: 16-beat incrementing burst"
|
|
newline
|
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hexmask.long.word 0x4 0.--15. 1. "MAX_PORT1_WAITING,Address High on Port 1"
|
|
rgroup.long 0x88++0x3
|
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line.long 0x0 "MINFO1_NB_TRANSFERS_MODE,Monitor Information Port 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P1_NB_TRANSFERS,Number of Transfers on Port 1"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "MINFO1_TOTAL_LATENCY_MODE,Monitor Information Port 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P1_TOTAL_LATENCY,Total Latency on Port 1"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "MINFO1_TOTAL_LATENCY_QOS01_MODE,Monitor Information Port 1 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "P1_TOTAL_LATENCY_QOS1,Total Latency on Port 1 when value of qos is 1"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "P1_TOTAL_LATENCY_QOS0,Total Latency on Port 0 when value of qos is 0"
|
|
rgroup.long 0x88++0x7
|
|
line.long 0x0 "MINFO1_TOTAL_LATENCY_QOS23_MODE,Monitor Information Port 1 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "P1_TOTAL_LATENCY_QOS3,Total Latency on Port 3 when value of qos is 3"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "P1_TOTAL_LATENCY_QOS2,Total Latency on Port 2 when value of qos is 2"
|
|
line.long 0x4 "MINFO2_MAX_WAIT_MODE,Monitor Information Port 2 Register"
|
|
bitfld.long 0x4 25.--26. "LQOS,Value of Quality Of Service on Port 2" "0: Background transfers,1: Bandwidth sensitive,2: Latency sensitive,3: Latency critical"
|
|
newline
|
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bitfld.long 0x4 24. "READ_WRITE,Read or Write Access on Port 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "SIZE,Transfer Size on Port 2" "0: Byte transfer,1: Halfword transfer,2: Word transfer,3: Dword transfer,?,?,?,?"
|
|
newline
|
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bitfld.long 0x4 16.--18. "BURST,Type of Burst on Port 2" "0: Single transfer,1: Incrementing burst of unspecified length,2: 4-beat wrapping burst,3: 4-beat incrementing burst,4: 8-beat wrapping burst,5: 8-beat incrementing burst,6: 16-beat wrapping burst,7: 16-beat incrementing burst"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "MAX_PORT2_WAITING,Address High on Port 2"
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x0 "MINFO2_NB_TRANSFERS_MODE,Monitor Information Port 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P2_NB_TRANSFERS,Number of Transfers on Port 2"
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x0 "MINFO2_TOTAL_LATENCY_MODE,Monitor Information Port 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P2_TOTAL_LATENCY,Total Latency on Port 2"
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x0 "MINFO2_TOTAL_LATENCY_QOS01_MODE,Monitor Information Port 2 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "P2_TOTAL_LATENCY_QOS1,Total Latency on Port 1 when value of qos is 1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "P2_TOTAL_LATENCY_QOS0,Total Latency on Port 0 when value of qos is 0"
|
|
rgroup.long 0x8C++0x7
|
|
line.long 0x0 "MINFO2_TOTAL_LATENCY_QOS23_MODE,Monitor Information Port 2 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "P2_TOTAL_LATENCY_QOS3,Total Latency on Port 3 when value of qos is 3"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "P2_TOTAL_LATENCY_QOS2,Total Latency on Port 2 when value of qos is 2"
|
|
line.long 0x4 "MINFO3_MAX_WAIT_MODE,Monitor Information Port 3 Register"
|
|
bitfld.long 0x4 25.--26. "LQOS,Value of Quality Of Service on Port 3" "0: Background transfers,1: Bandwidth sensitive,2: Latency sensitive,3: Latency critical"
|
|
newline
|
|
bitfld.long 0x4 24. "READ_WRITE,Read or Write Access on Port 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "SIZE,Transfer Size on Port 3" "0: Byte transfer,1: Halfword transfer,2: Word transfer,3: Dword transfer,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "BURST,Type of Burst on Port 3" "0: Single transfer,1: Incrementing burst of unspecified length,2: 4-beat wrapping burst,3: 4-beat incrementing burst,4: 8-beat wrapping burst,5: 8-beat incrementing burst,6: 16-beat wrapping burst,7: 16-beat incrementing burst"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "MAX_PORT3_WAITING,Address High on Port 3"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "MINFO3_NB_TRANSFERS_MODE,Monitor Information Port 3 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P3_NB_TRANSFERS,Number of Transfers on Port 3"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "MINFO3_TOTAL_LATENCY_MODE,Monitor Information Port 3 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P3_TOTAL_LATENCY,Total Latency on Port 3"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "MINFO3_TOTAL_LATENCY_QOS01_MODE,Monitor Information Port 3 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "P3_TOTAL_LATENCY_QOS1,Total Latency on Port 1 when value of qos is 1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "P3_TOTAL_LATENCY_QOS0,Total Latency on Port 0 when value of qos is 0"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "MINFO3_TOTAL_LATENCY_QOS23_MODE,Monitor Information Port 3 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "P3_TOTAL_LATENCY_QOS3,Total Latency on Port 3 when value of qos is 3"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "P3_TOTAL_LATENCY_QOS2,Total Latency on Port 2 when value of qos is 2"
|
|
wgroup.long 0xC0++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "RD_ERR,Read Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SEC,Security and /or Safety Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 1. "RD_ERR,Read Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SEC,Security and /or Safety Interrupt Disable" "0,1"
|
|
rgroup.long 0xC8++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 1. "RD_ERR,Read Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SEC,Security and /or Safety Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 1. "RD_ERR,Read Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SEC,Security and /or Safety Event" "0,1"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "SAFETY,Safety Register"
|
|
bitfld.long 0x0 28. "EN,Enable Periodic Check of Memory Device" "0,1"
|
|
newline
|
|
hexmask.long 0x0 0.--27. 1. "ADDRESS,Memory Device Address"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: An access is performed into some registers after.."
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SWETYP,Software Error Type (cleared on read)" "0: A write-only register has been read (warning).,1: MPDDRC is enabled and a write access has been..,2: Access to an undefined address (warning).,3: Abnormal use of MPDDRC user interface when.."
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "OTPC (OTP Memory Controller)"
|
|
base ad:0xEFF00000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Programming Key"
|
|
bitfld.long 0x0 15. "REFRESH,Refresh the Area" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "KBSTOP,Key Bus Transfer Stop" "0,1"
|
|
bitfld.long 0x0 8. "KBSTART,Key Bus Transfer Start" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "FLUSH,Flush Temporary Registers" "0,1"
|
|
bitfld.long 0x0 6. "READ,Read Area" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "HIDE,Hide Packet" "0,1"
|
|
bitfld.long 0x0 2. "INVLD,Invalidate Packet" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CKSGEN,Generate Checksum" "0,1"
|
|
bitfld.long 0x0 0. "PGM,Program Packet" "0,1"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "ADDR,Address"
|
|
bitfld.long 0x0 15. "LOCK,Lock Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "KBDST,Key Bus Destination" "0: The TDES is the destination of the key transfer.,1: The AES is the destination of the key transfer."
|
|
bitfld.long 0x0 9. "WRDIS,Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RDDIS,Read Disable" "0,1"
|
|
bitfld.long 0x0 7. "EMUL,Emulation Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "NPCKT,New Packet" "0,1"
|
|
bitfld.long 0x0 0. "UHCRRDIS,User Hardware Configuration Register Read Disable" "0,1"
|
|
line.long 0x4 "AR,Address Register"
|
|
bitfld.long 0x4 16. "INCRT,Increment Type" "0: Increment DADDR after a read of OTPC_DR.,1: Increment DADDR after a write of OTPC_DR."
|
|
hexmask.long.byte 0x4 0.--7. 1. "DADDR,Data Address"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 11. "UNLOCK,OTP Registers Unlocked" "0,1"
|
|
bitfld.long 0x0 9. "ONEF,One Found" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HIDE,Hiding On-Going" "0,1"
|
|
bitfld.long 0x0 7. "FLUSH,Flush On-Going" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "READ,Read On-Going" "0,1"
|
|
bitfld.long 0x0 5. "SKBB,Slave Key Bus Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MKBB,Master Key Bus Busy" "0,1"
|
|
bitfld.long 0x0 3. "EMUL,Emulation Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "INVLD,Invalidation On-Going" "0,1"
|
|
bitfld.long 0x0 1. "LOCK,Lock On-Going" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PGM,Programming On-Going" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "KBERR,Key Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "HDERR,Hide Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 13. "COERR,Corruption Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CKERR,Checksum Check Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "EORF,End Of Refresh Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EOH,End Of Hide Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "EOF,End Of Flush Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EOR,End Of Read Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "WERR,Write Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IVERR,Invalidation Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "LKERR,Locking Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PGERR,Programming Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "EOKT,End Of Key Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EOI,End Of Invalidation Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "EOL,End Of Locking Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOP,End Of Programming Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 28. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "KBERR,Key Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "HDERR,Hide Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 13. "COERR,Corruption Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CKERR,Checksum Check Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 11. "EORF,End Of Refresh Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "EOH,End Of Hide Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "EOF,End Of Flush Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "EOR,End Of Read Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "WERR,Write Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "IVERR,Invalidation Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "LKERR,Locking Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PGERR,Programming Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "EOKT,End Of Key Transfer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EOI,End Of Invalidation Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "EOL,End Of Locking Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EOP,End Of Programming Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "KBERR,Key Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "HDERR,Hide Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 13. "COERR,Corruption Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CKERR,Checksum Check Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 11. "EORF,End Of Refresh Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EOH,End Of Hide Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "EOF,End Of Flush Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EOR,End Of Read Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "WERR,Write Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IVERR,Invalidation Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "LKERR,Locking Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PGERR,Programming Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "EOKT,End Of Key Transfer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EOI,End Of Invalidation Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "EOL,End Of Locking Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOP,End Of Programming Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 28. "SECE,Security and/or Safety Event (cleared on read)" "0,1"
|
|
bitfld.long 0x4 16. "KBERR,Key Bus Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "HDERR,Hide Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 13. "COERR,Corruption Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CKERR,Checksum Check Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 11. "EORF,End Of Refresh (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "EOH,End Of Hide (cleared on read)" "0,1"
|
|
bitfld.long 0x4 9. "EOF,End Of Flush (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "EOR,End Of Read (cleared on read)" "0,1"
|
|
bitfld.long 0x4 7. "WERR,Write Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "IVERR,Invalidation Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 5. "LKERR,Locking Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PGERR,Programming Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 3. "EOKT,End Of Key Transfer (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EOI,End Of Invalidation (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "EOL,End Of Locking (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EOP,End Of Programming (cleared on read)" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "HR,Header Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CHECKSUM,Packet Checksum"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SIZE,Packet Size"
|
|
newline
|
|
bitfld.long 0x0 7. "ONE,One" "0,1"
|
|
bitfld.long 0x0 4.--5. "INVLD,Invalid Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 3. "LOCK,Lock Status" "0,1"
|
|
bitfld.long 0x0 0.--2. "PACKET,Packet Type" "?,1: Regular packet accessible through the User..,2: Key packet accessible only through the Key Buses,3: Boot Configuration packet,4: Secure Boot Configuration packet,5: Hardware Configuration packet,6: Custom packet,?"
|
|
line.long 0x4 "DR,Data Register"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Packet Data"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "BAR,Boot Addresses Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "SBCADDR,Secure Boot Configuration Address"
|
|
hexmask.long.word 0x0 0.--15. 1. "BCADDR,Boot Configuration Address"
|
|
line.long 0x4 "CAR,Custom Address Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CADDR,Custom Address"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "UHC0R,User Hardware Configuration 0 Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "JTAGDIS,JTAG Disable"
|
|
line.long 0x4 "UHC1R,User Hardware Configuration 1 Register"
|
|
bitfld.long 0x4 17. "URFDIS,User Refresh Disable" "0,1"
|
|
bitfld.long 0x4 16. "CPGDIS,Custom Packet Program Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CLKDIS,Custom Packet Lock Disable" "0,1"
|
|
bitfld.long 0x4 14. "CINVDIS,Custom Packet Invalidation Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SBCPGDIS,Secure Boot Configuration Packet Program Disable" "0,1"
|
|
bitfld.long 0x4 9. "SBCLKDIS,Secure Boot Configuration Packet Lock Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SBCINVDIS,Secure Boot Configuration Packet Invalidation Disable" "0,1"
|
|
bitfld.long 0x4 7. "BCPGDIS,Boot Configuration Packet Program Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "BCLKDIS,Boot Configuration Packet Lock Disable" "0,1"
|
|
bitfld.long 0x4 5. "BCINVDIS,Boot Configuration Packet Invalidation Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "UHCPGDIS,User Hardware Configuration Packet Program Disable" "0,1"
|
|
bitfld.long 0x4 3. "UHCLKDIS,User Hardware Configuration Packet Lock Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "UHCINVDIS,User Hardware Configuration Packet Invalidation Disable" "0,1"
|
|
bitfld.long 0x4 1. "UPGDIS,User programming Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "URDDIS,User Read Disable" "0,1"
|
|
rgroup.long 0x60++0xF
|
|
line.long 0x0 "UID0R,Product UID x Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "UID,Unique Product ID"
|
|
line.long 0x4 "UID1R,Product UID x Register 1"
|
|
hexmask.long 0x4 0.--31. 1. "UID,Unique Product ID"
|
|
line.long 0x8 "UID2R,Product UID x Register 2"
|
|
hexmask.long 0x8 0.--31. 1. "UID,Unique Product ID"
|
|
line.long 0xC "UID3R,Product UID x Register 3"
|
|
hexmask.long 0xC 0.--31. 1. "UID,Unique Product ID"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCTEN,Write Protection Control Enable" "0,1"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPCFEN,Write Protection Configuration Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class" "0: An abnormal access that does not have any impact.,1: An abnormal access that may have an impact."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type"
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "PIO (Parallel Input/Output Controller)"
|
|
base ad:0x0
|
|
tree "PIOA"
|
|
base ad:0xFFFFF400
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "PER,PIO Enable Register"
|
|
bitfld.long 0x0 31. "P31,PIO Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,PIO Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,PIO Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,PIO Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,PIO Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,PIO Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,PIO Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,PIO Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,PIO Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,PIO Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,PIO Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,PIO Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,PIO Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,PIO Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,PIO Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,PIO Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,PIO Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,PIO Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,PIO Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,PIO Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,PIO Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,PIO Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,PIO Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,PIO Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,PIO Enable" "0,1"
|
|
line.long 0x4 "PDR,PIO Disable Register"
|
|
bitfld.long 0x4 31. "P31,PIO Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,PIO Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,PIO Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,PIO Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,PIO Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,PIO Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,PIO Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,PIO Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,PIO Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,PIO Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,PIO Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,PIO Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,PIO Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,PIO Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,PIO Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,PIO Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,PIO Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,PIO Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,PIO Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,PIO Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,PIO Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,PIO Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,PIO Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,PIO Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,PIO Disable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "PSR,PIO Status Register"
|
|
bitfld.long 0x0 31. "P31,PIO Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,PIO Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,PIO Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,PIO Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,PIO Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,PIO Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,PIO Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,PIO Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,PIO Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,PIO Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,PIO Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,PIO Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,PIO Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,PIO Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,PIO Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,PIO Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,PIO Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,PIO Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,PIO Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,PIO Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,PIO Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,PIO Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,PIO Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,PIO Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,PIO Status" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "OER,Output Enable Register"
|
|
bitfld.long 0x0 31. "P31,Output Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Enable" "0,1"
|
|
line.long 0x4 "ODR,Output Disable Register"
|
|
bitfld.long 0x4 31. "P31,Output Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Output Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Output Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Output Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Output Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Output Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Output Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Output Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Output Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Output Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Output Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Output Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Output Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Output Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Output Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Output Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Output Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Output Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Output Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Output Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Output Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Output Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Output Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Output Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Output Disable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "OSR,Output Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Status" "0,1"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "IFER,Glitch Input Filter Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Filter Enable" "0,1"
|
|
line.long 0x4 "IFDR,Glitch Input Filter Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Filter Disable" "0,1"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "IFSR,Glitch Input Filter Status Register"
|
|
bitfld.long 0x0 31. "P31,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Filter Status" "0,1"
|
|
wgroup.long 0x30++0x7
|
|
line.long 0x0 "SODR,Set Output Data Register"
|
|
bitfld.long 0x0 31. "P31,Set Output Data" "0,1"
|
|
bitfld.long 0x0 30. "P30,Set Output Data" "0,1"
|
|
bitfld.long 0x0 29. "P29,Set Output Data" "0,1"
|
|
bitfld.long 0x0 28. "P28,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Set Output Data" "0,1"
|
|
bitfld.long 0x0 26. "P26,Set Output Data" "0,1"
|
|
bitfld.long 0x0 25. "P25,Set Output Data" "0,1"
|
|
bitfld.long 0x0 24. "P24,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Set Output Data" "0,1"
|
|
bitfld.long 0x0 22. "P22,Set Output Data" "0,1"
|
|
bitfld.long 0x0 21. "P21,Set Output Data" "0,1"
|
|
bitfld.long 0x0 20. "P20,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Set Output Data" "0,1"
|
|
bitfld.long 0x0 18. "P18,Set Output Data" "0,1"
|
|
bitfld.long 0x0 17. "P17,Set Output Data" "0,1"
|
|
bitfld.long 0x0 16. "P16,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Set Output Data" "0,1"
|
|
bitfld.long 0x0 14. "P14,Set Output Data" "0,1"
|
|
bitfld.long 0x0 13. "P13,Set Output Data" "0,1"
|
|
bitfld.long 0x0 12. "P12,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Set Output Data" "0,1"
|
|
bitfld.long 0x0 10. "P10,Set Output Data" "0,1"
|
|
bitfld.long 0x0 9. "P9,Set Output Data" "0,1"
|
|
bitfld.long 0x0 8. "P8,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Set Output Data" "0,1"
|
|
bitfld.long 0x0 6. "P6,Set Output Data" "0,1"
|
|
bitfld.long 0x0 5. "P5,Set Output Data" "0,1"
|
|
bitfld.long 0x0 4. "P4,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Set Output Data" "0,1"
|
|
bitfld.long 0x0 2. "P2,Set Output Data" "0,1"
|
|
bitfld.long 0x0 1. "P1,Set Output Data" "0,1"
|
|
bitfld.long 0x0 0. "P0,Set Output Data" "0,1"
|
|
line.long 0x4 "CODR,Clear Output Data Register"
|
|
bitfld.long 0x4 31. "P31,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 30. "P30,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 29. "P29,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 28. "P28,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 26. "P26,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 25. "P25,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 24. "P24,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 22. "P22,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 21. "P21,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 20. "P20,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 18. "P18,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 17. "P17,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 16. "P16,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 14. "P14,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 13. "P13,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 12. "P12,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 10. "P10,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 9. "P9,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 8. "P8,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 6. "P6,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 5. "P5,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 4. "P4,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 2. "P2,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 1. "P1,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 0. "P0,Clear Output Data" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "ODSR,Output Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PDSR,Pin Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
wgroup.long 0x40++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0,1"
|
|
rgroup.long 0x48++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0,1"
|
|
wgroup.long 0x50++0x7
|
|
line.long 0x0 "MDER,Multi-driver Enable Register"
|
|
bitfld.long 0x0 31. "P31,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Multi-drive Enable" "0,1"
|
|
line.long 0x4 "MDDR,Multi-driver Disable Register"
|
|
bitfld.long 0x4 31. "P31,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Multi-drive Disable" "0,1"
|
|
rgroup.long 0x58++0x3
|
|
line.long 0x0 "MDSR,Multi-driver Status Register"
|
|
bitfld.long 0x0 31. "P31,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Multi-drive Status" "0,1"
|
|
wgroup.long 0x60++0x7
|
|
line.long 0x0 "PUDR,Pull-Up Disable Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Up Disable" "0,1"
|
|
line.long 0x4 "PUER,Pull-Up Enable Register"
|
|
bitfld.long 0x4 31. "P31,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Pull-Up Enable" "0,1"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "PUSR,Pad Pull-Up Status Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Up Status" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "ABCDSR[$1],Peripheral ABCD Select Register"
|
|
bitfld.long 0x0 31. "P31,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 30. "P30,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 29. "P29,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 28. "P28,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 26. "P26,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 25. "P25,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 24. "P24,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 22. "P22,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 21. "P21,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 20. "P20,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 18. "P18,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 17. "P17,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 16. "P16,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 14. "P14,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 13. "P13,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 12. "P12,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 10. "P10,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 9. "P9,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 8. "P8,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 6. "P6,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 5. "P5,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 4. "P4,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 2. "P2,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 1. "P1,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 0. "P0,Peripheral Select" "0,1"
|
|
repeat.end
|
|
wgroup.long 0x80++0x7
|
|
line.long 0x0 "IFSCDR,Input Filter Slow Clock Disable Register"
|
|
bitfld.long 0x0 31. "P31,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 30. "P30,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 29. "P29,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 28. "P28,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 26. "P26,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 25. "P25,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 24. "P24,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 22. "P22,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 21. "P21,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 20. "P20,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 18. "P18,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 17. "P17,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 16. "P16,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 14. "P14,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 13. "P13,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 12. "P12,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 10. "P10,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 9. "P9,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 8. "P8,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 6. "P6,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 5. "P5,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 4. "P4,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 2. "P2,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 1. "P1,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 0. "P0,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
line.long 0x4 "IFSCER,Input Filter Slow Clock Enable Register"
|
|
bitfld.long 0x4 31. "P31,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 30. "P30,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 29. "P29,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 28. "P28,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 26. "P26,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 25. "P25,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 24. "P24,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 22. "P22,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 21. "P21,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 20. "P20,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 18. "P18,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 17. "P17,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 16. "P16,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 14. "P14,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 13. "P13,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 12. "P12,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 10. "P10,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 9. "P9,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 8. "P8,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 6. "P6,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 5. "P5,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 4. "P4,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 2. "P2,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 1. "P1,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 0. "P0,Slow Clock Debouncing Filtering Select" "0,1"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "IFSCSR,Input Filter Slow Clock Status Register"
|
|
bitfld.long 0x0 31. "P31,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "DIV,Slow Clock Divider Selection for Debouncing"
|
|
wgroup.long 0x90++0x7
|
|
line.long 0x0 "PPDDR,Pad Pull-Down Disable Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Down Disable" "0,1"
|
|
line.long 0x4 "PPDER,Pad Pull-Down Enable Register"
|
|
bitfld.long 0x4 31. "P31,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Pull-Down Enable" "0,1"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "PPDSR,Pad Pull-Down Status Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Down Status" "0,1"
|
|
wgroup.long 0xA0++0x7
|
|
line.long 0x0 "OWER,Output Write Enable"
|
|
bitfld.long 0x0 31. "P31,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Write Enable" "0,1"
|
|
line.long 0x4 "OWDR,Output Write Disable"
|
|
bitfld.long 0x4 31. "P31,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Output Write Disable" "0,1"
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x0 "OWSR,Output Write Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Write Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Write Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Write Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Write Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Write Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Write Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Write Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Write Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Write Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Write Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Write Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Write Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Write Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Write Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Write Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Write Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Write Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Write Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Write Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Write Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Write Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Write Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Write Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Write Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Write Status" "0,1"
|
|
wgroup.long 0xB0++0x7
|
|
line.long 0x0 "AIMER,Additional Interrupt Modes Enable Register"
|
|
bitfld.long 0x0 31. "P31,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Additional Interrupt Modes Enable" "0,1"
|
|
line.long 0x4 "AIMDR,Additional Interrupt Modes Disable Register"
|
|
bitfld.long 0x4 31. "P31,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Additional Interrupt Modes Disable" "0,1"
|
|
rgroup.long 0xB8++0x3
|
|
line.long 0x0 "AIMMR,Additional Interrupt Modes Mask Register"
|
|
bitfld.long 0x0 31. "P31,IO Line Index" "0,1"
|
|
bitfld.long 0x0 30. "P30,IO Line Index" "0,1"
|
|
bitfld.long 0x0 29. "P29,IO Line Index" "0,1"
|
|
bitfld.long 0x0 28. "P28,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,IO Line Index" "0,1"
|
|
bitfld.long 0x0 26. "P26,IO Line Index" "0,1"
|
|
bitfld.long 0x0 25. "P25,IO Line Index" "0,1"
|
|
bitfld.long 0x0 24. "P24,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,IO Line Index" "0,1"
|
|
bitfld.long 0x0 22. "P22,IO Line Index" "0,1"
|
|
bitfld.long 0x0 21. "P21,IO Line Index" "0,1"
|
|
bitfld.long 0x0 20. "P20,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,IO Line Index" "0,1"
|
|
bitfld.long 0x0 18. "P18,IO Line Index" "0,1"
|
|
bitfld.long 0x0 17. "P17,IO Line Index" "0,1"
|
|
bitfld.long 0x0 16. "P16,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,IO Line Index" "0,1"
|
|
bitfld.long 0x0 14. "P14,IO Line Index" "0,1"
|
|
bitfld.long 0x0 13. "P13,IO Line Index" "0,1"
|
|
bitfld.long 0x0 12. "P12,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,IO Line Index" "0,1"
|
|
bitfld.long 0x0 10. "P10,IO Line Index" "0,1"
|
|
bitfld.long 0x0 9. "P9,IO Line Index" "0,1"
|
|
bitfld.long 0x0 8. "P8,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,IO Line Index" "0,1"
|
|
bitfld.long 0x0 6. "P6,IO Line Index" "0,1"
|
|
bitfld.long 0x0 5. "P5,IO Line Index" "0,1"
|
|
bitfld.long 0x0 4. "P4,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,IO Line Index" "0,1"
|
|
bitfld.long 0x0 2. "P2,IO Line Index" "0,1"
|
|
bitfld.long 0x0 1. "P1,IO Line Index" "0,1"
|
|
bitfld.long 0x0 0. "P0,IO Line Index" "0,1"
|
|
wgroup.long 0xC0++0x7
|
|
line.long 0x0 "ESR,Edge Select Register"
|
|
bitfld.long 0x0 31. "P31,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Edge Interrupt Selection" "0,1"
|
|
line.long 0x4 "LSR,Level Select Register"
|
|
bitfld.long 0x4 31. "P31,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 30. "P30,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 29. "P29,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 28. "P28,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 26. "P26,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 25. "P25,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 24. "P24,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 22. "P22,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 21. "P21,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 20. "P20,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 18. "P18,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 17. "P17,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 16. "P16,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 14. "P14,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 13. "P13,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 12. "P12,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 10. "P10,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 9. "P9,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 8. "P8,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 6. "P6,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 5. "P5,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 4. "P4,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 2. "P2,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 1. "P1,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 0. "P0,Level Interrupt Selection" "0,1"
|
|
rgroup.long 0xC8++0x3
|
|
line.long 0x0 "ELSR,Edge/Level Status Register"
|
|
bitfld.long 0x0 31. "P31,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Edge/Level Interrupt Source Selection" "0,1"
|
|
wgroup.long 0xD0++0x7
|
|
line.long 0x0 "FELLSR,Falling Edge/Low-Level Select Register"
|
|
bitfld.long 0x0 31. "P31,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
line.long 0x4 "REHLSR,Rising Edge/High-Level Select Register"
|
|
bitfld.long 0x4 31. "P31,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 30. "P30,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 29. "P29,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 28. "P28,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 26. "P26,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 25. "P25,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 24. "P24,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 22. "P22,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 21. "P21,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 20. "P20,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 18. "P18,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 17. "P17,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 16. "P16,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 14. "P14,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 13. "P13,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 12. "P12,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 10. "P10,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 9. "P9,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 8. "P8,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 6. "P6,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 5. "P5,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 4. "P4,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 2. "P2,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 1. "P1,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 0. "P0,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x0 "FRLHSR,Fall/Rise - Low/High Status Register"
|
|
bitfld.long 0x0 31. "P31,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Edge/Level Interrupt Source Selection" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x0 31. "SCHMITT31,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 30. "SCHMITT30,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 29. "SCHMITT29,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 28. "SCHMITT28,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SCHMITT27,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 26. "SCHMITT26,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 25. "SCHMITT25,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 24. "SCHMITT24,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SCHMITT23,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 22. "SCHMITT22,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 21. "SCHMITT21,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 20. "SCHMITT20,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SCHMITT19,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 18. "SCHMITT18,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 17. "SCHMITT17,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 16. "SCHMITT16,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "SCHMITT15,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 14. "SCHMITT14,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 13. "SCHMITT13,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 12. "SCHMITT12,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SCHMITT11,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 10. "SCHMITT10,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 9. "SCHMITT9,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 8. "SCHMITT8,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SCHMITT7,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 6. "SCHMITT6,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 5. "SCHMITT5,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 4. "SCHMITT4,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SCHMITT3,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 2. "SCHMITT2,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 1. "SCHMITT1,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 0. "SCHMITT0,Schmitt Trigger Control" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "SLEWR,I/O Slewrate Control Register"
|
|
bitfld.long 0x0 31. "SR31,Slewrate Control for IO line 31" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 30. "SR30,Slewrate Control for IO line 30" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 29. "SR29,Slewrate Control for IO line 29" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 28. "SR28,Slewrate Control for IO line 28" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 27. "SR27,Slewrate Control for IO line 27" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 26. "SR26,Slewrate Control for IO line 26" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 25. "SR25,Slewrate Control for IO line 25" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 24. "SR24,Slewrate Control for IO line 24" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 23. "SR23,Slewrate Control for IO line 23" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 22. "SR22,Slewrate Control for IO line 22" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 21. "SR21,Slewrate Control for IO line 21" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 20. "SR20,Slewrate Control for IO line 20" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 19. "SR19,Slewrate Control for IO line 19" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 18. "SR18,Slewrate Control for IO line 18" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 17. "SR17,Slewrate Control for IO line 17" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 16. "SR16,Slewrate Control for IO line 16" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 15. "SR15,Slewrate Control for IO line 15" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 14. "SR14,Slewrate Control for IO line 14" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 13. "SR13,Slewrate Control for IO line 13" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 12. "SR12,Slewrate Control for IO line 12" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 11. "SR11,Slewrate Control for IO line 11" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 10. "SR10,Slewrate Control for IO line 10" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 9. "SR9,Slewrate Control for IO line 9" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 8. "SR8,Slewrate Control for IO line 8" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 7. "SR7,Slewrate Control for IO line 7" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 6. "SR6,Slewrate Control for IO line 6" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 5. "SR5,Slewrate Control for IO line 5" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 4. "SR4,Slewrate Control for IO line 4" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 3. "SR3,Slewrate Control for IO line 3" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 2. "SR2,Slewrate Control for IO line 2" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 1. "SR1,Slewrate Control for IO line 1" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 0. "SR0,Slewrate Control for IO line 0" "0: No slewrate control.,1: Slewrate controlled."
|
|
group.long 0x118++0x3
|
|
line.long 0x0 "DRIVER,I/O Drive Register"
|
|
bitfld.long 0x0 31. "DR31,Drive of I/O Line 31" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 30. "DR30,Drive of I/O Line 30" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 29. "DR29,Drive of I/O Line 29" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 28. "DR28,Drive of I/O Line 28" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 27. "DR27,Drive of I/O Line 27" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 26. "DR26,Drive of I/O Line 26" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 25. "DR25,Drive of I/O Line 25" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 24. "DR24,Drive of I/O Line 24" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 23. "DR23,Drive of I/O Line 23" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 22. "DR22,Drive of I/O Line 22" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 21. "DR21,Drive of I/O Line 21" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 20. "DR20,Drive of I/O Line 20" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 19. "DR19,Drive of I/O Line 19" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 18. "DR18,Drive of I/O Line 18" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 17. "DR17,Drive of I/O Line 17" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 16. "DR16,Drive of I/O Line 16" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 15. "DR15,Drive of I/O Line 15" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 14. "DR14,Drive of I/O Line 14" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 13. "DR13,Drive of I/O Line 13" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 12. "DR12,Drive of I/O Line 12" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 11. "DR11,Drive of I/O Line 11" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 10. "DR10,Drive of I/O Line 10" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 9. "DR9,Drive of I/O Line 9" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 8. "DR8,Drive of I/O Line 8" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 7. "DR7,Drive of I/O Line 7" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 6. "DR6,Drive of I/O Line 6" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 5. "DR5,Drive of I/O Line 5" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 4. "DR4,Drive of I/O Line 4" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 3. "DR3,Drive of I/O Line 3" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 2. "DR2,Drive of I/O Line 2" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 1. "DR1,Drive of I/O Line 1" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 0. "DR0,Drive of I/O Line 0" "0: Lowest drive,1: Highest drive"
|
|
tree.end
|
|
tree "PIOB"
|
|
base ad:0xFFFFF600
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "PER,PIO Enable Register"
|
|
bitfld.long 0x0 31. "P31,PIO Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,PIO Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,PIO Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,PIO Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,PIO Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,PIO Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,PIO Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,PIO Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,PIO Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,PIO Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,PIO Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,PIO Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,PIO Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,PIO Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,PIO Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,PIO Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,PIO Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,PIO Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,PIO Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,PIO Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,PIO Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,PIO Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,PIO Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,PIO Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,PIO Enable" "0,1"
|
|
line.long 0x4 "PDR,PIO Disable Register"
|
|
bitfld.long 0x4 31. "P31,PIO Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,PIO Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,PIO Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,PIO Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,PIO Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,PIO Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,PIO Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,PIO Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,PIO Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,PIO Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,PIO Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,PIO Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,PIO Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,PIO Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,PIO Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,PIO Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,PIO Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,PIO Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,PIO Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,PIO Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,PIO Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,PIO Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,PIO Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,PIO Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,PIO Disable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "PSR,PIO Status Register"
|
|
bitfld.long 0x0 31. "P31,PIO Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,PIO Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,PIO Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,PIO Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,PIO Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,PIO Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,PIO Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,PIO Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,PIO Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,PIO Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,PIO Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,PIO Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,PIO Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,PIO Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,PIO Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,PIO Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,PIO Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,PIO Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,PIO Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,PIO Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,PIO Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,PIO Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,PIO Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,PIO Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,PIO Status" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "OER,Output Enable Register"
|
|
bitfld.long 0x0 31. "P31,Output Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Enable" "0,1"
|
|
line.long 0x4 "ODR,Output Disable Register"
|
|
bitfld.long 0x4 31. "P31,Output Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Output Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Output Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Output Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Output Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Output Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Output Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Output Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Output Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Output Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Output Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Output Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Output Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Output Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Output Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Output Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Output Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Output Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Output Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Output Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Output Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Output Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Output Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Output Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Output Disable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "OSR,Output Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Status" "0,1"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "IFER,Glitch Input Filter Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Filter Enable" "0,1"
|
|
line.long 0x4 "IFDR,Glitch Input Filter Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Filter Disable" "0,1"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "IFSR,Glitch Input Filter Status Register"
|
|
bitfld.long 0x0 31. "P31,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Filter Status" "0,1"
|
|
wgroup.long 0x30++0x7
|
|
line.long 0x0 "SODR,Set Output Data Register"
|
|
bitfld.long 0x0 31. "P31,Set Output Data" "0,1"
|
|
bitfld.long 0x0 30. "P30,Set Output Data" "0,1"
|
|
bitfld.long 0x0 29. "P29,Set Output Data" "0,1"
|
|
bitfld.long 0x0 28. "P28,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Set Output Data" "0,1"
|
|
bitfld.long 0x0 26. "P26,Set Output Data" "0,1"
|
|
bitfld.long 0x0 25. "P25,Set Output Data" "0,1"
|
|
bitfld.long 0x0 24. "P24,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Set Output Data" "0,1"
|
|
bitfld.long 0x0 22. "P22,Set Output Data" "0,1"
|
|
bitfld.long 0x0 21. "P21,Set Output Data" "0,1"
|
|
bitfld.long 0x0 20. "P20,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Set Output Data" "0,1"
|
|
bitfld.long 0x0 18. "P18,Set Output Data" "0,1"
|
|
bitfld.long 0x0 17. "P17,Set Output Data" "0,1"
|
|
bitfld.long 0x0 16. "P16,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Set Output Data" "0,1"
|
|
bitfld.long 0x0 14. "P14,Set Output Data" "0,1"
|
|
bitfld.long 0x0 13. "P13,Set Output Data" "0,1"
|
|
bitfld.long 0x0 12. "P12,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Set Output Data" "0,1"
|
|
bitfld.long 0x0 10. "P10,Set Output Data" "0,1"
|
|
bitfld.long 0x0 9. "P9,Set Output Data" "0,1"
|
|
bitfld.long 0x0 8. "P8,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Set Output Data" "0,1"
|
|
bitfld.long 0x0 6. "P6,Set Output Data" "0,1"
|
|
bitfld.long 0x0 5. "P5,Set Output Data" "0,1"
|
|
bitfld.long 0x0 4. "P4,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Set Output Data" "0,1"
|
|
bitfld.long 0x0 2. "P2,Set Output Data" "0,1"
|
|
bitfld.long 0x0 1. "P1,Set Output Data" "0,1"
|
|
bitfld.long 0x0 0. "P0,Set Output Data" "0,1"
|
|
line.long 0x4 "CODR,Clear Output Data Register"
|
|
bitfld.long 0x4 31. "P31,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 30. "P30,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 29. "P29,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 28. "P28,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 26. "P26,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 25. "P25,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 24. "P24,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 22. "P22,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 21. "P21,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 20. "P20,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 18. "P18,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 17. "P17,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 16. "P16,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 14. "P14,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 13. "P13,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 12. "P12,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 10. "P10,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 9. "P9,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 8. "P8,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 6. "P6,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 5. "P5,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 4. "P4,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 2. "P2,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 1. "P1,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 0. "P0,Clear Output Data" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "ODSR,Output Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PDSR,Pin Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
wgroup.long 0x40++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0,1"
|
|
rgroup.long 0x48++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0,1"
|
|
wgroup.long 0x50++0x7
|
|
line.long 0x0 "MDER,Multi-driver Enable Register"
|
|
bitfld.long 0x0 31. "P31,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Multi-drive Enable" "0,1"
|
|
line.long 0x4 "MDDR,Multi-driver Disable Register"
|
|
bitfld.long 0x4 31. "P31,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Multi-drive Disable" "0,1"
|
|
rgroup.long 0x58++0x3
|
|
line.long 0x0 "MDSR,Multi-driver Status Register"
|
|
bitfld.long 0x0 31. "P31,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Multi-drive Status" "0,1"
|
|
wgroup.long 0x60++0x7
|
|
line.long 0x0 "PUDR,Pull-Up Disable Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Up Disable" "0,1"
|
|
line.long 0x4 "PUER,Pull-Up Enable Register"
|
|
bitfld.long 0x4 31. "P31,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Pull-Up Enable" "0,1"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "PUSR,Pad Pull-Up Status Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Up Status" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "ABCDSR[$1],Peripheral ABCD Select Register"
|
|
bitfld.long 0x0 31. "P31,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 30. "P30,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 29. "P29,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 28. "P28,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 26. "P26,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 25. "P25,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 24. "P24,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 22. "P22,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 21. "P21,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 20. "P20,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 18. "P18,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 17. "P17,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 16. "P16,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 14. "P14,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 13. "P13,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 12. "P12,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 10. "P10,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 9. "P9,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 8. "P8,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 6. "P6,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 5. "P5,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 4. "P4,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 2. "P2,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 1. "P1,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 0. "P0,Peripheral Select" "0,1"
|
|
repeat.end
|
|
wgroup.long 0x80++0x7
|
|
line.long 0x0 "IFSCDR,Input Filter Slow Clock Disable Register"
|
|
bitfld.long 0x0 31. "P31,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 30. "P30,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 29. "P29,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 28. "P28,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 26. "P26,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 25. "P25,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 24. "P24,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 22. "P22,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 21. "P21,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 20. "P20,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 18. "P18,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 17. "P17,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 16. "P16,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 14. "P14,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 13. "P13,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 12. "P12,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 10. "P10,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 9. "P9,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 8. "P8,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 6. "P6,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 5. "P5,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 4. "P4,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 2. "P2,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 1. "P1,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 0. "P0,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
line.long 0x4 "IFSCER,Input Filter Slow Clock Enable Register"
|
|
bitfld.long 0x4 31. "P31,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 30. "P30,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 29. "P29,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 28. "P28,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 26. "P26,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 25. "P25,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 24. "P24,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 22. "P22,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 21. "P21,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 20. "P20,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 18. "P18,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 17. "P17,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 16. "P16,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 14. "P14,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 13. "P13,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 12. "P12,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 10. "P10,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 9. "P9,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 8. "P8,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 6. "P6,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 5. "P5,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 4. "P4,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 2. "P2,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 1. "P1,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 0. "P0,Slow Clock Debouncing Filtering Select" "0,1"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "IFSCSR,Input Filter Slow Clock Status Register"
|
|
bitfld.long 0x0 31. "P31,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "DIV,Slow Clock Divider Selection for Debouncing"
|
|
wgroup.long 0x90++0x7
|
|
line.long 0x0 "PPDDR,Pad Pull-Down Disable Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Down Disable" "0,1"
|
|
line.long 0x4 "PPDER,Pad Pull-Down Enable Register"
|
|
bitfld.long 0x4 31. "P31,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Pull-Down Enable" "0,1"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "PPDSR,Pad Pull-Down Status Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Down Status" "0,1"
|
|
wgroup.long 0xA0++0x7
|
|
line.long 0x0 "OWER,Output Write Enable"
|
|
bitfld.long 0x0 31. "P31,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Write Enable" "0,1"
|
|
line.long 0x4 "OWDR,Output Write Disable"
|
|
bitfld.long 0x4 31. "P31,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Output Write Disable" "0,1"
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x0 "OWSR,Output Write Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Write Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Write Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Write Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Write Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Write Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Write Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Write Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Write Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Write Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Write Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Write Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Write Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Write Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Write Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Write Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Write Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Write Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Write Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Write Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Write Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Write Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Write Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Write Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Write Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Write Status" "0,1"
|
|
wgroup.long 0xB0++0x7
|
|
line.long 0x0 "AIMER,Additional Interrupt Modes Enable Register"
|
|
bitfld.long 0x0 31. "P31,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Additional Interrupt Modes Enable" "0,1"
|
|
line.long 0x4 "AIMDR,Additional Interrupt Modes Disable Register"
|
|
bitfld.long 0x4 31. "P31,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Additional Interrupt Modes Disable" "0,1"
|
|
rgroup.long 0xB8++0x3
|
|
line.long 0x0 "AIMMR,Additional Interrupt Modes Mask Register"
|
|
bitfld.long 0x0 31. "P31,IO Line Index" "0,1"
|
|
bitfld.long 0x0 30. "P30,IO Line Index" "0,1"
|
|
bitfld.long 0x0 29. "P29,IO Line Index" "0,1"
|
|
bitfld.long 0x0 28. "P28,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,IO Line Index" "0,1"
|
|
bitfld.long 0x0 26. "P26,IO Line Index" "0,1"
|
|
bitfld.long 0x0 25. "P25,IO Line Index" "0,1"
|
|
bitfld.long 0x0 24. "P24,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,IO Line Index" "0,1"
|
|
bitfld.long 0x0 22. "P22,IO Line Index" "0,1"
|
|
bitfld.long 0x0 21. "P21,IO Line Index" "0,1"
|
|
bitfld.long 0x0 20. "P20,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,IO Line Index" "0,1"
|
|
bitfld.long 0x0 18. "P18,IO Line Index" "0,1"
|
|
bitfld.long 0x0 17. "P17,IO Line Index" "0,1"
|
|
bitfld.long 0x0 16. "P16,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,IO Line Index" "0,1"
|
|
bitfld.long 0x0 14. "P14,IO Line Index" "0,1"
|
|
bitfld.long 0x0 13. "P13,IO Line Index" "0,1"
|
|
bitfld.long 0x0 12. "P12,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,IO Line Index" "0,1"
|
|
bitfld.long 0x0 10. "P10,IO Line Index" "0,1"
|
|
bitfld.long 0x0 9. "P9,IO Line Index" "0,1"
|
|
bitfld.long 0x0 8. "P8,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,IO Line Index" "0,1"
|
|
bitfld.long 0x0 6. "P6,IO Line Index" "0,1"
|
|
bitfld.long 0x0 5. "P5,IO Line Index" "0,1"
|
|
bitfld.long 0x0 4. "P4,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,IO Line Index" "0,1"
|
|
bitfld.long 0x0 2. "P2,IO Line Index" "0,1"
|
|
bitfld.long 0x0 1. "P1,IO Line Index" "0,1"
|
|
bitfld.long 0x0 0. "P0,IO Line Index" "0,1"
|
|
wgroup.long 0xC0++0x7
|
|
line.long 0x0 "ESR,Edge Select Register"
|
|
bitfld.long 0x0 31. "P31,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Edge Interrupt Selection" "0,1"
|
|
line.long 0x4 "LSR,Level Select Register"
|
|
bitfld.long 0x4 31. "P31,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 30. "P30,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 29. "P29,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 28. "P28,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 26. "P26,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 25. "P25,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 24. "P24,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 22. "P22,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 21. "P21,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 20. "P20,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 18. "P18,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 17. "P17,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 16. "P16,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 14. "P14,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 13. "P13,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 12. "P12,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 10. "P10,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 9. "P9,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 8. "P8,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 6. "P6,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 5. "P5,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 4. "P4,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 2. "P2,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 1. "P1,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 0. "P0,Level Interrupt Selection" "0,1"
|
|
rgroup.long 0xC8++0x3
|
|
line.long 0x0 "ELSR,Edge/Level Status Register"
|
|
bitfld.long 0x0 31. "P31,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Edge/Level Interrupt Source Selection" "0,1"
|
|
wgroup.long 0xD0++0x7
|
|
line.long 0x0 "FELLSR,Falling Edge/Low-Level Select Register"
|
|
bitfld.long 0x0 31. "P31,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
line.long 0x4 "REHLSR,Rising Edge/High-Level Select Register"
|
|
bitfld.long 0x4 31. "P31,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 30. "P30,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 29. "P29,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 28. "P28,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 26. "P26,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 25. "P25,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 24. "P24,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 22. "P22,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 21. "P21,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 20. "P20,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 18. "P18,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 17. "P17,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 16. "P16,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 14. "P14,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 13. "P13,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 12. "P12,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 10. "P10,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 9. "P9,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 8. "P8,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 6. "P6,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 5. "P5,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 4. "P4,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 2. "P2,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 1. "P1,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 0. "P0,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x0 "FRLHSR,Fall/Rise - Low/High Status Register"
|
|
bitfld.long 0x0 31. "P31,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Edge/Level Interrupt Source Selection" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x0 31. "SCHMITT31,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 30. "SCHMITT30,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 29. "SCHMITT29,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 28. "SCHMITT28,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SCHMITT27,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 26. "SCHMITT26,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 25. "SCHMITT25,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 24. "SCHMITT24,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SCHMITT23,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 22. "SCHMITT22,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 21. "SCHMITT21,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 20. "SCHMITT20,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SCHMITT19,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 18. "SCHMITT18,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 17. "SCHMITT17,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 16. "SCHMITT16,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "SCHMITT15,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 14. "SCHMITT14,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 13. "SCHMITT13,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 12. "SCHMITT12,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SCHMITT11,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 10. "SCHMITT10,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 9. "SCHMITT9,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 8. "SCHMITT8,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SCHMITT7,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 6. "SCHMITT6,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 5. "SCHMITT5,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 4. "SCHMITT4,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SCHMITT3,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 2. "SCHMITT2,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 1. "SCHMITT1,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 0. "SCHMITT0,Schmitt Trigger Control" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "SLEWR,I/O Slewrate Control Register"
|
|
bitfld.long 0x0 31. "SR31,Slewrate Control for IO line 31" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 30. "SR30,Slewrate Control for IO line 30" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 29. "SR29,Slewrate Control for IO line 29" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 28. "SR28,Slewrate Control for IO line 28" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 27. "SR27,Slewrate Control for IO line 27" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 26. "SR26,Slewrate Control for IO line 26" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 25. "SR25,Slewrate Control for IO line 25" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 24. "SR24,Slewrate Control for IO line 24" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 23. "SR23,Slewrate Control for IO line 23" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 22. "SR22,Slewrate Control for IO line 22" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 21. "SR21,Slewrate Control for IO line 21" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 20. "SR20,Slewrate Control for IO line 20" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 19. "SR19,Slewrate Control for IO line 19" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 18. "SR18,Slewrate Control for IO line 18" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 17. "SR17,Slewrate Control for IO line 17" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 16. "SR16,Slewrate Control for IO line 16" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 15. "SR15,Slewrate Control for IO line 15" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 14. "SR14,Slewrate Control for IO line 14" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 13. "SR13,Slewrate Control for IO line 13" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 12. "SR12,Slewrate Control for IO line 12" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 11. "SR11,Slewrate Control for IO line 11" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 10. "SR10,Slewrate Control for IO line 10" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 9. "SR9,Slewrate Control for IO line 9" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 8. "SR8,Slewrate Control for IO line 8" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 7. "SR7,Slewrate Control for IO line 7" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 6. "SR6,Slewrate Control for IO line 6" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 5. "SR5,Slewrate Control for IO line 5" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 4. "SR4,Slewrate Control for IO line 4" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 3. "SR3,Slewrate Control for IO line 3" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 2. "SR2,Slewrate Control for IO line 2" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 1. "SR1,Slewrate Control for IO line 1" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 0. "SR0,Slewrate Control for IO line 0" "0: No slewrate control.,1: Slewrate controlled."
|
|
group.long 0x118++0x3
|
|
line.long 0x0 "DRIVER,I/O Drive Register"
|
|
bitfld.long 0x0 31. "DR31,Drive of I/O Line 31" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 30. "DR30,Drive of I/O Line 30" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 29. "DR29,Drive of I/O Line 29" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 28. "DR28,Drive of I/O Line 28" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 27. "DR27,Drive of I/O Line 27" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 26. "DR26,Drive of I/O Line 26" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 25. "DR25,Drive of I/O Line 25" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 24. "DR24,Drive of I/O Line 24" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 23. "DR23,Drive of I/O Line 23" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 22. "DR22,Drive of I/O Line 22" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 21. "DR21,Drive of I/O Line 21" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 20. "DR20,Drive of I/O Line 20" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 19. "DR19,Drive of I/O Line 19" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 18. "DR18,Drive of I/O Line 18" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 17. "DR17,Drive of I/O Line 17" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 16. "DR16,Drive of I/O Line 16" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 15. "DR15,Drive of I/O Line 15" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 14. "DR14,Drive of I/O Line 14" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 13. "DR13,Drive of I/O Line 13" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 12. "DR12,Drive of I/O Line 12" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 11. "DR11,Drive of I/O Line 11" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 10. "DR10,Drive of I/O Line 10" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 9. "DR9,Drive of I/O Line 9" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 8. "DR8,Drive of I/O Line 8" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 7. "DR7,Drive of I/O Line 7" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 6. "DR6,Drive of I/O Line 6" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 5. "DR5,Drive of I/O Line 5" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 4. "DR4,Drive of I/O Line 4" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 3. "DR3,Drive of I/O Line 3" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 2. "DR2,Drive of I/O Line 2" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 1. "DR1,Drive of I/O Line 1" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 0. "DR0,Drive of I/O Line 0" "0: Lowest drive,1: Highest drive"
|
|
tree.end
|
|
tree "PIOC"
|
|
base ad:0xFFFFF800
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "PER,PIO Enable Register"
|
|
bitfld.long 0x0 31. "P31,PIO Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,PIO Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,PIO Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,PIO Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,PIO Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,PIO Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,PIO Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,PIO Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,PIO Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,PIO Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,PIO Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,PIO Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,PIO Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,PIO Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,PIO Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,PIO Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,PIO Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,PIO Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,PIO Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,PIO Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,PIO Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,PIO Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,PIO Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,PIO Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,PIO Enable" "0,1"
|
|
line.long 0x4 "PDR,PIO Disable Register"
|
|
bitfld.long 0x4 31. "P31,PIO Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,PIO Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,PIO Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,PIO Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,PIO Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,PIO Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,PIO Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,PIO Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,PIO Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,PIO Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,PIO Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,PIO Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,PIO Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,PIO Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,PIO Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,PIO Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,PIO Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,PIO Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,PIO Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,PIO Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,PIO Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,PIO Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,PIO Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,PIO Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,PIO Disable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "PSR,PIO Status Register"
|
|
bitfld.long 0x0 31. "P31,PIO Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,PIO Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,PIO Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,PIO Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,PIO Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,PIO Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,PIO Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,PIO Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,PIO Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,PIO Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,PIO Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,PIO Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,PIO Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,PIO Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,PIO Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,PIO Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,PIO Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,PIO Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,PIO Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,PIO Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,PIO Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,PIO Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,PIO Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,PIO Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,PIO Status" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "OER,Output Enable Register"
|
|
bitfld.long 0x0 31. "P31,Output Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Enable" "0,1"
|
|
line.long 0x4 "ODR,Output Disable Register"
|
|
bitfld.long 0x4 31. "P31,Output Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Output Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Output Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Output Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Output Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Output Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Output Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Output Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Output Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Output Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Output Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Output Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Output Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Output Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Output Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Output Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Output Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Output Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Output Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Output Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Output Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Output Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Output Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Output Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Output Disable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "OSR,Output Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Status" "0,1"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "IFER,Glitch Input Filter Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Filter Enable" "0,1"
|
|
line.long 0x4 "IFDR,Glitch Input Filter Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Filter Disable" "0,1"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "IFSR,Glitch Input Filter Status Register"
|
|
bitfld.long 0x0 31. "P31,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Filter Status" "0,1"
|
|
wgroup.long 0x30++0x7
|
|
line.long 0x0 "SODR,Set Output Data Register"
|
|
bitfld.long 0x0 31. "P31,Set Output Data" "0,1"
|
|
bitfld.long 0x0 30. "P30,Set Output Data" "0,1"
|
|
bitfld.long 0x0 29. "P29,Set Output Data" "0,1"
|
|
bitfld.long 0x0 28. "P28,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Set Output Data" "0,1"
|
|
bitfld.long 0x0 26. "P26,Set Output Data" "0,1"
|
|
bitfld.long 0x0 25. "P25,Set Output Data" "0,1"
|
|
bitfld.long 0x0 24. "P24,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Set Output Data" "0,1"
|
|
bitfld.long 0x0 22. "P22,Set Output Data" "0,1"
|
|
bitfld.long 0x0 21. "P21,Set Output Data" "0,1"
|
|
bitfld.long 0x0 20. "P20,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Set Output Data" "0,1"
|
|
bitfld.long 0x0 18. "P18,Set Output Data" "0,1"
|
|
bitfld.long 0x0 17. "P17,Set Output Data" "0,1"
|
|
bitfld.long 0x0 16. "P16,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Set Output Data" "0,1"
|
|
bitfld.long 0x0 14. "P14,Set Output Data" "0,1"
|
|
bitfld.long 0x0 13. "P13,Set Output Data" "0,1"
|
|
bitfld.long 0x0 12. "P12,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Set Output Data" "0,1"
|
|
bitfld.long 0x0 10. "P10,Set Output Data" "0,1"
|
|
bitfld.long 0x0 9. "P9,Set Output Data" "0,1"
|
|
bitfld.long 0x0 8. "P8,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Set Output Data" "0,1"
|
|
bitfld.long 0x0 6. "P6,Set Output Data" "0,1"
|
|
bitfld.long 0x0 5. "P5,Set Output Data" "0,1"
|
|
bitfld.long 0x0 4. "P4,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Set Output Data" "0,1"
|
|
bitfld.long 0x0 2. "P2,Set Output Data" "0,1"
|
|
bitfld.long 0x0 1. "P1,Set Output Data" "0,1"
|
|
bitfld.long 0x0 0. "P0,Set Output Data" "0,1"
|
|
line.long 0x4 "CODR,Clear Output Data Register"
|
|
bitfld.long 0x4 31. "P31,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 30. "P30,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 29. "P29,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 28. "P28,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 26. "P26,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 25. "P25,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 24. "P24,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 22. "P22,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 21. "P21,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 20. "P20,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 18. "P18,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 17. "P17,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 16. "P16,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 14. "P14,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 13. "P13,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 12. "P12,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 10. "P10,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 9. "P9,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 8. "P8,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 6. "P6,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 5. "P5,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 4. "P4,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 2. "P2,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 1. "P1,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 0. "P0,Clear Output Data" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "ODSR,Output Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PDSR,Pin Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
wgroup.long 0x40++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0,1"
|
|
rgroup.long 0x48++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0,1"
|
|
wgroup.long 0x50++0x7
|
|
line.long 0x0 "MDER,Multi-driver Enable Register"
|
|
bitfld.long 0x0 31. "P31,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Multi-drive Enable" "0,1"
|
|
line.long 0x4 "MDDR,Multi-driver Disable Register"
|
|
bitfld.long 0x4 31. "P31,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Multi-drive Disable" "0,1"
|
|
rgroup.long 0x58++0x3
|
|
line.long 0x0 "MDSR,Multi-driver Status Register"
|
|
bitfld.long 0x0 31. "P31,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Multi-drive Status" "0,1"
|
|
wgroup.long 0x60++0x7
|
|
line.long 0x0 "PUDR,Pull-Up Disable Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Up Disable" "0,1"
|
|
line.long 0x4 "PUER,Pull-Up Enable Register"
|
|
bitfld.long 0x4 31. "P31,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Pull-Up Enable" "0,1"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "PUSR,Pad Pull-Up Status Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Up Status" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "ABCDSR[$1],Peripheral ABCD Select Register"
|
|
bitfld.long 0x0 31. "P31,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 30. "P30,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 29. "P29,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 28. "P28,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 26. "P26,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 25. "P25,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 24. "P24,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 22. "P22,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 21. "P21,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 20. "P20,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 18. "P18,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 17. "P17,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 16. "P16,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 14. "P14,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 13. "P13,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 12. "P12,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 10. "P10,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 9. "P9,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 8. "P8,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 6. "P6,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 5. "P5,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 4. "P4,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 2. "P2,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 1. "P1,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 0. "P0,Peripheral Select" "0,1"
|
|
repeat.end
|
|
wgroup.long 0x80++0x7
|
|
line.long 0x0 "IFSCDR,Input Filter Slow Clock Disable Register"
|
|
bitfld.long 0x0 31. "P31,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 30. "P30,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 29. "P29,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 28. "P28,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 26. "P26,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 25. "P25,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 24. "P24,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 22. "P22,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 21. "P21,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 20. "P20,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 18. "P18,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 17. "P17,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 16. "P16,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 14. "P14,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 13. "P13,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 12. "P12,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 10. "P10,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 9. "P9,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 8. "P8,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 6. "P6,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 5. "P5,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 4. "P4,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 2. "P2,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 1. "P1,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 0. "P0,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
line.long 0x4 "IFSCER,Input Filter Slow Clock Enable Register"
|
|
bitfld.long 0x4 31. "P31,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 30. "P30,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 29. "P29,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 28. "P28,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 26. "P26,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 25. "P25,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 24. "P24,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 22. "P22,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 21. "P21,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 20. "P20,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 18. "P18,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 17. "P17,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 16. "P16,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 14. "P14,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 13. "P13,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 12. "P12,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 10. "P10,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 9. "P9,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 8. "P8,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 6. "P6,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 5. "P5,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 4. "P4,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 2. "P2,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 1. "P1,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 0. "P0,Slow Clock Debouncing Filtering Select" "0,1"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "IFSCSR,Input Filter Slow Clock Status Register"
|
|
bitfld.long 0x0 31. "P31,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "DIV,Slow Clock Divider Selection for Debouncing"
|
|
wgroup.long 0x90++0x7
|
|
line.long 0x0 "PPDDR,Pad Pull-Down Disable Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Down Disable" "0,1"
|
|
line.long 0x4 "PPDER,Pad Pull-Down Enable Register"
|
|
bitfld.long 0x4 31. "P31,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Pull-Down Enable" "0,1"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "PPDSR,Pad Pull-Down Status Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Down Status" "0,1"
|
|
wgroup.long 0xA0++0x7
|
|
line.long 0x0 "OWER,Output Write Enable"
|
|
bitfld.long 0x0 31. "P31,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Write Enable" "0,1"
|
|
line.long 0x4 "OWDR,Output Write Disable"
|
|
bitfld.long 0x4 31. "P31,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Output Write Disable" "0,1"
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x0 "OWSR,Output Write Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Write Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Write Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Write Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Write Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Write Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Write Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Write Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Write Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Write Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Write Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Write Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Write Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Write Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Write Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Write Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Write Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Write Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Write Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Write Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Write Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Write Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Write Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Write Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Write Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Write Status" "0,1"
|
|
wgroup.long 0xB0++0x7
|
|
line.long 0x0 "AIMER,Additional Interrupt Modes Enable Register"
|
|
bitfld.long 0x0 31. "P31,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Additional Interrupt Modes Enable" "0,1"
|
|
line.long 0x4 "AIMDR,Additional Interrupt Modes Disable Register"
|
|
bitfld.long 0x4 31. "P31,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Additional Interrupt Modes Disable" "0,1"
|
|
rgroup.long 0xB8++0x3
|
|
line.long 0x0 "AIMMR,Additional Interrupt Modes Mask Register"
|
|
bitfld.long 0x0 31. "P31,IO Line Index" "0,1"
|
|
bitfld.long 0x0 30. "P30,IO Line Index" "0,1"
|
|
bitfld.long 0x0 29. "P29,IO Line Index" "0,1"
|
|
bitfld.long 0x0 28. "P28,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,IO Line Index" "0,1"
|
|
bitfld.long 0x0 26. "P26,IO Line Index" "0,1"
|
|
bitfld.long 0x0 25. "P25,IO Line Index" "0,1"
|
|
bitfld.long 0x0 24. "P24,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,IO Line Index" "0,1"
|
|
bitfld.long 0x0 22. "P22,IO Line Index" "0,1"
|
|
bitfld.long 0x0 21. "P21,IO Line Index" "0,1"
|
|
bitfld.long 0x0 20. "P20,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,IO Line Index" "0,1"
|
|
bitfld.long 0x0 18. "P18,IO Line Index" "0,1"
|
|
bitfld.long 0x0 17. "P17,IO Line Index" "0,1"
|
|
bitfld.long 0x0 16. "P16,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,IO Line Index" "0,1"
|
|
bitfld.long 0x0 14. "P14,IO Line Index" "0,1"
|
|
bitfld.long 0x0 13. "P13,IO Line Index" "0,1"
|
|
bitfld.long 0x0 12. "P12,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,IO Line Index" "0,1"
|
|
bitfld.long 0x0 10. "P10,IO Line Index" "0,1"
|
|
bitfld.long 0x0 9. "P9,IO Line Index" "0,1"
|
|
bitfld.long 0x0 8. "P8,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,IO Line Index" "0,1"
|
|
bitfld.long 0x0 6. "P6,IO Line Index" "0,1"
|
|
bitfld.long 0x0 5. "P5,IO Line Index" "0,1"
|
|
bitfld.long 0x0 4. "P4,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,IO Line Index" "0,1"
|
|
bitfld.long 0x0 2. "P2,IO Line Index" "0,1"
|
|
bitfld.long 0x0 1. "P1,IO Line Index" "0,1"
|
|
bitfld.long 0x0 0. "P0,IO Line Index" "0,1"
|
|
wgroup.long 0xC0++0x7
|
|
line.long 0x0 "ESR,Edge Select Register"
|
|
bitfld.long 0x0 31. "P31,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Edge Interrupt Selection" "0,1"
|
|
line.long 0x4 "LSR,Level Select Register"
|
|
bitfld.long 0x4 31. "P31,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 30. "P30,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 29. "P29,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 28. "P28,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 26. "P26,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 25. "P25,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 24. "P24,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 22. "P22,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 21. "P21,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 20. "P20,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 18. "P18,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 17. "P17,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 16. "P16,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 14. "P14,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 13. "P13,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 12. "P12,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 10. "P10,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 9. "P9,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 8. "P8,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 6. "P6,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 5. "P5,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 4. "P4,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 2. "P2,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 1. "P1,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 0. "P0,Level Interrupt Selection" "0,1"
|
|
rgroup.long 0xC8++0x3
|
|
line.long 0x0 "ELSR,Edge/Level Status Register"
|
|
bitfld.long 0x0 31. "P31,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Edge/Level Interrupt Source Selection" "0,1"
|
|
wgroup.long 0xD0++0x7
|
|
line.long 0x0 "FELLSR,Falling Edge/Low-Level Select Register"
|
|
bitfld.long 0x0 31. "P31,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
line.long 0x4 "REHLSR,Rising Edge/High-Level Select Register"
|
|
bitfld.long 0x4 31. "P31,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 30. "P30,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 29. "P29,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 28. "P28,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 26. "P26,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 25. "P25,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 24. "P24,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 22. "P22,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 21. "P21,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 20. "P20,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 18. "P18,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 17. "P17,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 16. "P16,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 14. "P14,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 13. "P13,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 12. "P12,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 10. "P10,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 9. "P9,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 8. "P8,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 6. "P6,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 5. "P5,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 4. "P4,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 2. "P2,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 1. "P1,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 0. "P0,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x0 "FRLHSR,Fall/Rise - Low/High Status Register"
|
|
bitfld.long 0x0 31. "P31,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Edge/Level Interrupt Source Selection" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x0 31. "SCHMITT31,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 30. "SCHMITT30,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 29. "SCHMITT29,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 28. "SCHMITT28,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SCHMITT27,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 26. "SCHMITT26,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 25. "SCHMITT25,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 24. "SCHMITT24,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SCHMITT23,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 22. "SCHMITT22,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 21. "SCHMITT21,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 20. "SCHMITT20,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SCHMITT19,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 18. "SCHMITT18,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 17. "SCHMITT17,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 16. "SCHMITT16,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "SCHMITT15,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 14. "SCHMITT14,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 13. "SCHMITT13,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 12. "SCHMITT12,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SCHMITT11,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 10. "SCHMITT10,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 9. "SCHMITT9,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 8. "SCHMITT8,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SCHMITT7,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 6. "SCHMITT6,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 5. "SCHMITT5,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 4. "SCHMITT4,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SCHMITT3,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 2. "SCHMITT2,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 1. "SCHMITT1,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 0. "SCHMITT0,Schmitt Trigger Control" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "SLEWR,I/O Slewrate Control Register"
|
|
bitfld.long 0x0 31. "SR31,Slewrate Control for IO line 31" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 30. "SR30,Slewrate Control for IO line 30" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 29. "SR29,Slewrate Control for IO line 29" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 28. "SR28,Slewrate Control for IO line 28" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 27. "SR27,Slewrate Control for IO line 27" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 26. "SR26,Slewrate Control for IO line 26" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 25. "SR25,Slewrate Control for IO line 25" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 24. "SR24,Slewrate Control for IO line 24" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 23. "SR23,Slewrate Control for IO line 23" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 22. "SR22,Slewrate Control for IO line 22" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 21. "SR21,Slewrate Control for IO line 21" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 20. "SR20,Slewrate Control for IO line 20" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 19. "SR19,Slewrate Control for IO line 19" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 18. "SR18,Slewrate Control for IO line 18" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 17. "SR17,Slewrate Control for IO line 17" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 16. "SR16,Slewrate Control for IO line 16" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 15. "SR15,Slewrate Control for IO line 15" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 14. "SR14,Slewrate Control for IO line 14" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 13. "SR13,Slewrate Control for IO line 13" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 12. "SR12,Slewrate Control for IO line 12" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 11. "SR11,Slewrate Control for IO line 11" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 10. "SR10,Slewrate Control for IO line 10" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 9. "SR9,Slewrate Control for IO line 9" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 8. "SR8,Slewrate Control for IO line 8" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 7. "SR7,Slewrate Control for IO line 7" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 6. "SR6,Slewrate Control for IO line 6" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 5. "SR5,Slewrate Control for IO line 5" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 4. "SR4,Slewrate Control for IO line 4" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 3. "SR3,Slewrate Control for IO line 3" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 2. "SR2,Slewrate Control for IO line 2" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 1. "SR1,Slewrate Control for IO line 1" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 0. "SR0,Slewrate Control for IO line 0" "0: No slewrate control.,1: Slewrate controlled."
|
|
group.long 0x118++0x3
|
|
line.long 0x0 "DRIVER,I/O Drive Register"
|
|
bitfld.long 0x0 31. "DR31,Drive of I/O Line 31" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 30. "DR30,Drive of I/O Line 30" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 29. "DR29,Drive of I/O Line 29" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 28. "DR28,Drive of I/O Line 28" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 27. "DR27,Drive of I/O Line 27" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 26. "DR26,Drive of I/O Line 26" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 25. "DR25,Drive of I/O Line 25" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 24. "DR24,Drive of I/O Line 24" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 23. "DR23,Drive of I/O Line 23" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 22. "DR22,Drive of I/O Line 22" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 21. "DR21,Drive of I/O Line 21" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 20. "DR20,Drive of I/O Line 20" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 19. "DR19,Drive of I/O Line 19" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 18. "DR18,Drive of I/O Line 18" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 17. "DR17,Drive of I/O Line 17" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 16. "DR16,Drive of I/O Line 16" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 15. "DR15,Drive of I/O Line 15" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 14. "DR14,Drive of I/O Line 14" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 13. "DR13,Drive of I/O Line 13" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 12. "DR12,Drive of I/O Line 12" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 11. "DR11,Drive of I/O Line 11" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 10. "DR10,Drive of I/O Line 10" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 9. "DR9,Drive of I/O Line 9" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 8. "DR8,Drive of I/O Line 8" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 7. "DR7,Drive of I/O Line 7" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 6. "DR6,Drive of I/O Line 6" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 5. "DR5,Drive of I/O Line 5" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 4. "DR4,Drive of I/O Line 4" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 3. "DR3,Drive of I/O Line 3" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 2. "DR2,Drive of I/O Line 2" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 1. "DR1,Drive of I/O Line 1" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 0. "DR0,Drive of I/O Line 0" "0: Lowest drive,1: Highest drive"
|
|
tree.end
|
|
tree "PIOD"
|
|
base ad:0xFFFFFA00
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "PER,PIO Enable Register"
|
|
bitfld.long 0x0 31. "P31,PIO Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,PIO Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,PIO Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,PIO Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,PIO Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,PIO Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,PIO Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,PIO Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,PIO Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,PIO Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,PIO Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,PIO Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,PIO Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,PIO Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,PIO Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,PIO Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,PIO Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,PIO Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,PIO Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,PIO Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,PIO Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,PIO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,PIO Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,PIO Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,PIO Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,PIO Enable" "0,1"
|
|
line.long 0x4 "PDR,PIO Disable Register"
|
|
bitfld.long 0x4 31. "P31,PIO Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,PIO Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,PIO Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,PIO Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,PIO Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,PIO Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,PIO Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,PIO Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,PIO Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,PIO Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,PIO Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,PIO Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,PIO Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,PIO Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,PIO Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,PIO Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,PIO Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,PIO Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,PIO Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,PIO Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,PIO Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,PIO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,PIO Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,PIO Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,PIO Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,PIO Disable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "PSR,PIO Status Register"
|
|
bitfld.long 0x0 31. "P31,PIO Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,PIO Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,PIO Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,PIO Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,PIO Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,PIO Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,PIO Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,PIO Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,PIO Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,PIO Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,PIO Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,PIO Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,PIO Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,PIO Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,PIO Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,PIO Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,PIO Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,PIO Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,PIO Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,PIO Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,PIO Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,PIO Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,PIO Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,PIO Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,PIO Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,PIO Status" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "OER,Output Enable Register"
|
|
bitfld.long 0x0 31. "P31,Output Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Enable" "0,1"
|
|
line.long 0x4 "ODR,Output Disable Register"
|
|
bitfld.long 0x4 31. "P31,Output Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Output Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Output Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Output Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Output Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Output Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Output Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Output Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Output Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Output Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Output Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Output Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Output Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Output Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Output Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Output Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Output Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Output Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Output Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Output Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Output Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Output Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Output Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Output Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Output Disable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "OSR,Output Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Status" "0,1"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "IFER,Glitch Input Filter Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Filter Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Filter Enable" "0,1"
|
|
line.long 0x4 "IFDR,Glitch Input Filter Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Filter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Input Filter Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Filter Disable" "0,1"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "IFSR,Glitch Input Filter Status Register"
|
|
bitfld.long 0x0 31. "P31,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Filter Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Filter Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Filter Status" "0,1"
|
|
wgroup.long 0x30++0x7
|
|
line.long 0x0 "SODR,Set Output Data Register"
|
|
bitfld.long 0x0 31. "P31,Set Output Data" "0,1"
|
|
bitfld.long 0x0 30. "P30,Set Output Data" "0,1"
|
|
bitfld.long 0x0 29. "P29,Set Output Data" "0,1"
|
|
bitfld.long 0x0 28. "P28,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Set Output Data" "0,1"
|
|
bitfld.long 0x0 26. "P26,Set Output Data" "0,1"
|
|
bitfld.long 0x0 25. "P25,Set Output Data" "0,1"
|
|
bitfld.long 0x0 24. "P24,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Set Output Data" "0,1"
|
|
bitfld.long 0x0 22. "P22,Set Output Data" "0,1"
|
|
bitfld.long 0x0 21. "P21,Set Output Data" "0,1"
|
|
bitfld.long 0x0 20. "P20,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Set Output Data" "0,1"
|
|
bitfld.long 0x0 18. "P18,Set Output Data" "0,1"
|
|
bitfld.long 0x0 17. "P17,Set Output Data" "0,1"
|
|
bitfld.long 0x0 16. "P16,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Set Output Data" "0,1"
|
|
bitfld.long 0x0 14. "P14,Set Output Data" "0,1"
|
|
bitfld.long 0x0 13. "P13,Set Output Data" "0,1"
|
|
bitfld.long 0x0 12. "P12,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Set Output Data" "0,1"
|
|
bitfld.long 0x0 10. "P10,Set Output Data" "0,1"
|
|
bitfld.long 0x0 9. "P9,Set Output Data" "0,1"
|
|
bitfld.long 0x0 8. "P8,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Set Output Data" "0,1"
|
|
bitfld.long 0x0 6. "P6,Set Output Data" "0,1"
|
|
bitfld.long 0x0 5. "P5,Set Output Data" "0,1"
|
|
bitfld.long 0x0 4. "P4,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Set Output Data" "0,1"
|
|
bitfld.long 0x0 2. "P2,Set Output Data" "0,1"
|
|
bitfld.long 0x0 1. "P1,Set Output Data" "0,1"
|
|
bitfld.long 0x0 0. "P0,Set Output Data" "0,1"
|
|
line.long 0x4 "CODR,Clear Output Data Register"
|
|
bitfld.long 0x4 31. "P31,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 30. "P30,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 29. "P29,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 28. "P28,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 26. "P26,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 25. "P25,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 24. "P24,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 22. "P22,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 21. "P21,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 20. "P20,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 18. "P18,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 17. "P17,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 16. "P16,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 14. "P14,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 13. "P13,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 12. "P12,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 10. "P10,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 9. "P9,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 8. "P8,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 6. "P6,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 5. "P5,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 4. "P4,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 2. "P2,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 1. "P1,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 0. "P0,Clear Output Data" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "ODSR,Output Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "PDSR,Pin Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
wgroup.long 0x40++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0,1"
|
|
rgroup.long 0x48++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0,1"
|
|
wgroup.long 0x50++0x7
|
|
line.long 0x0 "MDER,Multi-driver Enable Register"
|
|
bitfld.long 0x0 31. "P31,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Multi-drive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Multi-drive Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Multi-drive Enable" "0,1"
|
|
line.long 0x4 "MDDR,Multi-driver Disable Register"
|
|
bitfld.long 0x4 31. "P31,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Multi-drive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Multi-drive Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Multi-drive Disable" "0,1"
|
|
rgroup.long 0x58++0x3
|
|
line.long 0x0 "MDSR,Multi-driver Status Register"
|
|
bitfld.long 0x0 31. "P31,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Multi-drive Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Multi-drive Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Multi-drive Status" "0,1"
|
|
wgroup.long 0x60++0x7
|
|
line.long 0x0 "PUDR,Pull-Up Disable Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Up Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Up Disable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Up Disable" "0,1"
|
|
line.long 0x4 "PUER,Pull-Up Enable Register"
|
|
bitfld.long 0x4 31. "P31,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Pull-Up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Pull-Up Enable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Pull-Up Enable" "0,1"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "PUSR,Pad Pull-Up Status Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Up Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Up Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Up Status" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "ABCDSR[$1],Peripheral ABCD Select Register"
|
|
bitfld.long 0x0 31. "P31,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 30. "P30,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 29. "P29,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 28. "P28,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 26. "P26,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 25. "P25,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 24. "P24,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 22. "P22,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 21. "P21,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 20. "P20,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 18. "P18,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 17. "P17,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 16. "P16,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 14. "P14,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 13. "P13,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 12. "P12,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 10. "P10,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 9. "P9,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 8. "P8,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 6. "P6,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 5. "P5,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 4. "P4,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 2. "P2,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 1. "P1,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 0. "P0,Peripheral Select" "0,1"
|
|
repeat.end
|
|
wgroup.long 0x80++0x7
|
|
line.long 0x0 "IFSCDR,Input Filter Slow Clock Disable Register"
|
|
bitfld.long 0x0 31. "P31,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 30. "P30,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 29. "P29,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 28. "P28,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 26. "P26,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 25. "P25,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 24. "P24,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 22. "P22,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 21. "P21,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 20. "P20,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 18. "P18,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 17. "P17,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 16. "P16,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 14. "P14,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 13. "P13,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 12. "P12,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 10. "P10,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 9. "P9,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 8. "P8,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 6. "P6,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 5. "P5,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 4. "P4,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 2. "P2,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 1. "P1,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
bitfld.long 0x0 0. "P0,Peripheral Clock Glitch Filtering Select" "0,1"
|
|
line.long 0x4 "IFSCER,Input Filter Slow Clock Enable Register"
|
|
bitfld.long 0x4 31. "P31,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 30. "P30,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 29. "P29,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 28. "P28,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 26. "P26,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 25. "P25,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 24. "P24,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 22. "P22,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 21. "P21,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 20. "P20,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 18. "P18,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 17. "P17,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 16. "P16,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 14. "P14,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 13. "P13,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 12. "P12,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 10. "P10,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 9. "P9,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 8. "P8,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 6. "P6,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 5. "P5,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 4. "P4,Slow Clock Debouncing Filtering Select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 2. "P2,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 1. "P1,Slow Clock Debouncing Filtering Select" "0,1"
|
|
bitfld.long 0x4 0. "P0,Slow Clock Debouncing Filtering Select" "0,1"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "IFSCSR,Input Filter Slow Clock Status Register"
|
|
bitfld.long 0x0 31. "P31,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Glitch or Debouncing Filter Selection Status" "0,1"
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "SCDR,Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "DIV,Slow Clock Divider Selection for Debouncing"
|
|
wgroup.long 0x90++0x7
|
|
line.long 0x0 "PPDDR,Pad Pull-Down Disable Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Down Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Down Disable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Down Disable" "0,1"
|
|
line.long 0x4 "PPDER,Pad Pull-Down Enable Register"
|
|
bitfld.long 0x4 31. "P31,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Pull-Down Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Pull-Down Enable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Pull-Down Enable" "0,1"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "PPDSR,Pad Pull-Down Status Register"
|
|
bitfld.long 0x0 31. "P31,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Pull-Down Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Pull-Down Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Pull-Down Status" "0,1"
|
|
wgroup.long 0xA0++0x7
|
|
line.long 0x0 "OWER,Output Write Enable"
|
|
bitfld.long 0x0 31. "P31,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Write Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Write Enable" "0,1"
|
|
line.long 0x4 "OWDR,Output Write Disable"
|
|
bitfld.long 0x4 31. "P31,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Output Write Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Output Write Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Output Write Disable" "0,1"
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x0 "OWSR,Output Write Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Write Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Write Status" "0,1"
|
|
bitfld.long 0x0 29. "P29,Output Write Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Write Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Write Status" "0,1"
|
|
bitfld.long 0x0 25. "P25,Output Write Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Write Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Write Status" "0,1"
|
|
bitfld.long 0x0 21. "P21,Output Write Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Write Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Write Status" "0,1"
|
|
bitfld.long 0x0 17. "P17,Output Write Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Write Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Write Status" "0,1"
|
|
bitfld.long 0x0 13. "P13,Output Write Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Write Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Write Status" "0,1"
|
|
bitfld.long 0x0 9. "P9,Output Write Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Write Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Write Status" "0,1"
|
|
bitfld.long 0x0 5. "P5,Output Write Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Write Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Write Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Write Status" "0,1"
|
|
bitfld.long 0x0 1. "P1,Output Write Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Write Status" "0,1"
|
|
wgroup.long 0xB0++0x7
|
|
line.long 0x0 "AIMER,Additional Interrupt Modes Enable Register"
|
|
bitfld.long 0x0 31. "P31,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 29. "P29,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 25. "P25,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 21. "P21,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 17. "P17,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 13. "P13,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 9. "P9,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 5. "P5,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Additional Interrupt Modes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 1. "P1,Additional Interrupt Modes Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Additional Interrupt Modes Enable" "0,1"
|
|
line.long 0x4 "AIMDR,Additional Interrupt Modes Disable Register"
|
|
bitfld.long 0x4 31. "P31,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 29. "P29,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 25. "P25,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 21. "P21,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 17. "P17,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 13. "P13,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 9. "P9,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 5. "P5,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Additional Interrupt Modes Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 1. "P1,Additional Interrupt Modes Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Additional Interrupt Modes Disable" "0,1"
|
|
rgroup.long 0xB8++0x3
|
|
line.long 0x0 "AIMMR,Additional Interrupt Modes Mask Register"
|
|
bitfld.long 0x0 31. "P31,IO Line Index" "0,1"
|
|
bitfld.long 0x0 30. "P30,IO Line Index" "0,1"
|
|
bitfld.long 0x0 29. "P29,IO Line Index" "0,1"
|
|
bitfld.long 0x0 28. "P28,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,IO Line Index" "0,1"
|
|
bitfld.long 0x0 26. "P26,IO Line Index" "0,1"
|
|
bitfld.long 0x0 25. "P25,IO Line Index" "0,1"
|
|
bitfld.long 0x0 24. "P24,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,IO Line Index" "0,1"
|
|
bitfld.long 0x0 22. "P22,IO Line Index" "0,1"
|
|
bitfld.long 0x0 21. "P21,IO Line Index" "0,1"
|
|
bitfld.long 0x0 20. "P20,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,IO Line Index" "0,1"
|
|
bitfld.long 0x0 18. "P18,IO Line Index" "0,1"
|
|
bitfld.long 0x0 17. "P17,IO Line Index" "0,1"
|
|
bitfld.long 0x0 16. "P16,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,IO Line Index" "0,1"
|
|
bitfld.long 0x0 14. "P14,IO Line Index" "0,1"
|
|
bitfld.long 0x0 13. "P13,IO Line Index" "0,1"
|
|
bitfld.long 0x0 12. "P12,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,IO Line Index" "0,1"
|
|
bitfld.long 0x0 10. "P10,IO Line Index" "0,1"
|
|
bitfld.long 0x0 9. "P9,IO Line Index" "0,1"
|
|
bitfld.long 0x0 8. "P8,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,IO Line Index" "0,1"
|
|
bitfld.long 0x0 6. "P6,IO Line Index" "0,1"
|
|
bitfld.long 0x0 5. "P5,IO Line Index" "0,1"
|
|
bitfld.long 0x0 4. "P4,IO Line Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,IO Line Index" "0,1"
|
|
bitfld.long 0x0 2. "P2,IO Line Index" "0,1"
|
|
bitfld.long 0x0 1. "P1,IO Line Index" "0,1"
|
|
bitfld.long 0x0 0. "P0,IO Line Index" "0,1"
|
|
wgroup.long 0xC0++0x7
|
|
line.long 0x0 "ESR,Edge Select Register"
|
|
bitfld.long 0x0 31. "P31,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Edge Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Edge Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Edge Interrupt Selection" "0,1"
|
|
line.long 0x4 "LSR,Level Select Register"
|
|
bitfld.long 0x4 31. "P31,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 30. "P30,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 29. "P29,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 28. "P28,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 26. "P26,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 25. "P25,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 24. "P24,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 22. "P22,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 21. "P21,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 20. "P20,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 18. "P18,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 17. "P17,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 16. "P16,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 14. "P14,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 13. "P13,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 12. "P12,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 10. "P10,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 9. "P9,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 8. "P8,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 6. "P6,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 5. "P5,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 4. "P4,Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 2. "P2,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 1. "P1,Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 0. "P0,Level Interrupt Selection" "0,1"
|
|
rgroup.long 0xC8++0x3
|
|
line.long 0x0 "ELSR,Edge/Level Status Register"
|
|
bitfld.long 0x0 31. "P31,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Edge/Level Interrupt Source Selection" "0,1"
|
|
wgroup.long 0xD0++0x7
|
|
line.long 0x0 "FELLSR,Falling Edge/Low-Level Select Register"
|
|
bitfld.long 0x0 31. "P31,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Falling Edge/Low-Level Interrupt Selection" "0,1"
|
|
line.long 0x4 "REHLSR,Rising Edge/High-Level Select Register"
|
|
bitfld.long 0x4 31. "P31,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 30. "P30,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 29. "P29,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 28. "P28,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 26. "P26,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 25. "P25,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 24. "P24,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 22. "P22,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 21. "P21,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 20. "P20,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 18. "P18,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 17. "P17,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 16. "P16,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 14. "P14,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 13. "P13,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 12. "P12,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 10. "P10,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 9. "P9,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 8. "P8,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 6. "P6,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 5. "P5,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 4. "P4,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 2. "P2,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 1. "P1,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
bitfld.long 0x4 0. "P0,Rising Edge/High-Level Interrupt Selection" "0,1"
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x0 "FRLHSR,Fall/Rise - Low/High Status Register"
|
|
bitfld.long 0x0 31. "P31,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 30. "P30,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 29. "P29,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 28. "P28,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 26. "P26,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 25. "P25,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 24. "P24,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 22. "P22,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 21. "P21,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 20. "P20,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 18. "P18,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 17. "P17,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 16. "P16,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 14. "P14,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 13. "P13,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 12. "P12,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 10. "P10,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 9. "P9,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 8. "P8,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 6. "P6,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 5. "P5,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 4. "P4,Edge/Level Interrupt Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 2. "P2,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 1. "P1,Edge/Level Interrupt Source Selection" "0,1"
|
|
bitfld.long 0x0 0. "P0,Edge/Level Interrupt Source Selection" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "SCHMITT,Schmitt Trigger Register"
|
|
bitfld.long 0x0 31. "SCHMITT31,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 30. "SCHMITT30,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 29. "SCHMITT29,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 28. "SCHMITT28,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SCHMITT27,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 26. "SCHMITT26,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 25. "SCHMITT25,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 24. "SCHMITT24,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SCHMITT23,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 22. "SCHMITT22,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 21. "SCHMITT21,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 20. "SCHMITT20,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SCHMITT19,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 18. "SCHMITT18,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 17. "SCHMITT17,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 16. "SCHMITT16,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "SCHMITT15,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 14. "SCHMITT14,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 13. "SCHMITT13,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 12. "SCHMITT12,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SCHMITT11,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 10. "SCHMITT10,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 9. "SCHMITT9,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 8. "SCHMITT8,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SCHMITT7,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 6. "SCHMITT6,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 5. "SCHMITT5,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 4. "SCHMITT4,Schmitt Trigger Control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SCHMITT3,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 2. "SCHMITT2,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 1. "SCHMITT1,Schmitt Trigger Control" "0,1"
|
|
bitfld.long 0x0 0. "SCHMITT0,Schmitt Trigger Control" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "SLEWR,I/O Slewrate Control Register"
|
|
bitfld.long 0x0 31. "SR31,Slewrate Control for IO line 31" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 30. "SR30,Slewrate Control for IO line 30" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 29. "SR29,Slewrate Control for IO line 29" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 28. "SR28,Slewrate Control for IO line 28" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 27. "SR27,Slewrate Control for IO line 27" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 26. "SR26,Slewrate Control for IO line 26" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 25. "SR25,Slewrate Control for IO line 25" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 24. "SR24,Slewrate Control for IO line 24" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 23. "SR23,Slewrate Control for IO line 23" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 22. "SR22,Slewrate Control for IO line 22" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 21. "SR21,Slewrate Control for IO line 21" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 20. "SR20,Slewrate Control for IO line 20" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 19. "SR19,Slewrate Control for IO line 19" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 18. "SR18,Slewrate Control for IO line 18" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 17. "SR17,Slewrate Control for IO line 17" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 16. "SR16,Slewrate Control for IO line 16" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 15. "SR15,Slewrate Control for IO line 15" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 14. "SR14,Slewrate Control for IO line 14" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 13. "SR13,Slewrate Control for IO line 13" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 12. "SR12,Slewrate Control for IO line 12" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 11. "SR11,Slewrate Control for IO line 11" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 10. "SR10,Slewrate Control for IO line 10" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 9. "SR9,Slewrate Control for IO line 9" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 8. "SR8,Slewrate Control for IO line 8" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 7. "SR7,Slewrate Control for IO line 7" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 6. "SR6,Slewrate Control for IO line 6" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 5. "SR5,Slewrate Control for IO line 5" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 4. "SR4,Slewrate Control for IO line 4" "0: No slewrate control.,1: Slewrate controlled."
|
|
newline
|
|
bitfld.long 0x0 3. "SR3,Slewrate Control for IO line 3" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 2. "SR2,Slewrate Control for IO line 2" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 1. "SR1,Slewrate Control for IO line 1" "0: No slewrate control.,1: Slewrate controlled."
|
|
bitfld.long 0x0 0. "SR0,Slewrate Control for IO line 0" "0: No slewrate control.,1: Slewrate controlled."
|
|
group.long 0x118++0x3
|
|
line.long 0x0 "DRIVER,I/O Drive Register"
|
|
bitfld.long 0x0 31. "DR31,Drive of I/O Line 31" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 30. "DR30,Drive of I/O Line 30" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 29. "DR29,Drive of I/O Line 29" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 28. "DR28,Drive of I/O Line 28" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 27. "DR27,Drive of I/O Line 27" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 26. "DR26,Drive of I/O Line 26" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 25. "DR25,Drive of I/O Line 25" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 24. "DR24,Drive of I/O Line 24" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 23. "DR23,Drive of I/O Line 23" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 22. "DR22,Drive of I/O Line 22" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 21. "DR21,Drive of I/O Line 21" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 20. "DR20,Drive of I/O Line 20" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 19. "DR19,Drive of I/O Line 19" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 18. "DR18,Drive of I/O Line 18" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 17. "DR17,Drive of I/O Line 17" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 16. "DR16,Drive of I/O Line 16" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 15. "DR15,Drive of I/O Line 15" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 14. "DR14,Drive of I/O Line 14" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 13. "DR13,Drive of I/O Line 13" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 12. "DR12,Drive of I/O Line 12" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 11. "DR11,Drive of I/O Line 11" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 10. "DR10,Drive of I/O Line 10" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 9. "DR9,Drive of I/O Line 9" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 8. "DR8,Drive of I/O Line 8" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 7. "DR7,Drive of I/O Line 7" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 6. "DR6,Drive of I/O Line 6" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 5. "DR5,Drive of I/O Line 5" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 4. "DR4,Drive of I/O Line 4" "0: Lowest drive,1: Highest drive"
|
|
newline
|
|
bitfld.long 0x0 3. "DR3,Drive of I/O Line 3" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 2. "DR2,Drive of I/O Line 2" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 1. "DR1,Drive of I/O Line 1" "0: Lowest drive,1: Highest drive"
|
|
bitfld.long 0x0 0. "DR0,Drive of I/O Line 0" "0: Lowest drive,1: Highest drive"
|
|
tree.end
|
|
tree.end
|
|
tree "PIT (Periodic Interval Timer)"
|
|
base ad:0xFFFFFE40
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 25. "PITIEN,Periodic Interval Timer Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "PITEN,Period Interval Timer Enabled" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "PIV,Periodic Interval Value"
|
|
rgroup.long 0x4++0xB
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 0. "PITS,Periodic Interval Timer Status" "0,1"
|
|
line.long 0x4 "PIVR,Periodic Interval Value Register"
|
|
hexmask.long.word 0x4 20.--31. 1. "PICNT,Periodic Interval Counter"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "CPIV,Current Periodic Interval Value"
|
|
line.long 0x8 "PIIR,Periodic Interval Image Register"
|
|
hexmask.long.word 0x8 20.--31. 1. "PICNT,Periodic Interval Counter"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "CPIV,Current Periodic Interval Value"
|
|
tree.end
|
|
tree "PIT64B (Periodic Interval Timer 64-bit)"
|
|
base ad:0xF0028000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 0. "START,Start Timer" "0,1"
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRESCALER,Prescaler Period"
|
|
bitfld.long 0x0 4. "SMOD,Start Mode" "0,1"
|
|
bitfld.long 0x0 3. "SGCLK,Generic Clock Selection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CONT,Continuous Mode" "0,1"
|
|
line.long 0x4 "LSBPR,LSB Period Register"
|
|
hexmask.long 0x4 0.--31. 1. "LSBPERIOD,32 LSB of the Timer Period"
|
|
line.long 0x8 "MSBPR,MSB Period Register"
|
|
hexmask.long 0x8 0.--31. 1. "MSBPERIOD,32 MSB of the Timer Period"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 4. "SECE,Safety and/or Security Report Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0xF
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 4. "SECE,Safety/Security Report (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Status Flag (cleared on read)" "0,1"
|
|
line.long 0x8 "TLSBR,Timer LSB Current Value Register"
|
|
hexmask.long 0x8 0.--31. 1. "LSBTIMER,Current 32 LSB of the Timer"
|
|
line.long 0xC "TMSBR,Timer MSB Current Value Register"
|
|
hexmask.long 0xC 0.--31. 1. "MSBTIMER,Current 32 MSB of the Timer"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: A write access is performed into PIT64B_MR.."
|
|
bitfld.long 0x0 24.--25. "SWETYP,Software Error Type (cleared on read)" "0: A write-only register has been read (warning).,1: A write access has been performed on a read-only..,2: Access to an undefined address (warning).,3: A write access is performed into PIT64B_MR.."
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0xFFFFFC00
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "SCER,System Clock Enable Register"
|
|
bitfld.long 0x0 19. "QSPICLK,QSPI 2x Clock Enable" "0,1"
|
|
bitfld.long 0x0 9. "PCK1,Programmable Clock 1 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PCK0,Programmable Clock 0 Output Enable" "0,1"
|
|
bitfld.long 0x0 6. "UHP,USB Host OHCI Clocks Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DDRCK,MPDDRC/SDRAMC Clock Enable" "0,1"
|
|
line.long 0x4 "SCDR,System Clock Disable Register"
|
|
bitfld.long 0x4 19. "QSPICLK,QSPI 2x Clock Disable" "0,1"
|
|
bitfld.long 0x4 9. "PCK1,Programmable Clock 1 Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "PCK0,Programmable Clock 0 Output Disable" "0,1"
|
|
bitfld.long 0x4 6. "UHP,USB Host OHCI Clocks Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DDRCK,MPDDRC/SDRAMC Clock Disable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SCSR,System Clock Status Register"
|
|
bitfld.long 0x0 19. "QSPICLK,QSPI 2x Clock Status" "0,1"
|
|
bitfld.long 0x0 9. "PCK1,Programmable Clock 1 Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PCK0,Programmable Clock 0 Output Status" "0,1"
|
|
bitfld.long 0x0 6. "UHP,USB Host OHCI Clocks Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DDRCK,MPDDRC/SDRAMC Clock Status" "0,1"
|
|
group.long 0xC++0x1F
|
|
line.long 0x0 "PLL_CTRL0,PLL Control Register 0"
|
|
bitfld.long 0x0 31. "ENLOCK,Enable PLL Lock" "0,1"
|
|
bitfld.long 0x0 29. "ENPLLCK,Enable PLL Clock for PMC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "ENPLL,Enable PLL" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIVPMC,Divider for PMC"
|
|
line.long 0x4 "PLL_CTRL1,PLL Control Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "MUL,Multiplier Factor Value"
|
|
hexmask.long.tbyte 0x4 0.--21. 1. "FRACR,Fractional Loop Divider Setting"
|
|
line.long 0x8 "PLL_SSR,PLL Spread Spectrum Register"
|
|
bitfld.long 0x8 28. "ENSPREAD,Spread Spectrum Enable" "0,1"
|
|
hexmask.long.byte 0x8 16.--23. 1. "NSTEP,Spread Spectrum Number of Steps"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "STEP,Spread Spectrum Step Size"
|
|
line.long 0xC "PLL_ACR,PLL Analog Control Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "LOOP_FILTER,LOOP Filter Selection"
|
|
bitfld.long 0xC 16.--18. "LOCK_THR,PLL Lock Threshold Value Selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 13. "UTMIBG,UPLL Bandgap Control" "0,1"
|
|
bitfld.long 0xC 12. "UTMIVR,UPLL Voltage Regulator Control" "0,1"
|
|
newline
|
|
hexmask.long.word 0xC 0.--11. 1. "CONTROL,PLL CONTROL Value Selection"
|
|
line.long 0x10 "PLL_UPDT,PLL Update Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. "STUPTIM,Startup Time"
|
|
bitfld.long 0x10 8. "UPDATE,PLL Setting Update (write-only)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "ID,PLL ID" "0,1"
|
|
line.long 0x14 "CKGR_MOR,Main Oscillator Register"
|
|
bitfld.long 0x14 30. "AUTOCPUSW,Automatic Processor Clock Source Switching" "0,1"
|
|
bitfld.long 0x14 29. "AUTOMAINSW,Automatic Main Clock Source Switching" "0,1"
|
|
newline
|
|
bitfld.long 0x14 26. "XT32KFME,32.768 kHz Crystal Oscillator Frequency Monitoring Enable" "0,1"
|
|
bitfld.long 0x14 25. "CFDEN,Clock Failure Detector Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 24. "MOSCSEL,Main Clock Oscillator Selection" "0: The Main RC oscillator is selected.,1: The Main crystal oscillator is selected."
|
|
hexmask.long.byte 0x14 16.--23. 1. "KEY,Write Access Password"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "MOSCXTST,Main Crystal Oscillator Startup Time"
|
|
bitfld.long 0x14 3. "MOSCRCEN,Main RC Oscillator Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "ULP1,ULP Mode 1 Command (write-only)" "0,1"
|
|
bitfld.long 0x14 0. "MOSCXTEN,Main Crystal Oscillator Enable" "0,1"
|
|
line.long 0x18 "CKGR_MCFR,Main Clock Frequency Register"
|
|
bitfld.long 0x18 24. "CCSS,Counter Clock Source Selection" "0,1"
|
|
bitfld.long 0x18 20. "RCMEAS,RC Oscillator Frequency Measure (write-only)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 16. "MAINFRDY,Main Clock Frequency Measure Ready" "0,1"
|
|
hexmask.long.word 0x18 0.--15. 1. "MAINF,Main Clock Frequency"
|
|
line.long 0x1C "CPU_CKR,CPU Clock Register"
|
|
bitfld.long 0x1C 8.--10. "MDIV,MCK Division" "0: MCK is FCLK divided by 1. MCK_2X is FCLK divided..,1: MCK is FCLK divided by 2. MCK_2X is FCLK divided..,2: MCK is FCLK divided by 4. MCK_2X is FCLK divided..,3: MCK is FCLK divided by 3. MCK_2X is FCLK divided..,?,?,?,?"
|
|
bitfld.long 0x1C 4.--6. "PRES,Processor Clock Prescaler" "0: Selected clock,1: Selected clock divided by 2,2: Selected clock divided by 4,3: Selected clock divided by 8,4: Selected clock divided by 16,5: Selected clock divided by 32,6: Selected clock divided by 64,7: Selected clock divided by 3"
|
|
newline
|
|
bitfld.long 0x1C 0.--1. "CSS,MCK Source Selection" "0: MD_SLCK is selected,1: MAINCK is selected,2: PLLACK is selected,3: UPLL is selected"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "USB,USB Clock Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "USBDIV,Divider for USB OHCI Clock"
|
|
bitfld.long 0x0 0.--1. "USBS,USB OHCI/EHCI Input Clock Selection" "0: USB Clock Input is PLLACK.,1: USB Clock Input is UPLLCK.,2: USB Clock Input is MAINXTALCK.,?"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "PCK[$1],Programmable Clock Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "PRES,Programmable Clock Prescaler"
|
|
hexmask.long.byte 0x0 0.--4. 1. "CSS,Programmable Clock Source Selection"
|
|
repeat.end
|
|
wgroup.long 0x60++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 25. "PLL_INT,PLL Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 23. "MCKMON,Master Clock Clock Monitor Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "XT32KERR,32.768 kHz Crystal Oscillator Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "CFDEV,Clock Failure Detector Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MOSCRCS,Main RC Oscillator Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MCKRDY,Master Clock Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "MOSCXTS,Main Crystal Oscillator Status Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 25. "PLL_INT,PLL Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 23. "MCKMON,Master Clock Clock Monitor Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "XT32KERR,32.768 kHz Crystal Oscillator Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "CFDEV,Clock Failure Detector Event Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MOSCRCS,Main RC Status Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MCKRDY,Master Clock Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "MOSCXTS,Main Crystal Oscillator Status Interrupt Disable" "0,1"
|
|
rgroup.long 0x68++0x7
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 25. "PLL_INT,PLL Interrupt Status" "0,1"
|
|
bitfld.long 0x0 24. "GCLKRDY,GCLK Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MCKMON,Master Clock Clock Monitor Error" "0,1"
|
|
bitfld.long 0x0 21. "XT32KERR,Slow Crystal Oscillator Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "FOS,Clock Failure Detector Fault Output Status" "0,1"
|
|
bitfld.long 0x0 19. "CFDS,Clock Failure Detector Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CFDEV,Clock Failure Detector Event" "0,1"
|
|
bitfld.long 0x0 17. "MOSCRCS,Main RC Oscillator Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MOSCSELS,Main Clock Source Oscillator Selection Status" "0,1"
|
|
bitfld.long 0x0 9. "PCKRDY1,Programmable Clock Ready Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PCKRDY0,Programmable Clock Ready Status" "0,1"
|
|
bitfld.long 0x0 3. "MCKRDY,Master Clock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MOSCXTS,Main Crystal Oscillator Status" "0,1"
|
|
line.long 0x4 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x4 25. "PLL_INT,PLL Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 23. "MCKMON,Master Clock Monitor Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "XT32KERR,32.768 kHz Crystal Oscillator Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 18. "CFDEV,Clock Failure Detector Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MOSCRCS,Main RC Status Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MCKRDY,Master Clock Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 0. "MOSCXTS,Main Crystal Oscillator Status Interrupt Mask" "0,1"
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "FSMR,Fast Startup Mode Register"
|
|
bitfld.long 0x0 25. "WLAN1,Wakeup on LAN[x]" "0,1"
|
|
bitfld.long 0x0 24. "WLAN0,Wakeup on LAN[x]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "USBAL,USB Alarm Enable" "0,1"
|
|
bitfld.long 0x0 17. "RTCAL,RTC Alarm Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RTTAL,RTT Alarm Enable" "0,1"
|
|
line.long 0x4 "WCR,Wakeup Control Register"
|
|
bitfld.long 0x4 24. "CMD,Command" "0,1"
|
|
bitfld.long 0x4 17. "WIP,Wakeup Input Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "EN,Wakeup Input Enable" "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "WKPIONB,Wakeup Input Number"
|
|
wgroup.long 0x78++0x3
|
|
line.long 0x0 "FOCR,Fault Output Clear Register"
|
|
bitfld.long 0x0 0. "FOCLR,Fault Output Clear" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
group.long 0x88++0x7
|
|
line.long 0x0 "PCR,Peripheral Control Register"
|
|
bitfld.long 0x0 31. "CMD,Command" "0,1"
|
|
bitfld.long 0x0 29. "GCLKEN,Generic Clock Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EN,Enable" "0,1"
|
|
hexmask.long.byte 0x0 20.--27. 1. "GCLKDIV,Generic Clock Division Ratio"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "GCLKCSS,Generic Clock Source Selection"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PID,Peripheral ID"
|
|
line.long 0x4 "OCR,Oscillator Calibration Register"
|
|
bitfld.long 0x4 23. "SEL12,Selection of Main RC Oscillator Calibration Bits" "0,1"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CAL12,Main RC Oscillator Calibration Bits"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "MCKLIM,MCK Monitor Limits Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MCK_HIGH_IT,MCK Monitoring High IT Limit"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MCK_LOW_IT,MCK Monitoring Low IT Limit"
|
|
rgroup.long 0xA0++0x7
|
|
line.long 0x0 "CSR0,Peripheral Clock Status Register 0"
|
|
bitfld.long 0x0 30. "PID30,Peripheral Clock 30 Status" "0,1"
|
|
bitfld.long 0x0 29. "PID29,Peripheral Clock 29 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "PID28,Peripheral Clock 28 Status" "0,1"
|
|
bitfld.long 0x0 27. "PID27,Peripheral Clock 27 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "PID26,Peripheral Clock 26 Status" "0,1"
|
|
bitfld.long 0x0 25. "PID25,Peripheral Clock 25 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "PID24,Peripheral Clock 24 Status" "0,1"
|
|
bitfld.long 0x0 23. "PID23,Peripheral Clock 23 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "PID22,Peripheral Clock 22 Status" "0,1"
|
|
bitfld.long 0x0 20. "PID20,Peripheral Clock 20 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PID19,Peripheral Clock 19 Status" "0,1"
|
|
bitfld.long 0x0 18. "PID18,Peripheral Clock 18 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PID17,Peripheral Clock 17 Status" "0,1"
|
|
bitfld.long 0x0 16. "PID16,Peripheral Clock 16 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "PID15,Peripheral Clock 15 Status" "0,1"
|
|
bitfld.long 0x0 14. "PID14,Peripheral Clock 14 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PID13,Peripheral Clock 13 Status" "0,1"
|
|
bitfld.long 0x0 12. "PID12,Peripheral Clock 12 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PID11,Peripheral Clock 11 Status" "0,1"
|
|
bitfld.long 0x0 10. "PID10,Peripheral Clock 10 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PID9,Peripheral Clock 9 Status" "0,1"
|
|
bitfld.long 0x0 8. "PID8,Peripheral Clock 8 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PID7,Peripheral Clock 7 Status" "0,1"
|
|
bitfld.long 0x0 6. "PID6,Peripheral Clock 6 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PID5,Peripheral Clock 5 Status" "0,1"
|
|
bitfld.long 0x0 4. "PID4,Peripheral Clock 4 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PID3,Peripheral Clock 3 Status" "0,1"
|
|
bitfld.long 0x0 2. "PID2,Peripheral Clock 2 Status" "0,1"
|
|
line.long 0x4 "CSR1,Peripheral Clock Status Register 1"
|
|
bitfld.long 0x4 13. "PID45,Peripheral Clock 45 Status" "0,1"
|
|
bitfld.long 0x4 12. "PID44,Peripheral Clock 44 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "PID43,Peripheral Clock 43 Status" "0,1"
|
|
bitfld.long 0x4 10. "PID42,Peripheral Clock 42 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PID41,Peripheral Clock 41 Status" "0,1"
|
|
bitfld.long 0x4 8. "PID40,Peripheral Clock 40 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PID39,Peripheral Clock 39 Status" "0,1"
|
|
bitfld.long 0x4 6. "PID38,Peripheral Clock 38 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PID37,Peripheral Clock 37 Status" "0,1"
|
|
bitfld.long 0x4 4. "PID36,Peripheral Clock 36 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PID35,Peripheral Clock 35 Status" "0,1"
|
|
bitfld.long 0x4 2. "PID34,Peripheral Clock 34 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PID33,Peripheral Clock 33 Status" "0,1"
|
|
bitfld.long 0x4 0. "PID32,Peripheral Clock 32 Status" "0,1"
|
|
rgroup.long 0xC0++0x7
|
|
line.long 0x0 "GCSR0,Generic Clock Status Register 0"
|
|
bitfld.long 0x0 26. "GPID26,Generic Clock 26 Status" "0,1"
|
|
bitfld.long 0x0 25. "GPID25,Generic Clock 25 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "GPID19,Generic Clock 19 Status" "0,1"
|
|
bitfld.long 0x0 17. "GPID17,Generic Clock 17 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "GPID16,Generic Clock 16 Status" "0,1"
|
|
bitfld.long 0x0 15. "GPID15,Generic Clock 15 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "GPID14,Generic Clock 14 Status" "0,1"
|
|
bitfld.long 0x0 13. "GPID13,Generic Clock 13 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "GPID12,Generic Clock 12 Status" "0,1"
|
|
bitfld.long 0x0 11. "GPID11,Generic Clock 11 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "GPID10,Generic Clock 10 Status" "0,1"
|
|
bitfld.long 0x0 9. "GPID9,Generic Clock 9 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "GPID8,Generic Clock 8 Status" "0,1"
|
|
bitfld.long 0x0 7. "GPID7,Generic Clock 7 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "GPID6,Generic Clock 6 Status" "0,1"
|
|
bitfld.long 0x0 5. "GPID5,Generic Clock 5 Status" "0,1"
|
|
line.long 0x4 "GCSR1,Generic Clock Status Register 1"
|
|
bitfld.long 0x4 15. "GPID47,Generic Clock 47 Status" "0,1"
|
|
bitfld.long 0x4 13. "GPID45,Generic Clock 45 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "GPID42,Generic Clock 42 Status" "0,1"
|
|
bitfld.long 0x4 5. "GPID37,Generic Clock 37 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "GPID34,Generic Clock 34 Status" "0,1"
|
|
bitfld.long 0x4 1. "GPID33,Generic Clock 33 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "GPID32,Generic Clock 32 Status" "0,1"
|
|
wgroup.long 0xE0++0x7
|
|
line.long 0x0 "PLL_IER,PLL Interrupt Enable Register"
|
|
bitfld.long 0x0 17. "UNLOCKU,UPLL Unlock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "UNLOCKA,PLLA Unlock Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOCKU,UPLL Lock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "LOCKA,PLLA Lock Interrupt Enable" "0,1"
|
|
line.long 0x4 "PLL_IDR,PLL Interrupt Disable Register"
|
|
bitfld.long 0x4 17. "UNLOCKU,UPLL Unlock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "UNLOCKA,PLLA Unlock Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOCKU,UPLL Lock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "LOCKA,PLLA Lock Interrupt Disable" "0,1"
|
|
rgroup.long 0xE8++0xB
|
|
line.long 0x0 "PLL_IMR,PLL Interrupt Mask Register"
|
|
bitfld.long 0x0 17. "UNLOCKU,UPLL Unlock Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "UNLOCKA,PLLA Unlock Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOCKU,UPLL Lock Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "LOCKA,PLLA Lock Interrupt Mask" "0,1"
|
|
line.long 0x4 "PLL_ISR0,PLL Interrupt Status Register 0"
|
|
bitfld.long 0x4 17. "UNLOCKU,UPLL Unlock Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "UNLOCKA,PLLA Unlock Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOCKU,UPLL Lock Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "LOCKA,PLLA Lock Interrupt Status" "0,1"
|
|
line.long 0x8 "PLL_ISR1,PLL Interrupt Status Register 1"
|
|
bitfld.long 0x8 17. "OVRU,UPLL Overflow" "0,1"
|
|
bitfld.long 0x8 16. "OVRA,PLLA Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "UDRU,UPLL Underflow" "0,1"
|
|
bitfld.long 0x8 0. "UDRA,PLLA Underflow" "0,1"
|
|
tree.end
|
|
tree "PMECC (Programmable Multibit Error Correction Code Controller)"
|
|
base ad:0xFFFFE000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CFG,PMECC Configuration Register"
|
|
bitfld.long 0x0 20. "AUTO,Automatic Mode Enable" "0,1"
|
|
bitfld.long 0x0 16. "SPAREEN,Spare Enable" "0,1"
|
|
bitfld.long 0x0 12. "NANDWR,NAND Write Access" "0,1"
|
|
bitfld.long 0x0 8.--9. "PAGESIZE,Number of Sectors in the Page" "0: 1 sector for main area (512 or 1024 bytes),1: 2 sectors for main area (1024 or 2048 bytes),2: 4 sectors for main area (2048 or 4096 bytes),3: 8 sectors for main area (4096 or 8192 bytes)"
|
|
bitfld.long 0x0 4. "SECTORSZ,Sector Size" "0,1"
|
|
bitfld.long 0x0 0.--2. "BCH_ERR,Error Correct Capability" "0: 2 errors,1: 4 errors,2: 8 errors,3: 12 errors,4: 24 errors,?,?,?"
|
|
line.long 0x4 "SAREA,PMECC Spare Area Size Register"
|
|
hexmask.long.word 0x4 0.--8. 1. "SPARESIZE,Spare Area Size"
|
|
line.long 0x8 "SADDR,PMECC Start Address Register"
|
|
hexmask.long.word 0x8 0.--8. 1. "STARTADDR,ECC Area Start Address (byte oriented address)"
|
|
line.long 0xC "EADDR,PMECC End Address Register"
|
|
hexmask.long.word 0xC 0.--8. 1. "ENDADDR,ECC Area End Address (byte oriented address)"
|
|
line.long 0x10 "CLK,PMECC Clock Control Register"
|
|
bitfld.long 0x10 0.--2. "CLKCTRL,Clock Control Register" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "CTRL,PMECC Control Register"
|
|
bitfld.long 0x0 5. "DISABLE,PMECC Module Disable" "0,1"
|
|
bitfld.long 0x0 4. "ENABLE,PMECC Module Enable" "0,1"
|
|
bitfld.long 0x0 2. "USER,Start a User Mode Phase" "0,1"
|
|
bitfld.long 0x0 1. "DATA,Start a Data Phase" "0,1"
|
|
bitfld.long 0x0 0. "RST,Reset the PMECC Module" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "SR,PMECC Status Register"
|
|
bitfld.long 0x0 4. "ENABLE,PMECC Module Status" "0,1"
|
|
bitfld.long 0x0 0. "BUSY,The Kernel of the PMECC is Busy" "0,1"
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "IER,PMECC Interrupt Enable register"
|
|
bitfld.long 0x0 0. "ERRIE,Error Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,PMECC Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "ERRID,Error Interrupt Disable" "0,1"
|
|
rgroup.long 0x24++0x7
|
|
line.long 0x0 "IMR,PMECC Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "ERRIM,Error Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,PMECC Interrupt Status Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ERRIS,Error Interrupt Status"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0xFFFFE040 ad:0xFFFFE080 ad:0xFFFFE0C0 ad:0xFFFFE100 ad:0xFFFFE140 ad:0xFFFFE180 ad:0xFFFFE1C0 ad:0xFFFFE200)
|
|
tree "PMECC_ECC[$1]"
|
|
base $2
|
|
repeat 11. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "ECC[$1],PMECC ECC 0 Register (sec_num = 0)"
|
|
hexmask.long 0x0 0.--31. 1. "ECC,BCH Redundancy"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0xFFFFE240 ad:0xFFFFE280 ad:0xFFFFE2C0 ad:0xFFFFE300 ad:0xFFFFE340 ad:0xFFFFE380 ad:0xFFFFE3C0 ad:0xFFFFE400)
|
|
tree "PMECC_REM[$1]"
|
|
base $2
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "REM[$1],PMECC REM 0 Register (sec_num = 0)"
|
|
hexmask.long.word 0x0 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x0 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PMERRLOC (Programmable Multibit ECC Error Location)"
|
|
base ad:0xFFFFE600
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ELCFG,Configuration Register"
|
|
hexmask.long.byte 0x0 16.--20. 1. "ERRNUM,Number of Errors"
|
|
bitfld.long 0x0 0. "SECTORSZ,Sector Size" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "ELPRIM,Primitive Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PRIMITIV,Primitive Polynomial"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "ELEN,Enable Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "ENINIT,Initial Number of Bits in the Codeword"
|
|
line.long 0x4 "ELDIS,Disable Register"
|
|
bitfld.long 0x4 0. "DIS,Disable Error Location Engine" "0,1"
|
|
line.long 0x8 "ELSR,Status Register"
|
|
bitfld.long 0x8 0. "BUSY,Error Location Engine Busy" "0,1"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "ELIER,Interrupt Enable Register"
|
|
bitfld.long 0x0 0. "DONE,Computation Terminated Interrupt Enable" "0,1"
|
|
line.long 0x4 "ELIDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "DONE,Computation Terminated Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "ELIMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "DONE,Computation Terminated Interrupt Mask" "0,1"
|
|
line.long 0x4 "ELISR,Interrupt Status Register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "ERR_CNT,Error Counter Value"
|
|
bitfld.long 0x4 0. "DONE,Computation Terminated Interrupt Status" "0,1"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "SIGMA0,SIGMA0 Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "SIGMA0,Coefficient of Degree 0 in the SIGMA Polynomial"
|
|
group.long 0x2C++0x5F
|
|
line.long 0x0 "SIGMA1,SIGMA1 Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "SIGMA1,Coefficient of Degree 1 in the SIGMA Polynomial."
|
|
line.long 0x4 "SIGMA2,SIGMA2 Register"
|
|
hexmask.long.word 0x4 0.--13. 1. "SIGMA2,Coefficient of Degree 2 in the SIGMA Polynomial."
|
|
line.long 0x8 "SIGMA3,SIGMA3 Register"
|
|
hexmask.long.word 0x8 0.--13. 1. "SIGMA3,Coefficient of Degree 3 in the SIGMA Polynomial."
|
|
line.long 0xC "SIGMA4,SIGMA4 Register"
|
|
hexmask.long.word 0xC 0.--13. 1. "SIGMA4,Coefficient of Degree 4 in the SIGMA Polynomial."
|
|
line.long 0x10 "SIGMA5,SIGMA5 Register"
|
|
hexmask.long.word 0x10 0.--13. 1. "SIGMA5,Coefficient of Degree 5 in the SIGMA Polynomial."
|
|
line.long 0x14 "SIGMA6,SIGMA6 Register"
|
|
hexmask.long.word 0x14 0.--13. 1. "SIGMA6,Coefficient of Degree 6 in the SIGMA Polynomial."
|
|
line.long 0x18 "SIGMA7,SIGMA7 Register"
|
|
hexmask.long.word 0x18 0.--13. 1. "SIGMA7,Coefficient of Degree 7 in the SIGMA Polynomial."
|
|
line.long 0x1C "SIGMA8,SIGMA8 Register"
|
|
hexmask.long.word 0x1C 0.--13. 1. "SIGMA8,Coefficient of Degree 8 in the SIGMA Polynomial."
|
|
line.long 0x20 "SIGMA9,SIGMA9 Register"
|
|
hexmask.long.word 0x20 0.--13. 1. "SIGMA9,Coefficient of Degree 9 in the SIGMA Polynomial."
|
|
line.long 0x24 "SIGMA10,SIGMA10 Register"
|
|
hexmask.long.word 0x24 0.--13. 1. "SIGMA10,Coefficient of Degree 10 in the SIGMA Polynomial."
|
|
line.long 0x28 "SIGMA11,SIGMA11 Register"
|
|
hexmask.long.word 0x28 0.--13. 1. "SIGMA11,Coefficient of Degree 11 in the SIGMA Polynomial."
|
|
line.long 0x2C "SIGMA12,SIGMA12 Register"
|
|
hexmask.long.word 0x2C 0.--13. 1. "SIGMA12,Coefficient of Degree 12 in the SIGMA Polynomial."
|
|
line.long 0x30 "SIGMA13,SIGMA13 Register"
|
|
hexmask.long.word 0x30 0.--13. 1. "SIGMA13,Coefficient of Degree 13 in the SIGMA Polynomial."
|
|
line.long 0x34 "SIGMA14,SIGMA14 Register"
|
|
hexmask.long.word 0x34 0.--13. 1. "SIGMA14,Coefficient of Degree 14 in the SIGMA Polynomial."
|
|
line.long 0x38 "SIGMA15,SIGMA15 Register"
|
|
hexmask.long.word 0x38 0.--13. 1. "SIGMA15,Coefficient of Degree 15 in the SIGMA Polynomial."
|
|
line.long 0x3C "SIGMA16,SIGMA16 Register"
|
|
hexmask.long.word 0x3C 0.--13. 1. "SIGMA16,Coefficient of Degree 16 in the SIGMA Polynomial."
|
|
line.long 0x40 "SIGMA17,SIGMA17 Register"
|
|
hexmask.long.word 0x40 0.--13. 1. "SIGMA17,Coefficient of Degree 17 in the SIGMA Polynomial."
|
|
line.long 0x44 "SIGMA18,SIGMA18 Register"
|
|
hexmask.long.word 0x44 0.--13. 1. "SIGMA18,Coefficient of Degree 18 in the SIGMA Polynomial."
|
|
line.long 0x48 "SIGMA19,SIGMA19 Register"
|
|
hexmask.long.word 0x48 0.--13. 1. "SIGMA19,Coefficient of Degree 19 in the SIGMA Polynomial."
|
|
line.long 0x4C "SIGMA20,SIGMA20 Register"
|
|
hexmask.long.word 0x4C 0.--13. 1. "SIGMA20,Coefficient of Degree 20 in the SIGMA Polynomial."
|
|
line.long 0x50 "SIGMA21,SIGMA21 Register"
|
|
hexmask.long.word 0x50 0.--13. 1. "SIGMA21,Coefficient of Degree 21 in the SIGMA Polynomial."
|
|
line.long 0x54 "SIGMA22,SIGMA22 Register"
|
|
hexmask.long.word 0x54 0.--13. 1. "SIGMA22,Coefficient of Degree 22 in the SIGMA Polynomial."
|
|
line.long 0x58 "SIGMA23,SIGMA23 Register"
|
|
hexmask.long.word 0x58 0.--13. 1. "SIGMA23,Coefficient of Degree 23 in the SIGMA Polynomial."
|
|
line.long 0x5C "SIGMA24,SIGMA24 Register"
|
|
hexmask.long.word 0x5C 0.--13. 1. "SIGMA24,Coefficient of Degree 24 in the SIGMA Polynomial."
|
|
repeat 24. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x8C)++0x3
|
|
line.long 0x0 "EL[$1],Error Location 0 Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "ERRLOCN,Error Position within the Set {sector area spare area}."
|
|
repeat.end
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation Controller)"
|
|
base ad:0xF8034000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MR,PWM Mode Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PREB,CLKB Source Clock Selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DIVB,CLKB Divide Factor"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PREA,CLKA Source Clock Selection"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIVA,CLKA Divide Factor"
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "ENA,PWM Enable Register"
|
|
bitfld.long 0x0 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0,1"
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0,1"
|
|
line.long 0x4 "DIS,PWM Disable Register"
|
|
bitfld.long 0x4 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Channel ID" "0,1"
|
|
bitfld.long 0x4 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Channel ID" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,PWM Status Register"
|
|
bitfld.long 0x0 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0,1"
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,PWM Interrupt Enable Register"
|
|
bitfld.long 0x0 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0,1"
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0,1"
|
|
line.long 0x4 "IDR,PWM Interrupt Disable Register"
|
|
bitfld.long 0x4 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Channel ID" "0,1"
|
|
bitfld.long 0x4 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Channel ID" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,PWM Interrupt Mask Register"
|
|
bitfld.long 0x0 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0,1"
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0,1"
|
|
line.long 0x4 "ISR,PWM Interrupt Status Register"
|
|
bitfld.long 0x4 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Channel ID" "0,1"
|
|
bitfld.long 0x4 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Channel ID" "0,1"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xF8034200 ad:0xF8034220 ad:0xF8034240 ad:0xF8034260)
|
|
tree "PWM_CH_NUM[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "CMR,PWM Channel Mode Register"
|
|
bitfld.long 0x0 10. "CPD,Channel Update Period" "0,1"
|
|
bitfld.long 0x0 9. "CPOL,Channel Polarity" "0: Waveform starts at low level,1: Waveform starts at high level"
|
|
bitfld.long 0x0 8. "CALG,Channel Alignment" "0: Left aligned,1: Center aligned"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CPRE,Channel Prescaler"
|
|
line.long 0x4 "CDTY,PWM Channel Duty Cycle Register"
|
|
hexmask.long 0x4 0.--31. 1. "CDTY,Channel Duty Cycle"
|
|
line.long 0x8 "CPRD,PWM Channel Period Register"
|
|
hexmask.long 0x8 0.--31. 1. "CPRD,Channel Period"
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "CCNT,PWM Channel Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "CNT,Channel Counter Register"
|
|
wgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "CUPD,PWM Channel Update Register"
|
|
hexmask.long 0x0 0.--31. 1. "CUPD,Channel Update Register"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "QSPI (Quad Serial Peripheral Interface)"
|
|
base ad:0xF0014000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
bitfld.long 0x0 7. "SWRST,QSPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "QSPIDIS,QSPI Disable" "0,1"
|
|
bitfld.long 0x0 0. "QSPIEN,QSPI Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYCS,Minimum Inactive QCS Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
bitfld.long 0x0 13. "QICMEN,QSPI Inter-chip Mode Enable" "0: QSPI_WICR.WROPT and QSPI_RICR.RDOPT define the..,1: No dummy cycles are inserted for write accesses.."
|
|
hexmask.long.byte 0x0 8.--11. 1. "NBBITS,Number Of Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 7. "TAMPCLR,Tamper Clear Enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "CSMODE,Chip Select Mode" "0: The chip select is deasserted if QSPI_TDR.TD has..,1: The chip select is deasserted when the bit..,2: The chip select is deasserted systematically..,?"
|
|
newline
|
|
bitfld.long 0x0 3. "SMRM,Serial Memory Register Mode" "0,1"
|
|
bitfld.long 0x0 2. "WDRBT,Wait Data Read Before Transfer" "0: No effect. In SPI mode a transfer can be..,1: In SPI mode a transfer can start only if the.."
|
|
newline
|
|
bitfld.long 0x0 0. "SMM,Serial Memory Mode" "0: The QSPI is in SPI mode.,1: The QSPI is in Serial Memory mode."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR,Receive Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 24. "QSPIENS,QSPI Enable Status" "0,1"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CSS,Chip Select Status" "0,1"
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty (cleared by writing QSPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing QSPI_TDR)" "0,1"
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading QSPI_RDR)" "0,1"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "CSS,Chip Select Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 10. "INSTRE,Instruction End Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "CSS,Chip Select Status Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CSR,Chip Select Rise Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
bitfld.long 0x4 1. "TDRE,Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "CSS,Chip Select Status Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SCR,Serial Clock Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before QSCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Baud Rate"
|
|
newline
|
|
bitfld.long 0x0 1. "CPHA,Clock Phase" "0,1"
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
group.long 0x30++0x13
|
|
line.long 0x0 "IAR,Instruction Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address"
|
|
line.long 0x4 "WICR,Write Instruction Code Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "WROPT,Write Option Code"
|
|
hexmask.long.byte 0x4 0.--7. 1. "WRINST,Write Instruction Code"
|
|
line.long 0x8 "IFR,Instruction Frame Register"
|
|
bitfld.long 0x8 26. "DDRCMDEN,DDR Mode Command Enable" "0: Transfer of instruction field is performed in..,1: Transfer of instruction field is performed in.."
|
|
bitfld.long 0x8 24. "APBTFRTYP,APB Transfer Type" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "NBDUM,Number Of Dummy Cycles"
|
|
bitfld.long 0x8 15. "DDREN,DDR Mode Enable" "0: Transfers are performed in Single Data Rate mode.,1: Transfers are performed in Double Data Rate mode.."
|
|
newline
|
|
bitfld.long 0x8 14. "CRM,Continuous Read Mode" "0: Continuous Read mode is disabled.,1: Continuous Read mode is enabled."
|
|
bitfld.long 0x8 12. "TFRTYP,Data Transfer Type" "0: Read/Write transfer from the serial memory.,1: Read/Write data transfer from the serial memory."
|
|
newline
|
|
bitfld.long 0x8 10. "ADDRL,Address Length" "0: The address is 24 bits long.,1: The address is 32 bits long."
|
|
bitfld.long 0x8 8.--9. "OPTL,Option Code Length" "0: The option code is 1 bit long.,1: The option code is 2 bits long.,2: The option code is 4 bits long.,3: The option code is 8 bits long."
|
|
newline
|
|
bitfld.long 0x8 7. "DATAEN,Data Enable" "0,1"
|
|
bitfld.long 0x8 6. "OPTEN,Option Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "ADDREN,Address Enable" "0,1"
|
|
bitfld.long 0x8 4. "INSTEN,Instruction Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "WIDTH,Width of Instruction Code Address Option Code and Data" "0: Instruction: Single-bit SPI / Address-Option:..,1: Instruction: Single-bit SPI / Address-Option:..,2: Instruction: Single-bit SPI / Address-Option:..,3: Instruction: Single-bit SPI / Address-Option:..,4: Instruction: Single-bit SPI / Address-Option:..,5: Instruction: Dual SPI / Address-Option: Dual SPI..,6: Instruction: Quad SPI / Address-Option: Quad SPI..,?"
|
|
line.long 0xC "RICR,Read Instruction Code Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "RDOPT,Read Option Code"
|
|
hexmask.long.byte 0xC 0.--7. 1. "RDINST,Read Instruction Code"
|
|
line.long 0x10 "SMR,Scrambling Mode Register"
|
|
bitfld.long 0x10 2. "SCRKL,Scrambling Key Lock" "0,1"
|
|
bitfld.long 0x10 1. "RVDIS,Scrambling/Unscrambling Random Value Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "SCREN,Scrambling/Unscrambling Enable" "0: The scrambling/unscrambling is disabled.,1: The scrambling/unscrambling is enabled."
|
|
wgroup.long 0x44++0x3
|
|
line.long 0x0 "SKR,Scrambling Key Register"
|
|
hexmask.long 0x0 0.--31. 1. "USRK,User Scrambling Key"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0xFFFFFE00
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,System Reset Key"
|
|
bitfld.long 0x0 3. "EXTRST,External Reset" "0,1"
|
|
bitfld.long 0x0 0. "PROCRST,Processor Reset" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 17. "SRCMP,Software Reset Command in Progress" "0,1"
|
|
bitfld.long 0x0 16. "NRSTL,NRST Pin Level" "0,1"
|
|
bitfld.long 0x0 8.--10. "RSTTYP,Reset Type" "0: First powerup reset,1: Return from Backup mode,2: Watchdog fault occurred,3: Processor reset required by the software,4: NRST pin detected low,?,?,7: 32.768 kHz crystal failure detection fault.."
|
|
bitfld.long 0x0 0. "URSTS,User Reset Status" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Write Access Password"
|
|
bitfld.long 0x0 20. "ENGCLR,Enable GPBR Clear on Tamper Event" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "ERSTL,External Reset Length"
|
|
bitfld.long 0x0 4. "URSTIEN,User Reset Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "URSTASYNC,User Reset Asynchronous Control" "0,1"
|
|
bitfld.long 0x0 1. "SCKSW,Slow Clock Switching" "0,1"
|
|
bitfld.long 0x0 0. "URSTEN,User Reset Enable" "0,1"
|
|
tree.end
|
|
tree "RTC (Real-time Clock)"
|
|
base ad:0xFFFFFEA8
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 16.--17. "CALEVSEL,Calendar Event Selection" "0: Week change (every Monday at time 00:00:00),1: Month change (every 01 of each month at time..,2: Year change (every January 1 at time 00:00:00),?"
|
|
bitfld.long 0x0 8.--9. "TIMEVSEL,Time Event Selection" "0: Minute change,1: Hour change,2: Every day at midnight,3: Every day at noon"
|
|
newline
|
|
bitfld.long 0x0 1. "UPDCAL,Update Request Calendar Register" "0,1"
|
|
bitfld.long 0x0 0. "UPDTIM,Update Request Time Register" "0,1"
|
|
line.long 0x4 "MR,Mode Register"
|
|
bitfld.long 0x4 28.--29. "TPERIOD,Period of the Output Pulse" "0: 1 second,1: 500 ms,2: 250 ms,3: 125 ms"
|
|
bitfld.long 0x4 24.--26. "THIGH,High Duration of the Output Pulse" "0: 31.2 ms,1: 15.6 ms,2: 3.91 ms,3: 976 us,4: 488 us,5: 122 us,6: 30.5 us,7: 15.2 us"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "OUT1,ADC Last Channel Trigger Event Source Selection" "0: No waveform stuck at '0',1: 1 Hz square wave,2: 32 Hz square wave,3: 64 Hz square wave,4: 512 Hz square wave,5: Output toggles when alarm flag rises,6: Output is a copy of the alarm flag,7: Duty cycle programmable pulse"
|
|
bitfld.long 0x4 16.--18. "OUT0,All ADC Channel Trigger Event Source Selection" "0: No waveform stuck at '0',1: 1 Hz square wave,2: 32 Hz square wave,3: 64 Hz square wave,4: 512 Hz square wave,5: Output toggles when alarm flag rises,6: Output is a copy of the alarm flag,7: Duty cycle programmable pulse"
|
|
newline
|
|
bitfld.long 0x4 15. "HIGHPPM,HIGH PPM Correction" "0,1"
|
|
hexmask.long.byte 0x4 8.--14. 1. "CORRECTION,Slow Clock Correction"
|
|
newline
|
|
bitfld.long 0x4 4. "NEGPPM,NEGative PPM Correction" "0,1"
|
|
bitfld.long 0x4 2. "UTC,UTC Time Format" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PERSIAN,PERSIAN Calendar" "0,1"
|
|
bitfld.long 0x4 0. "HRMOD,12-/24-hour Mode" "0,1"
|
|
line.long 0x8 "TIMR,Time Register"
|
|
bitfld.long 0x8 22. "AMPM,Ante Meridiem Post Meridiem Indicator" "0,1"
|
|
hexmask.long.byte 0x8 16.--21. 1. "HOUR,Current Hour"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 1. "MIN,Current Minute"
|
|
hexmask.long.byte 0x8 0.--6. 1. "SEC,Current Second"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "TIMR_UTC_MODE_MODE,Time Register"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,Current UTC Time"
|
|
line.long 0x4 "CALR,Calendar Register"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Current Day in Current Month"
|
|
bitfld.long 0x4 21.--23. "DAY,Current Day in Current Week" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Current Month"
|
|
hexmask.long.byte 0x4 8.--15. 1. "YEAR,Current Year"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "CENT,Current Century"
|
|
line.long 0x8 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x8 23. "HOUREN,Hour Alarm Enable" "0,1"
|
|
bitfld.long 0x8 22. "AMPM,AM/PM Indicator" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "HOUR,Hour Alarm"
|
|
bitfld.long 0x8 15. "MINEN,Minute Alarm Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 1. "MIN,Minute Alarm"
|
|
bitfld.long 0x8 7. "SECEN,Second Alarm Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "SEC,Second Alarm"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "TIMALR_UTC_MODE_MODE,Time Alarm Register"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,UTC_TIME Alarm"
|
|
line.long 0x4 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x4 31. "DATEEN,Date Alarm Enable" "0,1"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Date Alarm"
|
|
newline
|
|
bitfld.long 0x4 23. "MTHEN,Month Alarm Enable" "0,1"
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Month Alarm"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CALALR_UTC_MODE_MODE,Calendar Alarm Register"
|
|
bitfld.long 0x0 0. "UTCEN,UTC Alarm Enable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 5. "TDERR,Time and/or Date Free Running Error" "0: The internal free running counters are carrying..,1: The internal free running counters have been.."
|
|
bitfld.long 0x0 4. "CALEV,Calendar Event" "0: No calendar event has occurred since the last..,1: At least one calendar event has occurred since.."
|
|
newline
|
|
bitfld.long 0x0 3. "TIMEV,Time Event" "0: No time event has occurred since the last clear.,1: At least one time event has occurred since the.."
|
|
bitfld.long 0x0 2. "SEC,Second Event" "0: No second event has occurred since the last clear.,1: At least one second event has occurred since the.."
|
|
newline
|
|
bitfld.long 0x0 1. "ALARM,Alarm Flag" "0: No alarm matching condition occurred.,1: An alarm matching condition has occurred."
|
|
bitfld.long 0x0 0. "ACKUPD,Acknowledge for Update" "0: Time and calendar registers cannot be updated.,1: Time and calendar registers can be updated."
|
|
wgroup.long 0x1C++0xB
|
|
line.long 0x0 "SCCR,Status Clear Command Register"
|
|
bitfld.long 0x0 5. "TDERRCLR,Time and/or Date Free Running Error Clear" "0,1"
|
|
bitfld.long 0x0 4. "CALCLR,Calendar Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIMCLR,Time Clear" "0,1"
|
|
bitfld.long 0x0 2. "SECCLR,Second Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRCLR,Alarm Clear" "0,1"
|
|
bitfld.long 0x0 0. "ACKCLR,Acknowledge Clear" "0,1"
|
|
line.long 0x4 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x4 5. "TDERREN,Time and/or Date Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "CALEN,Calendar Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TIMEN,Time Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "SECEN,Second Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALREN,Alarm Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "ACKEN,Acknowledge Update Interrupt Enable" "0,1"
|
|
line.long 0x8 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x8 5. "TDERRDIS,Time and/or Date Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 4. "CALDIS,Calendar Event Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TIMDIS,Time Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 2. "SECDIS,Second Event Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ALRDIS,Alarm Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 0. "ACKDIS,Acknowledge Update Interrupt Disable" "0,1"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 5. "TDERR,Time and/or Date Error Mask" "0,1"
|
|
bitfld.long 0x0 4. "CAL,Calendar Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIM,Time Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "SEC,Second Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALR,Alarm Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "ACK,Acknowledge Update Interrupt Mask" "0,1"
|
|
line.long 0x4 "VER,Valid Entry Register"
|
|
bitfld.long 0x4 3. "NVCALALR,Non-valid Calendar Alarm" "0,1"
|
|
bitfld.long 0x4 2. "NVTIMALR,Non-valid Time Alarm" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NVCAL,Non-valid Calendar" "0,1"
|
|
bitfld.long 0x4 0. "NVTIM,Non-valid Time" "0,1"
|
|
group.long 0x58++0x7
|
|
line.long 0x0 "TMR,Tamper Mode register"
|
|
bitfld.long 0x0 31. "TRLOCK,Tamper Registers Lock (Write-once cleared by VDDCORE reset)" "0: RTC_TMR and RTC_TDPR can be written.,1: RTC_TMR and RTC_TDPR cannot be written until the.."
|
|
bitfld.long 0x0 23. "POL7,WKUPx+1 Polarity" "0: If the source of tamper remains low for a..,1: If the source of tamper remains high for a.."
|
|
newline
|
|
bitfld.long 0x0 22. "POL6,WKUPx+1 Polarity" "0: If the source of tamper remains low for a..,1: If the source of tamper remains high for a.."
|
|
bitfld.long 0x0 21. "POL5,WKUPx+1 Polarity" "0: If the source of tamper remains low for a..,1: If the source of tamper remains high for a.."
|
|
newline
|
|
bitfld.long 0x0 20. "POL4,WKUPx+1 Polarity" "0: If the source of tamper remains low for a..,1: If the source of tamper remains high for a.."
|
|
bitfld.long 0x0 19. "POL3,WKUPx+1 Polarity" "0: If the source of tamper remains low for a..,1: If the source of tamper remains high for a.."
|
|
newline
|
|
bitfld.long 0x0 18. "POL2,WKUPx+1 Polarity" "0: If the source of tamper remains low for a..,1: If the source of tamper remains high for a.."
|
|
bitfld.long 0x0 17. "POL1,WKUPx+1 Polarity" "0: If the source of tamper remains low for a..,1: If the source of tamper remains high for a.."
|
|
newline
|
|
bitfld.long 0x0 16. "POL0,WKUPx+1 Polarity" "0: If the source of tamper remains low for a..,1: If the source of tamper remains high for a.."
|
|
bitfld.long 0x0 7. "EN7,WKUPx+1 Tamper Source Enable" "0: WKUP pin index x+1 is not enabled as a source of..,1: WKUP pin index x+1 is enabled as a source of.."
|
|
newline
|
|
bitfld.long 0x0 6. "EN6,WKUPx+1 Tamper Source Enable" "0: WKUP pin index x+1 is not enabled as a source of..,1: WKUP pin index x+1 is enabled as a source of.."
|
|
bitfld.long 0x0 5. "EN5,WKUPx+1 Tamper Source Enable" "0: WKUP pin index x+1 is not enabled as a source of..,1: WKUP pin index x+1 is enabled as a source of.."
|
|
newline
|
|
bitfld.long 0x0 4. "EN4,WKUPx+1 Tamper Source Enable" "0: WKUP pin index x+1 is not enabled as a source of..,1: WKUP pin index x+1 is enabled as a source of.."
|
|
bitfld.long 0x0 3. "EN3,WKUPx+1 Tamper Source Enable" "0: WKUP pin index x+1 is not enabled as a source of..,1: WKUP pin index x+1 is enabled as a source of.."
|
|
newline
|
|
bitfld.long 0x0 2. "EN2,WKUPx+1 Tamper Source Enable" "0: WKUP pin index x+1 is not enabled as a source of..,1: WKUP pin index x+1 is enabled as a source of.."
|
|
bitfld.long 0x0 1. "EN1,WKUPx+1 Tamper Source Enable" "0: WKUP pin index x+1 is not enabled as a source of..,1: WKUP pin index x+1 is enabled as a source of.."
|
|
newline
|
|
bitfld.long 0x0 0. "EN0,WKUPx+1 Tamper Source Enable" "0: WKUP pin index x+1 is not enabled as a source of..,1: WKUP pin index x+1 is enabled as a source of.."
|
|
line.long 0x4 "TDPR,Tamper Debounce Period register"
|
|
bitfld.long 0x4 23. "SELP7,WKUPx+1 Debounce Period Selection" "0: WKUP pin index x+1 is debounced with PERA period.,1: WKUP pin index x+1 is debounced with PERB period."
|
|
bitfld.long 0x4 22. "SELP6,WKUPx+1 Debounce Period Selection" "0: WKUP pin index x+1 is debounced with PERA period.,1: WKUP pin index x+1 is debounced with PERB period."
|
|
newline
|
|
bitfld.long 0x4 21. "SELP5,WKUPx+1 Debounce Period Selection" "0: WKUP pin index x+1 is debounced with PERA period.,1: WKUP pin index x+1 is debounced with PERB period."
|
|
bitfld.long 0x4 20. "SELP4,WKUPx+1 Debounce Period Selection" "0: WKUP pin index x+1 is debounced with PERA period.,1: WKUP pin index x+1 is debounced with PERB period."
|
|
newline
|
|
bitfld.long 0x4 19. "SELP3,WKUPx+1 Debounce Period Selection" "0: WKUP pin index x+1 is debounced with PERA period.,1: WKUP pin index x+1 is debounced with PERB period."
|
|
bitfld.long 0x4 18. "SELP2,WKUPx+1 Debounce Period Selection" "0: WKUP pin index x+1 is debounced with PERA period.,1: WKUP pin index x+1 is debounced with PERB period."
|
|
newline
|
|
bitfld.long 0x4 17. "SELP1,WKUPx+1 Debounce Period Selection" "0: WKUP pin index x+1 is debounced with PERA period.,1: WKUP pin index x+1 is debounced with PERB period."
|
|
bitfld.long 0x4 16. "SELP0,WKUPx+1 Debounce Period Selection" "0: WKUP pin index x+1 is debounced with PERA period.,1: WKUP pin index x+1 is debounced with PERB period."
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "PERB,Debounce Period B"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PERA,Debounce Period A"
|
|
repeat 2. (list 0x0 0x1)(list ad:0xFFFFFF58 ad:0xFFFFFF64)
|
|
tree "RTC_TS[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "TSTR,TimeStamp Time Register 0"
|
|
bitfld.long 0x0 31. "BACKUP,System Mode of the Tamper (cleared by reading RTC_TSSR0)" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TEVCNT,Tamper Events Counter (cleared by reading RTC_TSSR0)"
|
|
bitfld.long 0x0 22. "AMPM,AM/PM Indicator of the Tamper (cleared by reading RTC_TSSR0)" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "HOUR,Hours of the Tamper (cleared by reading RTC_TSSR0)"
|
|
hexmask.long.byte 0x0 8.--14. 1. "MIN,Minutes of the Tamper (cleared by reading RTC_TSSR0)"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SEC,Seconds of the Tamper (cleared by reading RTC_TSSR0)"
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "TSTR_UTC_MODE_MODE,TimeStamp Time Register 0"
|
|
bitfld.long 0x0 31. "BACKUP,System Mode of the Tamper (cleared by reading RTC_TSSR0)" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TEVCNT,Tamper Events Counter (cleared by reading RTC_TSSR0)"
|
|
line.long 0x4 "TSDR,TimeStamp Date Register 0"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Date of the Tamper (cleared by reading RTC_TSSRx)"
|
|
bitfld.long 0x4 21.--23. "DAY,Day of the Tamper (cleared by reading RTC_TSSRx)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Month of the Tamper (cleared by reading RTC_TSSRx)"
|
|
hexmask.long.byte 0x4 8.--15. 1. "YEAR,Year of the Tamper (cleared by reading RTC_TSSRx)"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CENT,Century of the Tamper (cleared by reading RTC_TSSRx)"
|
|
rgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "TSDR_UTC_MODE_MODE,TimeStamp Date Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,Time of the Tamper (UTC format)"
|
|
line.long 0x4 "TSSR,TimeStamp Source Register 0"
|
|
bitfld.long 0x4 23. "DET7,Tamper Detection on VDDCORE WKUP[8:1] (cleared on read)" "0,1"
|
|
bitfld.long 0x4 22. "DET6,Tamper Detection on VDDCORE WKUP[8:1] (cleared on read)" "0,1"
|
|
bitfld.long 0x4 21. "DET5,Tamper Detection on VDDCORE WKUP[8:1] (cleared on read)" "0,1"
|
|
bitfld.long 0x4 20. "DET4,Tamper Detection on VDDCORE WKUP[8:1] (cleared on read)" "0,1"
|
|
bitfld.long 0x4 19. "DET3,Tamper Detection on VDDCORE WKUP[8:1] (cleared on read)" "0,1"
|
|
bitfld.long 0x4 18. "DET2,Tamper Detection on VDDCORE WKUP[8:1] (cleared on read)" "0,1"
|
|
bitfld.long 0x4 17. "DET1,Tamper Detection on VDDCORE WKUP[8:1] (cleared on read)" "0,1"
|
|
bitfld.long 0x4 16. "DET0,Tamper Detection on VDDCORE WKUP[8:1] (cleared on read)" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "RTT (Real-time Timer)"
|
|
base ad:0xFFFFFE20
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 24. "RTC1HZ,Real-Time Clock 1Hz Clock Selection" "0,1"
|
|
bitfld.long 0x0 21. "INC2AEN,RTTINC2 Alarm and Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "RTTDIS,Real-time Timer Disable" "0,1"
|
|
bitfld.long 0x0 18. "RTTRST,Real-time Timer Restart" "0,1"
|
|
bitfld.long 0x0 17. "RTTINCIEN,Real-time Timer Increment Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "ALMIEN,Alarm Interrupt Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "RTPRES,Real-time Timer Prescaler Value"
|
|
line.long 0x4 "AR,Alarm Register"
|
|
hexmask.long 0x4 0.--31. 1. "ALMV,Alarm Value"
|
|
rgroup.long 0x8++0x7
|
|
line.long 0x0 "VR,Value Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRTV,Current Real-time Value"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 2. "RTTINC2,Predefined Number of Prescaler Roll-overs Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "RTTINC,Prescaler Roll-over Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 0. "ALMS,Real-time Alarm Status (cleared on read)" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "MODR,Modulo Selection Register"
|
|
bitfld.long 0x0 0.--2. "SELINC2,Selection of the 32-bit Counter Modulo to generate RTTINC2 Flag" "0: The RTTINC2 flag never rises,1: The RTTINC2 flag is set when CRTV modulo 64..,2: The RTTINC2 flag is set when CRTV modulo 128..,3: The RTTINC2 flag is set when CRTV modulo 256..,4: The RTTINC2 flag is set when CRTV modulo 512..,5: The RTTINC2 flag is set when CRTV modulo 1024..,6: The RTTINC2 flag is set when CRTV modulo 2048..,7: The RTTINC2 flag is set when CRTV modulo 4096.."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TSR,TimeStamp Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "TSTAMP,Real-time Timer Value Timestamp"
|
|
tree.end
|
|
tree "SCKC (Slow Clock Controller)"
|
|
base ad:0xFFFFFE50
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,Slow Clock Controller Configuration Register"
|
|
bitfld.long 0x0 24. "TD_OSCSEL,Timing Domain Slow Clock Selector" "0: Slow clock of the timing domain is driven by the..,1: Slow clock of the timing domain is driven by the.."
|
|
bitfld.long 0x0 2. "OSC32BYP,32.768 kHz Crystal Oscillator Bypass" "0,1"
|
|
bitfld.long 0x0 1. "OSC32EN,32.768 kHz Crystal Oscillator" "0,1"
|
|
tree.end
|
|
tree "SDMMC (Secure Digital MultiMedia Card Controller)"
|
|
base ad:0x0
|
|
tree "SDMMC0"
|
|
base ad:0x80000000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR,SDMA System Address / Argument 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,SDMA System Address"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR_CMD23_MODE,SDMA System Address / Argument 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG2,Argument 2"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "BSR,Block Size Register"
|
|
bitfld.word 0x0 12.--14. "BOUNDARY,SDMA Buffer Boundary" "0: 4-Kbyte boundary,1: 8-Kbyte boundary,2: 16-Kbyte boundary,3: 32-Kbyte boundary,4: 64-Kbyte boundary,5: 128-Kbyte boundary,6: 256-Kbyte boundary,7: 512-Kbyte boundary"
|
|
hexmask.word 0x0 0.--9. 1. "BLKSIZE,Transfer Block Size"
|
|
line.word 0x2 "BCR,Block Count Register"
|
|
hexmask.word 0x2 0.--15. 1. "BLKCNT,Block Count for Current Transfer"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ARG1R,Argument 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG1,Argument 1"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "TMR,Transfer Mode Register"
|
|
bitfld.word 0x0 5. "MSBSEL,Multi/Single Block Selection" "0,1"
|
|
bitfld.word 0x0 4. "DTDSEL,Data Transfer Direction Selection" "0: Writes data from the SDMMC to the device.,1: Reads data from the device to the SDMMC."
|
|
newline
|
|
bitfld.word 0x0 2.--3. "ACMDEN,Auto Command Enable" "0: Auto Command Disabled,1: Auto CMD12 Enabled,2: Auto CMD23 Enabled,?"
|
|
bitfld.word 0x0 1. "BCEN,Block Count Enable" "0: Block count is disabled.,1: Block count is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "DMAEN,DMA Enable" "0: DMA functionality is disabled.,1: DMA functionality is enabled."
|
|
line.word 0x2 "CR,Command Register"
|
|
hexmask.word.byte 0x2 8.--13. 1. "CMDIDX,Command Index"
|
|
bitfld.word 0x2 6.--7. "CMDTYP,Command Type" "0: Other commands,1: CMD52 to write 'Bus Suspend' in the Card Common..,2: CMD52 to write 'Function Select' in the Card..,3: CMD12 CMD52 to write 'I/O Abort' in the Card.."
|
|
newline
|
|
bitfld.word 0x2 5. "DPSEL,Data Present Select" "0,1"
|
|
bitfld.word 0x2 4. "CMDICEN,Command Index Check Enable" "0: The Command Index Check is disabled.,1: The Command Index Check is enabled."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDCCEN,Command CRC Check Enable" "0: The Command CRC Check is disabled.,1: The Command CRC Check is enabled."
|
|
bitfld.word 0x2 0.--1. "RESPTYP,Response Type" "0: No Response,1: Response Length 136,2: Response Length 48,3: Response Length 48 with Busy"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "RR[$1],Response Register"
|
|
hexmask.long 0x0 0.--31. 1. "CMDRESP,Command Response"
|
|
repeat.end
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BDPR,Buffer Data Port Register"
|
|
hexmask.long 0x0 0.--31. 1. "BUFDATA,Buffer Data"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PSR,Present State Register"
|
|
bitfld.long 0x0 24. "CMDLL,CMD Line Level" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "DATLL,DAT[3:0] Line Level"
|
|
newline
|
|
bitfld.long 0x0 11. "BUFRDEN,Buffer Read Enable" "0,1"
|
|
bitfld.long 0x0 10. "BUFWREN,Buffer Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RTACT,Read Transfer Active" "0,1"
|
|
bitfld.long 0x0 8. "WTACT,Write Transfer Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DLACT,DAT Line Active" "0,1"
|
|
bitfld.long 0x0 1. "CMDINHD,Command Inhibit (DAT)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDINHC,Command Inhibit (CMD)" "0,1"
|
|
group.byte 0x28++0x0
|
|
line.byte 0x0 "HC1R_SD_SDIO_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
bitfld.byte 0x0 0. "LEDCTRL,LED Control" "0: LED off.,1: LED on."
|
|
group.byte 0x28++0x2
|
|
line.byte 0x0 "HC1R_E_MMC_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 5. "EXTDW,Extended Data Width" "0,1"
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
newline
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0,1"
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
line.byte 0x1 "PCR,Power Control Register"
|
|
bitfld.byte 0x1 0. "SDBPWR,SD Bus Power" "0,1"
|
|
line.byte 0x2 "BGCR_SD_SDIO_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x2 3. "INTBG,Interrupt at Block Gap" "0: Interrupt detection disabled.,1: Interrupt detection enabled."
|
|
bitfld.byte 0x2 2. "RWCTRL,Read Wait Control" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 1. "CONTR,Continue Request" "0,1"
|
|
bitfld.byte 0x2 0. "STPBGR,Stop At Block Gap Request" "0,1"
|
|
group.byte 0x2A++0x1
|
|
line.byte 0x0 "BGCR_E_MMC_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x0 1. "CONTR,Continue Request" "0,1"
|
|
bitfld.byte 0x0 0. "STPBGR,Stop At Block Gap Request" "0,1"
|
|
line.byte 0x1 "WCR,Wakeup Control Register"
|
|
bitfld.byte 0x1 0. "WKENCINT,Wakeup Event Enable on Card Interrupt" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "CCR,Clock Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
bitfld.word 0x0 6.--7. "USDCLKFSEL,Upper Bits of SDCLK Frequency Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 5. "CLKGSEL,Clock Generator Select" "0,1"
|
|
bitfld.word 0x0 2. "SDCLKEN,SD Clock Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "INTCLKS,Internal Clock Stable" "0,1"
|
|
bitfld.word 0x0 0. "INTCLKEN,Internal Clock Enable" "0,1"
|
|
group.byte 0x2E++0x1
|
|
line.byte 0x0 "TCR,Timeout Control Register"
|
|
hexmask.byte 0x0 0.--3. 1. "DTCVAL,Data Timeout Counter Value"
|
|
line.byte 0x1 "SRR,Software Reset Register"
|
|
bitfld.byte 0x1 2. "SWRSTDAT,Software reset for DAT line" "0,1"
|
|
bitfld.byte 0x1 1. "SWRSTCMD,Software reset for CMD line" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "SWRSTALL,Software reset for All" "0,1"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "NISTR_SD_SDIO_MODE,Normal Interrupt Status Register"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0,1"
|
|
bitfld.word 0x0 8. "CINT,Card Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0,1"
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0,1"
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0,1"
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0,1"
|
|
group.word 0x30++0x3
|
|
line.word 0x0 "NISTR_E_MMC_MODE,Normal Interrupt Status Register"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0,1"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0,1"
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0,1"
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0,1"
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0,1"
|
|
line.word 0x2 "EISTR_SD_SDIO_MODE,Error Interrupt Status Register"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error" "0,1"
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error" "0,1"
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC error" "0,1"
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error" "0,1"
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error" "0,1"
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error" "0,1"
|
|
group.word 0x32++0x3
|
|
line.word 0x0 "EISTR_E_MMC_MODE,Error Interrupt Status Register"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error" "0,1"
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error" "0,1"
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error" "0,1"
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout error" "0,1"
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error" "0,1"
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error" "0,1"
|
|
line.word 0x2 "NISTER_SD_SDIO_MODE,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x2 8. "CINT,Card Interrupt Status Enable" "0: The CINT status flag in SDMMC_NISTR is masked.,1: The CINT status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "NISTER_E_MMC_MODE,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received Status Enable" "0: The BOOTAR status flag in SDMMC_NISTR is masked.,1: The BOOTAR status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
|
|
line.word 0x2 "EISTER_SD_SDIO_MODE,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
|
|
group.word 0x36++0x3
|
|
line.word 0x0 "EISTER_E_MMC_MODE,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error Status Enable" "0: The BOOTAE status flag in SDMMC_EISTR is masked.,1: The BOOTAE status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
|
|
line.word 0x2 "NISIER_SD_SDIO_MODE,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x2 8. "CINT,Card Interrupt Signal Enable" "0: No interrupt is generated when the CINT status..,1: An interrupt is generated when the CINT status.."
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
|
group.word 0x38++0x3
|
|
line.word 0x0 "NISIER_E_MMC_MODE,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received Signal Enable" "0: No interrupt is generated when the BOOTAR status..,1: An interrupt is generated when the BOOTAR status.."
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
|
line.word 0x2 "EISIER_SD_SDIO_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
group.word 0x3A++0x1
|
|
line.word 0x0 "EISIER_E_MMC_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error Signal Enable" "0: No interrupt is generated when the BOOTAE status..,1: An interrupt is generated when the BOOTAE status.."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
rgroup.word 0x3C++0x1
|
|
line.word 0x0 "ACESR,Auto CMD Error Status Register"
|
|
bitfld.word 0x0 7. "CMDNI,Command Not Issued by Auto CMD12 Error" "0,1"
|
|
bitfld.word 0x0 4. "ACMDIDX,Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Auto CMD End Bit Error" "0,1"
|
|
bitfld.word 0x0 2. "ACMDCRC,Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Auto CMD12 Not Executed" "0,1"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_SD_SDIO_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0,1"
|
|
bitfld.word 0x0 14. "ASINTEN,Asynchronous Interrupt Enable" "0,1"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_E_MMC_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "CA0R,Capabilities 0 Register"
|
|
bitfld.long 0x0 30.--31. "SLTYPE,Slot Type" "0: Removable Card Slot,1: Embedded Slot for One Device,?,?"
|
|
bitfld.long 0x0 29. "ASINTSUP,Asynchronous Interrupt Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "SB64SUP,64-Bit System Bus Support" "0,1"
|
|
bitfld.long 0x0 26. "V18VSUP,Voltage Support 1.8V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "V30VSUP,Voltage Support 3.0V" "0,1"
|
|
bitfld.long 0x0 24. "V33VSUP,Voltage Support 3.3V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SRSUP,Suspend/Resume Support" "0,1"
|
|
bitfld.long 0x0 22. "SDMASUP,SDMA Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "HSSUP,High Speed Support" "0,1"
|
|
bitfld.long 0x0 19. "ADMA2SUP,ADMA2 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "ED8SUP,8-Bit Support for Embedded Device" "0,1"
|
|
bitfld.long 0x0 16.--17. "MAXBLKL,Max Block Length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BASECLKF,Base Clock Frequency"
|
|
bitfld.long 0x0 7. "TEOCLKU,Timeout Clock Unit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TEOCLKF,Timeout Clock Frequency"
|
|
line.long 0x4 "CA1R,Capabilities 1 Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLKMULT,Clock Multiplier"
|
|
bitfld.long 0x4 6. "DRVDSUP,Driver Type D Support" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DRVCSUP,Driver Type C Support" "0,1"
|
|
bitfld.long 0x4 4. "DRVASUP,Driver Type A Support" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DDR50SUP,DDR50 Support" "0,1"
|
|
bitfld.long 0x4 1. "SDR104SUP,SDR104 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SDR50SUP,SDR50 Support" "0,1"
|
|
line.long 0x8 "MCCAR,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "MAXCUR18V,Maximum Current for 1.8V"
|
|
hexmask.long.byte 0x8 8.--15. 1. "MAXCUR30V,Maximum Current for 3.0V"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "MAXCUR33V,Maximum Current for 3.3V"
|
|
wgroup.word 0x50++0x3
|
|
line.word 0x0 "FERACES,Force Event Register for Auto CMD Error Status"
|
|
bitfld.word 0x0 7. "CMDNI,Force Event for Command Not Issued by Auto CMD12 Error" "0,1"
|
|
bitfld.word 0x0 4. "ACMDIDX,Force Event for Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Force Event for Auto CMD End Bit Error" "0,1"
|
|
bitfld.word 0x0 2. "ACMDCRC,Force Event for Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Force Event for Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Force Event for Auto CMD12 Not Executed" "0,1"
|
|
line.word 0x2 "FEREIS,Force Event Register for Error Interrupt Status"
|
|
bitfld.word 0x2 12. "BOOTAE,Force Event for Boot Acknowledge Error" "0,1"
|
|
bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "ACMD,Force Event for Auto CMD Error" "0,1"
|
|
bitfld.word 0x2 7. "CURLIM,Force Event for Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "DATEND,Force Event for Data End Bit Error" "0,1"
|
|
bitfld.word 0x2 5. "DATCRC,Force Event for Data CRC error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DATTEO,Force Event for Data Timeout error" "0,1"
|
|
bitfld.word 0x2 3. "CMDIDX,Force Event for Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "CMDEND,Force Event for Command End Bit Error" "0,1"
|
|
bitfld.word 0x2 1. "CMDCRC,Force Event for Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "CMDTEO,Force Event for Command Timeout Error" "0,1"
|
|
rgroup.byte 0x54++0x0
|
|
line.byte 0x0 "AESR,ADMA Error Status Register"
|
|
bitfld.byte 0x0 2. "LMIS,ADMA Length Mismatch Error" "0,1"
|
|
bitfld.byte 0x0 0.--1. "ERRST,ADMA Error State" "0: (Stop DMA) SDMMC_ASAR points to the descriptor..,1: (Fetch Descriptor) SDMMC_ASAR points to the..,?,3: (Transfer Data) SDMMC_ASAR points to the.."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ASAR0,ADMA System Address Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ADMASA,ADMA System Address"
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x60)++0x1
|
|
line.word 0x0 "PVR[$1],Preset Value Register 0 (for initialization)"
|
|
bitfld.word 0x0 10. "CLKGSEL,Clock Generator Select" "0,1"
|
|
hexmask.word 0x0 0.--9. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
repeat.end
|
|
rgroup.word 0xFC++0x3
|
|
line.word 0x0 "SISR,Slot Interrupt Status Register"
|
|
bitfld.word 0x0 0.--1. "INTSSL,Interrupt Signal for Each Slot" "0,1,2,3"
|
|
line.word 0x2 "HCVR,Host Controller Version Register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "VVER,Vendor Version Number"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SVER,Specification Version Number"
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x0 "APSR,Additional Present State Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "HDATLL,DAT[7:4] High Line Level"
|
|
group.byte 0x204++0x0
|
|
line.byte 0x0 "MC1R,e.MMC Control 1 Register"
|
|
bitfld.byte 0x0 5. "BOOTA,e.MMC Boot Acknowledge Enable" "0,1"
|
|
bitfld.byte 0x0 4. "OPD,e.MMC Open Drain Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "DDR,e.MMC HSDDR Mode" "0,1"
|
|
bitfld.byte 0x0 0.--1. "CMDTYP,e.MMC Command Type" "0: The command is not an e.MMC specific command.,1: This bit must be set to 1 when the e.MMC is in..,2: This bit must be set to 1 in the case of Stream..,3: Starts a Boot Operation mode at the next write.."
|
|
wgroup.byte 0x205++0x0
|
|
line.byte 0x0 "MC2R,e.MMC Control 2 Register"
|
|
bitfld.byte 0x0 1. "ABOOT,e.MMC Abort Boot" "0,1"
|
|
bitfld.byte 0x0 0. "SRESP,e.MMC Abort Wait IRQ" "0,1"
|
|
group.long 0x208++0x7
|
|
line.long 0x0 "ACR,AHB Control Register"
|
|
bitfld.long 0x0 5. "B1KBDIS,1kB Boundary Disable" "0,1"
|
|
bitfld.long 0x0 4. "HNBRDIS,HNBREQ Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "BMAX,AHB Maximum Burst" "0: The maximum burst size is INCR16.,1: The maximum burst size is INCR8.,2: The maximum burst size is INCR4.,3: Only SINGLE transfers are performed."
|
|
line.long 0x4 "CC2R,Clock Control 2 Register"
|
|
bitfld.long 0x4 0. "FSDCLKD,Force SDCLK Disabled" "0,1"
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x0 "TUNSR,Tuning Status Register"
|
|
bitfld.long 0x0 8. "SMPLES,Tuning Sampling SDCLK Edge Status" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DLLPS,Tuning DLL Phase Status"
|
|
group.long 0x230++0x7
|
|
line.long 0x0 "CACR,Capabilities Control Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEY,Key"
|
|
bitfld.long 0x0 0. "CAPWREN,Capabilities Write Enable" "0,1"
|
|
line.long 0x4 "DBGR,Debug Register"
|
|
bitfld.long 0x4 0. "NIDBG,Nonintrusive Debug" "0: Reading the SDMMC_BDPR via debugger increments..,1: Reading the SDMMC_BDPR via debugger does not.."
|
|
tree.end
|
|
tree "SDMMC1"
|
|
base ad:0x90000000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR,SDMA System Address / Argument 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,SDMA System Address"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR_CMD23_MODE,SDMA System Address / Argument 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG2,Argument 2"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "BSR,Block Size Register"
|
|
bitfld.word 0x0 12.--14. "BOUNDARY,SDMA Buffer Boundary" "0: 4-Kbyte boundary,1: 8-Kbyte boundary,2: 16-Kbyte boundary,3: 32-Kbyte boundary,4: 64-Kbyte boundary,5: 128-Kbyte boundary,6: 256-Kbyte boundary,7: 512-Kbyte boundary"
|
|
hexmask.word 0x0 0.--9. 1. "BLKSIZE,Transfer Block Size"
|
|
line.word 0x2 "BCR,Block Count Register"
|
|
hexmask.word 0x2 0.--15. 1. "BLKCNT,Block Count for Current Transfer"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ARG1R,Argument 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG1,Argument 1"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "TMR,Transfer Mode Register"
|
|
bitfld.word 0x0 5. "MSBSEL,Multi/Single Block Selection" "0,1"
|
|
bitfld.word 0x0 4. "DTDSEL,Data Transfer Direction Selection" "0: Writes data from the SDMMC to the device.,1: Reads data from the device to the SDMMC."
|
|
newline
|
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bitfld.word 0x0 2.--3. "ACMDEN,Auto Command Enable" "0: Auto Command Disabled,1: Auto CMD12 Enabled,2: Auto CMD23 Enabled,?"
|
|
bitfld.word 0x0 1. "BCEN,Block Count Enable" "0: Block count is disabled.,1: Block count is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "DMAEN,DMA Enable" "0: DMA functionality is disabled.,1: DMA functionality is enabled."
|
|
line.word 0x2 "CR,Command Register"
|
|
hexmask.word.byte 0x2 8.--13. 1. "CMDIDX,Command Index"
|
|
bitfld.word 0x2 6.--7. "CMDTYP,Command Type" "0: Other commands,1: CMD52 to write 'Bus Suspend' in the Card Common..,2: CMD52 to write 'Function Select' in the Card..,3: CMD12 CMD52 to write 'I/O Abort' in the Card.."
|
|
newline
|
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bitfld.word 0x2 5. "DPSEL,Data Present Select" "0,1"
|
|
bitfld.word 0x2 4. "CMDICEN,Command Index Check Enable" "0: The Command Index Check is disabled.,1: The Command Index Check is enabled."
|
|
newline
|
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bitfld.word 0x2 3. "CMDCCEN,Command CRC Check Enable" "0: The Command CRC Check is disabled.,1: The Command CRC Check is enabled."
|
|
bitfld.word 0x2 0.--1. "RESPTYP,Response Type" "0: No Response,1: Response Length 136,2: Response Length 48,3: Response Length 48 with Busy"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "RR[$1],Response Register"
|
|
hexmask.long 0x0 0.--31. 1. "CMDRESP,Command Response"
|
|
repeat.end
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BDPR,Buffer Data Port Register"
|
|
hexmask.long 0x0 0.--31. 1. "BUFDATA,Buffer Data"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PSR,Present State Register"
|
|
bitfld.long 0x0 24. "CMDLL,CMD Line Level" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "DATLL,DAT[3:0] Line Level"
|
|
newline
|
|
bitfld.long 0x0 11. "BUFRDEN,Buffer Read Enable" "0,1"
|
|
bitfld.long 0x0 10. "BUFWREN,Buffer Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RTACT,Read Transfer Active" "0,1"
|
|
bitfld.long 0x0 8. "WTACT,Write Transfer Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DLACT,DAT Line Active" "0,1"
|
|
bitfld.long 0x0 1. "CMDINHD,Command Inhibit (DAT)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDINHC,Command Inhibit (CMD)" "0,1"
|
|
group.byte 0x28++0x0
|
|
line.byte 0x0 "HC1R_SD_SDIO_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
bitfld.byte 0x0 0. "LEDCTRL,LED Control" "0: LED off.,1: LED on."
|
|
group.byte 0x28++0x2
|
|
line.byte 0x0 "HC1R_E_MMC_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 5. "EXTDW,Extended Data Width" "0,1"
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
newline
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0,1"
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
line.byte 0x1 "PCR,Power Control Register"
|
|
bitfld.byte 0x1 0. "SDBPWR,SD Bus Power" "0,1"
|
|
line.byte 0x2 "BGCR_SD_SDIO_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x2 3. "INTBG,Interrupt at Block Gap" "0: Interrupt detection disabled.,1: Interrupt detection enabled."
|
|
bitfld.byte 0x2 2. "RWCTRL,Read Wait Control" "0,1"
|
|
newline
|
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bitfld.byte 0x2 1. "CONTR,Continue Request" "0,1"
|
|
bitfld.byte 0x2 0. "STPBGR,Stop At Block Gap Request" "0,1"
|
|
group.byte 0x2A++0x1
|
|
line.byte 0x0 "BGCR_E_MMC_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x0 1. "CONTR,Continue Request" "0,1"
|
|
bitfld.byte 0x0 0. "STPBGR,Stop At Block Gap Request" "0,1"
|
|
line.byte 0x1 "WCR,Wakeup Control Register"
|
|
bitfld.byte 0x1 0. "WKENCINT,Wakeup Event Enable on Card Interrupt" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "CCR,Clock Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
bitfld.word 0x0 6.--7. "USDCLKFSEL,Upper Bits of SDCLK Frequency Select" "0,1,2,3"
|
|
newline
|
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bitfld.word 0x0 5. "CLKGSEL,Clock Generator Select" "0,1"
|
|
bitfld.word 0x0 2. "SDCLKEN,SD Clock Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "INTCLKS,Internal Clock Stable" "0,1"
|
|
bitfld.word 0x0 0. "INTCLKEN,Internal Clock Enable" "0,1"
|
|
group.byte 0x2E++0x1
|
|
line.byte 0x0 "TCR,Timeout Control Register"
|
|
hexmask.byte 0x0 0.--3. 1. "DTCVAL,Data Timeout Counter Value"
|
|
line.byte 0x1 "SRR,Software Reset Register"
|
|
bitfld.byte 0x1 2. "SWRSTDAT,Software reset for DAT line" "0,1"
|
|
bitfld.byte 0x1 1. "SWRSTCMD,Software reset for CMD line" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "SWRSTALL,Software reset for All" "0,1"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "NISTR_SD_SDIO_MODE,Normal Interrupt Status Register"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0,1"
|
|
bitfld.word 0x0 8. "CINT,Card Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0,1"
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0,1"
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0,1"
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0,1"
|
|
group.word 0x30++0x3
|
|
line.word 0x0 "NISTR_E_MMC_MODE,Normal Interrupt Status Register"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0,1"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0,1"
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0,1"
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0,1"
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0,1"
|
|
line.word 0x2 "EISTR_SD_SDIO_MODE,Error Interrupt Status Register"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error" "0,1"
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error" "0,1"
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC error" "0,1"
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error" "0,1"
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error" "0,1"
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error" "0,1"
|
|
group.word 0x32++0x3
|
|
line.word 0x0 "EISTR_E_MMC_MODE,Error Interrupt Status Register"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error" "0,1"
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error" "0,1"
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error" "0,1"
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout error" "0,1"
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error" "0,1"
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error" "0,1"
|
|
line.word 0x2 "NISTER_SD_SDIO_MODE,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x2 8. "CINT,Card Interrupt Status Enable" "0: The CINT status flag in SDMMC_NISTR is masked.,1: The CINT status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "NISTER_E_MMC_MODE,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received Status Enable" "0: The BOOTAR status flag in SDMMC_NISTR is masked.,1: The BOOTAR status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
|
|
line.word 0x2 "EISTER_SD_SDIO_MODE,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
|
|
group.word 0x36++0x3
|
|
line.word 0x0 "EISTER_E_MMC_MODE,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error Status Enable" "0: The BOOTAE status flag in SDMMC_EISTR is masked.,1: The BOOTAE status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
|
|
line.word 0x2 "NISIER_SD_SDIO_MODE,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x2 8. "CINT,Card Interrupt Signal Enable" "0: No interrupt is generated when the CINT status..,1: An interrupt is generated when the CINT status.."
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
|
group.word 0x38++0x3
|
|
line.word 0x0 "NISIER_E_MMC_MODE,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received Signal Enable" "0: No interrupt is generated when the BOOTAR status..,1: An interrupt is generated when the BOOTAR status.."
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
|
line.word 0x2 "EISIER_SD_SDIO_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
group.word 0x3A++0x1
|
|
line.word 0x0 "EISIER_E_MMC_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error Signal Enable" "0: No interrupt is generated when the BOOTAE status..,1: An interrupt is generated when the BOOTAE status.."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
rgroup.word 0x3C++0x1
|
|
line.word 0x0 "ACESR,Auto CMD Error Status Register"
|
|
bitfld.word 0x0 7. "CMDNI,Command Not Issued by Auto CMD12 Error" "0,1"
|
|
bitfld.word 0x0 4. "ACMDIDX,Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Auto CMD End Bit Error" "0,1"
|
|
bitfld.word 0x0 2. "ACMDCRC,Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Auto CMD12 Not Executed" "0,1"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_SD_SDIO_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0,1"
|
|
bitfld.word 0x0 14. "ASINTEN,Asynchronous Interrupt Enable" "0,1"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_E_MMC_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "CA0R,Capabilities 0 Register"
|
|
bitfld.long 0x0 30.--31. "SLTYPE,Slot Type" "0: Removable Card Slot,1: Embedded Slot for One Device,?,?"
|
|
bitfld.long 0x0 29. "ASINTSUP,Asynchronous Interrupt Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "SB64SUP,64-Bit System Bus Support" "0,1"
|
|
bitfld.long 0x0 26. "V18VSUP,Voltage Support 1.8V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "V30VSUP,Voltage Support 3.0V" "0,1"
|
|
bitfld.long 0x0 24. "V33VSUP,Voltage Support 3.3V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SRSUP,Suspend/Resume Support" "0,1"
|
|
bitfld.long 0x0 22. "SDMASUP,SDMA Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "HSSUP,High Speed Support" "0,1"
|
|
bitfld.long 0x0 19. "ADMA2SUP,ADMA2 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "ED8SUP,8-Bit Support for Embedded Device" "0,1"
|
|
bitfld.long 0x0 16.--17. "MAXBLKL,Max Block Length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BASECLKF,Base Clock Frequency"
|
|
bitfld.long 0x0 7. "TEOCLKU,Timeout Clock Unit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TEOCLKF,Timeout Clock Frequency"
|
|
line.long 0x4 "CA1R,Capabilities 1 Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLKMULT,Clock Multiplier"
|
|
bitfld.long 0x4 6. "DRVDSUP,Driver Type D Support" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DRVCSUP,Driver Type C Support" "0,1"
|
|
bitfld.long 0x4 4. "DRVASUP,Driver Type A Support" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DDR50SUP,DDR50 Support" "0,1"
|
|
bitfld.long 0x4 1. "SDR104SUP,SDR104 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SDR50SUP,SDR50 Support" "0,1"
|
|
line.long 0x8 "MCCAR,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "MAXCUR18V,Maximum Current for 1.8V"
|
|
hexmask.long.byte 0x8 8.--15. 1. "MAXCUR30V,Maximum Current for 3.0V"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "MAXCUR33V,Maximum Current for 3.3V"
|
|
wgroup.word 0x50++0x3
|
|
line.word 0x0 "FERACES,Force Event Register for Auto CMD Error Status"
|
|
bitfld.word 0x0 7. "CMDNI,Force Event for Command Not Issued by Auto CMD12 Error" "0,1"
|
|
bitfld.word 0x0 4. "ACMDIDX,Force Event for Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Force Event for Auto CMD End Bit Error" "0,1"
|
|
bitfld.word 0x0 2. "ACMDCRC,Force Event for Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Force Event for Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Force Event for Auto CMD12 Not Executed" "0,1"
|
|
line.word 0x2 "FEREIS,Force Event Register for Error Interrupt Status"
|
|
bitfld.word 0x2 12. "BOOTAE,Force Event for Boot Acknowledge Error" "0,1"
|
|
bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "ACMD,Force Event for Auto CMD Error" "0,1"
|
|
bitfld.word 0x2 7. "CURLIM,Force Event for Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "DATEND,Force Event for Data End Bit Error" "0,1"
|
|
bitfld.word 0x2 5. "DATCRC,Force Event for Data CRC error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DATTEO,Force Event for Data Timeout error" "0,1"
|
|
bitfld.word 0x2 3. "CMDIDX,Force Event for Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "CMDEND,Force Event for Command End Bit Error" "0,1"
|
|
bitfld.word 0x2 1. "CMDCRC,Force Event for Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "CMDTEO,Force Event for Command Timeout Error" "0,1"
|
|
rgroup.byte 0x54++0x0
|
|
line.byte 0x0 "AESR,ADMA Error Status Register"
|
|
bitfld.byte 0x0 2. "LMIS,ADMA Length Mismatch Error" "0,1"
|
|
bitfld.byte 0x0 0.--1. "ERRST,ADMA Error State" "0: (Stop DMA) SDMMC_ASAR points to the descriptor..,1: (Fetch Descriptor) SDMMC_ASAR points to the..,?,3: (Transfer Data) SDMMC_ASAR points to the.."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ASAR0,ADMA System Address Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ADMASA,ADMA System Address"
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x60)++0x1
|
|
line.word 0x0 "PVR[$1],Preset Value Register 0 (for initialization)"
|
|
bitfld.word 0x0 10. "CLKGSEL,Clock Generator Select" "0,1"
|
|
hexmask.word 0x0 0.--9. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
repeat.end
|
|
rgroup.word 0xFC++0x3
|
|
line.word 0x0 "SISR,Slot Interrupt Status Register"
|
|
bitfld.word 0x0 0.--1. "INTSSL,Interrupt Signal for Each Slot" "0,1,2,3"
|
|
line.word 0x2 "HCVR,Host Controller Version Register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "VVER,Vendor Version Number"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SVER,Specification Version Number"
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x0 "APSR,Additional Present State Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "HDATLL,DAT[7:4] High Line Level"
|
|
group.byte 0x204++0x0
|
|
line.byte 0x0 "MC1R,e.MMC Control 1 Register"
|
|
bitfld.byte 0x0 5. "BOOTA,e.MMC Boot Acknowledge Enable" "0,1"
|
|
bitfld.byte 0x0 4. "OPD,e.MMC Open Drain Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "DDR,e.MMC HSDDR Mode" "0,1"
|
|
bitfld.byte 0x0 0.--1. "CMDTYP,e.MMC Command Type" "0: The command is not an e.MMC specific command.,1: This bit must be set to 1 when the e.MMC is in..,2: This bit must be set to 1 in the case of Stream..,3: Starts a Boot Operation mode at the next write.."
|
|
wgroup.byte 0x205++0x0
|
|
line.byte 0x0 "MC2R,e.MMC Control 2 Register"
|
|
bitfld.byte 0x0 1. "ABOOT,e.MMC Abort Boot" "0,1"
|
|
bitfld.byte 0x0 0. "SRESP,e.MMC Abort Wait IRQ" "0,1"
|
|
group.long 0x208++0x7
|
|
line.long 0x0 "ACR,AHB Control Register"
|
|
bitfld.long 0x0 5. "B1KBDIS,1kB Boundary Disable" "0,1"
|
|
bitfld.long 0x0 4. "HNBRDIS,HNBREQ Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "BMAX,AHB Maximum Burst" "0: The maximum burst size is INCR16.,1: The maximum burst size is INCR8.,2: The maximum burst size is INCR4.,3: Only SINGLE transfers are performed."
|
|
line.long 0x4 "CC2R,Clock Control 2 Register"
|
|
bitfld.long 0x4 0. "FSDCLKD,Force SDCLK Disabled" "0,1"
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x0 "TUNSR,Tuning Status Register"
|
|
bitfld.long 0x0 8. "SMPLES,Tuning Sampling SDCLK Edge Status" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DLLPS,Tuning DLL Phase Status"
|
|
group.long 0x230++0x7
|
|
line.long 0x0 "CACR,Capabilities Control Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEY,Key"
|
|
bitfld.long 0x0 0. "CAPWREN,Capabilities Write Enable" "0,1"
|
|
line.long 0x4 "DBGR,Debug Register"
|
|
bitfld.long 0x4 0. "NIDBG,Nonintrusive Debug" "0: Reading the SDMMC_BDPR via debugger increments..,1: Reading the SDMMC_BDPR via debugger does not.."
|
|
tree.end
|
|
tree.end
|
|
tree "SDRAMC (SDRAM Controller)"
|
|
base ad:0xFFFFEC00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 0.--2. "MODE,SDRAMC Command Mode" "0: Normal mode. Any access to the SDRAM is decoded..,1: The SDRAMC issues a NOP command when the SDRAM..,2: The SDRAMC issues an 'All Banks Precharge'..,3: The SDRAMC issues a 'Load Mode Register' command..,4: The SDRAMC issues an 'Autorefresh' Command when..,5: The SDRAMC issues an 'Extended Load Mode..,6: Deep Powerdown mode. Enters Deep Powerdown mode.,?"
|
|
line.long 0x4 "TR,Refresh Timer Register"
|
|
hexmask.long.word 0x4 0.--11. 1. "COUNT,SDRAMC Refresh Timer Count"
|
|
line.long 0x8 "CR,Configuration Register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "TXSR,Exit Self-Refresh to Active Delay"
|
|
hexmask.long.byte 0x8 24.--27. 1. "TRAS,Active to Precharge Delay"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "TRCD,Row to Column Delay"
|
|
hexmask.long.byte 0x8 16.--19. 1. "TRP,Row Precharge Delay"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "TRC_TRFC,Row Cycle Delay and Row Refresh Cycle"
|
|
hexmask.long.byte 0x8 8.--11. 1. "TWR,Write Recovery Delay"
|
|
newline
|
|
bitfld.long 0x8 7. "DBW,Data Bus Width" "0,1"
|
|
bitfld.long 0x8 5.--6. "CAS,CAS Latency" "?,?,2: 2-cycle latency,3: 3-cycle latency"
|
|
newline
|
|
bitfld.long 0x8 4. "NB,Number of Banks" "0: 2 banks,1: 4 banks"
|
|
bitfld.long 0x8 2.--3. "NR,Number of Row Bits" "0: 11 bits to define the row number up to 2048 rows,1: 12 bits to define the row number up to 4096 rows,2: 13 bits to define the row number up to 8192 rows,?"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NC,Number of Column Bits" "0: 8 bits to define the column number up to 256..,1: 9 bits to define the column number up to 512..,2: 10 bits to define the column number up to 1024..,3: 11 bits to define the column number up to 2048.."
|
|
line.long 0xC "HSR,High-Speed Register"
|
|
bitfld.long 0xC 0. "DA,Decode Cycle Enable" "0,1"
|
|
line.long 0x10 "LPR,Low-Power Register"
|
|
bitfld.long 0x10 16. "SELFDONE,Self-refresh Done (read-only)" "0,1"
|
|
bitfld.long 0x10 14. "SELFAUTO,Self-refresh Exit Autorefresh" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12.--13. "TIMEOUT,Time to Define When Low-power Mode Is Enabled" "0: The SDRAMC activates the SDRAM Low-power mode..,1: The SDRAMC activates the SDRAM Low-power mode 64..,2: The SDRAMC activates the SDRAM Low-power mode..,?"
|
|
bitfld.long 0x10 10.--11. "DS,Drive Strength (only for low-power SDRAM)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 8.--9. "TCSR,Temperature Compensated Self-Refresh (only for low-power SDRAM)" "0,1,2,3"
|
|
bitfld.long 0x10 4.--6. "PASR,Partial Array Self-refresh (only for low-power SDRAM)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 0.--1. "LPCB,Low-power Configuration Bits" "0: The low-power feature is inhibited: no Powerdown..,1: The SDRAMC issues a Self-refresh command to the..,2: The SDRAMC issues a Powerdown Command to the..,3: The SDRAMC issues a Deep Powerdown command to.."
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "RES,Refresh Error Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 1. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "RES,Refresh Error Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 1. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "RES,Refresh Error Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 1. "SECE,Security and/or Safety Event (cleared on read)" "0,1"
|
|
bitfld.long 0x4 0. "RES,Refresh Error Status (cleared on read)" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "MDR,Memory Device Register"
|
|
bitfld.long 0x0 4.--5. "SHIFT_SAMPLING,Shift Sampling Point of Data" "?,1: Sampling point is shifted by one cycle.,2: Sampling point is shifted by two cycles.,3: Sampling point is shifted by three cycles."
|
|
bitfld.long 0x0 0.--1. "MD,Memory Device Type" "0: SDRAM,1: Low-power SDRAM,?,?"
|
|
line.long 0x4 "CFR1,Configuration Register 1"
|
|
bitfld.long 0x4 11. "CMD_MUX,Commands are Multiplexed with Address and Data" "0: Commands are not multiplexed with address and..,1: Commands are multiplexed with address and data."
|
|
bitfld.long 0x4 10. "ADD_DATA_MUX,Multiplexed Address and Data" "0: Data and address are not multiplexed,1: Data and address are multiplexed"
|
|
newline
|
|
bitfld.long 0x4 8. "UNAL,This bit must be always written to 1" "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "TMRD,Load Mode Register Command to Active or Refresh Command"
|
|
line.long 0x8 "OCMS,OCMS Register"
|
|
bitfld.long 0x8 4. "TAMPCLR,Tamper Clear Enable" "0,1"
|
|
bitfld.long 0x8 0. "SDR_SE,SDRAM Memory Controller Scrambling Enable" "0,1"
|
|
wgroup.long 0x30++0x7
|
|
line.long 0x0 "OCMS_KEY1,OCMS KEY1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY1,Off-chip Memory Scrambling (OCMS) Key Part 1"
|
|
line.long 0x4 "OCMS_KEY2,OCMS KEY2 Register"
|
|
hexmask.long 0x4 0.--31. 1. "KEY2,Off-chip Memory Scrambling (OCMS) Key Part 2"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access is performed but it does not..,1: An access is performed into some registers after.."
|
|
bitfld.long 0x0 24.--26. "SWETYP,Software Error Type (cleared on read)" "0: A write-only register has been read (Warning).,1: A write access has been performed on a read-only..,2: Access to an undefined address (Warning).,3: Write access performed into some configuration..,?,?,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "SFR (Special Function Registers)"
|
|
base ad:0xF8050000
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CCFG_EBICSA,EBI Chip Select Register"
|
|
bitfld.long 0x0 25. "DDR_MP_EN,DDR Multi-port Enable" "0,1"
|
|
bitfld.long 0x0 24. "NFD0_ON_D16,NAND Flash Databus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DQIEN_F,Force Analog Input Comparator Configuration" "0,1"
|
|
bitfld.long 0x0 16. "EBI_DRIVE,EBI I/O Drive Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EBI_DBPDC,EBI Data Bus Pulldown Configuration" "0,1"
|
|
bitfld.long 0x0 8. "EBI_DBPUC,EBI Data Bus Pullup Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EBI_CS5A,EBI Chip Select 5 Assignment" "0,1"
|
|
bitfld.long 0x0 4. "EBI_CS4A,EBI Chip Select 4 Assignment" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EBI_CS3A,EBI Chip Select 3 Assignment" "0,1"
|
|
bitfld.long 0x0 1. "EBI_CS1A,EBI Chip Select 1 Assignment" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "OHCIICR,OHCI Interrupt Configuration Register"
|
|
bitfld.long 0x0 23. "UDPPUDIS" "0,1"
|
|
bitfld.long 0x0 10. "SUSP2,USB PORTx" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SUSP1,USB PORTx" "0,1"
|
|
bitfld.long 0x0 8. "SUSP0,USB PORTx" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "APPSTART" "0,1"
|
|
bitfld.long 0x0 4. "ARIE,OHCI Asynchronous Resume Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RES2,USB PORTx Reset" "0,1"
|
|
bitfld.long 0x0 1. "RES1,USB PORTx Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RES0,USB PORTx Reset" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "OHCIISR,OHCI Interrupt Status Register"
|
|
bitfld.long 0x0 2. "RIS2,OHCI Resume Interrupt Status Port 2" "0,1"
|
|
bitfld.long 0x0 1. "RIS1,OHCI Resume Interrupt Status Port 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS0,OHCI Resume Interrupt Status Port 0" "0,1"
|
|
group.long 0x34++0xB
|
|
line.long 0x0 "UTMIHSTRIM,UTMI High-Speed Trimming Register"
|
|
bitfld.long 0x0 16.--18. "SLOPE2,UTMI HS PORTx Transceiver Slope Trimming" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. "SLOPE1,UTMI HS PORTx Transceiver Slope Trimming" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "SLOPE0,UTMI HS PORTx Transceiver Slope Trimming" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "UTMIFSTRIM,UTMI Full-Speed Trimming Register"
|
|
bitfld.long 0x4 28.--30. "ZP_CAL,FS Transceiver PMOS Impedance Calibration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24.--26. "ZN_CAL,FS Transceiver NMOS Impedance Calibration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "ZP,FS Transceiver PMOS Impedance Trimming" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 16.--18. "ZN,FS Transceiver NMOS Impedance Trimming" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UTMISWAP,UTMI DP/DM Pin Swapping Register"
|
|
bitfld.long 0x8 2. "PORT2,PORT 2 DP/DM Pin Swapping" "0: DP/DM normal pinout.,1: DP/DM swapped pinout."
|
|
bitfld.long 0x8 1. "PORT1,PORT 1 DP/DM Pin Swapping" "0: DP/DM normal pinout.,1: DP/DM swapped pinout."
|
|
newline
|
|
bitfld.long 0x8 0. "PORT0,PORT 0 DP/DM Pin Swapping" "0: DP/DM normal pinout.,1: DP/DM swapped pinout."
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "LS,Light Sleep Register"
|
|
bitfld.long 0x0 16. "MEM_POWER_GATING_ULP1_EN,Light Sleep Value for ULP1 Power-Gated Memories" "0,1"
|
|
bitfld.long 0x0 9. "LS9,Light Sleep Value (ARM926)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LS8,Light Sleep Value (ROM + OTPC)" "0,1"
|
|
bitfld.long 0x0 7. "LS7,Light Sleep Value (SRAM1 (OTPC))" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LS6,Light Sleep Value (SRAM0)" "0,1"
|
|
bitfld.long 0x0 5. "LS5,Light Sleep Value (EHCI/OHCI)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LS4,Light Sleep Value (HXDMA)" "0,1"
|
|
bitfld.long 0x0 3. "LS3,Light Sleep Value (HUSB)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "LS2,Light Sleep Value (SDMMC)" "0,1"
|
|
bitfld.long 0x0 1. "LS1,Light Sleep Value (HLCDC5)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LS0,Light Sleep Value (GFX2D)" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "SHA (Secure Hash Algorithm)"
|
|
base ad:0xF002C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "UNLOCK,Unlock Processing" "0,1"
|
|
bitfld.long 0x0 13. "WUIEHV,Write User Initial or Expected Hash Values" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "WUIHV,Write User Initial Hash Values" "0,1"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FIRST,First Block of a Message" "0,1"
|
|
bitfld.long 0x0 0. "START,Start Processing" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CHKCNT,Check Counter"
|
|
bitfld.long 0x0 24.--25. "CHECK,Hash Check" "0: No check is performed,1: Check is performed with expected hash stored in..,2: Check is performed with expected hash provided..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "DUALBUFF,Dual Input Buffer" "0: SHA_IDATARx and SHA_IODATARx cannot be written..,1: SHA_IDATARx and SHA_IODATARx can be written.."
|
|
bitfld.long 0x0 15. "TMPLCK,Tamper Lock Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "ALGO,SHA Algorithm"
|
|
bitfld.long 0x0 7. "BPE,Block Processing End" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UIEHV,User Initial or Expected Hash Value Registers" "0,1"
|
|
bitfld.long 0x0 5. "UIHV,User Initial Hash Value Registers" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PROCDLY,Processing Delay" "0: SHA processing runtime is the shortest one,1: SHA processing runtime is the longest one.."
|
|
bitfld.long 0x0 3. "AOE,Always ON Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SMOD,Start Mode" "0: Manual mode,1: Auto mode,2: SHA_IDATAR0 access only mode (mandatory when DMA..,?"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "CHECKF,Check Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "CHECKF,Check Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "CHECKF,Check Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 24. "SECE,Security and/or Safety Event" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "CHKST,Check Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx)"
|
|
newline
|
|
bitfld.long 0x4 16. "CHECKF,Check Done Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx)" "0,1"
|
|
bitfld.long 0x4 12.--14. "URAT,Unspecified Register Access Type (cleared by writing a 1 to SWRST bit in SHA_CR)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status (cleared by writing a 1 to SWRST bit in SHA_CR)" "0,1"
|
|
bitfld.long 0x4 4. "WRDY,Input Data Register Write Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared by writing a 1 to bit SWRST or START in SHA_CR or by reading SHA_IODATARx)" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "MSR,Message Size Register"
|
|
hexmask.long 0x0 0.--31. 1. "MSGSIZE,Message Size"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "BCR,Bytes Count Register"
|
|
hexmask.long 0x0 0.--31. 1. "BYTCNT,Remaining Byte Count Before Auto Padding"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "IODATAR[$1],Input/Output Data 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IODATA,Input/Output Data"
|
|
repeat.end
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 5.--6. "ACTION,Action on Abnormal Event Detection" "0: No action (stop or clear key) is performed when..,1: If a processing is in progress when the..,2: If a processing is in progress when the..,3: If a processing is in progress when the.."
|
|
newline
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Configuration Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: An access is performed into key input data.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "SHDWC (Shutdown Controller)"
|
|
base ad:0xFFFFFE10
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "SHDW_CR,Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 0. "SHDW,Shutdown Command" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "SHDW_MR,Mode Register"
|
|
bitfld.long 0x0 24.--26. "WKUPDBC,Wakeup Inputs Debouncer Period" "0: Immediate no debouncing detected active at least..,1: WKUP shall be in its active state for at least 3..,2: WKUP shall be in its active state for at least..,3: WKUP shall be in its active state for at least..,4: WKUP shall be in its active state for at least 4..,5: WKUP shall be in its active state for at least..,?,?"
|
|
bitfld.long 0x0 17. "RTCWKEN,Real-time Clock Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RTTWKEN,Real-time Timer Wakeup Enable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SHDW_SR,Status Register"
|
|
bitfld.long 0x0 16. "WKUPIS0,Wakeup 0 Input Status" "0: The wakeup 0 input is disabled or was inactive..,1: The wakeup 0 input was active at the time the.."
|
|
bitfld.long 0x0 5. "RTCWK,Real-time Clock Wakeup" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RTTWK,Real-time Timer Wakeup" "0,1"
|
|
bitfld.long 0x0 0. "WKUPS,WKUP Wakeup Status" "0: No wakeup due to the assertion of the WKUP pin..,1: At least one wakeup due to the assertion of the.."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "SHDW_WUIR,Wakeup Inputs Register"
|
|
bitfld.long 0x0 16. "WKUPT0,Wakeup 0 Input Type" "0: A falling edge followed by a low level on the..,1: A rising edge followed by a high level on the.."
|
|
bitfld.long 0x0 0. "WKUPEN0,Wakeup 0 Input Enable" "0: The wakeup 0 input has no wakeup effect.,1: The wakeup 0 input forces wakeup of the core.."
|
|
tree.end
|
|
tree "SMC (Static Memory Controller)"
|
|
base ad:0xFFFFEA00
|
|
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0xFFFFEA00 ad:0xFFFFEA10 ad:0xFFFFEA20 ad:0xFFFFEA30 ad:0xFFFFEA40 ad:0xFFFFEA50)
|
|
tree "SMC_CS_NUMBER[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "SETUP,SMC Setup Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "NCS_RD_SETUP,NCS Setup Length in READ Access"
|
|
hexmask.long.byte 0x0 16.--21. 1. "NRD_SETUP,NRD Setup Length"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "NCS_WR_SETUP,NCS Setup Length in WRITE Access"
|
|
hexmask.long.byte 0x0 0.--5. 1. "NWE_SETUP,NWE Setup Length"
|
|
line.long 0x4 "PULSE,SMC Pulse Register"
|
|
hexmask.long.byte 0x4 24.--30. 1. "NCS_RD_PULSE,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. "NRD_PULSE,NRD Pulse Length"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "NCS_WR_PULSE,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x4 0.--6. 1. "NWE_PULSE,NWE Pulse Length"
|
|
line.long 0x8 "CYCLE,SMC Cycle Register"
|
|
hexmask.long.word 0x8 16.--24. 1. "NRD_CYCLE,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. "NWE_CYCLE,Total Write Cycle Length"
|
|
line.long 0xC "MODE,SMC Mode Register"
|
|
bitfld.long 0xC 28.--29. "PS,Page Size" "0: 4-byte page,1: 8-byte page,2: 16-byte page,3: 32-byte page"
|
|
bitfld.long 0xC 24. "PMEN,Page Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "TDF_MODE,TDF Optimization" "0,1"
|
|
hexmask.long.byte 0xC 16.--19. 1. "TDF_CYCLES,Data Float Time"
|
|
newline
|
|
bitfld.long 0xC 12.--13. "DBW,Data Bus Width" "0: 8-bit bus,1: 16-bit bus,2: 32-bit bus,?"
|
|
bitfld.long 0xC 8. "BAT,Byte Access Type" "0: Byte select access type: - Write operation is..,1: Byte write access type: - Write operation is.."
|
|
newline
|
|
bitfld.long 0xC 4.--5. "EXNW_MODE,NWAIT Mode" "0: Disabled Mode-The NWAIT input signal is ignored..,?,2: Frozen Mode-If asserted the NWAIT signal freezes..,3: Ready Mode-The NWAIT signal indicates the.."
|
|
bitfld.long 0xC 1. "WRITE_MODE,Selection of the Control Signal for Write Operation" "0: Write operation controlled by NCS signal-If TDF..,1: Write operation controlled by NWE signal-If TDF.."
|
|
newline
|
|
bitfld.long 0xC 0. "READ_MODE,Selection of the Control Signal for Read Operation" "0: Read operation controlled by NCS signal - If TDF..,1: Read operation controlled by NRD signal - If TDF.."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xFFFFEA00
|
|
newline
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "OCMS,SMC Off-Chip Memory Scrambling Register"
|
|
bitfld.long 0x0 13. "CS5SE,Chip Select (x = 0 to 5) Scrambling Enable" "0,1"
|
|
bitfld.long 0x0 12. "CS4SE,Chip Select (x = 0 to 5) Scrambling Enable" "0,1"
|
|
bitfld.long 0x0 11. "CS3SE,Chip Select (x = 0 to 5) Scrambling Enable" "0,1"
|
|
bitfld.long 0x0 10. "CS2SE,Chip Select (x = 0 to 5) Scrambling Enable" "0,1"
|
|
bitfld.long 0x0 9. "CS1SE,Chip Select (x = 0 to 5) Scrambling Enable" "0,1"
|
|
bitfld.long 0x0 8. "CS0SE,Chip Select (x = 0 to 5) Scrambling Enable" "0,1"
|
|
bitfld.long 0x0 4. "TAMPCLR,Tamper Clear Enable" "0,1"
|
|
bitfld.long 0x0 0. "SMSE,Static Memory Controller Scrambling Enable" "0,1"
|
|
wgroup.long 0x84++0x7
|
|
line.long 0x0 "KEY1,SMC Off-Chip Memory Scrambling KEY1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY1,Off-Chip Memory Scrambling (OCMS) Key Part 1"
|
|
line.long 0x4 "KEY2,SMC Off-Chip Memory Scrambling KEY2 Register"
|
|
hexmask.long 0x4 0.--31. 1. "KEY2,Off-Chip Memory Scrambling (OCMS) Key Part 2"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "SRIER,SMC Safety Report Interrupt Enable Register"
|
|
bitfld.long 0x0 0. "SRIE,Safety Report Interrupt Enable" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,SMC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,SMC Write Protection Status Register"
|
|
bitfld.long 0x0 24.--25. "SWETYP,Software Error Type (Cleared on read)" "0: A write-only register has been read.,1: A write access has been performed on a read-only..,2: Access to an undefined address.,?"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (Cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (Cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (Cleared on read)" "0,1"
|
|
tree.end
|
|
tree "SSC (Synchronous Serial Controller)"
|
|
base ad:0xF0010000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 15. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 9. "TXDIS,Transmit Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXEN,Transmit Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXDIS,Receive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXEN,Receive Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CMR,Clock Mode Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "DIV,Clock Divider"
|
|
group.long 0x10++0xF
|
|
line.long 0x0 "RCMR,Receive Clock Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PERIOD,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "STTDLY,Receive Start Delay"
|
|
newline
|
|
bitfld.long 0x0 12. "STOP,Receive Stop Selection" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "START,Receive Start Selection"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CKG,Receive Clock Gating Selection" "0: None,1: Receive Clock enabled only if RF Low,2: Receive Clock enabled only if RF High,?"
|
|
bitfld.long 0x0 5. "CKI,Receive Clock Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "CKO,Receive Clock Output Mode Selection" "0: None RK pin is an input,1: Continuous Receive Clock RK pin is an output,2: Receive Clock only during data transfers RK pin..,?,?,?,?,?"
|
|
bitfld.long 0x0 0.--1. "CKS,Receive Clock Selection" "0: Divided Clock,1: TK Clock signal,2: RK pin,?"
|
|
line.long 0x4 "RFMR,Receive Frame Mode Register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "FSLEN_EXT,FSLEN Field Extension"
|
|
bitfld.long 0x4 24. "FSEDGE,Frame Sync Edge Detection" "0: Positive Edge Detection,1: Negative Edge Detection"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "FSOS,Receive Frame Sync Output Selection" "0: None RF pin is an input,1: Negative Pulse RF pin is an output,2: Positive Pulse RF pin is an output,3: Driven Low during data transfer RF pin is an..,4: Driven High during data transfer RF pin is an..,5: Toggling at each start of data transfer RF pin..,?,?"
|
|
hexmask.long.byte 0x4 16.--19. 1. "FSLEN,Receive Frame Sync Length"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "DATNB,Data Number per Frame"
|
|
bitfld.long 0x4 7. "MSBF,Most Significant Bit First" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LOOP,Loop Mode" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DATLEN,Data Length"
|
|
line.long 0x8 "TCMR,Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "PERIOD,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x8 16.--23. 1. "STTDLY,Transmit Start Delay"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "START,Transmit Start Selection"
|
|
bitfld.long 0x8 6.--7. "CKG,Transmit Clock Gating Selection" "0: None,1: Transmit Clock enabled only if TF Low,2: Transmit Clock enabled only if TF High,?"
|
|
newline
|
|
bitfld.long 0x8 5. "CKI,Transmit Clock Inversion" "0,1"
|
|
bitfld.long 0x8 2.--4. "CKO,Transmit Clock Output Mode Selection" "0: None TK pin is an input,1: Continuous Transmit Clock TK pin is an output,2: Transmit Clock only during data transfers TK pin..,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "CKS,Transmit Clock Selection" "0: Divided Clock,1: RK Clock signal,2: TK pin,?"
|
|
line.long 0xC "TFMR,Transmit Frame Mode Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "FSLEN_EXT,FSLEN Field Extension"
|
|
bitfld.long 0xC 24. "FSEDGE,Frame Sync Edge Detection" "0: Positive Edge Detection,1: Negative Edge Detection"
|
|
newline
|
|
bitfld.long 0xC 23. "FSDEN,Frame Sync Data Enable" "0,1"
|
|
bitfld.long 0xC 20.--22. "FSOS,Transmit Frame Sync Output Selection" "0: None TF pin is an input,1: Negative Pulse TF pin is an output,2: Positive Pulse TF pin is an output,3: Driven Low during data transfer,4: Driven High during data transfer,5: Toggling at each start of data transfer,?,?"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--19. 1. "FSLEN,Transmit Frame Sync Length"
|
|
hexmask.long.byte 0xC 8.--11. 1. "DATNB,Data Number per Frame"
|
|
newline
|
|
bitfld.long 0xC 7. "MSBF,Most Significant Bit First" "0,1"
|
|
bitfld.long 0xC 5. "DATDEF,Data Default Value" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "DATLEN,Data Length"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "RHR,Receive Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "RDAT,Receive Data"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "TDAT,Transmit Data"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RSHR,Receive Sync. Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RSDAT,Receive Synchronization Data"
|
|
group.long 0x34++0xB
|
|
line.long 0x0 "TSHR,Transmit Sync. Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TSDAT,Transmit Synchronization Data"
|
|
line.long 0x4 "RC0R,Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CP0,Receive Compare Data 0"
|
|
line.long 0x8 "RC1R,Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CP1,Receive Compare Data 1"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 17. "RXEN,Receive Enable" "0,1"
|
|
bitfld.long 0x0 16. "TXEN,Transmit Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RXSYN,Receive Sync" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Transmit Sync" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1" "0,1"
|
|
bitfld.long 0x0 8. "CP0,Compare 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun" "0,1"
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready" "0,1"
|
|
wgroup.long 0x44++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 11. "RXSYN,Rx Sync Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Tx Sync Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "CP0,Compare 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 11. "RXSYN,Rx Sync Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TXSYN,Tx Sync Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CP1,Compare 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "CP0,Compare 0 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRUN,Receive Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "RXRDY,Receive Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXEMPTY,Transmit Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "TXRDY,Transmit Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 11. "RXSYN,Rx Sync Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Tx Sync Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "CP0,Compare 0 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Mask" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protect Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "SYSCWP (External Interrupt Controller)"
|
|
base ad:0xFFFFFEDC
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SYSC_WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection RTC Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SYSC_WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WVSRC,Write Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Register Violation Status" "0,1"
|
|
tree.end
|
|
tree "TC (Timer/Counter)"
|
|
base ad:0x0
|
|
tree "TC0"
|
|
base ad:0xF8008000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0xF8008000 ad:0xF8008040 ad:0xF8008080)
|
|
tree "TC_CHANNEL[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0,1"
|
|
bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0,1"
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
|
|
bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [17] GCLK[45]..,1: Clock selected: internal div8 clock signal (from..,2: Clock selected: internal div32 clock signal..,3: Clock selected: internal div128 clock signal..,4: Clock selected: internal MD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
|
|
newline
|
|
bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [17] GCLK[45]..,1: Clock selected: internal div8 clock signal (from..,2: Clock selected: internal div32 clock signal..,3: Clock selected: internal div128 clock signal..,4: Clock selected: internal MD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0,1"
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0,1"
|
|
rgroup.long ($2+0xC)++0x7
|
|
line.long 0x0 "RAB,Register AB"
|
|
hexmask.long 0x0 0.--31. 1. "RAB,Register A or Register B"
|
|
line.long 0x4 "CV,Counter Value"
|
|
hexmask.long 0x4 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0,1"
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 10. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0,1"
|
|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: The trigger/capture input B is driven internally..,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
|
|
rgroup.long ($2+0x34)++0x7
|
|
line.long 0x0 "CSR,Channel Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
line.long 0x4 "SSR,Safety Status Register"
|
|
bitfld.long 0x4 31. "ECLASS,Software Error Class" "0: An abnormal access that does not have any impact.,1: An abnormal access that may have an impact."
|
|
hexmask.long.byte 0x4 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.word 0x4 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
|
|
bitfld.long 0x4 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF8008000
|
|
newline
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0,1"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
|
|
bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0,1"
|
|
bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0,1"
|
|
bitfld.long 0x0 14. "INVB,Inverted PHB" "0,1"
|
|
bitfld.long 0x0 13. "INVA,Inverted PHA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0,1"
|
|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0,1"
|
|
bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0,1"
|
|
bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0,1"
|
|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
|
|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0,1"
|
|
rgroup.long 0xDC++0x3
|
|
line.long 0x0 "QSR,QDEC Status Register"
|
|
bitfld.long 0x0 8. "DIR,Direction" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "TC1"
|
|
base ad:0xF800C000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0xF800C000 ad:0xF800C040 ad:0xF800C080)
|
|
tree "TC_CHANNEL[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0,1"
|
|
bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0,1"
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
|
|
bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [17] GCLK[45]..,1: Clock selected: internal div8 clock signal (from..,2: Clock selected: internal div32 clock signal..,3: Clock selected: internal div128 clock signal..,4: Clock selected: internal MD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
|
|
newline
|
|
bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [17] GCLK[45]..,1: Clock selected: internal div8 clock signal (from..,2: Clock selected: internal div32 clock signal..,3: Clock selected: internal div128 clock signal..,4: Clock selected: internal MD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0,1"
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0,1"
|
|
rgroup.long ($2+0xC)++0x7
|
|
line.long 0x0 "RAB,Register AB"
|
|
hexmask.long 0x0 0.--31. 1. "RAB,Register A or Register B"
|
|
line.long 0x4 "CV,Counter Value"
|
|
hexmask.long 0x4 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0,1"
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 10. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0,1"
|
|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: The trigger/capture input B is driven internally..,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
|
|
rgroup.long ($2+0x34)++0x7
|
|
line.long 0x0 "CSR,Channel Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
line.long 0x4 "SSR,Safety Status Register"
|
|
bitfld.long 0x4 31. "ECLASS,Software Error Class" "0: An abnormal access that does not have any impact.,1: An abnormal access that may have an impact."
|
|
hexmask.long.byte 0x4 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.word 0x4 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
|
|
bitfld.long 0x4 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF800C000
|
|
newline
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0,1"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
|
|
bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0,1"
|
|
bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0,1"
|
|
bitfld.long 0x0 14. "INVB,Inverted PHB" "0,1"
|
|
bitfld.long 0x0 13. "INVA,Inverted PHA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0,1"
|
|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0,1"
|
|
bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0,1"
|
|
bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0,1"
|
|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
|
|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0,1"
|
|
rgroup.long 0xDC++0x3
|
|
line.long 0x0 "QSR,QDEC Status Register"
|
|
bitfld.long 0x0 8. "DIR,Direction" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "TDES (Triple Data Encryption Standard)"
|
|
base ad:0xF0038000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "UNLOCK,Unlock Processing" "0,1"
|
|
bitfld.long 0x0 16. "LOADSEED,Loadseed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 0. "START,Start Processing" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 31. "TAMPCLR,Tamper Pin Clear Key Enable" "0,1"
|
|
bitfld.long 0x0 30. "CMTYP7,Countermeasure Type 7" "0: Countermeasure type 7 is disabled.,1: Countermeasure type 7 is enabled."
|
|
newline
|
|
bitfld.long 0x0 29. "CMTYP6,Countermeasure Type 6" "0: Countermeasure type 6 is disabled.,1: Countermeasure type 6 is enabled."
|
|
bitfld.long 0x0 28. "CMTYP5,Countermeasure Type 5" "0: Countermeasure type 5 is disabled.,1: Countermeasure type 5 is enabled."
|
|
newline
|
|
bitfld.long 0x0 27. "CMTYP4,Countermeasure Type 4" "0: Countermeasure type 4 is disabled.,1: Countermeasure type 4 is enabled."
|
|
bitfld.long 0x0 26. "CMTYP3,Countermeasure Type 3" "0: Countermeasure type 3 is disabled.,1: Countermeasure type 3 is enabled."
|
|
newline
|
|
bitfld.long 0x0 25. "CMTYP2,Countermeasure Type 2" "0: Countermeasure type 2 is disabled.,1: Countermeasure type 2 is enabled."
|
|
bitfld.long 0x0 24. "CMTYP1,Countermeasure Type 1" "0: Countermeasure type 1 is disabled.,1: Countermeasure type 1 is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "CKEY,Countermeasure Key"
|
|
bitfld.long 0x0 16.--17. "CFBS,Cipher Feedback Data Size" "0: 64-bit,1: 32-bit,2: 16-bit,3: 8-bit"
|
|
newline
|
|
bitfld.long 0x0 15. "LOD,Last Output Data Mode" "0,1"
|
|
bitfld.long 0x0 12.--13. "OPMOD,Operating Mode" "0: Electronic Code Book mode,1: Cipher Block Chaining mode,2: Output Feedback mode,3: Cipher Feedback mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "SMOD,Start Mode" "0: Manual Mode,1: Auto Mode,2: TDES_IDATAR0 accesses only Auto mode,?"
|
|
bitfld.long 0x0 7. "PKRS,Private Key Internal Register Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "PKWO,Private Key Write Once" "0,1"
|
|
bitfld.long 0x0 4. "KEYMOD,Key Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "TDESMOD,ALGORITHM Mode" "0: Single DES processing using TDES_KEY1WRy.,1: Triple DES processing using TDES_KEY1WRy..,2: XTEA processing using TDES_KEY1WRy and..,?"
|
|
bitfld.long 0x0 0. "CIPHER,Processing Mode" "0: Decrypts data.,1: Encrypts data."
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 16. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 16. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 16. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 16. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 12.--13. "URAT,Unspecified Register Access (cleared by setting TDES_CR.SWRST)" "0: TDES_IDATAR written during data processing when..,1: TDES_ODATAR read during data processing.,2: TDES_MR written during data processing.,3: Write-only register read access."
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status (cleared by setting TDES_CR.SWRST)" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared by setting TDES_CR.START or TDES_CR.SWRST or by reading TDES_ODATARx)" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "KEY1WR[$1],Key 1 Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY1W,Key 1 Word"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "KEY2WR[$1],Key 2 Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY2W,Key 2 Word"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x30)++0x3
|
|
line.long 0x0 "KEY3WR[$1],Key 3 Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY3W,Key 3 Word"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "ODATAR[$1],Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "IVR[$1],Initialization Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "IV,Initialization Vector"
|
|
repeat.end
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "XTEA_RNDR,XTEA Rounds Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "XTEA_RNDS,Number of Rounds"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 5.--7. "ACTION,Action on Abnormal Event Detection" "0: No action (stop or clear key) is performed when..,1: If a processing is in progress when the..,2: If a processing is in progress when the..,3: If a processing is in progress when the..,4: If a processing is in progress when the..,5: If a processing is in progress when the..,6: If a processing is in progress when the..,?"
|
|
newline
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: An access is performed into key input data.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
|
|
bitfld.long 0x0 4. "PKRPVS,Private Key Register Protection Violation Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0xF0030000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WAKEY,Register Write Access Key"
|
|
bitfld.long 0x0 0. "ENABLE,Enable TRNG to Provide Random Values" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 0. "HALFR,Half Rate Enable" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PKBCR,Private Key Bus Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WAKEY,Register Write Access Key"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KLENGTH,Key Length"
|
|
bitfld.long 0x0 4.--5. "KSLAVE,Key Bus Slave" "0: Selects the TDES.,1: Selects the AES.,2: Selects the OTPC.,?"
|
|
bitfld.long 0x0 0. "KID,Key ID (Must be Always Written to 0)" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 2. "EOTPKB,End Of Transfer on Private Key Bus Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 2. "EOTPKB,End Of Transfer on Private Key Bus Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 2. "EOTPKB,End Of Transfer on Private Key Bus Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 2. "EOTPKB,End Of Transfer on Private Key Bus (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "SECE,Security and/or Safety Event (cleared on read)" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared on read)" "0,1"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "ODATA,Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: Reading TRNG_ODATA when TRNG was disabled or.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "UDPHS (USB High Speed Device Port)"
|
|
base ad:0xF803C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,UDPHS Control Register"
|
|
bitfld.long 0x0 11. "PULLD_DIS,Pulldown Disable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 10. "REWAKEUP,Send Remote Wakeup (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 9. "DETACH,Detach Command" "0,1"
|
|
bitfld.long 0x0 8. "EN_UDPHS,UDPHS Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "FADDR_EN,Function Address Enable (cleared upon USB reset)" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "DEV_ADDR,UDPHS Address (cleared upon USB reset)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "FNUM,UDPHS Frame Number Register"
|
|
bitfld.long 0x0 31. "FNUM_ERR,Frame Number CRC Error (cleared upon USB reset)" "0,1"
|
|
hexmask.long.word 0x0 3.--13. 1. "FRAME_NUMBER,Frame Number as defined in the Packet Field Formats (cleared upon USB reset)"
|
|
bitfld.long 0x0 0.--2. "MICRO_FRAME_NUM,Microframe Number (cleared upon USB reset)" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "IEN,UDPHS Interrupt Enable Register"
|
|
bitfld.long 0x0 30. "DMA_6,DMA Channel 6 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 29. "DMA_5,DMA Channel 5 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 28. "DMA_4,DMA Channel 4 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 27. "DMA_3,DMA Channel 3 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "DMA_2,DMA Channel 2 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 25. "DMA_1,DMA Channel 1 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 14. "EPT_6,Endpoint 6 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 13. "EPT_5,Endpoint 5 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EPT_4,Endpoint 4 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 11. "EPT_3,Endpoint 3 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 10. "EPT_2,Endpoint 2 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 9. "EPT_1,Endpoint 1 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EPT_0,Endpoint 0 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 7. "UPSTR_RES,Upstream Resume Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 6. "ENDOFRSM,End Of Resume Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 5. "WAKE_UP,Wake Up CPU Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRESET,End Of Reset Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 3. "INT_SOF,SOF Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 2. "MICRO_SOF,Micro-SOF Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 1. "DET_SUSPD,Suspend Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "INTSTA,UDPHS Interrupt Status Register"
|
|
bitfld.long 0x0 30. "DMA_6,DMA Channel 6 Interrupt" "0,1"
|
|
bitfld.long 0x0 29. "DMA_5,DMA Channel 5 Interrupt" "0,1"
|
|
bitfld.long 0x0 28. "DMA_4,DMA Channel 4 Interrupt" "0,1"
|
|
bitfld.long 0x0 27. "DMA_3,DMA Channel 3 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "DMA_2,DMA Channel 2 Interrupt" "0,1"
|
|
bitfld.long 0x0 25. "DMA_1,DMA Channel 1 Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "EPT_6,Endpoint 6 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 13. "EPT_5,Endpoint 5 Interrupt (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EPT_4,Endpoint 4 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 11. "EPT_3,Endpoint 3 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 10. "EPT_2,Endpoint 2 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 9. "EPT_1,Endpoint 1 Interrupt (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EPT_0,Endpoint 0 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 7. "UPSTR_RES,Upstream Resume Interrupt" "0,1"
|
|
bitfld.long 0x0 6. "ENDOFRSM,End Of Resume Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "WAKE_UP,Wake Up CPU Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRESET,End Of Reset Interrupt" "0,1"
|
|
bitfld.long 0x0 3. "INT_SOF,Start Of Frame Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "MICRO_SOF,Micro Start Of Frame Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "DET_SUSPD,Suspend Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPEED,Speed Status" "0,1"
|
|
wgroup.long 0x18++0x7
|
|
line.long 0x0 "CLRINT,UDPHS Clear Interrupt Register"
|
|
bitfld.long 0x0 7. "UPSTR_RES,Upstream Resume Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 6. "ENDOFRSM,End Of Resume Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 5. "WAKE_UP,Wake Up CPU Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 4. "ENDRESET,End Of Reset Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_SOF,Start Of Frame Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 2. "MICRO_SOF,Micro Start Of Frame Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 1. "DET_SUSPD,Suspend Interrupt Clear" "0,1"
|
|
line.long 0x4 "EPTRST,UDPHS Endpoints Reset Register"
|
|
bitfld.long 0x4 6. "EPT_6,Endpoint 6 Reset" "0,1"
|
|
bitfld.long 0x4 5. "EPT_5,Endpoint 5 Reset" "0,1"
|
|
bitfld.long 0x4 4. "EPT_4,Endpoint 4 Reset" "0,1"
|
|
bitfld.long 0x4 3. "EPT_3,Endpoint 3 Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EPT_2,Endpoint 2 Reset" "0,1"
|
|
bitfld.long 0x4 1. "EPT_1,Endpoint 1 Reset" "0,1"
|
|
bitfld.long 0x4 0. "EPT_0,Endpoint 0 Reset" "0,1"
|
|
group.long 0xD0++0x13
|
|
line.long 0x0 "TSTSOFCNT,UDPHS Test SOF Counter Register"
|
|
bitfld.long 0x0 7. "SOFCTLOAD,SOF Counter Load" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SOFCNTMAX,SOF Counter Max Value"
|
|
line.long 0x4 "TSTCNTA,UDPHS Test A Counter Register"
|
|
bitfld.long 0x4 15. "CNTALOAD,A Counter Load" "0,1"
|
|
hexmask.long.word 0x4 0.--14. 1. "CNTAMAX,A Counter Max Value"
|
|
line.long 0x8 "TSTCNTB,UDPHS Test B Counter Register"
|
|
bitfld.long 0x8 15. "CNTBLOAD,B Counter Load" "0,1"
|
|
hexmask.long.word 0x8 0.--14. 1. "CNTBMAX,B Counter Max Value"
|
|
line.long 0xC "TSTMODEREG,UDPHS Test Mode Register"
|
|
hexmask.long.byte 0xC 1.--5. 1. "TSTMODE,UDPHS Core TestModeReg"
|
|
line.long 0x10 "TST,UDPHS Test Register"
|
|
bitfld.long 0x10 5. "OPMODE2,OpMode2" "0,1"
|
|
bitfld.long 0x10 4. "TST_PKT,Test Packet Mode" "0,1"
|
|
bitfld.long 0x10 3. "TST_K,Test K Mode" "0,1"
|
|
bitfld.long 0x10 2. "TST_J,Test J Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--1. "SPEED_CFG,Speed Configuration" "0: Normal mode: The macro is in Full Speed mode..,?,2: Force High Speed: Set this value to force the..,3: Force Full Speed: Set this value to force the.."
|
|
repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0xF803C100 ad:0xF803C120 ad:0xF803C140 ad:0xF803C160 ad:0xF803C180 ad:0xF803C1A0 ad:0xF803C1C0)
|
|
tree "UDPHS_EPT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "EPTCFG,UDPHS Endpoint Configuration Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "EPT_MAPD,Endpoint Mapped (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 8.--9. "NB_TRANS,Number Of Transactions per Microframe (cleared upon USB reset)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "BK_NUMBER,Number of Banks (cleared upon USB reset)" "0: Zero bank the endpoint is not mapped in memory,1: One bank (bank 0),2: Double bank (Ping-Pong: bank0/bank1),3: Triple bank (bank0/bank1/bank2)"
|
|
bitfld.long 0x0 4.--5. "EPT_TYPE,Endpoint Type (cleared upon USB reset)" "0: Control endpoint,1: Isochronous endpoint,2: Bulk endpoint,3: Interrupt endpoint"
|
|
newline
|
|
bitfld.long 0x0 3. "EPT_DIR,Endpoint Direction (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 0.--2. "EPT_SIZE,Endpoint Size (cleared upon USB reset)" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes,4: 128 bytes,5: 256 bytes,6: 512 bytes,7: 1024 bytes"
|
|
wgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "EPTCTLENB,UDPHS Endpoint Control Enable Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet Send/Short Packet Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "BUSY_BANK,Busy Bank Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "NAK_OUT,NAKOUT Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "NAK_IN,NAKIN Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "STALL_SNT,Stall Sent Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "RX_SETUP,Received SETUP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXRDY,TX Packet Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "NYET_DIS,NYET Disable (Only for High Speed Bulk OUT endpoints)" "0,1"
|
|
bitfld.long 0x0 3. "INTDIS_DMA,Interrupts Disable DMA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_VALID,Packet Auto-Valid Enable" "0,1"
|
|
bitfld.long 0x0 0. "EPT_ENABL,Endpoint Enable" "0,1"
|
|
wgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "EPTCTLENB_ISOENDPT_MODE,UDPHS Endpoint Control Enable Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet Send/Short Packet Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "BUSY_BANK,Busy Bank Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "ERR_FLUSH,Bank Flush Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 13. "ERR_CRC_NTR,ISO CRC Error/Number of Transaction Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ERR_FL_ISO,Error Flow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "TXRDY_TRER,TX Packet Ready/Transaction Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "MDATA_RX,MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATAX_RX,DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)" "0,1"
|
|
bitfld.long 0x0 3. "INTDIS_DMA,Interrupts Disable DMA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_VALID,Packet Auto-Valid Enable" "0,1"
|
|
bitfld.long 0x0 0. "EPT_ENABL,Endpoint Enable" "0,1"
|
|
line.long 0x4 "EPTCTLDIS,UDPHS Endpoint Control Disable Register (endpoint = 0)"
|
|
bitfld.long 0x4 31. "SHRT_PCKT,Short Packet Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "BUSY_BANK,Busy Bank Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "NAK_OUT,NAKOUT Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "NAK_IN,NAKIN Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "STALL_SNT,Stall Sent Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "RX_SETUP,Received SETUP Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXRDY,TX Packet Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "TX_COMPLT,Transmitted IN Data Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RXRDY_TXKL,Received OUT Data Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "ERR_OVFLW,Overflow Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NYET_DIS,NYET Enable (Only for High Speed Bulk OUT endpoints)" "0,1"
|
|
bitfld.long 0x4 3. "INTDIS_DMA,Interrupts Disable DMA" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "AUTO_VALID,Packet Auto-Valid Disable" "0,1"
|
|
bitfld.long 0x4 0. "EPT_DISABL,Endpoint Disable" "0,1"
|
|
wgroup.long ($2+0x8)++0x3
|
|
line.long 0x0 "EPTCTLDIS_ISOENDPT_MODE,UDPHS Endpoint Control Disable Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 18. "BUSY_BANK,Busy Bank Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "ERR_FLUSH,bank flush error Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 13. "ERR_CRC_NTR,ISO CRC Error/Number of Transaction Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ERR_FL_ISO,Error Flow Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 11. "TXRDY_TRER,TX Packet Ready/Transaction Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 7. "MDATA_RX,MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATAX_RX,DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)" "0,1"
|
|
bitfld.long 0x0 3. "INTDIS_DMA,Interrupts Disable DMA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_VALID,Packet Auto-Valid Disable" "0,1"
|
|
bitfld.long 0x0 0. "EPT_DISABL,Endpoint Disable" "0,1"
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "EPTCTL,UDPHS Endpoint Control Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 18. "BUSY_BANK,Busy Bank Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "NAK_OUT,NAKOUT Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 14. "NAK_IN,NAKIN Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "STALL_SNT,Stall Sent Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 12. "RX_SETUP,Received SETUP Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXRDY,TX Packet Ready Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "NYET_DIS,NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 3. "INTDIS_DMA,Interrupt Disables DMA (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_VALID,Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 0. "EPT_ENABL,Endpoint Enable (cleared upon USB reset)" "0,1"
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "EPTCTL_ISOENDPT_MODE,UDPHS Endpoint Control Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 18. "BUSY_BANK,Busy Bank Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "ERR_FLUSH,Bank Flush Error Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 13. "ERR_CRC_NTR,ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ERR_FL_ISO,Error Flow Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 11. "TXRDY_TRER,TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 7. "MDATA_RX,MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATAX_RX,DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 3. "INTDIS_DMA,Interrupt Disables DMA (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_VALID,Packet Auto-Valid Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 0. "EPT_ENABL,Endpoint Enable (cleared upon USB reset)" "0,1"
|
|
wgroup.long ($2+0x14)++0x3
|
|
line.long 0x0 "EPTSETSTA,UDPHS Endpoint Set Status Register (endpoint = 0)"
|
|
bitfld.long 0x0 11. "TXRDY,TX Packet Ready Set" "0,1"
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,KILL Bank Set (for IN Endpoint)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "FRCESTALL,Stall Handshake Request Set" "0,1"
|
|
wgroup.long ($2+0x14)++0x7
|
|
line.long 0x0 "EPTSETSTA_ISOENDPT_MODE,UDPHS Endpoint Set Status Register (endpoint = 0)"
|
|
bitfld.long 0x0 11. "TXRDY_TRER,TX Packet Ready Set" "0,1"
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,KILL Bank Set (for IN Endpoint)" "0,1"
|
|
line.long 0x4 "EPTCLRSTA,UDPHS Endpoint Clear Status Register (endpoint = 0)"
|
|
bitfld.long 0x4 15. "NAK_OUT,NAKOUT Clear" "0,1"
|
|
bitfld.long 0x4 14. "NAK_IN,NAKIN Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "STALL_SNT,Stall Sent Clear" "0,1"
|
|
bitfld.long 0x4 12. "RX_SETUP,Received SETUP Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "TX_COMPLT,Transmitted IN Data Complete Clear" "0,1"
|
|
bitfld.long 0x4 9. "RXRDY_TXKL,Received OUT Data Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TOGGLESQ,Data Toggle Clear" "0,1"
|
|
bitfld.long 0x4 5. "FRCESTALL,Stall Handshake Request Clear" "0,1"
|
|
wgroup.long ($2+0x18)++0x3
|
|
line.long 0x0 "EPTCLRSTA_ISOENDPT_MODE,UDPHS Endpoint Clear Status Register (endpoint = 0)"
|
|
bitfld.long 0x0 14. "ERR_FLUSH,Bank Flush Error Clear" "0,1"
|
|
bitfld.long 0x0 13. "ERR_CRC_NTR,Number of Transaction Error Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ERR_FL_ISO,Error Flow Clear" "0,1"
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data Clear" "0,1"
|
|
bitfld.long 0x0 6. "TOGGLESQ,Data Toggle Clear" "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "EPTSTA,UDPHS Endpoint Status Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet (cleared upon USB reset)" "0,1"
|
|
hexmask.long.word 0x0 20.--30. 1. "BYTE_COUNT,UDPHS Byte Count (cleared upon USB reset)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "BUSY_BANK_STA,Busy Bank Number (cleared upon USB reset)" "0: All banks are free,1: 1 busy bank,2: 2 busy banks,3: 3 busy banks"
|
|
bitfld.long 0x0 16.--17. "CURBK_CTLDIR,Current Bank/Control Direction (cleared upon USB reset)" "0: Bank 0 (or single bank),1: Bank 1,2: Bank 2,?"
|
|
newline
|
|
bitfld.long 0x0 15. "NAK_OUT,NAK OUT (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 14. "NAK_IN,NAK IN (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "STALL_SNT,Stall Sent (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 12. "RX_SETUP,Received SETUP (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXRDY,TX Packet Ready (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data/KILL Bank (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TOGGLESQ_STA,Toggle Sequencing (cleared upon USB reset)" "0: DATA0,1: DATA1,2: Reserved for High Bandwidth Isochronous Endpoint,3: Reserved for High Bandwidth Isochronous Endpoint"
|
|
bitfld.long 0x0 5. "FRCESTALL,Stall Handshake Request (cleared upon USB reset)" "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "EPTSTA_ISOENDPT_MODE,UDPHS Endpoint Status Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet (cleared upon USB reset)" "0,1"
|
|
hexmask.long.word 0x0 20.--30. 1. "BYTE_COUNT,UDPHS Byte Count (cleared upon USB reset)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "BUSY_BANK_STA,Busy Bank Number (cleared upon USB reset)" "0: All banks are free,1: 1 busy bank,2: 2 busy banks,3: 3 busy banks"
|
|
bitfld.long 0x0 16.--17. "CURBK,Current Bank (cleared upon USB reset)" "0: Bank 0 (or single bank),1: Bank 1,2: Bank 2,?"
|
|
newline
|
|
bitfld.long 0x0 14. "ERR_FLUSH,Bank Flush Error (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 13. "ERR_CRC_NTR,CRC ISO Error/Number of Transaction Error (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ERR_FL_ISO,Error Flow (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 11. "TXRDY_TRER,TX Packet Ready/Transaction Error (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data/KILL Bank (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 6.--7. "TOGGLESQ_STA,Toggle Sequencing (cleared upon USB reset)" "0: DATA0,1: DATA1,2: Data2 (only for High Bandwidth Isochronous..,3: MData (only for High Bandwidth Isochronous.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0xF803C310 ad:0xF803C320 ad:0xF803C330 ad:0xF803C340 ad:0xF803C350 ad:0xF803C360)
|
|
tree "UDPHS_DMA$1"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "DMANXTDSC,UDPHS DMA Next Descriptor Address Register (channel = 0)"
|
|
hexmask.long 0x0 0.--31. 1. "NXT_DSC_ADD,Next Descriptor Address"
|
|
line.long 0x4 "DMAADDRESS,UDPHS DMA Channel Address Register (channel = 0)"
|
|
hexmask.long 0x4 0.--31. 1. "BUFF_ADD,Buffer Address"
|
|
line.long 0x8 "DMACONTROL,UDPHS DMA Channel Control Register (channel = 0)"
|
|
hexmask.long.word 0x8 16.--31. 1. "BUFF_LENGTH,Buffer Byte Length (Write-only)"
|
|
bitfld.long 0x8 7. "BURST_LCK,Burst Lock Enable" "0,1"
|
|
bitfld.long 0x8 6. "DESC_LD_IT,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 5. "END_BUFFIT,End of Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 4. "END_TR_IT,End of Transfer Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 3. "END_B_EN,End of Buffer Enable (Control)" "0,1"
|
|
bitfld.long 0x8 2. "END_TR_EN,End of Transfer Enable (Control)" "0,1"
|
|
bitfld.long 0x8 1. "LDNXT_DSC,Load Next Channel Transfer Descriptor Enable (Command)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CHANN_ENB,(Channel Enable Command)" "0,1"
|
|
line.long 0xC "DMASTATUS,UDPHS DMA Channel Status Register (channel = 0)"
|
|
hexmask.long.word 0xC 16.--31. 1. "BUFF_COUNT,Buffer Byte Count"
|
|
bitfld.long 0xC 6. "DESC_LDST,Descriptor Loaded Status" "0,1"
|
|
bitfld.long 0xC 5. "END_BF_ST,End of Channel Buffer Status" "0,1"
|
|
bitfld.long 0xC 4. "END_TR_ST,End of Channel Transfer Status" "0,1"
|
|
bitfld.long 0xC 1. "CHANN_ACT,Channel Active Status" "0,1"
|
|
bitfld.long 0xC 0. "CHANN_ENB,Channel Enable Status" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "UHPHS (USB Host High Speed Port)"
|
|
base ad:0x0
|
|
tree "UHPHS_EHCI"
|
|
base ad:0x700000
|
|
rgroup.long 0x0++0xB
|
|
line.long 0x0 "HCCAPBASE,UHPHS Host Controller Capability Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "HCIVERSION,Host Controller Interface Version Number"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CAPLENGTH,Capability Registers Length"
|
|
line.long 0x4 "HCSPARAMS,UHPHS Host Controller Structural Parameters Register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "N_DP,Debug Port Number"
|
|
bitfld.long 0x4 16. "P_INDICATOR,Port Indicators" "0,1"
|
|
hexmask.long.byte 0x4 12.--15. 1. "N_CC,Number of Companion Controllers"
|
|
hexmask.long.byte 0x4 8.--11. 1. "N_PCC,Number of Ports per Companion Controller"
|
|
newline
|
|
bitfld.long 0x4 4. "PPC,Port Power Control" "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "N_PORTS,Number of Ports"
|
|
line.long 0x8 "HCCPARAMS,UHPHS Host Controller Capability Parameters Register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "EECP,EHCI Extended Capabilities Pointer"
|
|
hexmask.long.byte 0x8 4.--7. 1. "IST,Isochronous Scheduling Threshold"
|
|
bitfld.long 0x8 2. "ASPC,Asynchronous Schedule Park Capability" "0,1"
|
|
bitfld.long 0x8 1. "PFLF,Programmable Frame List Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "AC,64-bit Addressing Capability" "0,1"
|
|
group.long 0x10++0x1B
|
|
line.long 0x0 "USBCMD,UHPHS USB Command Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ITC,Interrupt Threshold Control (read/write)"
|
|
bitfld.long 0x0 11. "ASPME,Asynchronous Schedule Park Mode Enable (optional) (read/write or read-only)" "0,1"
|
|
bitfld.long 0x0 8.--9. "ASPMC,Asynchronous Schedule Park Mode Count (optional) (read/write or read-only)" "0,1,2,3"
|
|
bitfld.long 0x0 7. "LHCR,Light Host Controller Reset (optional) (read/write)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IAAD,Interrupt on Async Advance Doorbell (read/write)" "0,1"
|
|
bitfld.long 0x0 5. "ASE,Asynchronous Schedule Enable (read/write)" "0,1"
|
|
bitfld.long 0x0 4. "PSE,Periodic Schedule Enable (read/write)" "0,1"
|
|
bitfld.long 0x0 2.--3. "FLS,Frame List Size (read/write or read-only)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "HCRESET,Host Controller Reset (read/write)" "0,1"
|
|
bitfld.long 0x0 0. "RS,Run/Stop (read/write)" "0,1"
|
|
line.long 0x4 "USBSTS,UHPHS USB Status Register"
|
|
bitfld.long 0x4 15. "ASS,Asynchronous Schedule Status (read-only)" "0,1"
|
|
bitfld.long 0x4 14. "PSS,Periodic Schedule Status (read-only)" "0,1"
|
|
bitfld.long 0x4 13. "RCM,Reclamation (read-only)" "0,1"
|
|
bitfld.long 0x4 12. "HCHLT,HCHalted (read-only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "IAA,Interrupt on Async Advance (cleared on write)" "0,1"
|
|
bitfld.long 0x4 4. "HSE,Host System Error (cleared on write)" "0,1"
|
|
bitfld.long 0x4 3. "FLR,Frame List Rollover (cleared on write)" "0,1"
|
|
bitfld.long 0x4 2. "PCD,Port Change Detect (cleared on write)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "USBERRINT,USB Error Interrupt (cleared on write)" "0,1"
|
|
bitfld.long 0x4 0. "USBINT,USB Interrupt (cleared on write)" "0,1"
|
|
line.long 0x8 "USBINTR,UHPHS USB Interrupt Enable Register"
|
|
bitfld.long 0x8 5. "IAAE,Interrupt on Async Advance Enable" "0,1"
|
|
bitfld.long 0x8 4. "HSEE,Host System Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 3. "FLRE,Frame List Rollover Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "PCIE,Port Change Detect Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "USBEIE,USBERRINT Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 0. "USBIE,USBINT Interrupt Enable" "0,1"
|
|
line.long 0xC "FRINDEX,UHPHS USB Frame Index Register"
|
|
hexmask.long.word 0xC 0.--13. 1. "FI,Frame Index"
|
|
line.long 0x10 "CTRLDSSEGMENT,UHPHS Control Data Structure Segment Register"
|
|
line.long 0x14 "PERIODICLISTBASE,UHPHS Periodic Frame List Base Address Register"
|
|
hexmask.long.tbyte 0x14 12.--31. 1. "BA,Base Address (Low)"
|
|
line.long 0x18 "ASYNCLISTADDR,UHPHS Asynchronous List Address Register"
|
|
hexmask.long 0x18 5.--31. 1. "LPL,Link Pointer Low"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "CONFIGFLAG,UHPHS Configured Flag Register"
|
|
bitfld.long 0x0 0. "CF,Configure Flag (Read/Write)" "0,1"
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x54)++0x3
|
|
line.long 0x0 "PORTSC[$1],UHPHS Port Status and Control Register (port = 0)"
|
|
bitfld.long 0x0 22. "WKOC_E,Wake on Over-current Enable (read/write)" "0,1"
|
|
bitfld.long 0x0 21. "WKDSCNNT_E,Wake on Disconnect Enable (read/write)" "0,1"
|
|
bitfld.long 0x0 20. "WKCNNT_E,Wake on Connect Enable (read/write)" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PTC,Port Test Control (read/write)"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "PIC,Port Indicator Control (read/write)" "0,1,2,3"
|
|
bitfld.long 0x0 13. "PO,Port Owner (read/write)" "0,1"
|
|
bitfld.long 0x0 12. "PP,Port Power (read/write or read-only)" "0,1"
|
|
bitfld.long 0x0 10.--11. "LS,Line Status (read-only)" "0: Not a low-speed device perform EHCI reset,1: Low-speed device release ownership of port,2: Not a low-speed device perform EHCI reset,3: Not a low-speed device perform EHCI reset"
|
|
newline
|
|
bitfld.long 0x0 8. "PR,Port Reset (read/write)" "0,1"
|
|
bitfld.long 0x0 7. "SUS,Suspend (read/write)" "0,1"
|
|
bitfld.long 0x0 6. "FPR,Force Port Resume (read/write)" "0,1"
|
|
bitfld.long 0x0 5. "OCC,Over-current Change (read/write clear)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "OCA,Over-current Active (read-only)" "0,1"
|
|
bitfld.long 0x0 3. "PEDC,Port Enable/Disable Change (read/write clear)" "0,1"
|
|
bitfld.long 0x0 2. "PED,Port Enabled/Disabled (read/write)" "0,1"
|
|
bitfld.long 0x0 1. "CSC,Connect Status Change (read/write clear)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CCS,Current Connect Status (read-only)" "0,1"
|
|
repeat.end
|
|
group.long 0xA8++0x7
|
|
line.long 0x0 "INSNREG06,EHCI Specific Registers 06"
|
|
bitfld.long 0x0 31. "AHB_ERR,AHB Error" "0,1"
|
|
bitfld.long 0x0 9.--11. "HBURST,Burst Value (Read-only)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 4.--8. 1. "Nb_Burst,Number of Bursts (Read-only)"
|
|
hexmask.long.byte 0x0 0.--3. 1. "Nb_Success_Burst,Number of Successful Bursts (Read-only)"
|
|
line.long 0x4 "INSNREG07,EHCI Specific Registers 07"
|
|
hexmask.long 0x4 0.--31. 1. "AHB_ADDR,AHB Address (Read Only)"
|
|
tree.end
|
|
tree "UHPHS_OHCI"
|
|
base ad:0x600000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "HcRevision,OHCI Revision Number Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "REV,OHCI Revision Number"
|
|
group.long 0x4++0x4F
|
|
line.long 0x0 "HcControl,HC Operating Mode Register"
|
|
bitfld.long 0x0 10. "RWE,Remote Wakeup Enable" "0,1"
|
|
bitfld.long 0x0 9. "RWC,Remote Wakeup Connected" "0,1"
|
|
bitfld.long 0x0 8. "IR,Interrupt Routing" "0,1"
|
|
bitfld.long 0x0 6.--7. "HCFS,Host Controller Functional State" "0,1,2,3"
|
|
bitfld.long 0x0 5. "BLE,Bulk List Enable" "0,1"
|
|
bitfld.long 0x0 4. "CLE,ControL List Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "IE,Isochronous Enable" "0,1"
|
|
bitfld.long 0x0 2. "PLE,Periodic List Enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CBSR,Control/Bulk Service Ratio" "0,1,2,3"
|
|
line.long 0x4 "HcCommandStatus,HC Command and Status Register"
|
|
bitfld.long 0x4 16.--17. "SOC,Scheduling Overrun Count (read-only)" "0,1,2,3"
|
|
bitfld.long 0x4 3. "OCR,Ownership Change Request (read/write)" "0,1"
|
|
bitfld.long 0x4 2. "BLF,Bulk List Filled (read/write)" "0,1"
|
|
bitfld.long 0x4 1. "CLF,Control List Filled (read/write)" "0,1"
|
|
bitfld.long 0x4 0. "HCR,Host Controller Reset (read/write)" "0,1"
|
|
line.long 0x8 "HcInterruptStatus,HC Interrupt and Status Register"
|
|
bitfld.long 0x8 30. "OC,Ownership Change (read-only)" "0,1"
|
|
bitfld.long 0x8 6. "RHSC,Root Hub Status Change (read/write write '1' to clear)" "0,1"
|
|
bitfld.long 0x8 5. "FNO,Frame Number Overflow (read/write write '1' to clear)" "0,1"
|
|
bitfld.long 0x8 4. "UE,Unrecoverable Error (read/write write '1' to clear)" "0,1"
|
|
bitfld.long 0x8 3. "RD,Resume Detected (read/write write '1' to clear)" "0,1"
|
|
bitfld.long 0x8 2. "SF,Start of Frame (read/write write '1' to clear)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "WDH,Write Done Head (read/write write '1' to clear)" "0,1"
|
|
bitfld.long 0x8 0. "SO,Scheduling Overrun (read/write write '1' to clear)" "0,1"
|
|
line.long 0xC "HcInterruptEnable,HC Interrupt Enable Register"
|
|
bitfld.long 0xC 31. "MIE,Master Interrupt Enable (read/write write '1' to set)" "0,1"
|
|
bitfld.long 0xC 30. "OC,Ownership Change (read-only)" "0,1"
|
|
bitfld.long 0xC 6. "RHSC,Root Hub Status Change (read/write write '1' to set)" "0,1"
|
|
bitfld.long 0xC 5. "FNO,Frame Number Overflow (read/write write '1' to set)" "0,1"
|
|
bitfld.long 0xC 4. "UE,Unrecoverable Error (read/write write '1' to set)" "0,1"
|
|
bitfld.long 0xC 3. "RD,Resume Detected (read/write write '1' to set)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "SF,Start of Frame (read/write write '1' to set)" "0,1"
|
|
bitfld.long 0xC 1. "WDH,Write Done Head (read/write write '1' to set)" "0,1"
|
|
bitfld.long 0xC 0. "SO,Scheduling Overrun (read/write write '1' to set)" "0,1"
|
|
line.long 0x10 "HcInterruptDisable,HC Interrupt Disable Register"
|
|
bitfld.long 0x10 31. "MIE,Master Interrupt Enable (read/write)" "0,1"
|
|
bitfld.long 0x10 30. "OC,Ownership Change (read-only)" "0,1"
|
|
bitfld.long 0x10 6. "RHSC,Root Hub Status Change (read/write)" "0,1"
|
|
bitfld.long 0x10 5. "FNO,Frame Number Overflow (read/write)" "0,1"
|
|
bitfld.long 0x10 4. "UE,Unrecoverable Error (read/write)" "0,1"
|
|
bitfld.long 0x10 3. "RD,Resume Detected (read/write)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "SF,Start of Frame (read/write)" "0,1"
|
|
bitfld.long 0x10 1. "WDH,Write Done Head (read/write)" "0,1"
|
|
bitfld.long 0x10 0. "SO,Scheduling Overrun (read/write)" "0,1"
|
|
line.long 0x14 "HcHCCA,HC HCCA Address Register"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "HCCA,Physical Address of the Beginning of the HCCA"
|
|
line.long 0x18 "HcPeriodCurrentED,HC Current Periodic Register"
|
|
hexmask.long 0x18 4.--31. 1. "PCED,Physical Address of the Current ED on the Periodic ED list"
|
|
line.long 0x1C "HcControlHeadED,HC Head Control Register"
|
|
hexmask.long 0x1C 4.--31. 1. "CHED,Physical Address of the Head ED on the Control ED list"
|
|
line.long 0x20 "HcControlCurrentED,HC Current Control Register"
|
|
hexmask.long 0x20 4.--31. 1. "CCED,Physical Address of the Current ED on the Control ED List"
|
|
line.long 0x24 "HcBulkHeadED,HC Head Bulk Register"
|
|
hexmask.long 0x24 4.--31. 1. "BHED,Physical Address of the Head ED on the Bulk ED List"
|
|
line.long 0x28 "HcBulkCurrentED,HC Current Bulk Register"
|
|
hexmask.long 0x28 4.--31. 1. "BCED,Physical Address of the Current ED on the Bulk ED List"
|
|
line.long 0x2C "HcDoneHead,HC Head Done Register"
|
|
hexmask.long 0x2C 4.--31. 1. "DH,Physical Address of the Last TD that has added to the done queue"
|
|
line.long 0x30 "HcFmInterval,HC Frame Interval Register"
|
|
bitfld.long 0x30 31. "FIT,Frame Interval Toggle" "0,1"
|
|
hexmask.long.word 0x30 16.--30. 1. "FSMPS,Largest Data Packet"
|
|
hexmask.long.word 0x30 0.--13. 1. "FRAMEINTERVAL,Frame Interval"
|
|
line.long 0x34 "HcFmRemaining,HC Frame Remaining Register"
|
|
bitfld.long 0x34 31. "FRT,Frame Remaining Toggle" "0,1"
|
|
hexmask.long.word 0x34 0.--13. 1. "FR,Frame Remaining"
|
|
line.long 0x38 "HcFmNumber,HC Frame Number Register"
|
|
hexmask.long.word 0x38 0.--15. 1. "FN,Frame Number"
|
|
line.long 0x3C "HcPeriodicStart,HC Periodic Start Register"
|
|
hexmask.long.word 0x3C 0.--13. 1. "PS,Periodic Start"
|
|
line.long 0x40 "HcLSThreshold,HC Low-Speed Threshold Register"
|
|
hexmask.long.word 0x40 0.--13. 1. "LST,Low-Speed Threshold"
|
|
line.long 0x44 "HcRhDescriptorA,HC Root Hub A Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. "POTPG,Power-On to Power-good Time (read/write)"
|
|
bitfld.long 0x44 12. "NOCP,No Overcurrent Protection (read/write)" "0,1"
|
|
bitfld.long 0x44 11. "OCPM,Overcurrent Protection Mode (read/write)" "0,1"
|
|
bitfld.long 0x44 10. "DT,Device Type (read-only)" "0,1"
|
|
bitfld.long 0x44 9. "NPS,No Power Switching (read/write)" "0,1"
|
|
bitfld.long 0x44 8. "PSM,Power Switching Mode (read/write)" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--7. 1. "NDP,Number of Downstream Ports (read-only)"
|
|
line.long 0x48 "HcRhDescriptorB,HC Root Hub B Register"
|
|
bitfld.long 0x48 31. "PPCM15,Port Power Control Mask" "0,1"
|
|
bitfld.long 0x48 30. "PPCM14,Port Power Control Mask" "0,1"
|
|
bitfld.long 0x48 29. "PPCM13,Port Power Control Mask" "0,1"
|
|
bitfld.long 0x48 28. "PPCM12,Port Power Control Mask" "0,1"
|
|
bitfld.long 0x48 27. "PPCM11,Port Power Control Mask" "0,1"
|
|
bitfld.long 0x48 26. "PPCM10,Port Power Control Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x48 25. "PPCM9,Port Power Control Mask" "0,1"
|
|
bitfld.long 0x48 24. "PPCM8,Port Power Control Mask" "0,1"
|
|
bitfld.long 0x48 23. "PPCM7,Port Power Control Mask" "0,1"
|
|
bitfld.long 0x48 22. "PPCM6,Port Power Control Mask" "0,1"
|
|
bitfld.long 0x48 21. "PPCM5,Port Power Control Mask" "0,1"
|
|
bitfld.long 0x48 20. "PPCM4,Port Power Control Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x48 19. "PPCM3,Port Power Control Mask for Downstream Port 3" "0,1"
|
|
bitfld.long 0x48 18. "PPCM2,Port Power Control Mask for Downstream Port 2" "0,1"
|
|
bitfld.long 0x48 17. "PPCM1,Port Power Control Mask for Downstream Port 1" "0,1"
|
|
bitfld.long 0x48 16. "PPCM0,Port Power Control Mask" "0,1"
|
|
bitfld.long 0x48 15. "DR15,Device Removable" "0,1"
|
|
bitfld.long 0x48 14. "DR14,Device Removable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 13. "DR13,Device Removable" "0,1"
|
|
bitfld.long 0x48 12. "DR12,Device Removable" "0,1"
|
|
bitfld.long 0x48 11. "DR11,Device Removable" "0,1"
|
|
bitfld.long 0x48 10. "DR10,Device Removable" "0,1"
|
|
bitfld.long 0x48 9. "DR9,Device Removable" "0,1"
|
|
bitfld.long 0x48 8. "DR8,Device Removable" "0,1"
|
|
newline
|
|
bitfld.long 0x48 7. "DR7,Device Removable" "0,1"
|
|
bitfld.long 0x48 6. "DR6,Device Removable" "0,1"
|
|
bitfld.long 0x48 5. "DR5,Device Removable" "0,1"
|
|
bitfld.long 0x48 4. "DR4,Device Removable" "0,1"
|
|
bitfld.long 0x48 3. "DR3,Device Removable Bit for Downstream Port 3" "0,1"
|
|
bitfld.long 0x48 2. "DR2,Device Removable Bit for Downstream Port 2" "0,1"
|
|
newline
|
|
bitfld.long 0x48 1. "DR1,Device Removable Bit for Downstream Port 1" "0,1"
|
|
bitfld.long 0x48 0. "DR0,Device Removable" "0,1"
|
|
line.long 0x4C "HcRhStatus,HC Root Hub Status Register"
|
|
bitfld.long 0x4C 31. "CRWE,Clear Remote Wakeup Enable (read/write)" "0,1"
|
|
bitfld.long 0x4C 17. "OCIC,Overcurrent Indication Change (read/write)" "0,1"
|
|
bitfld.long 0x4C 16. "LPSC,Local Power Status Change (read/write)" "0,1"
|
|
bitfld.long 0x4C 15. "DRWE,Device Remote Wakeup Enable (read/write)" "0,1"
|
|
bitfld.long 0x4C 1. "OCI,Overcurrent Indicator (read-only)" "0,1"
|
|
bitfld.long 0x4C 0. "LPS,Local Power Status (read/write)" "0,1"
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x54)++0x3
|
|
line.long 0x0 "HcRhPortStatus[$1],HC Port Status and Control Register (ndp = 0)"
|
|
bitfld.long 0x0 20. "PRSC,Port Reset Status Change (read/write write '1' to clear)" "0,1"
|
|
bitfld.long 0x0 19. "OCIC,Overcurrent Indicator Change (read/write)" "0,1"
|
|
bitfld.long 0x0 18. "PSSC,Port Suspend Status Change (read/write write '1' to clear)" "0,1"
|
|
bitfld.long 0x0 17. "PESC,Port Enable Status Change (read/write write '1' to clear)" "0,1"
|
|
bitfld.long 0x0 16. "CSC,Connect Status Change (read/write write '1' to clear)" "0,1"
|
|
bitfld.long 0x0 9. "LSDA,Low-speed Device Attached/clear Port Power (read/write)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PPS,Port Power Status/set Port Power (read/write)" "0,1"
|
|
bitfld.long 0x0 4. "PRS,Port Reset Status/set Port Reset (read/write)" "0,1"
|
|
bitfld.long 0x0 3. "POCI,Port Overcurrent Indicator/clear Suspend Status (read/write)" "0,1"
|
|
bitfld.long 0x0 2. "PSS,Port Suspend Status/set Port Suspend (read/write)" "0,1"
|
|
bitfld.long 0x0 1. "PES,Port Enable Status/set Port Enable (read/write)" "0,1"
|
|
bitfld.long 0x0 0. "CCS,Port Current Connection Status/clear Port Enable (read/write)" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0xFFFFFF80
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 4. "LOCKMR,Lock Mode Register Write Access" "0,1"
|
|
bitfld.long 0x0 0. "WDRSTT,Watchdog Restart" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 29. "WDIDLEHLT,Watchdog Idle Halt" "0,1"
|
|
bitfld.long 0x0 28. "WDDBGHLT,Watchdog Debug Halt" "0,1"
|
|
bitfld.long 0x0 12. "WDDIS,Watchdog Disable" "0,1"
|
|
bitfld.long 0x0 5. "RPTHRST,Minimum Restart Period" "0,1"
|
|
bitfld.long 0x0 4. "PERIODRST,Period Reset" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "VR,Value Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "COUNTER,Watchdog Down Counter Value"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "WLR,Window Level Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "RPTH,Repeat Threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "PERIOD,Watchdog Period"
|
|
line.long 0x4 "ILR,Interrupt Level Register"
|
|
hexmask.long.word 0x4 0.--11. 1. "LVLTH,Level Threshold"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 2. "LVLINT,Interrupt Level Threshold Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "RPTHINT,Repeat Threshold Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "PERINT,Period Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 2. "LVLINT,Interrupt Level Threshold Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "RPTHINT,Repeat Threshold Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "PERINT,Period Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x0 2. "LVLINT,Interrupt Level Threshold Interrupt Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "RPTHINT,Repeat Threshold Interrupt Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "PERINT,Period Interrupt Status (cleared on read)" "0,1"
|
|
line.long 0x4 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x4 2. "LVLINT,Interrupt Level Threshold Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 1. "RPTHINT,Repeat Threshold Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 0. "PERINT,Period Interrupt Mask" "0,1"
|
|
tree.end
|
|
tree "XDMAC (Extensible DMA Controller)"
|
|
base ad:0xF0008000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "GTYPE,Global Type Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "NB_REQ,Number of Peripheral Requests Minus One"
|
|
hexmask.long.word 0x0 5.--15. 1. "FIFO_SZ,Number of Bytes"
|
|
hexmask.long.byte 0x0 0.--4. 1. "NB_CH,Number of Channels Minus One"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "GCFG,Global Configuration Register"
|
|
bitfld.long 0x0 8. "BXKBEN,Boundary X Kilobyte Enable" "0,1"
|
|
bitfld.long 0x0 3. "CGDISIF,Bus Interface Clock Gating Disable" "0,1"
|
|
bitfld.long 0x0 2. "CGDISFIFO,FIFO Clock Gating Disable" "0,1"
|
|
bitfld.long 0x0 1. "CGDISPIPE,Pipeline Clock Gating Disable" "0,1"
|
|
bitfld.long 0x0 0. "CGDISREG,Configuration Registers Clock Gating Disable" "0,1"
|
|
line.long 0x4 "GWAC,Global Weighted Arbiter Configuration Register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "PW3,Pool Weight 3"
|
|
hexmask.long.byte 0x4 8.--11. 1. "PW2,Pool Weight 2"
|
|
hexmask.long.byte 0x4 4.--7. 1. "PW1,Pool Weight 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PW0,Pool Weight 0"
|
|
wgroup.long 0xC++0x7
|
|
line.long 0x0 "GIE,Global Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "IE15,XDMAC Channel 15 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "IE14,XDMAC Channel 14 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 13. "IE13,XDMAC Channel 13 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "IE12,XDMAC Channel 12 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "IE11,XDMAC Channel 11 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "IE10,XDMAC Channel 10 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "IE9,XDMAC Channel 9 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "IE8,XDMAC Channel 8 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "IE7,XDMAC Channel 7 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "IE6,XDMAC Channel 6 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IE5,XDMAC Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "IE4,XDMAC Channel 4 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "IE3,XDMAC Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "IE2,XDMAC Channel 2 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "IE1,XDMAC Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "IE0,XDMAC Channel 0 Interrupt Enable" "0,1"
|
|
line.long 0x4 "GID,Global Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "ID15,XDMAC Channel 15 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "ID14,XDMAC Channel 14 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 13. "ID13,XDMAC Channel 13 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "ID12,XDMAC Channel 12 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 11. "ID11,XDMAC Channel 11 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "ID10,XDMAC Channel 10 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "ID9,XDMAC Channel 9 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "ID8,XDMAC Channel 8 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "ID7,XDMAC Channel 7 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "ID6,XDMAC Channel 6 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ID5,XDMAC Channel 5 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "ID4,XDMAC Channel 4 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "ID3,XDMAC Channel 3 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "ID2,XDMAC Channel 2 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "ID1,XDMAC Channel 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "ID0,XDMAC Channel 0 Interrupt Disable" "0,1"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "GIM,Global Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "IM15,XDMAC Channel 15 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "IM14,XDMAC Channel 14 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 13. "IM13,XDMAC Channel 13 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "IM12,XDMAC Channel 12 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 11. "IM11,XDMAC Channel 11 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "IM10,XDMAC Channel 10 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "IM9,XDMAC Channel 9 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "IM8,XDMAC Channel 8 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "IM7,XDMAC Channel 7 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "IM6,XDMAC Channel 6 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IM5,XDMAC Channel 5 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "IM4,XDMAC Channel 4 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "IM3,XDMAC Channel 3 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "IM2,XDMAC Channel 2 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "IM1,XDMAC Channel 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "IM0,XDMAC Channel 0 Interrupt Mask" "0,1"
|
|
line.long 0x4 "GIS,Global Interrupt Status Register"
|
|
bitfld.long 0x4 15. "IS15,XDMAC Channel 15 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 14. "IS14,XDMAC Channel 14 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 13. "IS13,XDMAC Channel 13 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "IS12,XDMAC Channel 12 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 11. "IS11,XDMAC Channel 11 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "IS10,XDMAC Channel 10 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 9. "IS9,XDMAC Channel 9 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "IS8,XDMAC Channel 8 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 7. "IS7,XDMAC Channel 7 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "IS6,XDMAC Channel 6 Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "IS5,XDMAC Channel 5 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "IS4,XDMAC Channel 4 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 3. "IS3,XDMAC Channel 3 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "IS2,XDMAC Channel 2 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "IS1,XDMAC Channel 1 Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "IS0,XDMAC Channel 0 Interrupt Status" "0,1"
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "GE,Global Channel Enable Register"
|
|
bitfld.long 0x0 15. "EN15,XDMAC Channel 15 Enable" "0,1"
|
|
bitfld.long 0x0 14. "EN14,XDMAC Channel 14 Enable" "0,1"
|
|
bitfld.long 0x0 13. "EN13,XDMAC Channel 13 Enable" "0,1"
|
|
bitfld.long 0x0 12. "EN12,XDMAC Channel 12 Enable" "0,1"
|
|
bitfld.long 0x0 11. "EN11,XDMAC Channel 11 Enable" "0,1"
|
|
bitfld.long 0x0 10. "EN10,XDMAC Channel 10 Enable" "0,1"
|
|
bitfld.long 0x0 9. "EN9,XDMAC Channel 9 Enable" "0,1"
|
|
bitfld.long 0x0 8. "EN8,XDMAC Channel 8 Enable" "0,1"
|
|
bitfld.long 0x0 7. "EN7,XDMAC Channel 7 Enable" "0,1"
|
|
bitfld.long 0x0 6. "EN6,XDMAC Channel 6 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EN5,XDMAC Channel 5 Enable" "0,1"
|
|
bitfld.long 0x0 4. "EN4,XDMAC Channel 4 Enable" "0,1"
|
|
bitfld.long 0x0 3. "EN3,XDMAC Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 2. "EN2,XDMAC Channel 2 Enable" "0,1"
|
|
bitfld.long 0x0 1. "EN1,XDMAC Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 0. "EN0,XDMAC Channel 0 Enable" "0,1"
|
|
line.long 0x4 "GD,Global Channel Disable Register"
|
|
bitfld.long 0x4 15. "DI15,XDMAC Channel 15 Disable" "0,1"
|
|
bitfld.long 0x4 14. "DI14,XDMAC Channel 14 Disable" "0,1"
|
|
bitfld.long 0x4 13. "DI13,XDMAC Channel 13 Disable" "0,1"
|
|
bitfld.long 0x4 12. "DI12,XDMAC Channel 12 Disable" "0,1"
|
|
bitfld.long 0x4 11. "DI11,XDMAC Channel 11 Disable" "0,1"
|
|
bitfld.long 0x4 10. "DI10,XDMAC Channel 10 Disable" "0,1"
|
|
bitfld.long 0x4 9. "DI9,XDMAC Channel 9 Disable" "0,1"
|
|
bitfld.long 0x4 8. "DI8,XDMAC Channel 8 Disable" "0,1"
|
|
bitfld.long 0x4 7. "DI7,XDMAC Channel 7 Disable" "0,1"
|
|
bitfld.long 0x4 6. "DI6,XDMAC Channel 6 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DI5,XDMAC Channel 5 Disable" "0,1"
|
|
bitfld.long 0x4 4. "DI4,XDMAC Channel 4 Disable" "0,1"
|
|
bitfld.long 0x4 3. "DI3,XDMAC Channel 3 Disable" "0,1"
|
|
bitfld.long 0x4 2. "DI2,XDMAC Channel 2 Disable" "0,1"
|
|
bitfld.long 0x4 1. "DI1,XDMAC Channel 1 Disable" "0,1"
|
|
bitfld.long 0x4 0. "DI0,XDMAC Channel 0 Disable" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "GS,Global Channel Status Register"
|
|
bitfld.long 0x0 15. "ST15,XDMAC Channel 15 Status" "0,1"
|
|
bitfld.long 0x0 14. "ST14,XDMAC Channel 14 Status" "0,1"
|
|
bitfld.long 0x0 13. "ST13,XDMAC Channel 13 Status" "0,1"
|
|
bitfld.long 0x0 12. "ST12,XDMAC Channel 12 Status" "0,1"
|
|
bitfld.long 0x0 11. "ST11,XDMAC Channel 11 Status" "0,1"
|
|
bitfld.long 0x0 10. "ST10,XDMAC Channel 10 Status" "0,1"
|
|
bitfld.long 0x0 9. "ST9,XDMAC Channel 9 Status" "0,1"
|
|
bitfld.long 0x0 8. "ST8,XDMAC Channel 8 Status" "0,1"
|
|
bitfld.long 0x0 7. "ST7,XDMAC Channel 7 Status" "0,1"
|
|
bitfld.long 0x0 6. "ST6,XDMAC Channel 6 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ST5,XDMAC Channel 5 Status" "0,1"
|
|
bitfld.long 0x0 4. "ST4,XDMAC Channel 4 Status" "0,1"
|
|
bitfld.long 0x0 3. "ST3,XDMAC Channel 3 Status" "0,1"
|
|
bitfld.long 0x0 2. "ST2,XDMAC Channel 2 Status" "0,1"
|
|
bitfld.long 0x0 1. "ST1,XDMAC Channel 1 Status" "0,1"
|
|
bitfld.long 0x0 0. "ST0,XDMAC Channel 0 Status" "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "GRS,Global Channel Read Suspend Register"
|
|
bitfld.long 0x0 15. "RS15,XDMAC Channel 15 Read Suspend" "0,1"
|
|
bitfld.long 0x0 14. "RS14,XDMAC Channel 14 Read Suspend" "0,1"
|
|
bitfld.long 0x0 13. "RS13,XDMAC Channel 13 Read Suspend" "0,1"
|
|
bitfld.long 0x0 12. "RS12,XDMAC Channel 12 Read Suspend" "0,1"
|
|
bitfld.long 0x0 11. "RS11,XDMAC Channel 11 Read Suspend" "0,1"
|
|
bitfld.long 0x0 10. "RS10,XDMAC Channel 10 Read Suspend" "0,1"
|
|
bitfld.long 0x0 9. "RS9,XDMAC Channel 9 Read Suspend" "0,1"
|
|
bitfld.long 0x0 8. "RS8,XDMAC Channel 8 Read Suspend" "0,1"
|
|
bitfld.long 0x0 7. "RS7,XDMAC Channel 7 Read Suspend" "0,1"
|
|
bitfld.long 0x0 6. "RS6,XDMAC Channel 6 Read Suspend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RS5,XDMAC Channel 5 Read Suspend" "0,1"
|
|
bitfld.long 0x0 4. "RS4,XDMAC Channel 4 Read Suspend" "0,1"
|
|
bitfld.long 0x0 3. "RS3,XDMAC Channel 3 Read Suspend" "0,1"
|
|
bitfld.long 0x0 2. "RS2,XDMAC Channel 2 Read Suspend" "0,1"
|
|
bitfld.long 0x0 1. "RS1,XDMAC Channel 1 Read Suspend" "0,1"
|
|
bitfld.long 0x0 0. "RS0,XDMAC Channel 0 Read Suspend" "0,1"
|
|
line.long 0x4 "GWS,Global Channel Write Suspend Register"
|
|
bitfld.long 0x4 15. "WS15,XDMAC Channel 15 Write Suspend" "0,1"
|
|
bitfld.long 0x4 14. "WS14,XDMAC Channel 14 Write Suspend" "0,1"
|
|
bitfld.long 0x4 13. "WS13,XDMAC Channel 13 Write Suspend" "0,1"
|
|
bitfld.long 0x4 12. "WS12,XDMAC Channel 12 Write Suspend" "0,1"
|
|
bitfld.long 0x4 11. "WS11,XDMAC Channel 11 Write Suspend" "0,1"
|
|
bitfld.long 0x4 10. "WS10,XDMAC Channel 10 Write Suspend" "0,1"
|
|
bitfld.long 0x4 9. "WS9,XDMAC Channel 9 Write Suspend" "0,1"
|
|
bitfld.long 0x4 8. "WS8,XDMAC Channel 8 Write Suspend" "0,1"
|
|
bitfld.long 0x4 7. "WS7,XDMAC Channel 7 Write Suspend" "0,1"
|
|
bitfld.long 0x4 6. "WS6,XDMAC Channel 6 Write Suspend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "WS5,XDMAC Channel 5 Write Suspend" "0,1"
|
|
bitfld.long 0x4 4. "WS4,XDMAC Channel 4 Write Suspend" "0,1"
|
|
bitfld.long 0x4 3. "WS3,XDMAC Channel 3 Write Suspend" "0,1"
|
|
bitfld.long 0x4 2. "WS2,XDMAC Channel 2 Write Suspend" "0,1"
|
|
bitfld.long 0x4 1. "WS1,XDMAC Channel 1 Write Suspend" "0,1"
|
|
bitfld.long 0x4 0. "WS0,XDMAC Channel 0 Write Suspend" "0,1"
|
|
wgroup.long 0x30++0xB
|
|
line.long 0x0 "GRWS,Global Channel Read Write Suspend Register"
|
|
bitfld.long 0x0 15. "RWS15,XDMAC Channel 15 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 14. "RWS14,XDMAC Channel 14 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 13. "RWS13,XDMAC Channel 13 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 12. "RWS12,XDMAC Channel 12 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 11. "RWS11,XDMAC Channel 11 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 10. "RWS10,XDMAC Channel 10 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 9. "RWS9,XDMAC Channel 9 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 8. "RWS8,XDMAC Channel 8 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 7. "RWS7,XDMAC Channel 7 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 6. "RWS6,XDMAC Channel 6 Read Write Suspend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RWS5,XDMAC Channel 5 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 4. "RWS4,XDMAC Channel 4 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 3. "RWS3,XDMAC Channel 3 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 2. "RWS2,XDMAC Channel 2 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 1. "RWS1,XDMAC Channel 1 Read Write Suspend" "0,1"
|
|
bitfld.long 0x0 0. "RWS0,XDMAC Channel 0 Read Write Suspend" "0,1"
|
|
line.long 0x4 "GRWR,Global Channel Read Write Resume Register"
|
|
bitfld.long 0x4 15. "RWR15,XDMAC Channel 15 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 14. "RWR14,XDMAC Channel 14 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 13. "RWR13,XDMAC Channel 13 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 12. "RWR12,XDMAC Channel 12 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 11. "RWR11,XDMAC Channel 11 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 10. "RWR10,XDMAC Channel 10 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 9. "RWR9,XDMAC Channel 9 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 8. "RWR8,XDMAC Channel 8 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 7. "RWR7,XDMAC Channel 7 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 6. "RWR6,XDMAC Channel 6 Read Write Resume" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RWR5,XDMAC Channel 5 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 4. "RWR4,XDMAC Channel 4 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 3. "RWR3,XDMAC Channel 3 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 2. "RWR2,XDMAC Channel 2 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 1. "RWR1,XDMAC Channel 1 Read Write Resume" "0,1"
|
|
bitfld.long 0x4 0. "RWR0,XDMAC Channel 0 Read Write Resume" "0,1"
|
|
line.long 0x8 "GSWR,Global Channel Software Request Register"
|
|
bitfld.long 0x8 15. "SWREQ15,XDMAC Channel 15 Software Request" "0,1"
|
|
bitfld.long 0x8 14. "SWREQ14,XDMAC Channel 14 Software Request" "0,1"
|
|
bitfld.long 0x8 13. "SWREQ13,XDMAC Channel 13 Software Request" "0,1"
|
|
bitfld.long 0x8 12. "SWREQ12,XDMAC Channel 12 Software Request" "0,1"
|
|
bitfld.long 0x8 11. "SWREQ11,XDMAC Channel 11 Software Request" "0,1"
|
|
bitfld.long 0x8 10. "SWREQ10,XDMAC Channel 10 Software Request" "0,1"
|
|
bitfld.long 0x8 9. "SWREQ9,XDMAC Channel 9 Software Request" "0,1"
|
|
bitfld.long 0x8 8. "SWREQ8,XDMAC Channel 8 Software Request" "0,1"
|
|
bitfld.long 0x8 7. "SWREQ7,XDMAC Channel 7 Software Request" "0,1"
|
|
bitfld.long 0x8 6. "SWREQ6,XDMAC Channel 6 Software Request" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SWREQ5,XDMAC Channel 5 Software Request" "0,1"
|
|
bitfld.long 0x8 4. "SWREQ4,XDMAC Channel 4 Software Request" "0,1"
|
|
bitfld.long 0x8 3. "SWREQ3,XDMAC Channel 3 Software Request" "0,1"
|
|
bitfld.long 0x8 2. "SWREQ2,XDMAC Channel 2 Software Request" "0,1"
|
|
bitfld.long 0x8 1. "SWREQ1,XDMAC Channel 1 Software Request" "0,1"
|
|
bitfld.long 0x8 0. "SWREQ0,XDMAC Channel 0 Software Request" "0,1"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "GSWS,Global Channel Software Request Status Register"
|
|
bitfld.long 0x0 15. "SWRS15,XDMAC Channel 15 Software Request Status" "0,1"
|
|
bitfld.long 0x0 14. "SWRS14,XDMAC Channel 14 Software Request Status" "0,1"
|
|
bitfld.long 0x0 13. "SWRS13,XDMAC Channel 13 Software Request Status" "0,1"
|
|
bitfld.long 0x0 12. "SWRS12,XDMAC Channel 12 Software Request Status" "0,1"
|
|
bitfld.long 0x0 11. "SWRS11,XDMAC Channel 11 Software Request Status" "0,1"
|
|
bitfld.long 0x0 10. "SWRS10,XDMAC Channel 10 Software Request Status" "0,1"
|
|
bitfld.long 0x0 9. "SWRS9,XDMAC Channel 9 Software Request Status" "0,1"
|
|
bitfld.long 0x0 8. "SWRS8,XDMAC Channel 8 Software Request Status" "0,1"
|
|
bitfld.long 0x0 7. "SWRS7,XDMAC Channel 7 Software Request Status" "0,1"
|
|
bitfld.long 0x0 6. "SWRS6,XDMAC Channel 6 Software Request Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SWRS5,XDMAC Channel 5 Software Request Status" "0,1"
|
|
bitfld.long 0x0 4. "SWRS4,XDMAC Channel 4 Software Request Status" "0,1"
|
|
bitfld.long 0x0 3. "SWRS3,XDMAC Channel 3 Software Request Status" "0,1"
|
|
bitfld.long 0x0 2. "SWRS2,XDMAC Channel 2 Software Request Status" "0,1"
|
|
bitfld.long 0x0 1. "SWRS1,XDMAC Channel 1 Software Request Status" "0,1"
|
|
bitfld.long 0x0 0. "SWRS0,XDMAC Channel 0 Software Request Status" "0,1"
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "GSWF,Global Channel Software Flush Request Register"
|
|
bitfld.long 0x0 15. "SWF15,XDMAC Channel 15 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 14. "SWF14,XDMAC Channel 14 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 13. "SWF13,XDMAC Channel 13 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 12. "SWF12,XDMAC Channel 12 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 11. "SWF11,XDMAC Channel 11 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 10. "SWF10,XDMAC Channel 10 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 9. "SWF9,XDMAC Channel 9 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 8. "SWF8,XDMAC Channel 8 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 7. "SWF7,XDMAC Channel 7 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 6. "SWF6,XDMAC Channel 6 Software Flush Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SWF5,XDMAC Channel 5 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 4. "SWF4,XDMAC Channel 4 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 3. "SWF3,XDMAC Channel 3 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 2. "SWF2,XDMAC Channel 2 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 1. "SWF1,XDMAC Channel 1 Software Flush Request" "0,1"
|
|
bitfld.long 0x0 0. "SWF0,XDMAC Channel 0 Software Flush Request" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0xF0008050 ad:0xF0008090 ad:0xF00080D0 ad:0xF0008110 ad:0xF0008150 ad:0xF0008190 ad:0xF00081D0 ad:0xF0008210 ad:0xF0008250 ad:0xF0008290 ad:0xF00082D0 ad:0xF0008310 ad:0xF0008350 ad:0xF0008390 ad:0xF00083D0 ad:0xF0008410)
|
|
tree "XDMAC_CHID[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x7
|
|
line.long 0x0 "CIE,Channel Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "ROIE,Request Overflow Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "WBIE,Write Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RBIE,Read Bus Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "FIE,End of Flush Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DIE,End of Disable Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "LIE,End of Linked List Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BIE,End of Block Interrupt Enable" "0,1"
|
|
line.long 0x4 "CID,Channel Interrupt Disable Register"
|
|
bitfld.long 0x4 6. "ROID,Request Overflow Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "WBEID,Write Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RBEID,Read Bus Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "FID,End of Flush Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DID,End of Disable Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "LID,End of Linked List Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "BID,End of Block Interrupt Disable" "0,1"
|
|
rgroup.long ($2+0x8)++0x7
|
|
line.long 0x0 "CIM,Channel Interrupt Mask Register"
|
|
bitfld.long 0x0 6. "ROIM,Request Overflow Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "WBEIM,Write Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RBEIM,Read Bus Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "FIM,End of Flush Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DIM,End of Disable Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "LIM,End of Linked List Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BIM,End of Block Interrupt Mask" "0,1"
|
|
line.long 0x4 "CIS,Channel Interrupt Status Register"
|
|
bitfld.long 0x4 6. "ROIS,Request Overflow Error Interrupt Status" "0,1"
|
|
bitfld.long 0x4 5. "WBEIS,Write Bus Error Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RBEIS,Read Bus Error Interrupt Status" "0,1"
|
|
bitfld.long 0x4 3. "FIS,End of Flush Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DIS,End of Disable Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "LIS,End of Linked List Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "BIS,End of Block Interrupt Status" "0,1"
|
|
group.long ($2+0x10)++0x27
|
|
line.long 0x0 "CSA,Channel Source Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "SA,Channel 0 Source Address"
|
|
line.long 0x4 "CDA,Channel Destination Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "DA,Channel 0 Destination Address"
|
|
line.long 0x8 "CNDA,Channel Next Descriptor Address Register"
|
|
hexmask.long 0x8 2.--31. 1. "NDA,Channel 0 Next Descriptor Address"
|
|
bitfld.long 0x8 0. "NDAIF,Channel 0 Next Descriptor Interface" "0,1"
|
|
line.long 0xC "CNDC,Channel Next Descriptor Control Register"
|
|
bitfld.long 0xC 5.--6. "QOS,Channel Quality Of Service Level" "0,1,2,3"
|
|
bitfld.long 0xC 3.--4. "NDVIEW,Channel 0 Next Descriptor View" "0: Next Descriptor View 0,1: Next Descriptor View 1,2: Next Descriptor View 2,3: Next Descriptor View 3"
|
|
newline
|
|
bitfld.long 0xC 2. "NDDUP,Channel 0 Next Descriptor Destination Update" "0: Destination parameters remain unchanged.,1: Destination parameters are updated when the.."
|
|
bitfld.long 0xC 1. "NDSUP,Channel 0 Next Descriptor Source Update" "0: Source parameters remain unchanged.,1: Source parameters are updated when the.."
|
|
newline
|
|
bitfld.long 0xC 0. "NDE,Channel 0 Next Descriptor Enable" "0: Descriptor fetch is disabled.,1: Descriptor fetch is enabled."
|
|
line.long 0x10 "CUBC,Channel Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "UBLEN,Channel 0 Microblock Length"
|
|
line.long 0x14 "CBC,Channel Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. "BLEN,Channel 0 Block Length"
|
|
line.long 0x18 "CC,Channel Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. "PERID,Channel 0 Peripheral Hardware Request Line Identifier"
|
|
bitfld.long 0x18 23. "WRIP,Write in Progress (this bit is read-only)" "0: No active write transaction on the bus.,1: A write transaction is in progress."
|
|
newline
|
|
bitfld.long 0x18 22. "RDIP,Read in Progress (this bit is read-only)" "0: No active read transaction on the bus.,1: A read transaction is in progress."
|
|
bitfld.long 0x18 21. "INITD,Channel Initialization Done (this bit is read-only)" "0: Channel initialization is in progress.,1: Channel initialization is completed."
|
|
newline
|
|
bitfld.long 0x18 18.--19. "DAM,Channel 0 Destination Addressing Mode" "0: The address remains unchanged.,1: The addressing mode is incremented (the..,2: The microblock stride is added at the microblock..,3: The microblock stride is added at the microblock.."
|
|
bitfld.long 0x18 16.--17. "SAM,Channel 0 Source Addressing Mode" "0: The address remains unchanged.,1: The addressing mode is incremented (the..,2: The microblock stride is added at the microblock..,3: The microblock stride is added at the microblock.."
|
|
newline
|
|
bitfld.long 0x18 14. "DIF,Channel 0 Destination Interface Identifier" "0: The data is written through system bus interface..,1: The data is written though system bus interface 1."
|
|
bitfld.long 0x18 13. "SIF,Channel 0 Source Interface Identifier" "0: The data is read through system bus interface 0.,1: The data is read through system bus interface 1."
|
|
newline
|
|
bitfld.long 0x18 11.--12. "DWIDTH,Channel 0 Data Width" "0: The data size is set to 8 bits,1: The data size is set to 16 bits,2: The data size is set to 32 bits,?"
|
|
bitfld.long 0x18 8.--10. "CSIZE,Channel 0 Chunk Size" "0: 1 data transferred,1: 2 data transferred,2: 4 data transferred,3: 8 data transferred,4: 16 data transferred,?,?,?"
|
|
newline
|
|
bitfld.long 0x18 7. "MEMSET,Channel 0 Fill Block of Memory" "0: Memset is not activated.,1: Sets the block of memory pointed by DA field to.."
|
|
bitfld.long 0x18 6. "SWREQ,Channel 0 Software Request Trigger" "0: Hardware request line is connected to the..,1: Software request is connected to the peripheral.."
|
|
newline
|
|
bitfld.long 0x18 4. "DSYNC,Channel 0 Synchronization" "0: Peripheral-to-memory transfer.,1: Memory-to-peripheral transfer"
|
|
bitfld.long 0x18 1.--2. "MBSIZE,Channel 0 Memory Burst Size" "0: The memory burst size is set to one.,1: The memory burst size is set to four.,2: The memory burst size is set to eight.,3: The memory burst size is set to sixteen."
|
|
newline
|
|
bitfld.long 0x18 0. "TYPE,Channel 0 Transfer Type" "0: Self-triggered mode (memory-to-memory transfer).,1: Synchronized mode (peripheral-to-memory or.."
|
|
line.long 0x1C "CDS_MSP,Channel Data Stride Memory Set Pattern"
|
|
hexmask.long.word 0x1C 16.--31. 1. "DDS_MSP,Channel 0 Destination Data Stride or Memory Set Pattern"
|
|
hexmask.long.word 0x1C 0.--15. 1. "SDS_MSP,Channel 0 Source Data stride or Memory Set Pattern"
|
|
line.long 0x20 "CSUS,Channel Source Microblock Stride"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "SUBS,Channel 0 Source Microblock Stride"
|
|
line.long 0x24 "CDUS,Channel Destination Microblock Stride"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "DUBS,Channel 0 Destination Microblock Stride"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
newline
|
|
AUTOINDENT.OFF
|